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SiGe HBTs for System on Chip Applications

Wai Tung Ng, I-Shan Michael Sun, Huaping Edward Xu*, Hidenori Mochizuki, Masato Toita, Takaaki Kobayashi, Hisaya Imai, Akira Ishikawa, Nobuo Saito, Yukihiro Ueda, Satoru Tamura, Kaoru

Takasuka**, Yuichi Furukawa, Teiichiro Kohno, Suketaka Soga, Kentaro Sako, Hideaki Imai, Yasuhiro Ueshima***

*University of Toronto, Dept. of Elec. & Comp. Engineering, 10 King’s College Road, Toronto, Ontario, M5S 3G4

Tel: (416) 978-6249 E-mail: ngwt@vrg.utoronto.ca **Asahi Kasei Microsystems Co, Ltd., Atsugi AXT Maintower, 3050 Okada, Atsugi, Kanagawa 243-0021, Japan

***Asahi Kasei Corp., 2-1, Samejima, Fuji, Shizuoka, 416-8501, Japan

Abstract BiCMOS technology was spawned by the need for higher performance digital logics back in the early 1980s. Since then, with the aggressive scaling of CMOS technology, the cost/performance ratio of pure CMOS began to surpass that of the BiCMOS. This caused a temporary slow down in the development of BiCMOS technology in the late 1980s. The rapid development of recent wireless technology requiring high performance mixed signal and RF circuits has resurrected the focus in the current generation of BiCMOS technology. SiGe HBTs can be designed to be compatible with conventional silicon-based CMOS fabrication processes, but with performance that is far superior to Si-BJTs. SiGe HBTs will remain the key enabling technology for system on chip applications.

1. Introduction The original need to develop BiCMOS digital technology in the early 1980s was to provide better driving current capability against large capacitive loads (e.g. I/O and long internal bus lines). This was especially critical in SRAM and DRAM designs that were the driving force behind the development of VLSI technology of that era [1]. With the continuing shrinking of device dimensions into the sub-micron range, the performance gap between pure CMOS and BiCMOS technologies started to narrow by the late 1980s. The cost and complexity of BiCMOS fabrication processes became a negative factor that further limited their competitiveness to be only in specialized applications such as ECL and analog circuits [2].

With the aggressive scaling of CMOS technology into deep sub-micron regime, the speed and density of the logic circuits are already approaching clock frequency of a few GHz and 100 million transistors per chip [3]. This represents a data processing power of greater than 1000 MIPS, much more than most applications would require. To further enhance the functionality current 0.18 and 0.13µm CMOS processes, manufacturers are looking into the availability of more device options to allow for the integration of System on Chip (SOC) [4, 5].

Recently, the market for analog RF ICs for mobile communication has been growing rapidly. An overview of today’s typical wireless connection is as illustrated in Fig.

1. This trend pushes the need for new processing technologies that can achieve higher operating frequency, lower power consumption and more compact system integration. A brief selection of mixed signal wired and wireless products as listed in Table 1 are already being produced by leading manufacturers.

Table 1: A selection of mixed-signal SiGe products with significant levels of integration. After Meyerson [6]

Company Product Category

Description Part No. Status

AMCC wired 3.2 Gb/s 17×17 Crosspoint switch Multi-rate OC-48 Transceiver

S2018 S3058

4Q99; $200 1Q00; $135

Alcatel wired Complete 10Gb/s SONET System with all electronics

- 09/98

Harris (Intersil)

wireless PRISM II Chip Set — 11Mb/s (5 ICs, 2.4GHz) Power Amplifier and Detector

HFA3983

production

IBM/Leica wireless Direct-Conversion GPS Receiver and Engine

- 09/99

Siemens wireless 3G Mobile Cellular Base Station

- 08/99

2. Comparison of Bipolar Technologies When CMOS is used in radio frequency circuits, it does not perform as well as other processes such as GaAs HBTs, SiGe HBTs and Si BJT, due to its poorer compromise between cut-off frequency (fτ) and bias current. Even though a significant amount of literatures have demonstrated the feasibility of CMOS technology in RF applications [7], no CMOS-based commercial RF product has yet to be made.

It has been demonstrated that GaAs offers superior fτ and power added efficiency (PAE) [8], but is very expensive and is impossible to integrate with CMOS on silicon. The device structures of SiGe HBT and Si-BJT are very similar. The SiGe HBT has better fτ performance than Si-BJT and both can be integrated with CMOS. In cases where only moderately high frequency is needed, SiGe HBT would still be preferred over Si-BJT since it can provide the same performance at a lower bias current,

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resulting in lower power consumption. One advantage in incorporating a small percentage of Ge content in the silicon base region is the fact that a lowering in energy band-gap can be obtained. This naturally occurring change in potential results in a built-in electric field as shown in Fig. 2. This field will assist the transport of carriers in the HBT, hence high operating speed.

The best characteristics reported for each type of devices is summarized in Table 2.

Table 2: Performance comparison of various technologies

Tech

nolo

gy

f τ (G

Hz)

f max

(GH

z)

PAE

Line

arity

Cos

t

Proc

ess

CM

OS

Com

patib

le?

GaAs HBT 200 140

SiGe HBT 170 160

CMOS 135 N/A 2GHz -

Si BJT 100 74

Recent development in fabrication equipment has lowered the cost of SiGe production to an acceptable level. Coupled with the fact that most deep sub-micron CMOS processes are already incorporating more than 20 masking steps (e.g. including E²PROMs, DRAMs, high value poly-resistors and poly to poly capacitors, etc.), the added complexity of integrating the SiGe HBT will not be as significant as in previous generation CMOS technologies. Therefore, SiGe-BiCMOS is becoming an attractive and viable technology for many manufacturers with existing deep sub-micron CMOS processes [9].

3. SiGe BiCMOS Process With the substantial investment already made in today’s deep sub-micron processes and CMOS circuit designs, it is logically to base the development of the SiGe-BiCMOS on a CMOS process. One of the biggest challenge is the growth of the SiGe layer used to form the base region of the HBT. Although Si and Ge are both group IV elements and have similar atomic structure, they have slightly different atomic spacing. When Ge atoms are used to replace Si atoms in a crystalline structure, mechanic strain will result. This limits the percentage of Ge content (normally no more than 15% within a thickness of 500nm) that can be introduced and the thermal budget after the growth of this layer.

An economical approach to develop a full feature SOC technology is to use the modular approach. A standard CMOS flow is served as the base process. Additional devices (such as E²PROMs, multiple threshold devices, HBT, etc.) are developed as optional modular processing

steps that can be inserted at strategic locations. The insertion point of the HBT processing modules can be at several different stages as illustrated by the flow chart in Fig. 3. The compromise is mainly between the ease of the HBT device fabrication against the impact on the CMOS performance [10]. Therefore, SiGe-BiCMOS fabrication flow can be categorized into either “Base after Gate” or “Gate after Base” processes. In order to reduce the compromise on CMOS performance and to limit the thermal budget that the SiGe layer will experience, most manufacturers prefer the “Base after Gate” approach.

Our current focus is to co-develop a SiGe-BiCMOS process with Asahi Kasei Microsystems (AKM) that is based on their 0.35µm CMOS technology [11]. The SiGe HBT is obtained by adding an additional n+ buried layer, a p-type epitaxial deposition, a deep n-well implant, a SiGe base epi-growth and implant, and a poly-emitter deposition to the base process. The highlight of the process flow is as depicted in Fig. 4.

4. Simulation Results The entire fabrication steps for the AKM SiGe-BiCMOS process were simulated using TSUPREM4. The HBT structure is as shown in Fig. 5. The typical doping profile along a vertical plane in the emitter region is plotted in Fig. 6. The electrical characteristics of the device were then simulated using MEDICI. The IV curves in Fig. 7 showed a low output conductance (VA > 35V) and with a high breakdown voltage (BVCES > 5V). The Gummel plot in Fig. 8 showed more than 6 decades of linear operation. The HBT also exhibit a DC current gain of at least 50 over 5 decades of current range with a peak of 120 (see Fig. 9). The high frequency performance of the SiGe HBT as plotted in Fig. 10 showed a fτ of 50GHz. This represents a significant improvement over an equivalent Si-BJT structure [11] fabricated using similar process. In the next phase of this work, we will concentrate on verifying the advantages of this process with experimental results.

5. Conclusions The development of SiGe-BiCMOS technology will continue to be an attractive approach to add new device features and functionality to existing CMOS processes. The favorable cost/performance ratio and minimal added process complexity of the SiGe HBT will be the driving force behind future SOC integration for high speed wired and/or wireless applications.

Acknowledgment The authors thank AKM, CITO and NSERC for financial support, and to AKM for continuing technical support.

References [1] J.B. Kuo, “BiCMOS Digital ICs,” McGraw-Hill, 1996. [2] S.S. Rofail and K.S. Yeo, “ Low-Voltage, Low-Power

Digital BiCMOS Circuits,” Prentice Hall, 2000.

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[3] R. Mahajan, R. Nair, V. Wakharkar, J. Swan, J. Tang, and G. Vandentop, “Emerging Directions of Packaging Technologies,” Intel Tech. J., Vol. 6, No. 2, pp. 62-75, 2002.

[4] K.J. Kuhn, S. Ahmed, P. Vandervoorn, A. Murthy, B. Obradovic, K. Raol, W.K. Shih, I. Chao, I. Post, and S. Chambers, “Integration of Mixed-Signal Elecments into a High-Performance Digital CMOS Process,” Intel Tech. J., Vol. 6, No. 2, pp. 31-41, 2002.

[5] T.H. Ning, “Why BiCMOS and SOI BiCMOS,” IBM J. Res. & Dev., Vol. 46, No. 2/3, pp. 181-186, 2002.

[6] B.S. Meyerson, “SiGe based Mixed-Signal Technology for Optimization of Wired and Wireless Telecommunications,” IBM J. Res. & Dev., Vol. 44, No. 3, pp. 391-407, 2000.

[7] A. Abidi, P. Gray, R. Meyer.“Integrated circuits for wireless communications”, New York : IEEE Press, 1999.

[8] A. McShane and K. Shenai, “Technologies and Design of Low-Power RF Microsystems,” in Proc. IEEE MIEL, vol. 1, May 2000, pp. 107-115.

[9] D. Harame, “High Performance BiCMOS Process Integration: Trends, Issues, and Future Directions,” BCTM Tech. Dig., pp. 36-43, 1997.

[10] D. Knoll, B. Heinemann, K.-E. Ehwald, H.- Rücker, B. Tillack, H.-J. Osten,” Modular, High-Performance BiCMOS by Integration of SiGe:C HBTs,” Proc. 2nd Int. Symp. on ULSI Process Integration, March 25-30, 2001, Washington D.C., USA, Electrochem Society Proc. Vol. 2001-2, p.165.

[11] I.S.M. Sun, W.T. Ng, P.K.T. Mok, H. Mochizuki, K. Shinomura, H. Imai, A. Ishikawa, N. Saito, K. Miyashita, S. Tamura, and K. Takasuka, “A CMOS Compatible RF Bipolar Transistor Technology,” 2001 Asia-Pacific Workshop on Fundamental and Application of Advanced semiconductor Devices (AWAD), Tech. Dig., pp. 301-307, Cheju-Do, Korea, July 5-7, 2001.

Figure 1. Typical wireless connections available in today’s

wireless communication. After Meyerson [6].

e-

h+

30~50kV/cm

neutral

e-

h+

e-

h+

30~50kV/cm

neutral

Figure 2. The band-gap narrowing in the base region

resulted in a built-in electric field that helps to accelerate the carriers across the base.

Figure 3. Integration of the HBT by the insertion of a few

process modules to a standard CMOS flow. Placement of these modules can significantly impact on process compatibility. After Knoll [10].

After CMOS completion, blanket SiGe expitaxial growth, oxide deposition, p-base implant, base etch

p-substraten+ buried layer

deep n-well

n+p-well

n+ n+ p+n-well

n+ p+ p+

p-epi

p-baseimplant

SiO2SiO2SiO2 SiO2SiO2

SiGeSiO2

Emitter window etch, poly-emitter deposition, emitter implant, emitter poly etch

p-substraten+ buried layer

deep n-well

n+p-well

n+ n+ p+n-well

n+ p+ p+

p-epi

n+ and p+implant

SiO2SiO2SiO2 SiO2SiO2

SiGeSiO2

CVD oxide, open contact holes, metallization

p-substraten+ buried layer

collectorn+

p-welln+ n+ p+

n-welln+ p+ p+

p-epi

SiO2SiO2SiO2 SiO2SiO2

base collectordrainsource/bodysource/bodydrain

poly emitter HBTp-MOSFETn-MOSFET

Metal 1

Figure 4. A CMOS compatible fabrication process flow for

a “base after gate” SiGe HBT structure.

4

base contactpoly

emitter

collector

p-poly

LOCOSSiGe p-base

Figure 5. A cross-sectional view of the SiGe HBT structure simulated using TSUPREM4.

Germanium Concentration

Base (B)

SIC (P)

n+ diffusion (As)Polyemitter

Buried Layer (As)

Germanium Concentration

Base (B)

SIC (P)

n+ diffusion (As)Polyemitter

Buried Layer (As)

Figure 6. Typical doping concentration profile of SiGe HBT

structure simulated using TSUPREM4.

Figure 7. Simulated IV characteristics of a 0.35µm CMOS compatible SiGe HBT structure using MEDICI.

0.2 0.4 0.6 0.8 1.010-1310-1210-1110-1010-910-810-710-610-510-410-3

IcIb

Vbe, V

I b, I c ,

A/µ

m

Figure 8. Simulated Gummel plot of a 0.35µm CMOS compatible SiGe HBT structure using MEDICI.

10-9 10-8 10-7 10-6 10-5 10-4 10-30

50

100

150

βVbe=0.7V=112(M)

Beta

Jc, A/µm Figure 9. Simulated DC current gain versus collector

current (normalized to per µm width of the device) of a 0.35µm CMOS compatible SiGe HBT structure using MEDICI.

10-7 10-6 10-5 10-4 10-3

0

1x1010

2x1010

3x1010

4x1010

5x1010

6x1010

18 GHz ( Si-BJT )

SiGe-HBT Si-BJT

50 GHz ( SiGe )

f T ( H

z )

Jc ( A/µm ) Figure 10. Comparison of the simulated unity cutoff

frequency for a 0.35µm CMOS compatible SiGe HBT and an equivalent Si-BJT structure using MEDICI.