Thursday, April 13, 2023 Signal Description Of 8086 1

Agenda:

Signal Description Of 8086

Pin Configuration of 8086

Pin Purpose

Thursday, April 13, 2023 Signal Description Of 8086 2

Signal Description of 8086

1. Available with 3 clock rates(viz. 5, 8 & 10 MHz)

2. 40 pin CERDIP or plastic package.

3. Operates in single as well as in multiprocessor configuration to achieve high performance.

4. Some pins serves particular function in minimum mode & other function in maximum mode.

5. Signal Category Groups

Signals with common function in both mode

Signals with Special function in minimum mode

Signals with Special function in maximum mode

Thursday, April 13, 2023 Signal Description Of 8086 3

1234567891011121314151617181920

4039383736353433323130292827262524232221

GND

AD0-AD14

NMIINTR

GND

VCC(+5V)

RESET

CLK

AD15

RDMN/MX

RQ/GT0

LOCK

S1S2

S0QS0

TESTREADY

A16/S3A17/S4A18/S5A19/S6

BHE/S7

RQ/GT1

QS1

8086

Interrupt Control

Maximum Mode

Time Multiplexed memory I/O address & data lines

Time Multiplexed address & status lines

Minimum Mode

HOLDHLDAWRM/IODT/RDENALEINTA

Thursday, April 13, 2023 Signal Description Of 8086 4

AbbreviationsMaximum ModeAD0-AD15 ≡ Address GND ≡Ground INTR ≡ Interrupt Return CLK ≡ Clock Input VCC ≡ Power Supply BHE ≡ Bus High Enable RD ≡ Read INTR ≡ Interrupt Request NMI ≡ Non Maskable InterruptMN/MX ≡ Min/MaxA16/S3, A17/S4, A18/S5, A19/S6 ≡ Multiplexed Address & Status Lines

Minimum ModeM/I/O ≡ Memory I/O

INTA ≡ Interrupt Acknowledge ALE ≡ Address Latch Enable

DT/R ≡ Data Transmit/Receive DEN ≡ Data Enable

HLDA ≡ Hold Acknowledge

Thursday, April 13, 2023 Signal Description Of 8086 5

Pin Purpose of 80861. Bus High Enable BHE – indicates transfer of data over high

order(D8-D15)

2. Clock Input CLK- Basic timing for processor operations & bus control activity.

3. Reset – causes processor to stop current activity & start execution from FFFFFH.

4. Vcc- Power supply for internal circuit operations.

5. GND- Ground for internal circuit.

Thursday, April 13, 2023 Signal Description Of 8086 6

7. MN/MX- finds processors operating mode. i.e. minimum or maximum mode.

8.Intrrupt Acknowledge INTA– Admit interrupt

9. Address Latch Enable ALE-Availability of valid address on address/data lines, and is connected to latch enable input of latches.

10. Test- This Input is examined by a ‘WAIT’ instructions, If TEST input goes low then execution will continue else processor remain in an ideal state.

Cont’d…

Thursday, April 13, 2023 Signal Description Of 8086 7

11. Hold Acknowledge HLDA- When HOLD line goes high, it indicates to the processor that another master is requesting the bus access.

12.Data Enable– Indicates availability of valid data over address/ data lines.

13. Data Transmit/Receive DT/R-Used to decide the direction of data flow through transreceiver. deal state.

Cont’d…