SILENT: Serialized Low-Energy Transmission Coding for On-Chip Interconnection Networks

Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo

Semiconductor System Lab., Dept. of EECS,Korea Advanced Institute of Science and Technology

ICCAD 2004November 9, 2004

2ICCAD 2004

Outline

• Introduction– Power consumption on serial wire

• SILENT Coding– Coding method– Circuit Implementation

• Performance Analysis– Traffic patterns dependency– Real 3D graphics data traffic

• Application to Network-on-Chip [ISSCC 04]– Network Architecture– Implementation & Measurement results

• Conclusion

3ICCAD 2004

Synchronous Parallel Bus in a SoC

• Problems on parallel bus– Area Penalty– Skew b/w multi-bits– Crosstalk

Parallel bus

CLK

bus

timing violation

PMUuP DSP

GraphicsEngineMemories

PeripheralIPs

Interface

BridgeArbiter

32~128b

Introduction (1/3)

4ICCAD 2004

On-chip serial communicationsIntroduction (2/3)

SER

shield

Nbits

[ISSCC 03]*N:1

Parallel-bus Serial-busCrosstalk / Skew Serious None

Area 1 1/NSignal Freq. 1 N

Power 1 1 + α

(Benefit)

More Power!!

(Trade-off)

(Penalty)

New issue

* S.J. Lee, et al., “An 800MHz Star-connected On-Chip Network for SoC,” ISSCC, 2003

5ICCAD 2004

Power consumption on serial wireIntroduction (3/3)

Parallel Bus Serial busvs.

More transitions on a serial wireLosing Data correlation on most-significant bits(sign-extension or locality on multimedia stream)

Goal: Reduce transitions on the serial wire

0 0 0

1 0 0

1 1 0

1 1 10 0 0

1 1 10 0 0

1 1 1

D7

D6D5

D4D3D2

D1D0

(1) (2) (3)2 transitions

0 1 0 1 0 1 1 1 0 1 0 1 0 0 1 1 0 1 0 1 0 0 0 1

(1) (2) (3)

17 transitions

SiLENT (1/3)

6ICCAD 2004

Main idea of SiLENT• Serialized Low-Energy Transmission Coding

Unchanged bits Zeros0 0 0

1 0 0

1 1 0

1 1 10 0 0

1 1 10 0 0

1 1 1

D7

D6D5

D4D3D2

D1D0

Coding

0 0 0

1 1 0

1 0 1

1 0 00 0 0

1 0 00 0 0

1 0 0

D7

D6D5

D4D3D2

D1D0

silentNewInformation

EncodedInformation

Serial wirekeeps quiet

Serialwire

0 1 0 1 0 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0

7ICCAD 2004

Encoding algorithmEncode 1 when there is a transition on parallel dataEncode 0 when there is no transitionThen, Serialize the encoded parallel data

Serialization

0 1 0 1 0 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0

(R): Reference

0 0 0 0 0 1 01

0 0 0 0

1 0 1 1

0 0 0 0

0 0 0 0

1 0 0 0

1 0 0 0

1 1 0 1

1 0 0 0

Encoding

Transition= 1,

No-Trans.= 0

0 0 0 0

1 0 0 1

1 1 0 1

1 1 1 10 0 0 0

1 1 1 10 0 0 0

1 1 1 1

(R)

SiLENT (2/3)

8ICCAD 2004

Circuit implementationSiLENT (3/3)

Sender Enc. SER ReceiverDec.DES

b(t) B(t) D(t) d(t) = b(t)

En by S/W EnSerial wire

En

d(t-1)

D(t)d(t)

EnD(t)

d(t)d(t-1)

d(t-1)

390μW @ 32bits, 100MHz

b(t)

En

b(t-1)B(t)

Critical path385μW @ 32bits, 100MHz

9ICCAD 2004

Dependency on data patterns

ReceiverDec.4:32DES8mm

@ 100MHz, 0.18 μm

Power Analysis (1/3)

Sender Enc. 32:4SER

0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 320

2

4

6

8

10

12

# of transitions b/w successive data

Avg

. Pow

er [m

W] w/o coding

• Significant Power Saving@ x = {0~11, 22~32}

• Overhead, max. 14%@ x = {12~21}

with SILENT

Power saving

10ICCAD 2004

Traffic on real 3D graphics app.Power Analysis (2/3)

• Tracing the traffic of memory transactions3D Graphics Data

6x106 cycles

RISCI-MEMD-MEM

Inst.Data

AddressData

# of transitions b/w successive data

# of

Acc

ess

Instruction Mem. Access Data Mem. Access

0

0.5M

1M

1.5M

2M

2.5M

3M

99% of address60% of code

0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32

inst. addressinst. code

0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32

79% of address70% of data

0

100K

200K

300K

400K addressdata

11ICCAD 2004

Power with graphics applicationsPower Analysis (3/3)

• Normalized avg. power consumption

• Max. 77% Reductionon inst. mem. access

• 40 ~ 50% Reductionon data mem. access

: w/o coding : w/ SILENT coding

InstructionAddress

InstructionCode

Data Mem.Address

Data Mem.Data

0

0.2

0.4

0.6

0.8

1

0.23

0.87

0.510.62

SiLENT performs Significant Power Savingon multimediaapplication

12ICCAD 2004

As a SoC platform (1/9)Network-on-Chip (1/9)

• The next generation of on-chip communications

IP

IP

On-chip NetworkBackbone

FunctionalUnits

IP

IP

Switches

NetworkInterface

Packet switched networks Higher BandwidthPlesiochronous communications b/w IPs Plug & PlayMore Reliability / Flexibility / Scalability than Bus

L. Benini and G. De Micheli, “Network on chip: A new SoC Paradigm,” IEEE Computer, 2002

13ICCAD 2004

Network-on-Chip architectureNetwork-on-Chip (2/9)

RISC App.Proc.OGW

Master NI MNI MNI

Memory1

Memory2 FPGA

Slave NI SNI SNI

Peri.

Crossbar

PMU(PLL)

Off-Chip Network

Crossbar

IP Clocks

NW Clock

Global link(5mm)

Main Cluster Peripheral Cluster(Long Distance)

3.2GB/s(duplex)

Mem

.

Mem

.SNI SNI SNI

Serial linkSiLENTCODECSERDES

Network I/F

* Kangmin Lee, et al., “A 51mW 1.6GHz On-Chip Network for …,” ISSCC, 2004

14ICCAD 2004

Network Interface & ProtocolNetwork-on-Chip (3/9)

Packet format (max. 80bits)16b Header: RI, RW, Priority…32b Address or/and 32b Data

x10 Serialization & Speed-UpReduces network areaIncreases network bandwidth

Source-synchronous scheme

MASTERIP

32b32b

ADDR DATACMD

Header

Serializer

16b

Flow

Con

trol

80b @100MHz

8b @1.4GHz

Switch

8b

Stro

be

Pack

et

EOP

SiLENT-ENC

A3A2A1A0H1H0 D3D2D1D0

END

1.4GHz STROBE

EOP8bits

15ICCAD 2004

Software controlled SiLENT Network-on-Chip (4/9)

• Software enable/disable SiLENT coding

*

ldi 0x3, %r2ldi 0x7000000, %r5ldi 0x0, %r6ldi 0xcf000000, %r3st %r6, (%r3+0x0)

L2: sub 0x1, %r2jm L1jmp L2

L1: addq 0x1, %r6addq 0x4, %r5st %r6, (%r5+0x0)ldi 0x3, %r2... ...

Address mapped register

SiLENTENC.

SiLENT Enable

RISC(Tx)

addr.data

En SER

DES

HAD SiLENT

DEC.

En

packet

packet Slave(Rx)

Dynamic On/Off SiLENT coding by softwareON Multimedia streaming, Instruction addressOFF Random data (Instruction code)

* 2 cycle latency to flip the enable

16ICCAD 2004

Power Reduction on the NoCNetwork-on-Chip (5/9)

• Traffic: a real trace from 3D graphics operationA

vg. P

ower

[mW

]

SiLENTOFF

SiLENTON

ENC (0.2)

DEC (0.2)Rx-I/F

Tx-I/F13% reduction

N E T W

O R

K

0

4

8

12

16

20

24

Rx-I/F

Tx-I/F

N E T W

O R

K

Power overhead of CODEC is negligible

3D Graphics Data

6x106 cycles

17ICCAD 2004

Implementation resultsNetwork-on-Chip (6/9)

• Die Photograph

□ 0.18μm 6M CMOS Tech.□ 5mm x 5mm□ Power Supply

• 1.6V: Logic/Analog• 3.3V: I/O

□ OCN Power Consumption• Less than 51mW

□ Aggregate Bandwidth• 11.2GB/s

□ Various IPs for Multimedia App.• 32b μP x 2 (@ 100MHz)• FPGA (64LE)• 64kb SRAM x 2• Off-chip Gateway

18ICCAD 2004

Measurement resultsNetwork-on-Chip (7/9)

• Successful operation at 1.4GHz

Header Address Data

1 0 0 0 0 0 1 0 1 0

StrobeHigh-speed

small-swing I/O

PKG on board

Link[0]

1nsec/divEOP

[ internal signals on a chip ]

19ICCAD 2004

Measurement @ SiLENT OFFNetwork-on-Chip (8/9)

• 80bit Parallel Data • 8bit Serialized PacketHeader0x583e STB

[0]Address [1]

0x070000000x070000040x070000080x0700000C

[2][3][4]

[5]Data[6]0xC59ABA85

0xC59ABA890xC59ABA8D0xC59ABA92

[7]EOP

Total transitions: 134Total transitions: 11

20ICCAD 2004

Measurement @ SiLENT ONNetwork-on-Chip (9/9)

STROBELINK[0]

[1]

[2][3][4]

[5][6][7]

EOP

Total transitions: 134 Total transitions: 79

Without SiLENT With SiLENTSTB[0]

[1]

[2][3][4]

[5][6][7]EOP

21ICCAD 2004

Conclusion

• Proposed SiLENT coding– Low-power coding for on-chip serial communications– Efficient for multimedia applications

• Power reduction of 77% for instruction address• 40~50% for multimedia data traffic

• SiLENT Application to NoC for SoC platform– 13% power saving on the on-chip networks– SiLENT coding controlled by software– Successful 1.4GHz operation

• Real chip verification for the effectiveness of SiLENT

22ICCAD 2004

Supplementary (1/2)

• Area Overhead– DEC: 95 x 80 μm2 ENC: 95 x 160 μm2

Network Interface

ENC

DEC

RISC

Forward Network

Backward Network

23ICCAD 2004

Supplementary (2/2)

• BONE: NoC Protocol Standard– http://ssl.kaist.ac.kr/ocn

…