silicon systems group · proceedings and claims; and other risks described in applied’s sec...

External UseSILICON SYSTEMS GROUP External UseSILICON SYSTEMS GROUP

Because Innovation Matters™

Silicon Systems Group

Toru WatanabePresident, Applied Materials, Japan

Semicon JapanNovember 30, 2010

External UseSILICON SYSTEMS GROUP

Safe HarborThis presentation contains forward-looking statements, including those regarding the Applied Silicon Systems Group’s performance, strategic positions, products and opportunities. These statements are subject to known and unknown risks and uncertainties that could cause actual results to differ materially from those expressed or implied by such statements, including but not limited to: the level of demand for Applied’s products, which is subject to many factors, including: uncertain global economic and industry conditions, business and consumer spending, demand for electronic products and semiconductors, and customers’ utilization rates and new technology and capacity requirements; Applied’s ability to (i) develop, deliver and support a broad range of products, expand its markets and develop new markets, (ii) align its cost structure with business conditions, (iii) plan and manage its resources and production capability, (iv) implement initiatives that enhance global operations and efficiencies, (v) maintain effective internal controls and procedures, (vi) obtain and protect intellectual property rights in key technologies, and (vii) attract, motivate and retain key employees; risks related to legal proceedings and claims; and other risks described in Applied’s SEC filings. All forward-looking statements are based on management’s estimates, projections and assumptions as of November 30, 2010, and Applied undertakes no obligation to update any forward-looking statements..

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Silicon Systems Group Overview

#1 in the WFE and advanced packaging markets

In 2010, expect increased market sharein each SSG business

In 2011, expect to grow WFE market share for the 3rd consecutive year

Growth fueled by new product innovations aligned to technology inflections

3

Source: Gartner, April 2010


Astra™ DSA Anneal

Innovations Enable Inflections

4

Siconi™ for Epi

ADVANCEDPATTERNING

TRANSISTOR INTERCONNECTWAFER-LEVELPACKAGING

Mesa™ Etch

Avenir™ PVD/ALD

Centinel™ PVD

UVision® 4 Brightfield Reflexion® GT™CMPRaider-S™ ECD

InVia™ CVD

Avila™ CVD

Accelerating innovations – 15 new products in 15 months

Eterna™ FCVDTetra X™

Aera3™

Centris™ Etch

Silvia™ Etch

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Applied Materials Conductor Etch Innovations

Ellie YiehVP and GM, Etch Business Unit

Semicon JapanNovember 30, 2010

External UseSILICON SYSTEMS GROUP6

Conductor Etch is Fastest

Growing Etch Segment

Conductor etch ~ $1.6B market in 2010

New steps in advanced transistors, double patterning and advanced packaging driving growth

Applied already leads in advanced DRAM transistor critical etch

Source: Gartner, Sept 2010


Astra™ DSA Anneal

Innovations Enable Inflections

7

Siconi™ for Epi

ADVANCEDPATTERNING

TRANSISTOR INTERCONNECTWAFER-LEVELPACKAGING

Mesa™ Etch

Avenir™ PVD/ALD

Centinel™ PVD

UVision® 4 Brightfield Reflexion® GT™CMPRaider-S™ ECD

InVia™ CVD

Avila™ CVD

Accelerating innovations – 15 new products in 15 months

Eterna™ FCVDTetra X™

Aera3™

Centris™ Etch

Silvia™ Etch


Applied’s Conductor Etch Competitive Position

8

Leading in Advanced DRAM

(BBL/BWL architectures)

Requires <1 % Depth Non-Uniformity

VERTICAL SCALING

Expanding Positions in Double PatterningNAND, Foundry, Logic and DRAM

Requires <1 nm, 3σ CD Non-Uniformity

HORIZONTAL SCALING


Gap in Litho Roadmap is Etch Opportunity

9

Hard masks and double patterning enable below-wavelength patterning

Hard Mask Insertion

21.5

10.6

0.5 0.350.25

0.180.13

0.090.065

0.045

1980 1990 2000 2010 2012F

Above Wavelength

NearWavelength

BelowWavelength

Double Patterning

g-lineλ=436nm i-line

λ=365nm

DUVλ=248nm

193 (immersion)λ=193nm

193 (dry)λ=193nm

Resolution(µm)

Year of Production

0. 1

10

1

0.01

0.032

Lithography Gap

0.022

Sources: 2010 ITRS Roadmap, Applied Materials


Adding up the CD Variation

10

Tighter etch CD uniformity can give wider process window for litho

Logic / Foundry Double Patterning Scheme

Yield impacted by CD variation: (L1 , E2 , L3 , L4 , E5)

E2 = First hard mask etch CD variation

L1 = First litho CD variation

L3 + L4 = Second litho CD + overlay variation

E5 = Second hard mask etch CD variation


How Precise is the Etched Critical Dimension?

11

Etched CD variation range of

0.8 nm:

10,000X smaller than a red

blood cell diameter,matched over

thousands of wafers

Red Blood Cells


Patterning Etch Steps Growing

12

Added steps increase process cost for customers

+10 steps

DRAM 4X nm DRAM 2X nm

+6 steps

NAND 4X nm NAND 2X nm

Logic 45 nm

+10 steps

Logic 22 nm

Source: Applied Materials estimate


Relentless Cost-per-Bit Reduction

13

$ / M

B

Source: Gartner, Applied Materials

Cost reduction is key for customers

F F


Applied’s Etch Leadership in Productivity and Technology

14

30% lower cost-per-wafer with leading critical etch performance

Lower Cost-Per-Wafer (normalized)

Impr

oved

CD

Con

trol

CentrisPlatform

TraditionalPlatform


Applied’s Centris Platform: Performance Worth Repeating

15

Combines industry-leading Mesa chambers with high-productivity Centris platform


6 Mesa Chambers

Building a Productivity Powerhouse with Centris

Four-FOUP

Interface

Dual-Blade Robot

Optimized Gas Panel

En-Route Abatement


3 Etch Chambers

Seijo™ En-Route Abatement Doubles the Number of Etch Chambers

4 process chambers total

Traditional Platform

Abatement Chamber

6 Etch Chambers

Centris Platform

8 process chambers total

2 SeijoAbatement Chambers


AdvantEdge Mesa Chamber: Angstrom-level Precise Etch

18

Mesa Source

<1nm CD Uniformity<1% Etch Depth Uniformity

Pulsync™

Advanced plasma controlMicroloading benefit

Extending Silicon Etch Memory leadership

1st ultra-flat uniformity ICP* etcher enabling ≤3xnm node

Rapid adoption with >200 chambers in 9 months

Source

BiasPulse Pulse

* Inductively Coupled Plasma


Mesa Source: Breakthrough Etch Rate Uniformity

19

Traditional Mesa

Limited Uniformity Improved Uniformity

Limited Electrical Field Tunability Electrical Field Decoupled and Tunable

Breakthrough Mesa source delivers ultra-flat etch rate map

External UseSILICON SYSTEMS GROUP External UseSILICON SYSTEMS GROUPSILICON SYSTEMS GROUP

Mesa Pulsync Mitigates Microloading

20

SEVERE LOADING – No Pulsing

MINIMAL LOADING – With Pulsync

Mesa’s Pulsync technology minimizes micro-loading in etch depthSEM image used with customer permission

Challenge: Bi-Modal Trench Depth Distribution with Spacer Double Patterning


Auto-Calibration

Management Software

6 Mesa Chambers, Auto-

Calibrated to Same Standard

Centris Enables the Same CD Every Time

Central Reference Standards

E3™ software identifies

excursions


Improved Process Parameter Repeatabilityvia Auto-Calibration

22Patent Applied For

Ch ACh BCh CCh DCh ECh F

Auto-calibration

off

Auto-calibration

on

Base Pressure

Time (days)

OLD CONTROL LIMIT

NEW CONTROL LIMIT


38.0

39.0

40.0

41.0

42.0

43.0

0 250 500 750 1000

Centris Etch Matching of 4,000 Wafers

23

Chamber matching demonstrated at 0.8nm range across 4,000 wafers

Post

-Pro

cess

CD

(nm

)

Number of wafers

Upper Spec Limit

Lower Spec Limit


Device YieldDevice Yield

Device Yield Benefit from Tighter Controls

24

Centris PlatformPR

OC

ESS

PER

FOR

MAN

CE

Traditional PlatformPR

OD

UC

TPE

RFO

RM

ANC

E


Capital Productivity Benefit for Customers

NAND 2Xnm at 250K WSPM, One Etch Application

3 ETCH, 1 ABATEMENT PLATFORM

6 ETCH, 2 EN-ROUTE ABATEMENT PLATFORM

Unique 8-chamber architecture enables best-in-class productivity


“Green” Benefits of Lower Facilitization Costs

26

~35% improvement in energy savings from standard etchers

One Platform saves an Olympic-size swimming pool of water per year

Lower CO2 emissions per Platform: equivalent to taking 50 cars per year off the road

Assumes SEMI S23 standard calculations

Green benefits contribute one-third of cost-per-wafer savings


Applied’s Conductor Etch Platforms are Well Positioned at Leading Customers

2727

AdvantEdgeChamber

AdvantEdgeMesa Chamber

CentrisPlatform

>1500 chambers

>200 chambers in first 9 months

5 customers; includes entry

into 2 new customers


Applied’s Centris Platform: Performance Worth Repeating

28

Precise Intelligent ProductiveTightest CD uniformity

Tightest depth uniformity on each wafer

Auto-calibrating Industry-leading at 30% lower cost-per-wafer

silicon systems group · proceedings and claims; and other risks described in applied’s sec...

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