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Simulation Analysis of Novel Multilevel Inverter Topology

with Less Circuit Components

Dhivakar K Department of EEE

SSN College of Engineering

Chennai, India

Dev Ganesh S Department of EEE


Chennai, India

Thiyagarajan V Department of EEE


Chennai, India

Bala Murugan B Department of EEE


Chennai, India

Abstract—In this paper, a novel multilevel inverter

topology with less number of power electronics switches and

DC voltage sources is proposed. This topology uses reduced

number of components resulting in smaller inverter size, and

lower installation cost. The proposed inverter topology is

suitable for power conversion in renewable energy systems due

to its high power quality output. The proposed inverter

topology is able to provide more voltage levels with fewer

voltage sources and power switches compared to the

conventional CHB inverter. The proposed inverter topology is

designed to work in both symmetrical and asymmetrical

configurations. In this paper, the operation and overall

performance analysis of the proposed inverter in asymmetrical

configuration is done and presented.

Keywords—Multilevel, inverter, asymmetric; thirteen level,

THD, switching angle.

I. INTRODUCTION In Recent times, Multilevel inverters are becoming a

preferred choice for renewable energy power conversion system due to its several advantages. Basically, a Multilevel inverter is a power electronic circuit that derives a desired AC output voltage in the form of staircase from several DC voltage sources as inputs [1-3]. The advantages of multilevel inverter include low dV/dt stress, less electromagnetic interference and high power quality [4-6]. Based on the nature of components used and circuit configuration multilevel inverters are classified into three categories. They are (i) neutral-point-clamped multilevel inverters, (ii) flying capacitor multilevel inverters, and (iii) cascaded multilevel inverters [7-10]. Each topology has its own advantages and disadvantages. The former two categories, in addition to power electronic switches uses diodes and capacitors respectively. The Cascaded H-bridge inverter is implemented by connecting several H-bridges in series. These cascaded multilevel inverters can be broadly classified into two types .i.e., Symmetrical and Asymmetrical cascaded inverters. Symmetrical inverters have DC voltage sources with the same amplitude while the asymmetrical inverters have different magnitudes. The asymmetrical cascading of inverters is preferred over the symmetrical inverter as the former is capable of achieving more voltage steps than the latter configuration with the same number of power switches [11]. As a result of this, capital cost of installation and fabrication of an asymmetrical configuration of the inverter is lower compared to a symmetrical configuration of the inverter for producing the same voltage level. Since the first

design of multilevel inverters, many different multilevel inverter topologies have been proposed with reduced circuit components having higher efficiency, power rating, and portability. The main issue in these existing topologies is that the smoothness of the waveform is proportional to the number of voltage steps, but as we keep on increasing the number of voltage steps, the number of components as well as complexity of control circuit increases. This will also leads to increase in switching losses[12].

In this paper, a novel multilevel inverter topology with a less number of switches has been designed and simulated. This topology aims to reduce the total harmonic distortion (THD) as low as possible by adopting suitable switching strategy thereby improving the power conversion efficiency. In the following sections, the circuit configuration, operation, comparative analysis between existing topologies and proposed topology and simulation results of the proposed topology are discussed.

II. PROPOSED MULTILEVEL INVERTER TOPOLOGY Fig. 1 depicts the circuit configuration of the proposed

thirteen level multilevel inverter topology.

Fig. 1 Proposed Multilevel Inverter

The proposed multilevel inverter topology consists of nine power electronic switches and four DC voltage sources. This circuit has the compatibility to work in both symmetrical and asymmetrical configurations. In the symmetrical configuration, this setup can only generate only 9 levels, but in asymmetrical configuration it can generate 13 levels. So, in this paper, it is focused on the working of

International Journal of Applied Engineering Research ISSN 0973-4562 Volume 14, Number 11, 2019 (Special Issue) © Research India Publications. http://www.ripublication.com

Page 221 of 225

asymmetrical configuration. The various operating modes of the proposed multilevel inverter in asymmetrical configuration during positive cycle are shown in the Fig. 2. In mode-0, power switches S6 and S7 are in ON position, so

that the voltage at the load terminals is zero. In mode-1, switches S1, S5, S6, S9 are in ON position, giving an output of V1. In mode-2, switches S2, S5, S6, S9 are in ON, giving an output of V1+V2.

(a) (b)

(c) (d)

(e) (f)

(g)

Fig.2.Different modes of operation (a) Mode - 0 (b) Mode - 1 (c) Mode - 2 (d) Mode -3 (e) Mode - 4 (f) Mode - 5 (g) Mode - 6


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During mode-3, switches S1, S3, S6, S9 are in ON position, giving V1+V3 as output. In mode-4, switches S2, S3, S6, S9 are in ON, giving an output of V1+V2+V3. In mode-5, switches S1, S4, S6, S9 are in ON, giving an output of V1+V3+V4. In mode-6, switches S2, S4, S6, S9 are in ON, giving an output of V1+V2+V3+V4. In mode-7, switches S6 and S7 or S8 and S9 are enabled so circuit is short circuited, making output voltage as 0. In mode-8, switches S1, S5, S7, S8 are in ON position, giving an output of V1. In mode-9, switches S2, S5, S7, S8 are in ON, giving an output of -(V1+V2). During mode-10, switches S1, S3, S7, S8 are in ON position, giving –(V1+V3) as output. In mode-11, switches S2, S3, S7, S8 are in ON, giving an output of –(V1+V2+V3). In mode-12, switches S1, S4, S7, S8 are in ON, giving an output of –(V1+V3+V4). In mode-13, switches S2, S4, S7, S8 are in ON, giving an output of –(V1+V2+V3+V4). The modes of operation from mode-1 to mode-6 operate during positive cycle while mode-7 to mode-12 operate during negative cycle. The switching states for various operating modes of the proposed multilevel inverter are given in Table I. It is seen that two different operating modes are proposed for zero crossing in order to equally distribute the switching stresses among switches.

TABLE I SWITCHING STATES FOR VARIOUS OPERATING MODES

From the above switching table, it can be concluded that

the number of ON state switches during any mode from mode-1 to mode 12 is always 4. The comparison of the output voltage levels against the number of DC voltage sources and the number of switches for several multilevel inverter topologies are given in Table II.

TABLE II COMPARISON OF MULTILEVEL INVERTER TOPOLOGIES

From the table shown above, it can be observed that the proposed multilevel inverter topology requires minimum number of switches to achieve thirteen step output voltage. Also, the switching losses were considerably reduced in the proposed multilevel inverter topology when compared with the existing inverter topologies.

III. CALCULATION OF SWITCHING ANGLES There are several methods available for calculating

the switching angles for the multilevel inverter. Among the available methods, half height method is proven to be efficient method of switching angle calculation. In this section, half height method of switching angle calculation is discussed.

The principle behind half-height (HH) method is that when the function value increases to half the height of the level, the switching angle is set and thus a better smooth staircase output waveform is obtained. The main switching angles are obtained using the formula [13]:

2

1-N.... 3 2, 1, where,

1

12sin 1 i

N

ii

where, N denotes the number of steps at the output

voltage waveform.

This method gives better output voltage waveform when compared with other existing methods. The switching angles lying between the period 0o and 90o are known as main switching angles. For thirteen level inverter, the number of main switching angles is six and are obtained using the half-height method and is given in Table III. The switching waveform obtained using the half-height method is shown in Fig.3.

TABLE III MAIN SWITCHING ANGLES

Main Switching Angles (in degrees)

θ1 4.78 θ4 35.69

θ2 14.48 θ5 48.59

θ3 24.62 θ6 66.44

Mode S1 S2 S3 S4 S5 S6 S7 S8 S9 Output Voltage

0 0 0 0 0 0 1 1 0 0

0 0 0 0 0 0 0 0 1 1

1 1 0 0 0 1 1 0 0 1 V1

2 0 1 0 0 1 1 0 0 1 V1 +V2

3 1 0 1 0 0 1 0 0 1 V1+V3

4 0 1 1 0 0 1 0 0 1 V1+V2+V3

5 1 0 0 1 0 1 0 0 1 V1+V3+V4

6 0 1 0 1 0 1 0 0 1 V1+V2+V3+V4

7 1 0 0 0 1 0 1 1 0 -V1

8 0 1 0 0 1 0 1 1 0 -(V1 +V2)

9 1 0 1 0 0 0 1 1 0 -(V1+V3)

10 0 1 1 0 0 0 1 1 0 -(V1+V2+V3)

11 1 0 0 1 0 0 1 1 0 -(V1+V3+V4)

12 0 1 0 1 0 0 1 1 0 -(V1+V2+V3+V4)

Inverter

topology

Number

of DC

Sources

Number

of

Switches

Levels

Symmetric

Asymmetric

Ref.[3] 4 11 9 9

Ref. [4] 4 10 9 13

Ref. [9] 5 9 11 11

Ref. [11] 4 10 9 13

Ref. [12] 4 12 9 13

Proposed Inverter

4 9 9 13


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Fig.3.Switching Pulses

IV. SIMULATION RESULTS The results of the simulation analysis of proposed

asymmetrical thirteen level inverter obtained using MATLAB/SIMULINK are presented in this section. The proposed inverter consists of four DC voltage sources and nine switches. In the asymmetrical configuration, the voltage ratio of the DC voltage sources is chosen to be 1:1:2:2 for achieving thirteen level output. Therefore, the magnitudes of the DC voltage sources are chosen as V1 = V2 = 50 V and V3 = V4 = 100 V. The maximum output voltage obtained is 300 V (i.e., V1 + V2+ V3+V4). The 13-level output voltage is shown in Fig. 4 and the FFT analysis of the thirteen level output voltage waveform for half height method is shown in Fig.5.

Fig.4. Output Voltage

Fig.5.FFT Analysis

The FFT analysis result shows that the total harmonic

distortion of the output voltage waveform using the half height switching method is 6.34%.

V. CONCLUSION In this paper, a novel multilevel inverter topology with

less circuit components has been proposed. The topology is capable of achieving 13 levels at the output voltage in the asymmetrical configuration with voltage ratio V1:V2:V3:V4=1:1:2:2. The switching method used for the proposed topology is capable of achieving a lower THD of output voltage. The proposed inverter topology distributes the voltage stress equally among the power switches and has reduced switching losses. The operation and performance of the proposed multilevel inverter topology is analysed using MATLAB/SIMULINK and the results were presented in this paper.

ACKNOWLEDGMENT This research work was supported and funded by SSN

Trust.

REFERENCES [1] E. Babaei, M.F.Kangarlu, F. Mazgar, "Symmetric and asymmetric

multilevel inverter topologies with reduced switching devices", Electric Power Systems Research, Volume 86, May 2012, Pages 122–130

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[3] E. Babaei, S. Laali and Z. Bayat, "A Single-Phase Cascaded Multilevel Inverter Based on a New Basic Unit With Reduced Number of Power Switches," in IEEE Transactions on Industrial Electronics, vol. 62, no. 2, pp. 922-929, Feb. 2015.

[4] M. R. Banaei and E. Salary, "Asymmetric Cascaded Multi-level Inverter: A Solution to Obtain High Number of Voltage Levels", J Electric Eng Technology Vol. 8, No. 2: 316-325, 2013.

[5] V.Thiyagarajan and P.Somasundaram, " Multilevel Inverter Topology with Modified Pulse Width Modulation and Reduced Switch Count," Acta Polytechnica Hungarica, vol. 15, no. 2, pp. 141-167, 2018.


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[6] E. Babaei, S.H. Hosseini, G.B. Gharehpetian, M. Tarafdar Haque, M. Sabahi, "Reduction of dc voltage sources and switches in asymmetrical multilevel converters using a novel topology", Electric Power Systems Research 77 (2007) 1073–1085.

[7] N.Prabaharan and K. Palanisamy, “Investigation of Single Phase Reduced Switch Count Asymmetric Multilevel Inverter Using Advanced Pulse Width Modulation Technique”, Inter. Journal of Renewable Energy Research, Vol.5, No.3, 2015.

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[9] R.R Karasani, V. B. Borghate, P. M. Meshram, and H. M. Suryawanshi , “A Modified Switched-Diode Topology for Cascaded Multilevel Inverters”, Journal of Power Electronics, Vol. 16, No. 5, pp. 1706-1715, September 2016.

[10] V. Thiyagarajan and P. Somasundaram, "Modeling and analysis of novel multilevel inverter topology with minimum number of switching components," Comp. Model. in Engg. and Sci., vol.113, no. 4, pp. 461-473, 2017.

[11] E. Samadaei, S. A. Gholamian, A. Sheikholeslami and J. Adabi, "An Envelope Type (E-Type) Module: Asymmetric Multilevel Inverters With Reduced Components," in IEEE Transactions on Industrial Electronics, vol. 63, no. 11, pp. 7148-7156, Nov. 2016.

[12] E. Babaei, S. Laali and S. Alilu, "Cascaded Multilevel Inverter With Series Connection of Novel H-Bridge Basic Units," in IEEE Transactions on Industrial Electronics, vol. 61, no. 12, pp. 6664-6671, Dec. 2014.

[13] Luo F.L and Ye H, Advanced DC/AC Inverters, CRC Press LLC, 2013.


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