Document Number: 332219-002

Skylake Platform Controller Hub H and LP (SKL PCH H / LP)Register Information (UART, I2C, GSPI, eMMC, SDXC, and GPIO)

June 2015

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Copyright 2015, Intel Corporation. All Rights Reserved.

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Contents

1 UART Interface (D30:F0/F1 and D25:F0)............................................................... 331.1 UART PCI Configuration Registers Summary.......................................................... 33

1.1.1 Device ID and Vendor ID Register (DEVVENDID)Offset 0h......................... 331.1.2 Status and Command (STATUSCOMMAND)Offset 4h................................. 341.1.3 Revision ID and Class Code (REVCLASSCODE)Offset 8h ............................ 351.1.4 Cache Line Latency Header and BIST (CLLATHEADERBIST)Offset Ch .......... 361.1.5 Base Address Register (BAR)Offset 10h .................................................. 361.1.6 Base Address Register High (BAR_HIGH)Offset 14h.................................. 371.1.7 Base Address Register 1 (BAR1)Offset 18h.............................................. 371.1.8 Base Address Register1 High (BAR1_HIGH)Offset 1Ch .............................. 381.1.9 Subsystem Vendor and Subsystem ID (SUBSYSTEMID)Offset 2Ch.............. 391.1.10 Expansion ROM Base Address (EXPANSION_ROM_BASEADDR)Offset 30h .... 391.1.11 Capabilities Pointer (CAPABILITYPTR)Offset 34h....................................... 401.1.12 Interrupt Register (INTERRUPTREG)Offset 3Ch ........................................ 401.1.13 Power Management Capability ID (POWERCAPID)Offset 80h...................... 411.1.14 PME Control and Status (PMECTRLSTATUS)Offset 84h .............................. 42

1.2 UART Memory Mapped Registers Summary ........................................................... 431.2.1 Receive Buffer Register (RBR)Offset 0h .................................................. 431.2.2 Transmit Holding Register (THR)Offset 0h ............................................... 441.2.3 Divisor Latch Low Register (DLL)Offset 0h............................................... 441.2.4 Interrupt Enable Register (IER)Offset 4h................................................. 451.2.5 Divisor Latch High (DLH)Offset 4h.......................................................... 461.2.6 FIFO Control Register (FCR)Offset 8h ..................................................... 461.2.7 Line Control Register (LCR)Offset Ch ...................................................... 471.2.8 MCR (MCR)Offset 10h .......................................................................... 481.2.9 LSR (LSR)Offset 14h ............................................................................ 491.2.10 MSR (MSR)Offset 18h .......................................................................... 511.2.11 SCR (SCR)Offset 1Ch ........................................................................... 511.2.12 SRBR_STHR0 (SRBR_STHR0)Offset 30h ................................................. 521.2.13 FAR (FAR)Offset 70h ............................................................................ 531.2.14 TFR (TFR)Offset 74h ............................................................................ 541.2.15 RFW (RFW)Offset 78h .......................................................................... 541.2.16 USR (USR)Offset 7Ch........................................................................... 551.2.17 TFL (TFL)Offset 80h ............................................................................. 561.2.18 RFL (RFL)Offset 84h............................................................................. 561.2.19 SRR (SRR)Offset 88h ........................................................................... 571.2.20 SRTS (SRTS)Offset 8Ch........................................................................ 571.2.21 SBCR (SBCR)Offset 90h ....................................................................... 581.2.22 SDMAM (SDMAM)Offset 94h.................................................................. 591.2.23 SFE (SFE)Offset 98h ............................................................................ 591.2.24 SRT (SRT)Offset 9Ch............................................................................ 601.2.25 STET (STET)Offset A0h......................................................................... 601.2.26 HTX (HTX)Offset A4h ........................................................................... 611.2.27 DMASA (DMASA)Offset A8h .................................................................. 611.2.28 CPR (CPR)Offset F4h............................................................................ 62

1.0 UART Additional Registers Summary .................................................................... 641.1 CLOCKS (CLOCKS)Offset 200h .............................................................. 641.2 RESETS (RESETS)Offset 204h ............................................................... 651.3 Active LTR (ACTIVELTR_VALUE)Offset 210h ............................................ 651.4 IDLE LTR (IDLELTR_VALUE)Offset 214h.................................................. 66

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1.5 reg_TX_BYTE_COUNT (TX_BYTE_COUNT)Offset 218h ...............................671.6 reg_RX_BYTE_COUNT (RX_BYTE_COUNT)Offset 21Ch...............................681.7 SW SCRATCH 0 (SW_SCRATCH_0)Offset 228h.........................................691.8 reg_CLOCK_GATE (CLOCK_GATE)Offset 238h..........................................691.9 reg_REMAP_ADDR_LO (REMAP_ADDR_LO)Offset 240h..............................701.10 reg_REMAP_ADDR_HI (REMAP_ADDR_HI)Offset 244h...............................701.11 Capabilities (CAPABLITIES)Offset 2FCh ...................................................711.12 UART Byte Address Control (GEN_REGRW7)Offset 618h ............................72

1.3 UART DMA Controller Registers Summary .............................................................721.3.1 DMA Transfer Source Address Low (SAR_LO0)Offset 800h.........................731.3.2 DMA Transfer Source Address High (SAR_HI0)Offset 804h.........................741.3.3 DMA Transfer Destination Address Low (DAR_LO0)Offset 808h...................751.3.4 DMA Transfer Destination Address High (DAR_HI0)Offset 80Ch ..................761.3.5 Linked List Pointer Low (LLP_LO0)Offset 810h..........................................771.3.6 Linked List Pointer High (LLP_HI0)Offset 814h .........................................781.3.7 Control Register Low (CTL_LO0)Offset 818h ............................................781.3.8 Control Register High (CTL_HI0)Offset 81Ch............................................801.3.9 Source Status (SSTAT0)Offset 820h .......................................................811.3.10 Destination Status (DSTAT0)Offset 828h.................................................821.3.11 Source Status Address Low (SSTATAR_LO0)Offset 830h............................831.3.12 Source Status Address High (SSTATAR_HI0)Offset 834h ...........................831.3.13 Destination Status Address Low (DSTATAR_LO0)Offset 838h .....................841.3.14 Destination Status Address High (DSTATAR_HI0)Offset 83Ch.....................841.3.15 DMA Transfer Configuration Low (CFG_LO0)Offset 840h............................851.3.16 DMA Transfer Configuration High (CFG_HI0)Offset 844h............................871.3.17 Source Gather (SGR0)Offset 848h..........................................................881.3.18 Destination Scatter (DSR0)Offset 850h ...................................................891.3.19 Raw Interrupt Status (RawTfr)Offset AC0h ..............................................891.3.20 Raw Status for Block Interrupts (RawBlock)Offset AC8h ............................901.3.21 Raw Status for Source Transaction Interrupts (RawSrcTran)Offset AD0h......901.3.22 Raw Status for Destination Transaction Interrupts (RawDstTran)Offset

AD8h ....................................................................................................911.3.23 Raw Status for Error Interrupts (RawErr)Offset AE0h ................................911.3.24 Interrupt Status (StatusTfr)Offset AE8h ..................................................921.3.25 Status for Block Interrupts (StatusBlock)Offset AF0h ................................931.3.26 Status for Source Transaction Interrupts (StatusSrcTran)Offset AF8h..........931.3.27 Status for Destination Transaction Interrupts (StatusDstTran)Offset B00h ...931.3.28 Status for Error Interrupts (StatusErr)Offset B08h....................................941.3.29 Mask for Transfer Interrupts (MaskTfr)Offset B10h ...................................941.3.30 Mask for Block Interrupts (MaskBlock)Offset B18h....................................951.3.31 Mask for Source Transaction Interrupts (MaskSrcTran)Offset B20h .............961.3.32 Mask for Destination Transaction Interrupts (MaskDstTran)Offset B28h .......971.3.33 Mask for Error Interrupts (MaskErr)Offset B30h........................................971.3.34 Clear for Transfer Interrupts (ClearTfr)Offset B38h ...................................981.3.35 Clear for Block Interrupts (ClearBlock)Offset B40h....................................981.3.36 Clear for Source Transaction Interrupts (ClearSrcTran)Offset B48h .............991.3.37 Clear for Destination Transaction Interrupts (ClearDstTran)Offset B50h.......991.3.38 Clear for Error Interrupts (ClearErr)Offset B58h .....................................1001.3.39 Combined Status register (StatusInt)Offset B60h ...................................1001.3.40 DMA Configuration (DmaCfgReg)Offset B98h .........................................1011.3.41 DMA Channel Enable (ChEnReg)Offset BA0h ..........................................102

2 Generic SPI Interface (D30:F2).............................................................................1032.1 Generic SPI PCI Configuration Registers Summary ...............................................103

2.1.1 Device ID and Vendor ID Register (DEVVENDID)Offset 0h .......................103

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2.1.2 Status and Command (STATUSCOMMAND)Offset 4h............................... 1042.1.3 Revision ID and Class Code (REVCLASSCODE)Offset 8h .......................... 1052.1.4 Cache Line Latency Header and BIST (CLLATHEADERBIST)Offset Ch ........ 1052.1.5 Base Address Register (BAR)Offset 10h ................................................ 1062.1.6 Base Address Register High (BAR_HIGH)Offset 14h................................ 1072.1.7 Base Address Register 1 (BAR1)Offset 18h............................................ 1072.1.8 Base Address Register1 High (BAR1_HIGH)Offset 1Ch ............................ 1082.1.9 Subsystem Vendor and Subsystem ID (SUBSYSTEMID)Offset 2Ch............ 1092.1.10 Expansion ROM base address (EXPANSION_ROM_BASEADDR)Offset 30h .. 1092.1.11 Capabilities Pointer (CAPABILITYPTR)Offset 34h..................................... 1102.1.12 Interrupt Register (INTERRUPTREG)Offset 3Ch ...................................... 1102.1.13 PowerManagement Capability ID (POWERCAPID)Offset 80h..................... 1112.1.14 PME Control and Status (PMECTRLSTATUS)Offset 84h ............................ 111

2.2 Generic SPI (GSPI) Memory Mapped Registers Summary ...................................... 1122.2.1 SSP (GSPI) Control Register 0 (SSCR0)Offset 0h ................................... 1122.2.2 SSP (GSPI) Control Register 1 (SSCR1)Offset 4h ................................... 1142.2.3 SSP (GSPI) Status Register (SSSR)Offset 8h ......................................... 1152.2.4 SSP (GSPI) Data (SSDR)Offset 10h...................................................... 1162.2.5 SSP (GSPI) Time Out (SSTO)Offset 28h................................................ 1172.2.6 SPI Transmit FIFO (SITF)Offset 44h ..................................................... 1172.2.7 SPI Receive FIFO (SIRF)Offset 48h ...................................................... 118

2.3 Generic SPI (GSPI) Additional Registers Summary ............................................... 1192.3.1 CLOCKS (CLOCKS)Offset 200h ............................................................ 1192.3.2 RESETS (RESETS)Offset 204h ............................................................. 1202.3.3 ACTIVE LTR (ACTIVELTR_VALUE)Offset 210h ........................................ 1212.3.4 Idle LTR Value (IDLELTR_VALUE)Offset 214h ........................................ 1222.3.5 TX Bit Count (TX_BIT_COUNT)Offset 218h............................................ 1232.3.6 Rx Bit Count (RX_BIT_COUNT)Offset 21Ch............................................ 1232.3.7 reg_SSP_REG (SSP_REG)Offset 220h................................................... 1242.3.8 SPI CS CONTROL (SPI_CS_CONTROL)Offset 224h.................................. 1252.3.9 SW SCRATCH [3:0] (SW_SCRATCH)Offset 228h .................................... 1252.3.10 Clock Gate (CLOCK_GATE)Offset 238h ................................................. 1262.3.11 Remap Address Low (REMAP_ADDR_LO)Offset 240h .............................. 1262.3.12 Remap Address High (REMAP_ADDR_HI)Offset 244h .............................. 1272.3.13 Delay Rx Clock (DEL_RX_CLK)Offset 250h ............................................ 1272.3.14 Capabilities (CAPABLITIES)Offset 2FCh................................................. 128

2.4 Generic SPI (GSPI) DMA Controller Registers Summary ........................................ 1292.4.1 DMA Transfer Source Address Low (SAR_LO0)Offset 800h ...................... 1302.4.2 DMA Transfer Source Address High (SAR_HI0)Offset 804h ...................... 1312.4.3 DMA Transfer Destination Address Low (DAR_LO0)Offset 808h ................ 1322.4.4 DMA Transfer Destination Address High (DAR_HI0)Offset 80Ch................ 1332.4.5 Linked List Pointer Low (LLP_LO0)Offset 810h ....................................... 1342.4.6 Linked List Pointer High (LLP_HI0)Offset 814h....................................... 1352.4.7 Control Register Low (CTL_LO0)Offset 818h.......................................... 1352.4.8 Control Register High (CTL_HI0)Offset 81Ch ......................................... 1372.4.9 Source Status (SSTAT0)Offset 820h..................................................... 1382.4.10 Destination Status (DSTAT0)Offset 828h .............................................. 1392.4.11 Source Status Address Low (SSTATAR_LO0)Offset 830h ......................... 1392.4.12 Source Status Address High (SSTATAR_HI0)Offset 834h......................... 1402.4.13 Destination Status Address Low (DSTATAR_LO0)Offset 838h................... 1402.4.14 Destination Status Address High (DSTATAR_HI0)Offset 83Ch .................. 1412.4.15 DMA Transfer Configuration Low (CFG_LO0)Offset 840h ......................... 1422.4.16 DMA Transfer Configuration High (CFG_HI0)Offset 844h ......................... 1432.4.17 Source Gather (SGR0)Offset 848h ....................................................... 1442.4.18 Destination Scatter (DSR0)Offset 850h................................................. 145

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2.4.19 Raw Interrupt Status (RawTfr)Offset AC0h ............................................1452.4.20 Raw Status for Block Interrupts (RawBlock)Offset AC8h ..........................1462.4.21 Raw Status for Source Transaction Interrupts (RawSrcTran)Offset AD0h....1462.4.22 Raw Status for Destination Transaction Interrupts (RawDstTran)Offset

AD8h ..................................................................................................1472.4.23 Raw Status for Error Interrupts (RawErr)Offset AE0h ..............................1472.4.24 Interrupt Status (StatusTfr)Offset AE8h ................................................1482.4.25 Status for Block Interrupts (StatusBlock)Offset AF0h ..............................1482.4.26 Status for Source Transaction Interrupts (StatusSrcTran)Offset AF8h........1492.4.27 Status for Destination Transaction Interrupts (StatusDstTran)Offset B00h .1492.4.28 Status for Error Interrupts (StatusErr)Offset B08h..................................1502.4.29 Mask for Transfer Interrupts (MaskTfr)Offset B10h .................................1502.4.30 Mask for Block Interrupts (MaskBlock)Offset B18h..................................1512.4.31 Mask for Source Transaction Interrupts (MaskSrcTran)Offset B20h ...........1522.4.32 Mask for Destination Transaction Interrupts (MaskDstTran)Offset B28h .....1522.4.33 Mask for Error Interrupts (MaskErr)Offset B30h......................................1532.4.34 Clear for Transfer Interrupts (ClearTfr)Offset B38h .................................1532.4.35 Clear for Block Interrupts (ClearBlock)Offset B40h..................................1542.4.36 Clear for Source Transaction Interrupts (ClearSrcTran)Offset B48h ...........1542.4.37 Clear for Destination Transaction Interrupts (ClearDstTran)Offset B50h.....1552.4.38 Clear for Error Interrupts (ClearErr)Offset B58h .....................................1552.4.39 Combined Status register (StatusInt)Offset B60h ...................................1562.4.40 DMA Configuration (DmaCfgReg)Offset B98h .........................................1562.4.41 DMA Channel Enable (ChEnReg)Offset BA0h ..........................................157

3 EMMC Interface (D30:F4)......................................................................................1593.1 EMMC PCI Configuration Registers Summary .......................................................159

3.1.1 Device & Vendor ID (VID_DID)Offset 0h ...............................................1593.1.2 PCI Status & Command (STATUSCOMMAND)Offset 4h.............................1603.1.3 Rev ID & Class Code (REVCLASSCODE)Offset 8h....................................1613.1.4 Carche Line & Latency & Header Type & BIST (CLLATHEADERBIST)Offset

Ch ......................................................................................................1613.1.5 Base Address Low (BAR0)Offset 10h.....................................................1623.1.6 Base Address Register high (BAR0_HIGH)Offset 14h...............................1633.1.7 Base Address Register1 (BAR1)Offset 18h .............................................1633.1.8 (BAR1_HIGH)Offset 1Ch ....................................................................1643.1.9 Subsystem Vendor ID (SUBSYSTEMID)Offset 2Ch ..................................1653.1.10 (EXPANSION_ROM_BASEADDR)Offset 30h ............................................1653.1.11 Capabilities Pointer (CAPABILITYPTR)Offset 34h .....................................1663.1.12 (INTERRUPTREG)Offset 3Ch ................................................................1663.1.13 Power Management Capability ID Register (POWERCAPID)Offset 80h ........1673.1.14 Power Management Control and Status Register (PMECTRLSTATUS)Offset

84h.....................................................................................................1683.1.15 General Purpose PCI RW Register1 (GEN_REGRW1)Offset B0h .................1693.1.16 General Purpose PCI RW Register2 (GEN_REGRW2)Offset B4h .................1693.1.17 General Purpose PCI RW Register3 (GEN_REGRW3)Offset B8h .................1703.1.18 General Purpose PCI RW Register4 (GEN_REGRW4)Offset BCh .................1703.1.19 General Input Register (GEN_INPUT_REG)Offset C0h..............................171

3.2 EMMC Memory Mapped Registers Summary.........................................................1713.2.1 SDMA System Address Register/Argument2 Register (sdmasysaddr)Offset

0h ......................................................................................................1733.2.2 Block Size Register (blocksize)Offset 4h ................................................1733.2.3 Block Count Register (blockcount)Offset 6h ...........................................1743.2.4 Argument1 Register (argument1)Offset 8h ............................................1753.2.5 Transfer Mode Register (transfermode)Offset Ch ....................................175

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3.2.6 Command Register (command)Offset Eh............................................... 1763.2.7 Response Register (Reponse 0)Offset 10h............................................. 1773.2.8 Buffer Data Port Register (dataport)Offset 20h ...................................... 1783.2.9 Present State Register (presentstate)Offset 24h .................................... 1783.2.10 Host Control 1 Register (hostcontrol1)Offset 28h ................................... 1813.2.11 Power Control Register (powercontrol)Offset 29h ................................... 1823.2.12 Block Gap Control Register (blockgapcontrol)Offset 2Ah.......................... 1833.2.13 Wakeup Control Register (wakeupcontrol)Offset 2Bh .............................. 1843.2.14 Clock Control Register (clockcontrol)Offset 2Ch ..................................... 1853.2.15 Timeout Control Register (timeoutcontrol)Offset 2Eh .............................. 1863.2.16 Software Reset Register (softwarereset)Offset 2Fh................................. 1873.2.17 Normal Interrupt Status Register (normalintrsts)Offset 30h..................... 1883.2.18 Error Interrupt Status Register (errorintrsts)Offset 32h........................... 1903.2.19 Normal Interrupt Status Enable Register (normalintrstsena)Offset 34h...... 1913.2.20 Error Interrupt Status Enable Register (errorintrstsena)Offset 36h ........... 1933.2.21 Normal Interrupt Signal Enable Register (normalintrsigena)Offset 38h ...... 1943.2.22 Error Interrupt Signal Enable Register (errorintrsigena)Offset 3Ah............ 1953.2.23 Auto CMD12 Error Status Register (autocmderrsts)Offset 3Ch ................. 1963.2.24 Host Control2 Register (hostcontrol2)Offset 3Eh .................................... 1973.2.25 Capabilities Register (capabilities)Offset 40h ......................................... 1993.2.26 Maximum Current Capabilities Register (maxcurrentcap)Offset 48h .......... 2023.2.27 Force Event REGISTER for AUTO CMD Error Status

(ForceEventforAUTOCMDErrorStatus)Offset 50h..................................... 2033.2.28 Force Event Register for Error Interrupt Status

(forceeventforerrintsts)Offset 52h........................................................ 2043.2.29 ADMA Error Status Register (admaerrsts)Offset 54h............................... 2053.2.30 ADMA System Address Register0&1 (admasysaddr01)Offset 58h.............. 2063.2.31 ADMA System Address Register1 (admasysaddr2)Offset 5Ch................... 2073.2.32 ADMA System Address Register1 (admasysaddr3)Offset 5Eh ................... 2073.2.33 Preset Value Register for Initialization (Preset Value 0)Offset 60h ............ 2083.2.34 Preset Value Register for Default Speed (Preset Value 1)Offset 62h .......... 2093.2.35 Preset Value Register for High Speed (Preset Value 2)Offset 64h.............. 2093.2.36 Preset Value Register for SDR12 (Preset Value 3)Offset 66h .................... 2093.2.37 Preset Value Register for SDR25 (Preset Value 4)Offset 68h .................... 2093.2.38 Preset Value Register for SDR50 (Preset Value 5)Offset 6Ah.................... 2093.2.39 Preset Value Register for SDR104 (Preset Value 6)Offset 6Ch .................. 2093.2.40 Preset Value Register for DDR50 (Preset Value 7)Offset 6Eh.................... 2093.2.41 Boot Timeout Control Register (boottimeoutcnt)Offset 70h...................... 2103.2.42 Slot Interrupt Status Register (slotintrsts)Offset FCh .............................. 2103.2.43 Host Controller Version Register (hostcontrollerver)Offset FEh ................. 211

3.3 EMMC Additional Registers Summary ................................................................. 2113.3.1 Software LTR Value (SW_LTR_val)Offset 804h....................................... 2123.3.2 Auto LTR Value (Auto_LTR_val)Offset 808h........................................... 2133.3.3 Capabilities Bypass (Cap_byps)Offset 810h .......................................... 2143.3.4 Capabilities Bypass 1 (Cap_byps_reg1)Offset 814h ................................ 2143.3.5 Capabilities Bypass 2 (Cap_byps_reg2)Offset 818h ................................ 2153.3.6 (reg_D0i3)Offset 81Ch ...................................................................... 2163.3.7 (Tx_CMD_dly)Offset 820h.................................................................. 2173.3.8 (Tx_DATA_dly_1)Offset 824h ............................................................. 2183.3.9 (Tx_DATA_dly_2)Offset 828h ............................................................. 2183.3.10 (Rx_CMD_Data_dly_1)Offset 82Ch...................................................... 2193.3.11 (Rx_Strobe_Ctrl_Path)Offset 830h ...................................................... 2203.3.12 (Rx_CMD_Data_dly_2)Offset 834h...................................................... 2213.3.13 (Master_Dll)Offset 838h .................................................................... 2223.3.14 (Auto_tuning)Offset 840h .................................................................. 222

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4 SDXC (D30:F6).......................................................................................................2254.1 SDXC PCI Configuration Registers Summary........................................................225

4.1.1 Device & Vendor ID (DEVVENDID)Offset 0h...........................................2254.1.2 PCI Status & Command (STATUSCOMMAND)Offset 4h.............................2264.1.3 Rev ID & Class Code (REVCLASSCODE)Offset 8h....................................2274.1.4 Carche Line & Latency & Header Type & BIST (CLLATHEADERBIST)Offset

Ch ......................................................................................................2284.1.5 Base Address Low (BAR0)Offset 10h.....................................................2284.1.6 Base Address Register high (BAR0_HIGH)Offset 14h...............................2294.1.7 Base Address Register1 (BAR1)Offset 18h .............................................2304.1.8 (BAR1_HIGH)Offset 1Ch ....................................................................2304.1.9 Subsystem Vendor ID (SUBSYSTEMID)Offset 2Ch ..................................2314.1.10 (EXPANSION_ROM_BASEADDR)Offset 30h ............................................2314.1.11 Capabilities Pointer (CAPABILITYPTR)Offset 34h .....................................2324.1.12 (INTERRUPTREG)Offset 3Ch ................................................................2334.1.13 Power Management Capability ID Register (POWERCAPID)Offset 80h ........2334.1.14 Power Management Control and Status Register (PMECTRLSTATUS)Offset

84h.....................................................................................................2344.1.15 General Purpose PCI RW Register1 (GEN_REGRW1)Offset B0h .................2354.1.16 General Purpose PCI RW Register2 (GEN_REGRW2)Offset B4h .................2354.1.17 General Purpose PCI RW Register3 (GEN_REGRW3)Offset B8h .................2364.1.18 General Purpose PCI RW Register4 (GEN_REGRW4)Offset BCh .................2364.1.19 General Input Register (GEN_INPUT_REG)Offset C0h..............................237

4.2 SDXC Memory Mapped Registers Summary .........................................................2374.2.1 SDMA System Address Register/Argument2 Register (sdmasysaddr)Offset

0h ......................................................................................................2394.2.2 Block Size Register (blocksize)Offset 4h ................................................2394.2.3 Block Count Register (blockcount)Offset 6h ...........................................2404.2.4 Argument1 Register (argument1)Offset 8h ............................................2414.2.5 Transfer Mode Register (transfermode)Offset Ch ....................................2424.2.6 Command Register (command)Offset Eh ...............................................2424.2.7 Response Register (Reponse 0)Offset 10h .............................................2444.2.8 Buffer Data Port Register (dataport)Offset 20h.......................................2444.2.9 Present State Register (presentstate)Offset 24h.....................................2454.2.10 Host Control1 Register (hostcontrol1)Offset 28h.....................................2484.2.11 PowerControl Register (powercontrol)Offset 29h ....................................2494.2.12 Block Gap Control Register (blockgapcontrol)Offset 2Ah ..........................2504.2.13 Wakeup Control Register (wakeupcontrol)Offset 2Bh...............................2514.2.14 Clock Control Register (clockcontrol)Offset 2Ch......................................2524.2.15 Timeout Control Register (timeoutcontrol)Offset 2Eh ..............................2534.2.16 Software Reset Register (softwarereset)Offset 2Fh .................................2544.2.17 Normal Interrupt Status Register (normalintrsts)Offset 30h .....................2554.2.18 Error Interrupt Status (errorintrsts)Offset 32h .......................................2574.2.19 Normal Interrupt Status Enable Register (normalintrstsena)Offset 34h ......2584.2.20 Error Interrupt Status Enable Register (errorintrstsena)Offset 36h............2594.2.21 Normal Interrupt Signal Enable Register (normalintrsigena)Offset 38h ......2614.2.22 Error Interrupt Signal Enable Register (errorintrsigena)Offset 3Ah ............2624.2.23 Auto CMD12 Error Status Register (autocmderrsts)Offset 3Ch..................2634.2.24 Host Control 2 Register (hostcontrol2)Offset 3Eh....................................2644.2.25 Capabilities Register (capabilities)Offset 40h..........................................2664.2.26 Maximum Current Capabilities Register (maxcurrentcap)Offset 48h ..........2684.2.27 Force Event REGISTER for AUTO CMD Error Status

(ForceEventforAUTOCMDErrorStatus)Offset 50h .....................................2694.2.28 Force Event Register for Error Interrupt Status

(forceeventforerrintsts)Offset 52h ........................................................270

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4.2.29 ADMA Error Status Register (admaerrsts)Offset 54h............................... 2714.2.30 ADMA System Address Register0&1 (admasysaddr01)Offset 58h.............. 2724.2.31 ADMA System Address Register1 (admasysaddr2)Offset 5Ch................... 2734.2.32 ADMA System Address Register1 (admasysaddr3)Offset 5Eh ................... 2734.2.33 Preset Value Register for Initialization (Preset Value 0)Offset 60h ............ 2744.2.34 Preset Value Register for Default Speed (Preset Value 1)Offset 62h .......... 2754.2.35 Preset Value Register for High Speed (presetvalue2)Offset 64h................ 2754.2.36 Preset Value Register for SDR12 (presetvalue3)Offset 66h ...................... 2754.2.37 Preset Value Register for SDR25 (presetvalue4)Offset 68h ...................... 2754.2.38 Preset Value Register for SDR50 (presetvalue5)Offset 6Ah ...................... 2754.2.39 Preset Value Register for SDR104 (presetvalue6)Offset 6Ch .................... 2754.2.40 Preset Value Register for DDR50 (presetvalue7)Offset 6Eh ...................... 2754.2.41 Slot Interrupt Status Register (slotintrsts)Offset FCh .............................. 2754.2.42 Host Controller Version Register (hostcontrollerver)Offset FEh ................. 276

4.3 SDXC Additional Registers Summary.................................................................. 2774.3.1 Software LTR Value (SW_LTR_val)Offset 804h....................................... 2774.3.2 Auto LTR Value (Auto_LTR_val)Offset 808h........................................... 2784.3.3 (Cap_byps)Offset 810h ..................................................................... 2794.3.4 (Cap_byps_reg1)Offset 814h ............................................................. 2794.3.5 (Cap_byps_reg2)Offset 818h ............................................................. 2804.3.6 (reg_D0i3)Offset 81Ch ...................................................................... 2814.3.7 (Tx_CMD_dly)Offset 820h.................................................................. 2824.3.8 (Tx_DATA_dly_1)Offset 824h ............................................................. 2834.3.9 (Tx_DATA_dly_2)Offset 828h ............................................................. 2834.3.10 (Rx_CMD_Data_dly_1)Offset 82Ch...................................................... 2844.3.11 (Rx_Strobe_Ctrl_Path)Offset 830h ...................................................... 2854.3.12 (Rx_CMD_Data_dly_2)Offset 834h...................................................... 2864.3.13 (Master_Dll)Offset 838h .................................................................... 2864.3.14 (Auto_tuning)Offset 840h .................................................................. 287

5 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3) ..................................................... 2895.1 I2C PCI Configuration Registers Summary .......................................................... 289

5.1.1 Device ID and Vendor ID Register (DEVVENDID)Offset 0h....................... 2895.1.2 Status and Command (STATUSCOMMAND)Offset 4h............................... 2905.1.3 Revision ID and Class Code (REVCLASSCODE)Offset 8h .......................... 2915.1.4 Cache Line Latency Header and BIST (CLLATHEADERBIST)Offset Ch ........ 2925.1.5 Base Address Register (BAR)Offset 10h ................................................ 2925.1.6 Base Address Register High (BAR_HIGH)Offset 14h................................ 2935.1.7 Base Address Register 1 (BAR1)Offset 18h............................................ 2945.1.8 Base Address Register1 High (BAR1_HIGH)Offset 1Ch ............................ 2945.1.9 Subsystem Vendor and Subsystem ID (SUBSYSTEMID)Offset 2Ch............ 2955.1.10 Expansion ROM Base Address (EXPANSION_ROM_BASEADDR)Offset 30h .. 2955.1.11 Capabilities Pointer (CAPABILITYPTR)Offset 34h..................................... 2965.1.12 Interrupt Register (INTERRUPTREG)Offset 3Ch ...................................... 2965.1.13 PowerManagement Capability ID (POWERCAPID)Offset 80h..................... 2975.1.14 PME Control and Status (PMECTRLSTATUS)Offset 84h ............................ 2985.1.15 PCI Device Idle Capability Record (PCIDEVIDLE_CAP_RECORD)Offset 90h. 2985.1.16 SW LTR Update MMIO Location Register

(D0I3_CONTROL_SW_LTR_MMIO_REG)Offset 98h ................................. 2995.1.17 Device IDLE pointer register (DEVICE_IDLE_POINTER_REG)Offset 9Ch ..... 3005.1.18 Device PG Config (D0I3_MAX_POW_LAT_PG_CONFIG)Offset A0h............. 300

5.2 I2C Memory Mapped Registers Summary............................................................ 3015.2.1 I2C Control (IC_CON)Offset 0h............................................................ 3025.2.2 I2C Target Address (IC_TAR)Offset 4h ................................................. 3045.2.3 I2C High Speed Master Mode Code Address (IC_HS_MADDR)Offset Ch ..... 304

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5.2.4 I2C Rx/Tx Data Buffer and Command (IC_DATA_CMD)Offset 10h.............3055.2.5 Standard Speed I2C Clock SCL High Count (IC_SS_SCL_HCNT)Offset 14h .3065.2.6 Standard Speed I2C Clock SCL Low Count (IC_SS_SCL_LCNT)Offset 18h ..3075.2.7 Fast Speed I2C Clock SCL High Count (IC_FS_SCL_HCNT)Offset 1Ch ........3075.2.8 Fast Speed I2C Clock SCL Low Count (IC_FS_SCL_LCNT)Offset 20h..........3085.2.9 I2C Interrupt Status (IC_INTR_STAT)Offset 2Ch ....................................3095.2.10 I2C Interrupt Mask (IC_INTR_MASK)Offset 30h .....................................3105.2.11 I2C Raw Interrupt Status (IC_RAW_INTR_STAT)Offset 34h .....................3115.2.12 I2C Receive FIFO Threshold (IC_RX_TL)Offset 38h .................................3125.2.13 I2C Transmit FIFO Threshold (IC_TX_TL)Offset 3Ch................................3135.2.14 Clear Combined and Individual Interrupt (IC_CLR_INTR)Offset 40h ..........3135.2.15 Clear RX_UNDER Interrupt (IC_CLR_RX_UNDER)Offset 44h.....................3145.2.16 Clear RX_OVER Interrupt (IC_CLR_RX_OVER)Offset 48h .........................3145.2.17 Clear TX_OVER Interrupt (IC_CLR_TX_OVER)Offset 4Ch .........................3155.2.18 Clear RD_REQ Interrupt (IC_CLR_RD_REQ)Offset 50h ............................3155.2.19 Clear TX_ABRT Interrupt (IC_CLR_TX_ABRT)Offset 54h ..........................3165.2.20 Clear RX_DONE Interrupt (IC_CLR_RX_DONE)Offset 58h ........................3165.2.21 Clear ACTIVITY Interrupt (IC_CLR_ACTIVITY)Offset 5Ch .........................3175.2.22 Clear STOP_DET Interrupt (IC_CLR_STOP_DET)Offset 60h ......................3175.2.23 Clear START_DET Interrupt (IC_CLR_START_DET)Offset 64h ...................3185.2.24 Clear GEN_CALL Interrupt (IC_CLR_GEN_CALL)Offset 68h.......................3185.2.25 I2C Enable (IC_ENABLE)Offset 6Ch ......................................................3195.2.26 I2C Status (IC_STATUS)Offset 70h.......................................................3205.2.27 I2C Transmit FIFO Level (IC_TXFLR)Offset 74h ......................................3215.2.28 I2C Receive FIFO Level (IC_RXFLR)Offset 78h .......................................3215.2.29 I2C SDA Hold Time Length (IC_SDA_HOLD)Offset 7Ch............................3225.2.30 I2C Transmit Abort Source (IC_TX_ABRT_SOURCE)Offset 80h .................3225.2.31 DMA Control (IC_DMA_CR)Offset 88h ...................................................3245.2.32 DMA Transmit Data Level (IC_DMA_TDLR)Offset 8Ch..............................3255.2.33 I2C Receive Data Level (IC_DMA_RDLR)Offset 90h.................................3255.2.34 I2C ACK General Call (IC_ACK_GENERAL_CALL)Offset 98h ......................3265.2.35 I2C Enable Status (IC_ENABLE_STATUS)Offset 9Ch................................3265.2.36 I2C SS and FS Spike Suppression Limit (IC_FS_SPKLEN)Offset A0h ..........3275.2.37 Clear RESTART_DET Interrupt (IC_CLR_RESTRART_DET)Offset A8h..........328

5.3 I2C Additional Registers Summary .....................................................................3285.3.1 Soft Reset (RESETS)Offset 204h ..........................................................3295.3.2 Active LTR (ACTIVELTR_VALUE)Offset 210h...........................................3295.3.3 Idle LTR (IDLELTR_VALUE)Offset 214h..................................................3305.3.4 TX Ack Count (TX_ACK_COUNT)Offset 218h ..........................................3315.3.5 RX ACK Count (RX_BYTE_COUNT)Offset 21Ch .......................................3325.3.6 Interrupt Status for Tx Complete (TX_COMPLETE_INTR_STAT)Offset 220h 3335.3.7 Tx Complete Interrupt Clear (TX_COMPLETE_INTR_CLR)Offset 224h.........3335.3.8 SW Scratch Register 0 (SW_SCRATCH_0)Offset 228h .............................3345.3.9 SW Scratch Register 1 (SW_SCRATCH_1)Offset 22Ch .............................3345.3.10 SW Scratch Register 2 (SW_SCRATCH_2)Offset 230h .............................3355.3.11 SW Scratch Register 3 (SW_SCRATCH_3)Offset 234h .............................3355.3.12 Clock Gate (CLOCK_GATE)Offset 238h..................................................3365.3.13 Remap Address Low (REMAP_ADDR_LO)Offset 240h...............................3365.3.14 Remap Address High (REMAP_ADDR_HI)Offset 244h ..............................3375.3.15 Capabilities (CAPABLITIES)Offset 2FCh .................................................337

5.4 I2C DMA Controller Registers Summary ..............................................................3385.4.1 DMA Transfer Source Address Low (SAR_LO0)Offset 800h.......................3395.4.2 DMA Transfer Source Address High (SAR_HI0)Offset 804h.......................3405.4.3 DMA Transfer Destination Address Low (DAR_LO0)Offset 808h.................3415.4.4 DMA Transfer Destination Address High (DAR_HI0)Offset 80Ch ................342

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5.4.5 Linked List Pointer Low (LLP_LO0)Offset 810h ....................................... 3435.4.6 Linked List Pointer High (LLP_HI0)Offset 814h....................................... 3445.4.7 Control Register Low (CTL_LO0)Offset 818h.......................................... 3445.4.8 Control Register High (CTL_HI0)Offset 81Ch ......................................... 3465.4.9 Source Status (SSTAT0)Offset 820h..................................................... 3475.4.10 Destination Status (DSTAT0)Offset 828h .............................................. 3485.4.11 Source Status Address Low (SSTATAR_LO0)Offset 830h ......................... 3485.4.12 Source Status Address High (SSTATAR_HI0)Offset 834h......................... 3495.4.13 Destination Status Address Low (DSTATAR_LO0)Offset 838h................... 3505.4.14 Destination Status Address High (DSTATAR_HI0)Offset 83Ch .................. 3505.4.15 DMA Transfer Configuration Low (CFG_LO0)Offset 840h ......................... 3515.4.16 DMA Transfer Configuration High (CFG_HI0)Offset 844h ......................... 3525.4.17 Source Gather (SGR0)Offset 848h ....................................................... 3535.4.18 Destination Scatter (DSR0)Offset 850h................................................. 3545.4.19 Raw Interrupt Status (RawTfr)Offset AC0h............................................ 3555.4.20 Raw Status for Block Interrupts (RawBlock)Offset AC8h.......................... 3555.4.21 Raw Status for Source Transaction Interrupts (RawSrcTran)Offset AD0h ... 3565.4.22 Raw Status for Destination Transaction Interrupts (RawDstTran)Offset

AD8h.................................................................................................. 3565.4.23 Raw Status for Error Interrupts (RawErr)Offset AE0h.............................. 3575.4.24 Interrupt Status (StatusTfr)Offset AE8h................................................ 3585.4.25 Status for Block Interrupts (StatusBlock)Offset AF0h.............................. 3585.4.26 Status for Source Transaction Interrupts (StatusSrcTran)Offset AF8h ....... 3595.4.27 Status for Destination Transaction Interrupts (StatusDstTran)Offset B00h. 3595.4.28 Status for Error Interrupts (StatusErr)Offset B08h ................................. 3605.4.29 Mask for Transfer Interrupts (MaskTfr)Offset B10h................................. 3605.4.30 Mask for Block Interrupts (MaskBlock)Offset B18h ................................. 3615.4.31 Mask for Source Transaction Interrupts (MaskSrcTran)Offset B20h........... 3625.4.32 Mask for Destination Transaction Interrupts (MaskDstTran)Offset B28h..... 3625.4.33 Mask for Error Interrupts (MaskErr)Offset B30h ..................................... 3635.4.34 Clear for Transfer Interrupts (ClearTfr)Offset B38h................................. 3645.4.35 Clear for Block Interrupts (ClearBlock)Offset B40h ................................. 3645.4.36 Clear for Source Transaction Interrupts (ClearSrcTran)Offset B48h........... 3655.4.37 Clear for Destination Transaction Interrupts (ClearDstTran)Offset B50h .... 3655.4.38 Clear for Error Interrupts (ClearErr)Offset B58h..................................... 3655.4.39 Combined Status register (StatusInt)Offset B60h................................... 3665.4.40 DMA Configuration (DmaCfgReg)Offset B98h......................................... 3675.4.41 DMA Channel Enable (ChEnReg)Offset BA0h.......................................... 367

6 GPIO for SKL PCH-H .............................................................................................. 3696.1 GPIO Community 0 Registers Summary.............................................................. 369

6.1.1 Family Base Address (FAMBAR)Offset 8h .............................................. 3746.1.2 Pad Base Address (PADBAR)Offset Ch .................................................. 3756.1.3 Miscellaneous Configuration (MISCCFG)Offset 10h ................................. 3756.1.4 Pad Ownership (PAD_OWN_GPP_A_0)Offset 20h ................................... 3766.1.5 Pad Ownership (PAD_OWN_GPP_A_1)Offset 24h ................................... 3786.1.6 Pad Ownership (PAD_OWN_GPP_A_2)Offset 28h ................................... 3786.1.7 Pad Ownership (PAD_OWN_GPP_B_0)Offset 30h ................................... 3786.1.8 Pad Ownership (PAD_OWN_GPP_B_1)Offset 34h ................................... 3786.1.9 Pad Ownership (PAD_OWN_GPP_B_2)Offset 38h ................................... 3786.1.10 Pad Configuration Lock (PADCFGLOCK_GPP_A)Offset A0h ....................... 3786.1.11 Pad Configuration Lock (PADCFGLOCKTX_GPP_A)Offset A4h.................... 3806.1.12 Pad Configuration Lock (PADCFGLOCK_GPP_B)Offset A8h ....................... 3826.1.13 Pad Configuration Lock (PADCFGLOCKTX_GPP_B)Offset ACh ................... 3826.1.14 Host Software Pad Ownership (HOSTSW_OWN_GPP_A)Offset D0h ........... 382

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6.1.15 Host Software Pad Ownership (HOSTSW_OWN_GPP_B)Offset D4h............3836.1.16 GPI Interrupt Status (GPI_IS_GPP_A)Offset 100h...................................3836.1.17 GPI Interrupt Status (GPI_IS_GPP_B)Offset 104h...................................3856.1.18 GPI Interrupt Enable (GPI_IE_GPP_A)Offset 120h ..................................3856.1.19 GPI Interrupt Enable (GPI_IE_GPP_B)Offset 124h ..................................3876.1.20 GPI General Purpose Events Status (GPI_GPE_STS_GPP_A)Offset 140h ....3876.1.21 GPI General Purpose Events Status (GPI_GPE_STS_GPP_B)Offset 144h ....3896.1.22 GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A)Offset 160h......3896.1.23 GPI General Purpose Events Enable (GPI_GPE_EN_GPP_B)Offset 164h......3916.1.24 SMI Status (GPI_SMI_STS_GPP_B)Offset 184h ......................................3916.1.25 SMI Enable (GPI_SMI_EN_GPP_B)Offset 1A4h .......................................3926.1.26 NMI Status (GPI_NMI_STS_GPP_B)Offset 1C4h......................................3936.1.27 NMI Enable (GPI_NMI_EN_GPP_B)Offset 1E4h .......................................3946.1.28 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_0)Offset 400h................3956.1.29 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_0)Offset 404h................3976.1.30 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_1)Offset 408h................3986.1.31 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_1)Offset 40Ch ...............3986.1.32 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_2)Offset 410h................3986.1.33 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_2)Offset 414h................3986.1.34 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_3)Offset 418h................3996.1.35 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_3)Offset 41Ch ...............3996.1.36 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_4)Offset 420h................3996.1.37 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_4)Offset 424h................3996.1.38 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_5)Offset 428h................3996.1.39 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_5)Offset 42Ch ...............3996.1.40 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_6)Offset 430h................3996.1.41 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_6)Offset 434h................3996.1.42 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_7)Offset 438h................4006.1.43 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_7)Offset 43Ch ...............4006.1.44 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_8)Offset 440h................4006.1.45 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_8)Offset 444h................4006.1.46 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_9)Offset 448h................4006.1.47 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_9)Offset 44Ch ...............4006.1.48 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_10)Offset 450h..............4006.1.49 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_10)Offset 454h..............4006.1.50 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_11)Offset 458h..............4016.1.51 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_11)Offset 45Ch..............4016.1.52 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_12)Offset 460h..............4016.1.53 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_12)Offset 464h..............4016.1.54 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_13)Offset 468h..............4016.1.55 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_13)Offset 46Ch..............4016.1.56 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_14)Offset 470h..............4016.1.57 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_14)Offset 474h..............4016.1.58 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_15)Offset 478h..............4026.1.59 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_15)Offset 47Ch..............4026.1.60 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_16)Offset 480h..............4026.1.61 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_16)Offset 484h..............4026.1.62 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_17)Offset 488h..............4026.1.63 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_17)Offset 48Ch..............4026.1.64 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_18)Offset 490h..............4026.1.65 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_18)Offset 494h..............4026.1.66 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_19)Offset 498h..............4036.1.67 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_19)Offset 49Ch..............4036.1.68 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_20)Offset 4A0h..............4036.1.69 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_20)Offset 4A4h..............403

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6.1.70 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_21)Offset 4A8h ............. 4036.1.71 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_21)Offset 4ACh ............. 4036.1.72 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_22)Offset 4B0h ............. 4036.1.73 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_22)Offset 4B4h ............. 4036.1.74 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_23)Offset 4B8h ............. 4046.1.75 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_23)Offset 4BCh ............. 4046.1.76 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_0)Offset 4C0h ............... 4046.1.77 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_0)Offset 4C4h ............... 4046.1.78 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_1)Offset 4C8h ............... 4046.1.79 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_1)Offset 4CCh............... 4046.1.80 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_2)Offset 4D0h............... 4046.1.81 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_2)Offset 4D4h............... 4046.1.82 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_3)Offset 4D8h............... 4056.1.83 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_3)Offset 4DCh............... 4056.1.84 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_4)Offset 4E0h ............... 4056.1.85 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_4)Offset 4E4h ............... 4056.1.86 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_5)Offset 4E8h ............... 4056.1.87 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_5)Offset 4ECh ............... 4056.1.88 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_6)Offset 4F0h ............... 4056.1.89 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_6)Offset 4F4h ............... 4056.1.90 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_7)Offset 4F8h ............... 4066.1.91 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_7)Offset 4FCh ............... 4066.1.92 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_8)Offset 500h ............... 4066.1.93 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_8)Offset 504h ............... 4066.1.94 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_9)Offset 508h ............... 4066.1.95 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_9)Offset 50Ch ............... 4066.1.96 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_10)Offset 510h ............. 4066.1.97 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_10)Offset 514h ............. 4066.1.98 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_11)Offset 518h ............. 4076.1.99 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_11)Offset 51Ch ............. 4076.1.100Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_12)Offset 520h ............. 4076.1.101Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_12)Offset 524h ............. 4076.1.102Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_13)Offset 528h ............. 4076.1.103Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_13)Offset 52Ch ............. 4076.1.104Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_14)Offset 530h ............. 4076.1.105Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_14)Offset 534h ............. 4076.1.106Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_15)Offset 538h ............. 4086.1.107Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_15)Offset 53Ch ............. 4086.1.108Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_16)Offset 540h ............. 4086.1.109Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_16)Offset 544h ............. 4086.1.110Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_17)Offset 548h ............. 4086.1.111Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_17)Offset 54Ch ............. 4086.1.112Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_18)Offset 550h ............. 4086.1.113Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_18)Offset 554h ............. 4086.1.114Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_19)Offset 558h ............. 4096.1.115Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_19)Offset 55Ch ............. 4096.1.116Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_20)Offset 560h ............. 4096.1.117Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_20)Offset 564h ............. 4096.1.118Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_21)Offset 568h ............. 4096.1.119Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_21)Offset 56Ch ............. 4096.1.120Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_22)Offset 570h ............. 4096.1.121Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_22)Offset 574h ............. 4096.1.122Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_23)Offset 578h ............. 4106.1.123Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_23)Offset 57Ch ............. 410

6.2 GPIO Community 1 Registers Summary.............................................................. 410

14 332219-002

6.2.1 Family Base Address (FAMBAR)Offset 8h...............................................4196.2.2 Pad Base Address (PADBAR)Offset Ch...................................................4206.2.3 Miscellaneous Configuration (MISCCFG)Offset 10h..................................4206.2.4 Pad Ownership (PAD_OWN_GPP_C_0)Offset 20h....................................4216.2.5 Pad Ownership (PAD_OWN_GPP_C_1)Offset 24h....................................4236.2.6 Pad Ownership (PAD_OWN_GPP_C_2)Offset 28h....................................4236.2.7 Pad Ownership (PAD_OWN_GPP_D_0)Offset 2Ch ...................................4236.2.8 Pad Ownership (PAD_OWN_GPP_D_1)Offset 30h....................................4236.2.9 Pad Ownership (PAD_OWN_GPP_D_2)Offset 34h....................................4236.2.10 Pad Ownership (PAD_OWN_GPP_E_0)Offset 38h ....................................4236.2.11 Pad Ownership (PAD_OWN_GPP_E_1)Offset 3Ch....................................4236.2.12 Pad Ownership (PAD_OWN_GPP_F_0)Offset 40h ....................................4236.2.13 Pad Ownership (PAD_OWN_GPP_F_1)Offset 44h ....................................4236.2.14 Pad Ownership (PAD_OWN_GPP_F_2)Offset 48h ....................................4236.2.15 Pad Ownership (PAD_OWN_GPP_G_0)Offset 4Ch ...................................4236.2.16 Pad Ownership (PAD_OWN_GPP_G_1)Offset 50h....................................4236.2.17 Pad Ownership (PAD_OWN_GPP_G_2)Offset 54h....................................4236.2.18 Pad Ownership (PAD_OWN_GPP_H_0)Offset 58h....................................4246.2.19 Pad Ownership (PAD_OWN_GPP_H_1)Offset 5Ch....................................4246.2.20 Pad Ownership (PAD_OWN_GPP_H_2)Offset 60h....................................4246.2.21 Pad Configuration Lock (PADCFGLOCK_GPP_C_0)Offset 90h ....................4246.2.22 Pad Configuration Lock (PADCFGLOCKTX_GPP_C_0)Offset 94h.................4256.2.23 Pad Configuration Lock (PADCFGLOCK_GPP_D_0)Offset 98h ....................4276.2.24 Pad Configuration Lock (PADCFGLOCKTX_GPP_D_0)Offset 9Ch ................4276.2.25 Pad Configuration Lock (PADCFGLOCK_GPP_E_0)Offset A0h ....................4276.2.26 Pad Configuration Lock (PADCFGLOCKTX_GPP_E_0)Offset A4h.................4276.2.27 Pad Configuration Lock (PADCFGLOCK_GPP_F_0)Offset A8h ....................4286.2.28 Pad Configuration Lock (PADCFGLOCKTX_GPP_F_0)Offset ACh.................4286.2.29 Pad Configuration Lock (PADCFGLOCK_GPP_G_0)Offset B0h....................4286.2.30 Pad Configuration Lock (PADCFGLOCKTX_GPP_G_0)Offset B4h ................4286.2.31 Pad Configuration Lock (PADCFGLOCK_GPP_H_0)Offset B8h ....................4286.2.32 Pad Configuration Lock (PADCFGLOCKTX_GPP_H_0)Offset BCh ................4286.2.33 Host Software Pad Ownership (HOSTSW_OWN_GPP_C_0)Offset D0h ........4286.2.34 Host Software Pad Ownership (HOSTSW_OWN_GPP_D_0)Offset D4h ........4306.2.35 Host Software Pad Ownership (HOSTSW_OWN_GPP_E_0)Offset D8h ........4306.2.36 Host Software Pad Ownership (HOSTSW_OWN_GPP_F_0)Offset DCh ........4306.2.37 Host Software Pad Ownership (HOSTSW_OWN_GPP_G_0)Offset E0h ........4306.2.38 Host Software Pad Ownership (HOSTSW_OWN_GPP_H_0)Offset E4h ........4306.2.39 GPI Interrupt Status (GPI_IS_GPP_C_0)Offset 100h ...............................4316.2.40 GPI Interrupt Status (GPI_IS_GPP_D_0)Offset 104h...............................4326.2.41 GPI Interrupt Status (GPI_IS_GPP_E_0)Offset 108h ...............................4326.2.42 GPI Interrupt Status (GPI_IS_GPP_F_0)Offset 10Ch ...............................4326.2.43 GPI Interrupt Status (GPI_IS_GPP_G_0)Offset 110h...............................4326.2.44 GPI Interrupt Status (GPI_IS_GPP_H_0)Offset 114h...............................4336.2.45 GPI Interrupt Enable (GPI_IE_GPP_C_0)Offset 120h...............................4336.2.46 GPI Interrupt Enable (GPI_IE_GPP_D_0)Offset 124h...............................4346.2.47 GPI Interrupt Enable (GPI_IE_GPP_E_0)Offset 128h ...............................4346.2.48 GPI Interrupt Enable (GPI_IE_GPP_F_0)Offset 12Ch ...............................4346.2.49 GPI Interrupt Enable (GPI_IE_GPP_G_0)Offset 130h...............................4356.2.50 GPI Interrupt Enable (GPI_IE_GPP_H_0)Offset 134h...............................4356.2.51 GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_0)Offset 140h .4356.2.52 GPI General Purpose Events Status (GPI_GPE_STS_GPP_D_0)Offset 144h.4366.2.53 GPI General Purpose Events Status (GPI_GPE_STS_GPP_E_0)Offset 148h .4376.2.54 GPI General Purpose Events Status (GPI_GPE_STS_GPP_F_0)Offset 14Ch .4376.2.55 GPI General Purpose Events Status (GPI_GPE_STS_GPP_G_0)Offset 150h.437

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6.2.56 GPI General Purpose Events Status (GPI_GPE_STS_GPP_H_0)Offset 154h 4376.2.57 GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_0)Offset 160h.. 4376.2.58 GPI General Purpose Events Enable (GPI_GPE_EN_GPP_D_0)Offset 164h.. 4396.2.59 GPI General Purpose Events Enable (GPI_GPE_EN_GPP_E_0)Offset 168h .. 4396.2.60 GPI General Purpose Events Enable (GPI_GPE_EN_GPP_F_0)Offset 16Ch .. 4396.2.61 GPI General Purpose Events Enable (GPI_GPE_EN_GPP_G_0)Offset 170h.. 4396.2.62 GPI General Purpose Events Enable (GPI_GPE_EN_GPP_H_0)Offset 174h.. 4396.2.63 SMI Status (GPI_SMI_STS_GPP_C_0)Offset 180h .................................. 4396.2.64 SMI Status (GPI_SMI_STS_GPP_D_0)Offset 184h .................................. 4406.2.65 SMI Status (GPI_SMI_STS_GPP_E_0)Offset 188h .................................. 4416.2.66 SMI Enable (GPI_SMI_EN_GPP_C_0)Offset 1A0h ................................... 4426.2.67 SMI Enable (GPI_SMI_EN_GPP_D_0)Offset 1A4h ................................... 4436.2.68 SMI Enable (GPI_SMI_EN_GPP_E_0)Offset 1A8h ................................... 4446.2.69 NMI Status (GPI_NMI_STS_GPP_C_0)Offset 1C0h.................................. 4456.2.70 NMI Status (GPI_NMI_STS_GPP_D_0)Offset 1C4h ................................. 4466.2.71 NMI Status (GPI_NMI_STS_GPP_E_0)Offset 1C8h.................................. 4476.2.72 NMI Enable (GPI_NMI_EN_GPP_C_0)Offset 1E0h ................................... 4486.2.73 NMI Enable (GPI_NMI_EN_GPP_D_0)Offset 1E4h................................... 4496.2.74 NMI Enable (GPI_NMI_EN_GPP_E_0)Offset 1E8h ................................... 4506.2.75 PWM Control (PWMC)Offset 204h......................................................... 4516.2.76 GPIO Serial Blink Enable (GP_SER_BLINK)Offset 20Ch............................ 4516.2.77 GPIO Serial Blink Command/Status (GP_SER_CMDSTS)Offset 210h.......... 4526.2.78 GPIO Serial Blink Data (GP_SER_DATA)Offset 214h ............................... 4536.2.79 GSX Controller Capabilities (GSX_CAP)Offset 21Ch ................................ 4536.2.80 GSX Channel-0 Capabilities DW0 (GSX_C0CAP_DW0)Offset 220h............. 4546.2.81 GSX Channel-0 Capabilities DW1 (GSX_C0CAP_DW1)Offset 224h............. 4556.2.82 GSX Channel-0 GP Input Level DW0 (GSX_C0GPILVL_DW0)Offset 228h.... 4556.2.83 GSX Channel-0 GP Input Level DW1 (GSX_C0GPILVL_DW1)Offset 22Ch ... 4566.2.84 GSX Channel-0 GP Output Level DW0 (GSX_C0GPOLVL_DW0)Offset 230h 4566.2.85 GSX Channel-0 GP Output Level DW1 (GSX_C0GPOLVL_DW1)Offset 234h 4576.2.86 GSX Channel-0 Command (GSX_C0CMD)Offset 238h ............................. 4576.2.87 GSX Channel-0 Test Mode (GSX_C0TM)Offset 23Ch ............................... 4586.2.88 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_0)Offset 400h ............... 4596.2.89 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_0)Offset 404h ............... 4616.2.90 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_1)Offset 408h ............... 4626.2.91 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_1)Offset 40Ch ............... 4626.2.92 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_2)Offset 410h ............... 4626.2.93 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_2)Offset 414h ............... 4636.2.94 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_3)Offset 418h ............... 4636.2.95 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_3)Offset 41Ch ............... 4636.2.96 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_4)Offset 420h ............... 4636.2.97 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_4)Offset 424h ............... 4636.2.98 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_5)Offset 428h ............... 4636.2.99 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_5)Offset 42Ch ............... 4636.2.100Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_6)Offset 430h ............... 4636.2.101Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_6)Offset 434h ............... 4636.2.102Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_7)Offset 438h ............... 4646.2.103Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_7)Offset 43Ch ............... 4646.2.104Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_8)Offset 440h ............... 4646.2.105Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_8)Offset 444h ............... 4646.2.106Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_9)Offset 448h ............... 4646.2.107Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_9)Offset 44Ch ............... 4646.2.108Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_10)Offset 450h ............. 4646.2.109Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_10)Offset 454h ............. 4646.2.110Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_11)Offset 458h ............. 464

16 332219-002

6.2.111Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_11)Offset 45Ch..............4656.2.112Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_12)Offset 460h..............4656.2.113Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_12)Offset 464h..............4656.2.114Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_13)Offset 468h..............4656.2.115Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_13)Offset 46Ch..............4656.2.116Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_14)Offset 470h..............4656.2.117Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_14)Offset 474h..............4656.2.118Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_15)Offset 478h..............4656.2.119Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_15)Offset 47Ch..............4656.2.120Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_16)Offset 480h..............4666.2.121Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_16)Offset 484h..............4666.2.122Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_17)Offset 488h..............4676.2.123Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_17)Offset 48Ch..............4676.2.124Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_18)Offset 490h..............4676.2.125Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_18)Offset 494h..............4676.2.126Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_19)Offset 498h..............4676.2.127Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_19)Offset 49Ch..............4686.2.128Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_20)Offset 4A0h..............4686.2.129Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_20)Offset 4A4h..............4686.2.130Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_21)Offset 4A8h..............4686.2.131Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_21)Offset 4ACh..............4686.2.132Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_22)Offset 4B0h..............4686.2.133Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_22)Offset 4B4h..............4686.2.134Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_23)Offset 4B8h..............4686.2.135Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_23)Offset 4BCh..............4686.2.136Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_0)Offset 4C0h ...............4696.2.137Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_0)Offset 4C4h ...............4696.2.138Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_1)Offset 4C8h ...............4696.2.139Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_1)Offset 4CCh ...............4696.2.140Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_2)Offset 4D0h ...............4696.2.141Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_2)Offset 4D4h ...............4696.2.142Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_3)Offset 4D8h ...............4696.2.143Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_3)Offset 4DCh...............4696.2.144Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_4)Offset 4E0h ...............4696.2.145Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_4)Offset 4E4h ...............4706.2.146Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_5)Offset 4E8h ...............4706.2.147Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_5)Offset 4ECh ...............4706.2.148Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_6)Offset 4F0h................4706.2.149Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_6)Offset 4F4h................4706.2.150Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_7)Offset 4F8h................4706.2.151Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_7)Offset 4FCh ...............4706.2.152Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_8)Offset 500h ...............4706.2.153Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_8)Offset 504h ...............4706.2.154Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_9)Offset 508h ...............4716.2.155Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_9)Offset 50Ch ...............4716.2.156Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_10)Offset 510h..............4716.2.157Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_10)Offset 514h..............4716.2.158Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_11)Offset 518h..............4716.2.159Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_11)Offset 51Ch .............4716.2.160Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_12)Offset 520h..............4716.2.161Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_12)Offset 524h..............4716.2.162Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_13)Offset 528h..............4716.2.163Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_13)Offset 52Ch .............4726.2.164Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_14)Offset 530h..............4726.2.165Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_14)Offset 534h..............472

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6.2.166Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_15)Offset 538h ............. 4726.2.167Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_15)Offset 53Ch ............. 4726.2.168Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_16)Offset 540h ............. 4726.2.169Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_16)Offset 544h ............. 4726.2.170Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_17)Offset 548h ............. 4726.2.171Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_17)Offset 54Ch ............. 4726.2.172Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_18)Offset 550h ............. 4736.2.173Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_18)Offset 554h ............. 4736.2.174Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_19)Offset 558h ............. 4736.2.175Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_19)Offset 55Ch ............. 4736.2.176Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_20)Offset 560h ............. 4736.2.177Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_20)Offset 564h ............. 4736.2.178Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_21)Offset 568h ............. 4736.2.179Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_21)Offset 56Ch ............. 4736.2.180Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_22)Offset 570h ............. 4736.2.181Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_22)Offset 574h ............. 4746.2.182Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_23)Offset 578h ............. 4746.2.183Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_23)Offset 57Ch ............. 4746.2.184Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_0)Offset 580h ............... 4746.2.185Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_0)Offset 584h ............... 4746.2.186Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_1)Offset 588h ............... 4746.2.187Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_1)Offset 58Ch ............... 4746.2.188Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_2)Offset 590h ............... 4746.2.189Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_2)Offset 594h ............... 4746.2.190Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_3)Offset 598h ............... 4756.2.191Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_3)Offset 59Ch ............... 4756.2.192Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_4)Offset 5A0h ............... 4756.2.193Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_4)Offset 5A4h ............... 4756.2.194Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_5)Offset 5A8h ............... 4756.2.195Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_5)Offset 5ACh ............... 4756.2.196Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_6)Offset 5B0h ............... 4756.2.197Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_6)Offset 5B4h ............... 4756.2.198Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_7)Offset 5B8h ............... 4756.2.199Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_7)Offset 5BCh ............... 4766.2.200Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_8)Offset 5C0h ............... 4766.2.201Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_8)Offset 5C4h ............... 4766.2.202Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_9)Offset 5C8h ............... 4766.2.203Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_9)Offset 5CCh ............... 4766.2.204Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_10)Offset 5D0h ............. 4766.2.205Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_10)Offset 5D4h ............. 4766.2.206Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_11)Offset 5D8h ............. 4766.2.207Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_11)Offset 5DCh ............. 4766.2.208Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_12)Offset 5E0h.............. 4776.2.209Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_12)Offset 5E4h.............. 4776.2.210Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_0)Offset 5E8h ............... 4776.2.211Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_0)Offset 5ECh ............... 4776.2.212Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_1)Offset 5F0h................ 4776.2.213Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_1)Offset 5F4h................ 4776.2.214Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_2)Offset 5F8h................ 4776.2.215Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_2)Offset 5FCh ............... 4776.2.216Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_3)Offset 600h ............... 4776.2.217Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_3)Offset 604h ............... 4786.2.218Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_4)Offset 608h ............... 4786.2.219Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_4)Offset 60Ch ............... 4786.2.220Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_5)Offset 610h ............... 478

18 332219-002

6.2.221Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_5)Offset 614h................4786.2.222Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_6)Offset 618h................4786.2.223Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_6)Offset 61Ch................4786.2.224Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_7)Offset 620h................4786.2.225Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_7)Offset 624h................4786.2.226Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_8)Offset 628h................4796.2.227Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_8)Offset 62Ch................4796.2.228Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_9)Offset 630h................4796.2.229Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_9)Offset 634h................4796.2.230Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_10)Offset 638h ..............4796.2.231Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_10)Offset 63Ch ..............4796.2.232Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_11)Offset 640h ..............4796.2.233Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_11)Offset 644h ..............4796.2.234Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_12)Offset 648h ..............4796.2.235Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_12)Offset 64Ch ..............4806.2.236Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_13)Offset 650h ..............4806.2.237Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_13)Offset 654h ..............4806.2.238Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_14)Offset 658h ..............4806.2.239Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_14)Offset 65Ch ..............4806.2.240Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_15)Offset 660h ..............4806.2.241Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_15)Offset 664h ..............4806.2.242Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_16)Offset 668h ..............4806.2.243Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_16)Offset 66Ch ..............4806.2.244Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_17)Offset 670h ..............4816.2.245Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_17)Offset 674h ..............4816.2.246Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_18)Offset 678h ..............4816.2.247Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_18)Offset 67Ch ..............4816.2.248Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_19)Offset 680h ..............4816.2.249Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_19)Offset 684h ..............4816.2.250Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_20)Offset 688h ..............4816.2.251Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_20)Offset 68Ch ..............4816.2.252Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_21)Offset 690h ..............4816.2.253Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_21)Offset 694h ..............4826.2.254Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_22)Offset 698h ..............4826.2.255Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_22)Offset 69Ch ..............4826.2.256Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_23)Offset 6A0h ..............4826.2.257Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_23)Offset 6A4h ..............4826.2.258Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_0)Offset 6A8h ...............4826.2.259Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_0)Offset 6ACh ...............4826.2.260Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_1)Offset 6B0h ...............4826.2.261Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_1)Offset 6B4h ...............4826.2.262Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_2)Offset 6B8h ...............4836.2.263Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_2)Offset 6BCh ...............4836.2.264Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_3)Offset 6C0h ...............4836.2.265Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_3)Offset 6C4h ...............4836.2.266Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_4)Offset 6C8h ...............4836.2.267Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_4)Offset 6CCh ...............4836.2.268Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_5)Offset 6D0h ...............4836.2.269Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_5)Offset 6D4h ...............4836.2.270Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_6)Offset 6D8h ...............4836.2.271Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_6)Offset 6DCh...............4846.2.272Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_7)Offset 6E0h ...............4846.2.273Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_7)Offset 6E4h ...............4846.2.274Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_8)Offset 6E8h ...............4846.2.275Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_8)Offset 6ECh ...............484

332219-002 19

6.2.276Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_9)Offset 6F0h ............... 4846.2.277Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_9)Offset 6F4h ............... 4846.2.278Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_10)Offset 6F8h ............. 4846.2.279Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_10)Offset 6FCh ............. 4846.2.280Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_11)Offset 700h ............. 4856.2.281Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_11)Offset 704h ............. 4856.2.282Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_12)Offset 708h ............. 4856.2.283Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_12)Offset 70Ch ............. 4856.2.284Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_13)Offset 710h ............. 4856.2.285Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_13)Offset 714h ............. 4856.2.286Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_14)Offset 718h ............. 4856.2.287Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_14)Offset 71Ch ............. 4856.2.288Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_15)Offset 720h ............. 4856.2.289Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_15)Offset 724h ............. 4866.2.290Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_16)Offset 728h ............. 4866.2.291Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_16)Offset 72Ch ............. 4866.2.292Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_17)Offset 730h ............. 4866.2.293Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_17)Offset 734h ............. 4866.2.294Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_18)Offset 738h ............. 4866.2.295Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_18)Offset 73Ch ............. 4866.2.296Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_19)Offset 740h ............. 4866.2.297Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_19)Offset 744h ............. 4866.2.298Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_20)Offset 748h ............. 4876.2.299Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_20)Offset 74Ch ............. 4876.2.300Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_21)Offset 750h ............. 4876.2.301Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_21)Offset 754h ............. 4876.2.302Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_22)Offset 758h ............. 4876.2.303Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_22)Offset 75Ch ............. 4876.2.304Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_23)Offset 760h ............. 4876.2.305Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_23)Offset 764h ............. 4876.2.306Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_0)Offset 768h ............... 4876.2.307Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_0)Offset 76Ch............... 4886.2.308Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_1)Offset 770h ............... 4886.2.309Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_1)Offset 774h ............... 4886.2.310Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_2)Offset 778h ............... 4886.2.311Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_2)Offset 77Ch............... 4886.2.312Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_3)Offset 780h ............... 4886.2.313Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_3)Offset 784h ............... 4886.2.314Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_4)Offset 788h ............... 4886.2.315Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_4)Offset 78Ch............... 4886.2.316Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_5)Offset 790h ............... 4896.2.317Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_5)Offset 794h ............... 4896.2.318Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_6)Offset 798h ............... 4896.2.319Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_6)Offset 79Ch............... 4896.2.320Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_7)Offset 7A0h............... 4896.2.321Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_7)Offset 7A4h............... 4896.2.322Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_8)Offset 7A8h............... 4896.2.323Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_8)Offset 7ACh............... 4896.2.324Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_9)Offset 7B0h............... 4896.2.325Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_9)Offset 7B4h............... 4906.2.326Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_10)Offset 7B8h ............. 4906.2.327Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_10)Offset 7BCh ............. 4906.2.328Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_11)Offset 7C0h ............. 4906.2.329Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_11)Offset 7C4h ............. 4906.2.330Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_12)Offset 7C8h ............. 490

20 332219-002

6.2.331Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_12)Offset 7CCh .............4906.2.332Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_13)Offset 7D0h .............4906.2.333Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_13)Offset 7D4h .............4906.2.334Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_14)Offset 7D8h .............4916.2.335Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_14)Offset 7DCh .............4916.2.336Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_15)Offset 7E0h..............4916.2.337Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_15)Offset 7E4h..............4916.2.338Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_16)Offset 7E8h..............4916.2.339Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_16)Offset 7ECh..............4916.2.340Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_17)Offset 7F0h..............4916.2.341Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_17)Offset 7F4h..............4916.2.342Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_18)Offset 7F8h..............4916.2.343Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_18)Offset 7FCh..............4926.2.344Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_19)Offset 800h..............4926.2.345Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_19)Offset 804h..............4926.2.346Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_20)Offset 808h..............4926.2.347Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_20)Offset 80Ch .............4926.2.348Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_21)Offset 810h..............4926.2.349Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_21)Offset 814h..............4926.2.350Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_22)Offset 818h..............4926.2.351Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_22)Offset 81Ch .............4926.2.352Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_23)Offset 820h..............4936.2.353Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_23)Offset 824h..............493

6.3 GPIO Community 2 Registers Summary ..............................................................4936.3.1 Family Base Address (FAMBAR)Offset 8h...............................................4946.3.2 Pad Base Address (PADBAR)Offset Ch...................................................4956.3.3 Miscellaneous Configuration (MISCCFG)Offset 10h..................................4956.3.4 Pad Ownership (PAD_OWN_GPD_0)Offset 20h .......................................4976.3.5 Pad Ownership (PAD_OWN_GPD_1)Offset 24h .......................................4986.3.6 Pad Configuration Lock (PADCFGLOCK_GPD_0)Offset A0h .......................4986.3.7 Pad Configuration Lock (PADCFGLOCKTX_GPD_0)Offset A4h....................4996.3.8 Host Software Pad Ownership (HOSTSW_OWN_GPD_0)Offset D0h ...........5006.3.9 GPI Interrupt Status (GPI_IS_GPD_0)Offset 100h ..................................5026.3.10 GPI Interrupt Enable (GPI_IE_GPD_0)Offset 120h ..................................5036.3.11 GPI General Purpose Events Status (GPI_GPE_STS_GPD_0)Offset 140h ....5046.3.12 GPI General Purpose Events Enable (GPI_GPE_EN_GPD_0)Offset 160h .....5056.3.13 Pad Configuration DW0 (PAD_CFG_DW0_GPD_0)Offset 400h...................5066.3.14 Pad Configuration DW1 (PAD_CFG_DW1_GPD_0)Offset 404h...................5086.3.15 Pad Configuration DW0 (PAD_CFG_DW0_GPD_1)Offset 408h...................5096.3.16 Pad Configuration DW1 (PAD_CFG_DW1_GPD_1)Offset 40Ch...................5096.3.17 Pad Configuration DW0 (PAD_CFG_DW0_GPD_2)Offset 410h...................5096.3.18 Pad Configuration DW1 (PAD_CFG_DW1_GPD_2)Offset 414h...................5106.3.19 Pad Configuration DW0 (PAD_CFG_DW0_GPD_3)Offset 418h...................5106.3.20 Pad Configuration DW1 (PAD_CFG_DW1_GPD_3)Offset 41Ch...................5106.3.21 Pad Configuration DW0 (PAD_CFG_DW0_GPD_4)Offset 420h...................5106.3.22 Pad Configuration DW1 (PAD_CFG_DW1_GPD_4)Offset 424h...................5106.3.23 Pad Configuration DW0 (PAD_CFG_DW0_GPD_5)Offset 428h...................5106.3.24 Pad Configuration DW1 (PAD_CFG_DW1_GPD_5)Offset 42Ch...................5106.3.25 Pad Configuration DW0 (PAD_CFG_DW0_GPD_6)Offset 430h...................5106.3.26 Pad Configuration DW1 (PAD_CFG_DW1_GPD_6)Offset 434h...................5106.3.27 Pad Configuration DW0 (PAD_CFG_DW0_GPD_7)Offset 438h...................5116.3.28 Pad Configuration DW1 (PAD_CFG_DW1_GPD_7)Offset 43Ch...................5116.3.29 Pad Configuration DW0 (PAD_CFG_DW0_GPD_8)Offset 440h...................5116.3.30 Pad Configuration DW1 (PAD_CFG_DW1_GPD_8)Offset 444h...................5116.3.31 Pad Configuration DW0 (PAD_CFG_DW0_GPD_9)Offset 448h...................511

332219-002 21

6.3.32 Pad Configuration DW1 (PAD_CFG_DW1_GPD_9)Offset 44Ch .................. 5116.3.33 Pad Configuration DW0 (PAD_CFG_DW0_GPD_10)Offset 450h................. 5116.3.34 Pad Configuration DW1 (PAD_CFG_DW1_GPD_10)Offset 454h................. 5116.3.35 Pad Configuration DW0 (PAD_CFG_DW0_GPD_11)Offset 458h................. 5116.3.36 Pad Configuration DW1 (PAD_CFG_DW1_GPD_11)Offset 45Ch ................ 512

6.4 GPIO Community 3 Registers Summary.............................................................. 5126.4.1 Capability List Register (CAP_LIST_0)Offset 4h...................................... 5136.4.2 Family Base Address (FAMBAR)Offset 8h .............................................. 5146.4.3 Pad Base Address (PADBAR)Offset Ch .................................................. 5146.4.4 Miscellaneous Configuration (MISCCFG)Offset 10h ................................. 5156.4.5 Pad Ownership (PAD_OWN_GPP_I_0)Offset 20h .................................... 5166.4.6 Pad Ownership (PAD_OWN_GPP_I_1)Offset 24h .................................... 5176.4.7 Pad Configuration Lock (PADCFGLOCK_GPP_I_0)Offset 90h..................... 5176.4.8 Pad Configuration Lock (PADCFGLOCKTX_GPP_I_0)Offset 94h ................. 5186.4.9 Host Software Pad Ownership (HOSTSW_OWN_GPP_I_0)Offset D0h......... 5206.4.10 GPI Interrupt Status (GPI_IS_GPP_I_0)Offset 100h ............................... 5216.4.11 GPI Interrupt Enable (GPI_IE_GPP_I_0)Offset 120h ............................... 5226.4.12 GPI General Purpose Events Status (GPI_GPE_STS_GPP_I_0)Offset 140h . 5236.4.13 GPI General Purpose Events Enable (GPI_GPE_EN_GPP_I_0)Offset 160h... 5246.4.14 SMI Status (GPI_SMI_STS_GPP_I_0)Offset 180h.....................