Abstract— The proposed on-die termination (ODT)

calibration method is implemented by using a 0.18um CMOS technology. The proposed ODT can detect the impedance variations of each ODT/OCD independently with the help of the proposed local PVT variation sensor and can decrease the impedance mismatch error lower than 1% by calibration of global on-chip variation with small area overhead. The measured eye diagram area at 2Gbps is widened by 26% when the ODT is on. The random data rate used for testing the eye diagram is 2Gbps. The global impedance mismatch error is within 1% under the supply voltage variation from 1.7V to 1.9V. The ODT and its calibration circuit occupy 0.003mm2 and 0.015mm2, respectively. The power consumption of the calibration circuit is 10mW at 2Gbps.

I. INTRODUCTION

As the operating frequencies of the synchronous DRAM such as DDR3 and graphic SDRAMs such as GDDR3 and GDDR5 are rapidly increasing beyond 500MHz, the data rate of an I/O interface increases over 1Gbps [1],[2]. In this high data rate environment, the signal integrity can be affected through impedance mismatch between chip-to-chip path and internal I/O driver. Also, as the data bandwidth becomes higher, the termination resistor is integrated inside memories. Because there are many output pins in memory chips, the on chip driver (OCD) and on-die-termination (ODT) are often shared to reduce area.

As the process geometry and supply voltage level are decreasing, the process, supply voltage and temperature (PVT) variations also affect the I/O driver´s and on-die-termination resistor´s impedance significantly. To calibrate the impedance of ODT/OCD in this environment, the conventional ODT/OCD schemes use an external resistor at ZQ pin as a reference so that the impedance of ODT/OCD gets close to that of an external resistor [1]-[7]. However, they can adjust the ODT/OCD impedance finitely only if ODT/OCDs are located near the external resistor. If the ODT/OCDs are located far from the external resistor, it is difficult for the conventional ODT/OCD schemes to adjust the impedance of themselves with the error lower than 1% because they calibrate the ODT with the PVT condition at ZQ pin which are different from that of local DQ pins.

The proposed ODT scheme can detect the impedance variations of each I/O drivers and calibrate them with impedance error less than 1% by calibration of global on-chip variation. Although accurate ODT impedance control is important, the area overhead of ODT compensation circuit

Fig. 1. The block diagram of the proposed on-die termination.

also cannot be ignored because there are many output pins in contemporary memory chips. In this work, we minimized the area overhead while maintaining the accuracy of ODT.

II. OVERALL ARCHITECTURE

The impedance matching between I/O driver and off-chip signal path is an important factor for signal integrity in high-speed systems. The impedance mismatch makes signal amplitude decrease, which results in small eye diagram. There is a ZQ pin where an external resistor of 240Ω is connected and 32 DQ pins for data transmission. For conventional GDDR3 and GDDR4, OCD/ODT circuit use pseudo open drain (POD). At each DQ pin, there is OCD/ODT circuit where output impedance can be either 240Ω, 120Ω, 60Ω or 40Ω. The parallel combination of different impedances can be chosen according to the operation mode. The ODT designed to have a 240Ω resistance is calibrated first using the external 240Ω resistor.

The control code for this calibration then can be applied to other ODTs designed to have 120Ω, 60Ω, 40Ω and pull down network of OCD. If the impedance of OCD/ODT is equal to that of off-chip resistor of 240Ω, the voltage of the ZQ pin is a half of supply voltage. However, if I/O driver, whose output node is connected to the ZQ pin, has an impedance variation, the voltage of the ZQ pin deviates from the half of supply voltage. Based on this voltage variation, control signals are

Small-Area High-Accuracy ODT/OCD by calibration of Global On-Chip for 512M GDDR5 application

1Jabeom Koo, 1Gil-su Kim, 1Junyoung Song, 2Kwan-Weon Kim, 2Young Jung Choi, and 1Chulwoo Kim

1Department of Electrical Engineering, Korea University, Seoul, Korea 2Hynix Semiconductor, Icheon, Korea

717

IEEE 2009 Custom Intergrated Circuits Conference (CICC)

978-1-4244-4072-6/09/$25.00 ©2009 IEEE 24-5-1

VO

I M1

M2

M3

M4

M5

M6

M7

VREF

V1

M8

M11

M10

M9

M12

V3

Voltage adder Voltage subtractor

V2 V4

Vout

M13

Fig. 2. The block diagram of the local PVT variation sensor. generated to adjust the I/O driver impedance. As this conventional ODT structure assumes that the impedance variation of 32 OCD/ODT circuit at DQ0~DQ31 pins is same with that of OCD/ODT circuit at ZQ pin, control signals generated from ODT calibration circuit at ZQ pin are shared with OCD/ODT circuit at 32 DQ pins. Because the impedance variation of OCD/ODT circuit at the DQ pins may be different from that of ZQ pin, it results in impedance matching error. That is because PVT condition at each pin can be different from each other.

Fig. 1 shows the proposed ODT scheme which is designed for overcoming this problem. As shown in Fig. 1, the impedance calibration code, ical, generated by the ODT calibration block at ZQ pin is connected to ODT circuits at 32 DQ pins in conventional ODT calibration circuit. To increase the accuracy of ODT circuit under PVT variations, local PVT variation sensor is used in our design. Basically, each I/O driver has a proposed PVT variation sensor to detect an impedance mismatch. As it intends to keep the impedance error less than 1%, it should detect very small voltage variation (7mV~8mV) at the output node of OCD/ODT circuit. The pre-amplifier amplifies this voltage variation so that the comparator can detect the voltage variation easily. Comparator sends a signal to controller block, then controller block generates binary code signal to turn on or off the calibration resistors which consists of PMOS transistors and passive resistors. The schematics of ODT circuit, which consist of poly resistor and PMOS for good linearity and small area, and the comparator are shown in Fig. 1. Controller block consists of ring counter and a bunch of logic gates. The counter is running until the comparator sends a stop signal and then generates binary codes. Hence, the poly resistor value can be determined according to the 5-b binary code (ical).

III. CIRCUIT DESCRIPTION

A. The proposed local PVT variation sensor

Fig. 3. The block diagram of the controller.

Fig. 2 shows a schematic of PVT variation sensor. It

consists of current source, voltage adder, voltage subtractor and variation converter. If we assume that all PMOSes of voltage adder and subtractor operate in the saturation mode, the amounts of current flowing through M5 and M6 are same. That means the source-gate voltages of M5 and M6 are same and we can get V2 as VDD – V1. In this way, if we assume the amount of each current flowing through PMOSes of each stage (M5~M6, M7~M8, M9~M10) is same, we can obtain the value of VO, 2V1-VREF. As you can see, the VO value consists of current source voltages. That’s why we can get the constant value of VO. As it is connected to the NMOS gate, the NMOS serves as a current source. Then, the output voltage variation due to the PMOS and poly resistor’s impedance variation is shown to the output. The I/O driver’s impedance variation is same with that of PVT variation sensor block at a certain PVT condition as shown in Fig. 3(b). The only difference is that the amount of sensor block’s variation is three times bigger than that of I/O driver’s variation for the control. With this sensor block, each DQ I/O driver can adjust its impedance. However, as this sensor is designed to have impedance variation two to three times bigger than that of OCD/ODT, the impedance mismatch error would be occurred if ODT’s impedance variation is different from the expected value at a certain PVT condition.

B. The coupling block

To solve that problem, calibration scheme for global on-chip variation is proposed. At the first update of impedance calibration at DQ0 pin, it compares the amount of impedance variation between DQ0 pin and DQn pin with the comparator as shown in Fig. 1. If that difference is larger than double with the help of an adder, the coupling block makes the global controller generate 5-b control signal, incal. In this case, double number of calibration resistors is turned on or off. In conventional structure, 5-b control signals should be delivered to all I/O drivers. However, the proposed ODT structure requires only one signal line delivered to all I/O drivers, which reduces area significantly.

C. The controller block

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Fig. 4. The block diagram of ODT cells at each pin.

Fig. 5. Simulation results of entire performance. Fig. 3 shows the block diagram of the global controller.

Basically, it consists of ring counter and AND logic gates. The counter is running until the comparator sends a stop signal. If a impedance change at a certain DQ pins is different from three times of the ZQ’s impedance, the coupling block sends a coupling enable signal, Enable. This signal modifies 5-b signal incal. It adjusts turned-on calibration cells to decrease the impedance variation. The calibration cells consist of PMOS and poly resistor as shown in Fig. 4.

IV. MEASUREMENT RESULTS Fig. 5 shows the simulation results performed in three

process corners. The voltage of the ODT/OCD goes to a half of the supply voltage within several clock cycles. It means the impedance of the ODT/OCD becomes that of off-chip resistor connected to the ZQ pin. To test whether the impedance of the I/O driver output is equal to that of the off-chip resistor, the current and voltage are measured. With the measured current and voltage, the impedance can be calculated as shown in Fig. 6. To test whether the eye diagram is changed when the ODT is turned on or off, the random data signals are injected.

To measure the ODT impedance variation of the entire chip, five DQ pins and one ZQ pin are located as shown in Fig. 6(b).

Voltage variation1.9V1. 85V1.8V1. 75V1.7V

240ohm

237.6 ohm (-1%)

242.4 ohm (+1%)

Impedance

242.4 242.4

242242

242240

239238

242240

239.8 239.8

(a)

(b)

Fig. 6. (a) The measured impedance value of ODT and (b) its locations in the chip.

(a)

(b)

Fig. 7 The measured eye diagram at 2Gbps (a) ODT calibration off (b) ODT calibration on.

ODTs can calibrate the impedance to a target value (1%) under

supply voltage variation as shown in Fig. 6(a). The voltage variation is from 1.7V to 1.9V. If the impedance does not

match, there is a reflection when the signal comes to the input

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Fig. 8. Impedance mismatch errors

driver. That results in a smaller eye diagram of the signal. Fig. 7 shows eye diagrams when the ODT is turned on or off at the 2Gbps random data rate. The height and width of eye diagram become larger by 5.9% and 19%, respectively with the help of ODT calibration. As the data rate increases, the effect of ODT becomes clear. To simulate in the same environment of the real chip, each

ODTs should operate in the different corners. If the ODT works well with the local PVT variation sensor and coupling block, the impedance value of each ODTs becomes equal with that of ZQ even though ODTs are working at different corners each other. If the impedance value of ODT is same as that of ZQ, the voltage of ODT becomes a half of supply voltage, 0.9V in this block. Fig. 8 shows the simulation results of three cases. One is for using 32 ODTs. The others are for using 8 and 5 ODTs. The location of ODTs is based on the GDDR5 application. As shown in Fig. 8, the coupling block and local PVT variation sensor block works well even though each ODTs is simulated under different corners. The impedance error of each ODT is less than 1%. Fig. 9 shows the die photo of an ODT. The total area of ODT is 0.015mm2. The controller and ODT cells occupy most of area. The power consumption is 18mW at 1Gbps as shown in Table 1.

V. CONCLUSION The proposed on-die termination method can calibrate each I/O drivers’ impedance with 1% mismatch error. Each I/O driver has a proposed PVT variation sensor so that the impedance matching is achieved independently. The PVT variation sensor is designed to have equal voltage variation with the I/O driver’s voltage variation, but the amount of sensor’s variation is two to three times larger for high sensitivity. To test how the proposed ODT affects the signal integrity, 2Gbps random data is used. When the ODT is turned on, the area of the eye diagram becomes larger about 26%. The proposed ODT is implemented by using 0.18um CMOS technology and can be applied to high-speed memories such as GDDR5.

ACKNOWLEDGMENT This work was supported by Hynix Semiconductor Inc.

LSPACPController

BufferODT cells

Fig. 9. Die photo

REFERENCES [1] Seung-Jun Bae et al., “An 80nm 4Gb/s/pin 32bit 512Mb GDDR4

graphics DRAM with low power and low noise data bus inversion,” IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 121-131, Jan. 2008.

[2] Dong Uk Lee et al., “Multi-slew-rate output driver and optimized impedance-calibration circuit for 66nm 3.0Gb/s/pin DRAM interface,” in IEEE ISSCC Dig. Tech. Papers, pp. 280-281, Fab. 2008.

[3] Changsik Yoo et al., “A 1.8V 700Mb/s/pin 512Mb DDR-Ⅱ SDRAM with on-die termination and off-chip driver calibration,” IEEE J. Solid-State Circuits, vol. 39, no. 6, pp. 941-951, Jun. 2004.

[4] Jeong-Don Ihm, et al., “An 80nm 4Gb/s/pin 32b 512Mb GDDR4 graphics DRAM with low-power and low-noise data-bus inversion,” in ISSCC Dig. Tech Papers, Feb. 2007, pp. 492-617.

[5] C. Yoo, et al., “A 1.8V 700Mb/s/pin 512Mb DDR-SDRAM with on-die termination and off-chip driver calibration,” in ISSCC Dig. Tech Papers, Feb. 2003, pp. 312-496.

[6] J. Park, et al., “A high-speed memory interface circuit tolerant to PVT variations and channel noise,” in 27th European Solid-Sate Circuit Conference, pp. 293-296, Sep. 2001.

[7] Y. Kwak, et al., “A one-cycle time slew-rate controlled output driver,” in IEEE ISSCC Dig. Tech Papers, Feb. 2007, pp. 408-409.

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