soc power estimation
TRANSCRIPT
SOC POWER ESTIMATIONW A T MAHESH DANANJAYA
POWER ESTIMATION
System Power
Dynamic Power
Switching Power Internal Power
Static power
Leakage Power
SWICTHING POWER
โข Power generated due to output changes, thus
charging and discharging the load capacitance.
โข Switching power dissipates mainly depend on the,
โข System Clock Frequency
โข Activity Switching Frequency
โขSwitching Power Calculation depends on the three factors
โข ๐ช โ ๐ณ๐๐๐ ๐ช๐๐๐๐๐๐๐๐๐๐
โข ๐ โ ๐บ๐๐๐๐๐๐๐๐ ๐ญ๐๐๐๐๐๐๐
โข ๐ฝ โ ๐ซ๐๐๐๐๐๐ ๐ฝ๐๐๐๐๐๐
๐๐ = ๐ถ โ ๐2 โ ๐
INTERNAL POWER
โข Short circuit path has been created between power and ground at the
transition stage
โข Thus the short circuit current is generated
โข Both NMOS and PMOS transistors are conducting for a short period of
time
โข Power dissipation due to this temporary short circuit path and the
internal capacitance is Internal Power
โข Depends on some factors,
โข Input edge time
โข Slew Rate
โข Internal Capacitances
๐๐ผ = ๐ โ ๐ผ๐๐ถ
DYNAMIC POWER
โข Dynamic power is the sum of switching power and internal
power
๐ท๐ซ = ๐ท๐บ + ๐ท๐ฐ
๐ท๐ซ = ๐ช โ ๐ฝ๐ โ ๐ + ๐ท๐ฐ
๐ท๐ซ = ๐ช โ ๐ฝ๐ โ ๐ + ๐ฝ โ ๐ฐ๐บ๐ช
๐ท๐ซ โฉญ ๐ช๐๐๐ โ ๐ฝ๐ โ ๐๐๐๐๐๐๐
STATIC POWER
โข Due to non-idle characteristic of the transistor the
leakages can be taken place
โข Static power is nothing, but leakage power
โข There are two main types of leakages and their
subsidiaries
โข ๐ผ๐๐น๐น โ Sub-threshold leakage (Drain Leakage Current)
โข ๐ผ๐ท,๐ค๐๐๐ โ ๐๐ข๐ โ ๐กโ๐๐๐ โ๐๐๐ ๐ท๐๐๐๐ ๐ถ๐ข๐๐๐๐๐ก
โข ๐ผ๐๐๐ฃ โ ๐ ๐๐ฃ๐๐๐ ๐ ๐ต๐๐๐ ๐๐ ๐ถ๐ข๐๐๐๐๐ก
โข ๐ผ๐บ๐ผ๐ท๐ฟ โ ๐บ๐๐ก๐ ๐ผ๐๐๐ข๐๐๐ ๐ท๐๐๐๐ ๐ฟ๐๐๐๐๐๐
โข ๐ผ๐บ๐ด๐๐ธ โ Gate Leakage Current
โข ๐ผ๐๐๐๐๐ธ๐ฟ โ ๐บ๐๐ก๐ ๐๐ข๐๐๐๐๐๐๐
โข ๐ผ๐ป๐ถ โ ๐ป๐๐ก ๐ถ๐๐๐๐๐๐ ๐ผ๐๐๐๐๐ก๐๐๐
LEAKAGE POWER
๐ผ๐ฟ๐ธ๐ด๐พ๐ด๐บ๐ธ
๐ผ๐๐น๐น
๐ผ๐ผ๐๐ ๐ผ๐ท,๐๐ธ๐ด๐พ ๐ผ๐บ๐ผ๐ท๐ฟ
๐ผ๐บ๐ด๐๐ธ
๐ผ๐๐๐๐๐ธ๐ฟ ๐ผ๐ป๐ถ
LEAKAGE POWER
๐ฐ๐ณ๐ฌ๐จ๐ฒ๐จ๐ฎ๐ฌ = ๐ผ๐๐น๐น + ๐ผ๐บ๐ด๐๐ธ
๐ท๐บ = ๐ฝ โ ๐ฐ๐๐๐๐
๐ฐ๐ฎ๐จ๐ป๐ฌ = ๐ผ๐ป๐ถ + ๐ผ๐๐๐๐๐ธ๐ฟ
๐ฐ๐ถ๐ญ๐ญ = ๐ผ๐๐๐ฃ + ๐ผ๐ท,๐ค๐๐๐ + ๐ผ๐บ๐ผ๐ท๐ฟ
TRANSISTOR LEAKAGE MECHANISMS
โข ๐ผ๐๐น๐น โ ๐ท๐๐๐๐ ๐ฟ๐๐๐๐๐๐ ๐ถ๐ข๐๐๐๐๐ก โ ๐๐ข๐ โ ๐กโ๐๐๐ โ๐๐๐ ๐ฟ๐๐๐๐๐๐ ๐ถ๐ข๐๐๐๐๐ก
(๐๐๐๐ค๐ ๐๐๐๐ ๐๐๐๐๐ ๐ก๐ ๐ ๐๐ข๐๐๐ ๐๐ ๐๐๐๐ฆ)
โข ๐ผ๐ท,๐ค๐๐๐ โ ๐๐ข๐ โ ๐กโ๐๐๐ โ๐๐๐ ๐ท๐๐๐๐ ๐ถ๐ข๐๐๐๐๐ก
โข ๐ผ๐๐๐ฃ โ ๐ ๐๐ฃ๐๐๐ ๐ ๐ต๐๐๐ ๐๐ ๐ถ๐ข๐๐๐๐๐ก
โข ๐ผ๐บ๐ผ๐ท๐ฟ โ ๐บ๐๐ก๐ ๐ผ๐๐๐ข๐๐๐ ๐ท๐๐๐๐ ๐ฟ๐๐๐๐๐๐
โข ๐ผ๐บ๐ด๐๐ธ โ ๐บ๐๐ก๐ ๐ฟ๐๐๐๐๐๐ ๐ถ๐ข๐๐๐๐๐ก
(๐ฟ๐๐๐๐๐๐ ๐๐ข๐๐๐๐๐ก ๐กโ๐๐ก ๐๐๐๐๐๐๐ ๐กโ๐๐๐ข๐โ ๐กโ๐ ๐๐๐ก๐๐ ๐๐ ๐กโ๐ ๐ก๐๐๐๐ ๐๐ ๐ก๐๐)
โข ๐ผ๐๐๐๐๐ธ๐ฟ โ ๐บ๐๐ก๐ ๐๐ข๐๐๐๐๐๐๐
โข ๐ผ๐ป๐ถ โ ๐ป๐๐ก ๐ถ๐๐๐๐๐๐ ๐ผ๐๐๐๐๐ก๐๐๐
SUB-THRESHOLD LEAKAGE CURRENT (๐ฐ๐ถ๐ญ๐ญ) โข The sub-threshold leakage current of a transistor,๐ผ๐๐น๐น, is
defined as the drain current when ๐๐ โ ๐๐ = 0 and ๐๐ท โฅ 0. ๐ผ๐๐น๐น is
dependent on the various factors such as,
โข ๐๐ท๐ท โ ๐๐ข๐๐๐๐ฆ ๐๐๐๐ก๐๐๐
โข ๐๐กโ โ ๐โ๐๐๐ โ๐๐๐ ๐๐๐๐ก๐๐๐
โข Doping Concentration
โข ๐๐๐ โ ๐บ๐๐ก๐ ๐๐ฅ๐๐๐ ๐โ๐๐๐๐ ๐
โข As we mentioned earlier ๐ฐ๐ถ๐ญ๐ญ is consist of 3 sub leakage
components.
โข ๐ผ๐ท,๐ค๐๐๐ โ ๐๐ข๐ โ ๐กโ๐๐๐ โ๐๐๐ ๐ท๐๐๐๐ ๐ถ๐ข๐๐๐๐๐ก
โข ๐ผ๐๐๐ฃ โ ๐ ๐๐ฃ๐๐๐ ๐ ๐ต๐๐๐ ๐๐ ๐ถ๐ข๐๐๐๐๐ก
โข ๐ผ๐บ๐ผ๐ท๐ฟ โ ๐บ๐๐ก๐ ๐ผ๐๐๐ข๐๐๐ ๐ท๐๐๐๐ ๐ฟ๐๐๐๐๐๐
๐ฐ๐ถ๐ญ๐ญ = ๐ผ๐๐๐ฃ + ๐ผ๐ท,๐ค๐๐๐ + ๐ผ๐บ๐ผ๐ท๐ฟ
๐ฐ๐๐๐ โ ๐น๐๐๐๐๐๐ ๐ฉ๐๐๐๐๐ ๐ช๐๐๐๐๐๐
โข ๐ฐ๐๐๐ is the current that flows through the reverse biased diode
between the drain and the p region of the transistor, and it is
dependent on the junction area between the Source/Drain terminal
and the body and exponentially dependent to the temperature.
โข Leakage current for the inverse biased diode can be modelled as
follows where,
โข ๐๐ โ ๐โ๐๐๐๐๐ ๐๐๐๐ก๐๐๐ (๐๐๐๐๐๐๐ก๐ค๐ ๐๐๐๐๐๐๐๐ฆ ๐๐๐๐๐๐๐๐๐ก ๐๐ ๐กโ๐ ๐ฃ๐๐๐ก๐๐๐)
โข ๐ผ๐ โ ๐ ๐๐ฃ๐๐๐ ๐ ๐๐๐ก๐ข๐๐๐ก๐๐๐ ๐ถ๐ข๐๐๐๐๐ก (๐ผ๐๐ก๐๐๐๐ ๐๐ ๐๐๐๐๐๐๐ก๐๐ ๐๐๐ ๐กโ๐ ๐๐๐ฃ๐๐๐)
โข ๐๐ท โ ๐๐๐๐ก๐๐๐ ๐๐๐ก๐ค๐๐๐ ๐ท๐๐๐๐ ๐๐๐ ๐กโ๐ ๐ต๐๐๐ฆ๐๐ ๐กโ๐ ๐ก๐๐๐๐ ๐๐ ๐ก๐๐
โข ๐ฝ๐ผ๐๐ โ ๐๐๐ก๐ข๐๐๐ก๐๐๐ ๐ถ๐ข๐๐๐๐๐ก ๐ท๐๐๐ ๐๐ก๐ฆ
โข ๐ด๐ท โ ๐ท๐๐๐๐ข๐ ๐๐๐ ๐ด๐๐๐
๐ฐ๐ฐ๐ต๐ฝ = ๐ฐ๐บ(๐ ๐ฝ๐ซ ๐ผ๐ป โ ๐)
๐ฐ๐ฐ๐ต๐ฝ = ๐จ๐ซ โ ๐ฑ๐ฐ๐ต๐ฝ
๐ฐ๐ซ,๐๐๐๐ โ SUB-THRESHOLD DRAIN CURRENT
โข When,๐๐ < ๐๐กโ , ๐๐ โฅ 0.1 ๐๐๐ ๐๐ = ๐๐ = 0, transistor forms a weak
inversion layer. Transistor in a weak inversion has a constant voltage
across the semiconductor channel and the longitudinal electric field across
the channel is null. Thus there is no drift current generating inside.
Instead the leakage current ๐ฐ๐ซ,๐๐๐๐ is generated by the diffusion of
majority carriers across the channel. We can mathematically model this
sub-threshold drain leakage ๐ฐ๐ซ,๐๐๐๐ with the following factors.
โข ๐๐ โ ๐โ๐๐๐๐๐ ๐๐๐๐ก๐๐๐ (๐๐๐๐๐๐๐ก๐ค๐ ๐๐๐๐๐๐๐๐ฆ ๐๐๐๐๐๐๐๐๐ก ๐๐ ๐กโ๐ ๐ฃ๐๐๐ก๐๐๐)
โข ๐ฐ๐ โ ๐ผ๐๐๐ก๐๐๐ ๐ท๐ถ ๐๐๐๐ ๐๐ก ๐๐๐๐๐ ๐๐ข๐๐๐๐๐ก
โข It is paramount important to look at the exponential dependency of ๐ฐ๐ซ,๐๐๐๐
on ๐๐๐ as well as the linear offset based on ๐๐ท๐
๐ฐ๐ซ,๐๐๐๐ =๐พ
๐ณร ๐ฐ๐ ร ๐ ๐ฝ๐๐โ ๐ฝ๐๐ (๐ ๐ผ๐ป )
โ๐ร (๐ โ ๐โ๐ฝ๐ซ๐บ ร๐ร๐ผ๐ป
โ๐)
๐ฐ๐ฎ๐ฐ๐ซ๐ณ โ GATE INDUCED DRAIN LEAKAGE
โข Gate-induced drain leakage is generated when a large
enough gate to drain ๐๐๐voltage is applied to produce a band to
band electron tunneling near the interface between the gate
oxide and the semiconductor of the drain.
๐ฐ๐ฎ๐จ๐ป๐ฌ โ GATE LEAKAGE
โข The gate leakage current is dribbling across the gate to and
from the channel, substrate, and diffusion terminal.
โข This current avoid the treatment of the gate of a device as an
ideally insulated electrode. This gate leakage is basically
composed of two leakage components.
โข ๐ผ๐๐๐๐๐ธ๐ฟ โ ๐บ๐๐ก๐ ๐๐ข๐๐๐๐๐๐๐
โข ๐ผ๐ป๐ถ โ ๐ป๐๐ก ๐ถ๐๐๐๐๐๐ ๐ผ๐๐๐๐๐ก๐๐๐
๐ฐ๐ป๐ผ๐ต๐ต๐ฌ๐ณ โ GATE TUNNELING
โข This leakage current is generated due to carriers tunneling
through the gate of the transistor. There are two major
different way of carrier tunneling.
โข Fowler-Nordheim Tunneling
Tunneling into the conduction band of the dielectric. It
manifest itself as electron emission caused by the intense high
electric field.
โข Direct Tunneling
Tunneling to or from the gate through the forbidden band
gap of the dielectric
๐ฐ๐ฏ๐ช โ HOT CARRIER INJECTION
โข This current is known as Hot Carrier Leakage which is
origin whenever a carrier gains enough kinetic energy and
overcome the gate potential barrier.
โข This is more often happen to electrons since the voltage barrier
and effective mass of an electron is less than the one for holes.
VARIOUS OTHER POWER
โข Metastability
โข Output of the flops are remains on the undefined states which s caused
by the violation of setup time and hold time.
โข Set Up Time
โข Amount of time that the input signal needs to be stable before clocking the
flop
โข Hold Time
โข Amount of time that input signal wants to be stable after clocking the flop
โข Glitches
โข Glitches are unwanted or undesired changes in signals which are
resilient (self correcting).
โข caused by delays in lines and propagation delays of cells.
โข Latchups
โข LatchUps is a short circuit path between supply and the ground
TECHNOLOGY SCALING AND POWER ESTIMATION โข CMOS Device Scaling
โข Gate Oxide Thickness (๐ป๐ถ๐ฟ) Scaling
โข Channel Miniaturization
โข Supply Voltage and Threshold Voltage (๐ฝ๐ ๐ & ๐ฝ๐๐ ) Scaling
โข Doping Concentration
โข Source Drain Punchthrough
CMOS DEVICE SCALING
โข Although the rate is slowing device scaling is slowing
down and deviating from the actual moorโs law, technology
sand device scaling is happening so rapidly. Therefore
designers have potential of inexpensive doubling the number
of transistors every two years, which is possible thank to the
miniaturization of devices and the reduction of the cost of
computer power due to sales volume. Therefore designers
have to be careful about the stuff because in near future the
transistor miniaturization reaches atomic level. Some
challenges still remain for the future
โข Photolithography
โข Manufacturing Cost
โข Increased power density
โข ๐ผ ๐ผ current ratio
GATE OXIDE THICKNESS (๐ป๐ถ๐ฟ) SCALING
โข As long as semiconductor device is taking place, the gate oxide thickness and effective channel length is getting reduced. This thickness is one of the important parameter to FET and MOS devices where it is directly engaging with the MOS capacitance and all that.
According to some papers the relationship of the ๐ป๐ถ๐ฟ scaling can be
illustrated as ,
๐ฟ๐๐๐ = 45 ร ๐๐๐
๐ฟ๐๐๐ โ ๐ธ๐๐๐๐๐ก๐๐ฃ๐ ๐ถโ๐๐๐๐๐ ๐ฟ๐๐๐๐กโ
โข This relationship is usually leads to good ๐๐ โ ๐ผ๐transfer behavior. With this device scaling and other restrictions, Gate Oxide Thickness is limited to some typical level and create a barrier. There are two
leakage components which are affected by the ๐ป๐ถ๐ฟ scaling,
โข ๐ผ๐บ๐ผ๐ท๐ฟ โ ๐บ๐๐ก๐ ๐ผ๐๐๐ข๐๐๐ ๐ท๐๐๐๐ ๐ฟ๐๐๐๐๐๐
โข ๐ผ๐๐๐๐๐ธ๐ฟ โ ๐บ๐๐ก๐ ๐ท๐๐๐๐๐ก ๐๐ข๐๐๐๐๐๐๐
CHANNEL MINIATURIZATION
As long as technology scaling happens the effective channel is
reducing and short-channel effects are expected to worsen when
channel length is reduced.
DIBL โ Drain Induced Barrier Lowering is one such effect.
In DIBL scenario where depletion region of the source or drain
extends into the channel of a MOSFET device, effectively reducing the
channel length. This reduction in depletion layer lowers the potential
barrier for electrons, which results in an observable lowering of ๐๐กโ,
and hence in an increase on the ๐ฐ๐ซ,๐๐๐๐ current. And also channel
miniaturization reduces the junction area between the substrate and
the Source or Drain, effectively reducing the ๐ฐ๐๐๐. Channel
miniaturization is also closely related to scaling of the ๐ป๐ถ๐ฟ and
optimization is paramount importance for the best power
SUPPLY VOLTAGE AND THRESHOLD VOLTAGE (๐ฝ๐ ๐ & ๐ฝ๐๐ ) SCALING
โข ๐ฝ๐ ๐ and ๐ฝ๐๐ are two vital transistor characteristics.
โข Design engineers typically scale the supply voltage ๐ฝ๐ ๐ to
control dynamic power consumption and power density.
โข In the same time reduction of ๐ฝ๐ ๐ forces a dramatic reduction
in Threshold voltage (๐ฝ๐๐) in order to raise the performance
gains.
โข This reduction in ๐ฝ๐๐ typically causes a relatively large increase
in ๐ฐ๐ถ๐ญ๐ญ, while the reduction of ๐ฝ๐ ๐ reduces the leakage current
substantially.
DOPING CONCENTRATION
โข Electric field at a p-n junction strongly depends on the
junction doping. As long as technology and device scaling
continue, the doping concentration is rising, incrementing the
overall ๐ฐ๐๐๐ and ๐ฐ๐ป๐ผ๐ต๐ต๐ฌ๐ณ. Device engineers smart enough build a
smart doping profiles for the channel and the transistor
terminals to maximize active current driving through the
channel while minimizing the idle current.
SOURCE DRAIN PUNCHTHROUGH
โข Punchthrough happens when the depletion regions from
the source and the drain join in the absence of a depletion
region induced by gate. Punchthrough happens when voltages
between the source and the body are above then nominal range
of ๐๐๐, since this is not the common case for digital circuits.
Therefore model punchthough is very important to ASIC
designers.
EDA POWER ESTIMATION
โข Mostly based on the tech libraries
โข Based on two major calculations
โข Activity
โข The number of toggles per clock cycle on the signal, averaged
over many cycles
โข Probability
โข Percentage of the time that the signal will be high