splitter trigger board - board which split a bus of 32

SPLITTER TRIGGER board - Board which split a bus

of 32 differential ECL input into 3 bus of 32 differential

ECL output and generate a conditional trigger signal in

NIM mechanical module

J. Bouvier

To cite this version:

J. Bouvier. SPLITTER TRIGGER board - Board which split a bus of 32 differential ECLinput into 3 bus of 32 differential ECL output and generate a conditional trigger signal in NIMmechanical module. 2005, pp.1-30. <in2p3-00024932>

HAL Id: in2p3-00024932

http://hal.in2p3.fr/in2p3-00024932

Submitted on 26 Oct 2005

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http://hal.in2p3.fr/in2p3-00024932

Internal report LPSC 05-90

Ver.: 3

October 2005

SPLITTER_TRIGGER board

Board which split a bus of 32 differential ECL input into 3 bus of 32

differential ECL output and generate a conditional trigger signal in

NIM mechanical module.

Joel BOUVIER

Data Acquisition Team

SPLITTER & TRIGGER Module

Laboratory for Subatomic Physics and Cosmology, ver.: 3, October 2005, page 1

1. Overview

The purpose of this board is to generate a trigger signal, issued of 2 group of 16 input signals, for the CEDFPD board

and to replicate three time this 2 group of 16 bit signal.

2. Input / output

IN A, IN B this is 2 group of 16 input signals. Each signal is in complementary ECL technology ( NECL ).

Each group are located on different connector ( HE10 type connector ). The pinout of the different

connector are given in annex 10.

All the signal of a group must be driven due to the input signal technology . This technology of

signals does not regard the signals off-line as being at the low state.

OUTPUT A1

OUTPUT A2

OUTPUT A3

OUTPUT B1

OUTPUT B2

OUTPUT B3

This is the replicated signals of the INA, INB input group signals delayed by a time defined inside the

board by switch.

The delayed time can be :

21 ns

28 ns

35 ns

This signal are in complementary ECL technology ( NECL ) and there respective pinout are given in

annex 10

ORA, ORB : It is the OR of all the signal for a group ( ORA for INA and ORB for INB ). These outputs are

compatible NIM level.

These outputs must be continuously loaded by 50 ohm terminator . If not, the FAST CLEAR output

signal can be affected.

MULTA

MULTB

Multiplicity signals associated to a group ( MULTA for INA and MULTB for INB ).

These signals have amplitude of 50 mV / step under 50 ohms load and their duration can be

adjusted from 16 ns to 134 ns with the front panel potentiometer “MULT WIDTH”

TRIGA

TRIGB

Discriminated Multiplicity ( Mult signal > threshold ) associated to a group ( TRIGA for INA and TRIGB

for INB ).

These thresholds are regulated by a potentiometer located in the front of the module ( one potar for

INA and an other for INB ). Roughly 2 turns of the potentiometer are equivalent with a multiplicity

These output signals are NIM level compatible.

FAST CLEAR : Corresponds to the OR of ORA and ORB signals.

These output signals are NIM level compatible

TRIGGER0

TRIGGER1

These 2 outputs correspond to the logical AND of the TRIGA with the TRIGB signal.

An internal switch can be used to have or not an adjustable width or directly the width corresponding to

the input signals ( one switch by output ). The adjustable width lies between 3 and 95 nanoseco nd.

Another internal switch can be used to have a NIM or TTL outputs level. The choice can be different for

the 2 outputs.



3. « SPLITTER & TRIGGER » board Diagram

ECL NIM TRANSLATOR

Multiplicitygeneration

ECL NIM TRANSLATOR

ECL NIM TRANSLATOR

Multiplicitygeneration

ECL NIM TRANSLATOR

ECL NIM TRANSLATOR

INPUTA

INPUTB

OUTPUTA1

( ECL Dif. level)

OUTPUTB1

( ECL Dif. level)

OUTPUTA2

( ECL Dif. level)

OUTPUTA3

( ECL Dif. level)

OUTPUTB2

( ECL Dif. level)

OUTPUTB3

( ECL Dif. level)

OR A( NIM level )

OR B( NIM level )

FAST CLEAR( NIM level )

MULT A

MULT B

TRIG A( NIM level )

TRIG B( NIM level )

TRIGGER0( NIM or TTL level )

3-95ns

32 ns

signal

calibration

+

-+

-

VEEVEE

VEE

SPLIT

TER &

TRIG

GERS M

odule

LPSC, Grenoble

Ocotber 7th 2005

Ver.: 3.0

TRIGGER1( NIM or TTL level )

ECL LINERECEIVER

ECL LINERECEIVER

ECL TO TTLTRANSLATOR

TTL TO ECLTRANSLATOR






ECL TO TTLTRANSLATOR

MC10H115 SN10KHT5541

MC10H124

MC10H124

MC10H124

MC10H124

MC10H124

MC10H124SN10KHT5541

MC10H115

FPGAEPM3256APQFP144

INVERTER&

DELAYGENERATOR

POLARITY (*)

DELAY(1..0) (*)

OUTPUT_ENABLE (*)

FPGAEPM3256APQFP144

INVERTER&

DELAYGENERATOR

POLARITY (*)

DELAY(1..0) (*)

OUTPUT_ENABLE (*)

MC10H109 ( 2 1/2 )

MC10H109( 2 1/2 )

16

16

MAX9691

MAX9691

(*) The POLARITY, DELAY(1..0) and OUTPUT_ENABLE bits are are selected by onboard switchs

ECL NIM TRANSLATOR

ECL TTL TRANSLATOR

MC10H109 ( 1/2 )

MC10H109( 1/2 )

16

16

16 16 16 16

16 16

16 16

16 16

16 16

16 16

16 16

S1

S2

S3

S4

S5

S6

A00A01

AB

B00B01

MC10H158 ( 1/2 )

SEL

MULTI / OR

50 ΩΩΩΩ

50 ΩΩΩΩ



4. « SPLITTER & TRIGGER » Front view

Laboratoire de Physique Subatomique et de CosmologieGrenobleFrance

INP

UT

B

OUTB3

OUTB2

OUTB1

INP

UT

A

OUT A3 OUT A2

OUT A1

LEVEL MUL A

MULTWIDTH

LEVEL MUL B

SPLITTER / TRIGGER

FC

LRT

RG

BT

RG

1T

RG

AM

ULA

OR

A

TR

G0

OR

B

MU

LB

TRIGGER WIDTH



échelle : 1cotation en mm

INPUT A

INPUT B OUTPUT B1

OUTPUT B2

MULT A

MULT B / FCLR

OR B / TRIG B

TRIGGER0 / TRIGGER 1

OR A / TRIG A

OUTPUT B3

OUTPUT A1

OUTPUT A2

OUTPUT A3

WIDTH MULTIPLICITYMULTIPLICITY

Numberchannel A

MULTIPLICITYNumber

channel B

WIDTH FOR SIGNAL CALIBRATION

Laboratoire de Physique Subatomique et de CosmologieGrenobleFrance

INP

UT

B

OUTB3

OUTB2

OUTB1

INP

UT

A

OUT A3 OUT A2

OUT A1

LEVEL MUL A

MULTWIDTH

LEVEL MUL B

SPLITTER / TRIGGER

FC

LRT

RG

BT

RG

1T

RG

AM

ULA

OR

A

TR

G0

OR

B

MU

LB

TRIGGER WIDTH



5. Switches and setting

Output Polarity Control : - present : normal - absent : inverse

Full scale : ~ 35 ns

: ~ 21 ns

: ~ 28 ns

Delay generator :

UnusedInput A

no signalsOutput = TRIGA and TRIGB

TRIGGER0, TRIGGER1 Output signals

Never use this configuration

Signal is issued of the Signal Configuration System

Output A3 Output A2

Output A1

Output B3 Output B2 Output B1Input B

Output Polarity Control : - present : normal - absent : inverse

Full scale : ~ 35 ns

: ~ 21 ns

: ~ 28 ns

Delay generator :

UnusedTRIGGER0 :- TTL- NIM

TRIGGER1 :- TTL- NIM

Multiplicity

ORed input

TRIGGER GENERATION :

6. Board Power consumption

- 5v + 5 v - 12v + 12vTotal max power current : 6104,91 1215,00 138,77 16,00

Total typical power current : 5693,91 1019,00 128,77 6,00



VCC : 5VEE : -5

ECL Low level -1,62

ECL high level -0,88Inside resistor number : 196

Outside resistor number : 192ECL Pull down R value ( Ω ) : 680ECL Pull down R value ( Ω ) : 680

6.1. Maximum Value :

Power supply : VEE ( - 5,2v ) Power supply : VCC ( + 5v ) Power supply :-12v Power supply :+12v

Designation NumberPower Current( mA )

Chip consumption

( mW )

Total PowerCurrent( mA )

Power Current( mA )

Chip consumption

( mW )


Power Current( mA )

Chip consumption

( mW )


Power Current( mA )

Chip consumption

( mW )


MC10H101_dip 17 29 145,00 493,00 0,00 0,00

MC10H109_dip 6 15 75,00 90,00 0,00 0,00

MC10H115_dip 8 29 145,00 232,00 0,00 0,00

MC10H124_dip 24 72 360,00 1728,00 25 125,00 600,00

SN 10KHT5541_dip 4 33 165,00 132,00 120 600,00 480,00

MC10H125_dip 1 44 220,00 44,00 63 315,00 63,00

MC10H131_dip 17 62 310,00 1054,00 0,00 0,00

MC10192_dip 1 56 280,00 56,00 0,00 0,00

EPM3256A-10 PQF144 2 0,00 0,00 0 0,00 0,00

MAX9691 2 36 180,00 72,00 36 180,00 72,00

NE5532 1 0,00 0,00 0,00 0,00 16 16,00 16 16,00

OP400 2 0 0,00 0,00 0 0,00 0,00

Mutiplicity Generator 16 0,857 13,71

NIM generator 7 15,58 109,06

Subtotal : 3901,00 Subtotal : 1215,00 138,77 16,00

Inside pull down resistor

worst case : 253 6,06 0,025 1532,88

best case : 135 4,97 0,017 671,03

Subtotal : 2203,91

Subtotal : 6104,91



6.2. Typical Value : Typical Value

Power supply : VEE ( - 5,2v ) Power supply : VCC ( + 5v ) Power supply :-12v Power supply :+12v

Designation NumberPower Current( mA )

Chip consumption

( mW )


Power Current( mA )

Chip consumption

( mW )


Power Current( mA )

Chip consumption

( mW )


Power Current( mA )

Chip consumption

( mW )


MC10H101_dip 17 26 130,00 442,00 0,00 0,00

MC10H109_dip 6 14 70,00 84,00 0,00 0,00

MC10H115_dip 8 26 130,00 208,00 0,00 0,00

MC10H124_dip 24 66 330,00 1584,00 25 125,00 600,00

SN 10KHT5541_dip 4 22 110,00 88,00 80 400,00 320,00

MC10H125_dip 1 40 200,00 40,00 63 315,00 63,00

MC10H131_dip 17 56 280,00 952,00 0,00 0,00

MC10192_dip 1 56 280,00 56,00 0,00 0,00

EPM3256A-10 PQF144 2 0,00 0,00 0,00 0,00

MAX9691 2 18 90,00 36,00 18 90,00 36,00

NE5532 1 0,00 0,00 0,00 0,00 6 6,00 6 6,00

OP400 2 0 0,00 0,00 0 0,00 0,00

Mutiplicity Generator 16 0,857 13,71

NIM generator 7 15,58 109,06

Subtotal : 3490,00 Subtotal : 1019,00 128,77 6,00

Inside pull down resistor

worst case : 253 6,06 0,025 1532,88

best case : 135 4,97 0,017 671,03

Subtotal : 2203,91

Total power current : 5693,91



7. DELAY_50 Component

7.1. EPM3256A I/O and dedicated Pin-outs

EPM3256A ( 144-PinTQFP )

Dedicated Pin LAB

INPUT/GCLK1 125 A 1, 2, 139, 140, 141, 142, 143

INPUT/GCLRn 127 B 41,5, 6, 7, 8, 9, 10

INPUT/OE1 126 C 28, 29, 30, 31, 32, 34, 35, 36

INPUT/OE2/GCLK2 128 D 37, 38, 39, 40, 41, 42, 43, 44

TDI 1 4 E 131, 132, 133, 134, 136, 137, 138

TMS 1 20 F 11, 12, 14, 15, 16, 18, 19

TCK 1 89 G 20(1), 21, 22, 23, 25, 27

TDO 1 104 H 45, 46, 47, 48, 49, 53, 54

GNDINT 52, 57, 124, 129 I 116, 117, 118, 119, 120, 121, 122

GNDIO 3, 13, 17, 26, 33, 59, 64, 77,

85, 94, 105, 114, 135 J 90, 91, 92, 93, 96, 97

VCCINT (3.3 V Only) 51, 58, 123, 130 K 82, 83, 84, 86, 87, 88, 891

VCCIO (2.5 V or 3.3 V) 24, 50, 73, 76, 95, 115, 144 L 55, 56, 60, 61, 62, 63, 65

M 106, 107, 108, 109, 110, 111, 112, 113

N 98, 99, 100, 101, 102, 103, 1041

O 74, 75, 78, 79, 80, 81

P 66, 67, 68, 69, 70, 71, 72

1 This pin may function as either a JTAG port or a user I/O pin. When the device is configured to use the JTAG ports for

insystem programming, this pin is not available as a user I/O pin.

7.2. « DELAY_50 » Component pin report

Pin Name Loc. Dir. I/O level Volt.

Signal_in_a[13

] 1 bidir LVTTL

signal_in_a[14] 2 bidir LVTTL

GND 3 gnd

TDI 4 input LVTTL







signal_in_b[11] 11 bidir LVTTL


GND 13 gnd




GND 17 gnd




TMS 20 input LVTTL




VCCIO 24 power 3.3V


GND 26 gnd







GND 33 gnd




signal_in_c[13] 37 bidir LVTTL






signal_out[15] 40 output LVTTL










VCCIO 50 power 3.3V

VCCINT 51 power 3.3V

GND 52 gnd





GND 57 gnd


GND 59 gnd




signal_in_d[2] 63 bidir LVTTL

GND 64 gnd


RESERVED 66

RESERVED 67

cd_mux[0] 68 input LVTTL


RESERVED 70

RESERVED 71

CD_A 72 input LVTTL

VCCIO 73 power 3.3V

RESERVED 74


VCCIO 76 power 3.3V

GND 77 gnd

RESERVED 78

RESERVED 79


POLARITY 81 input LVTTL




GND 85 gnd





TCK 89 input LVTTL





GND 94 gnd

VCCIO 95 power 3.3V









TDO 104 output LVTTL

GND 105 gnd








signal_in[0] 113 input LVTTL

GND 114 gnd

VCCIO 115 power 3.3V









GND 124 gnd

GND+ 125

oe_signal 126 input LVTTL

GND+ 127

GND+ 128

GND 129 gnd






GND 135 gnd













VCCIO 144 power 3.3V

7.3. « DELAY_50 » Component Pinout

( SIGNAL_IN_A[13] )( SIGNAL_IN_A[14] )

GndTDI

( SIGNAL_IN_A[6] )( SIGNAL_IN_A[7] )( SIGNAL_IN_A[8] )

( SIGNAL_IN_A[10] )( SIGNAL_IN_A[11] )

( SIGNAL_IN_A[9] )( SIGNAL_IN_B[11] )( SIGNAL_IN_B[10] )

Gnd( SIGNAL_IN_B[9] )( SIGNAL_IN_B[8] )( SIGNAL_IN_B[7] )

Gnd( SIGNAL_IN_B[6] )( SIGNAL_IN_B[5] )

TMS( SIGNAL_IN_B[0] )( SIGNAL_IN_B[1] )( SIGNAL_IN_B[2] )

3V3( SIGNAL_IN_B[3] )

Gnd( SIGNAL_IN_B[4] )( SIGNAL_IN_A[4] )( SIGNAL_IN_A[5] )( SIGNAL_IN_A[3] )

( SIGNAL_IN_B[14] )( SIGNAL_IN_B[15] )

Gnd( SIGNAL_IN_A[0] )( SIGNAL_IN_A[1] )( SIGNAL_IN_A[2] )

3V3

( S

IGA

NL_

IN_A

[12]

)(

SIG

AN

L_IN

_A[1

5] )

SIG

NA

L_IN

[15]

SIG

NA

L_IN

[14]

SIG

NA

L_IN

[13]

( S

IGN

AL_

IN_B

[12]

)(

SIG

NA

L_IN

_B[1

3] )

SIG

NA

L_IN

[12]

Gnd

SIG

NA

L_IN

[11]

SIG

NA

L_IN

[10]

SIG

NA

L_IN

[9]

SIG

NA

L_IN

[8]

3V3

Gnd

Gnd

+G

nd+

OE

_SIG

NA

LG

nd+

Gnd

3V3

SIG

NA

L_IN

[7]

SIG

NA

L_IN

[6]

SIG

NA

L_IN

[5]

SIG

NA

L_IN

[4]

SIG

NA

L_IN

[3]

SIG

NA

L_IN

[2].

SIG

NA

L_IN

[1]

3V3

Gnd

SIG

NA

L_IN

[0]

( S

IGN

AL_

IN_D

[15]

)(

SIG

NA

L_IN

_D[1

4] )

( S

IGN

AL_

IN_D

[10]

)(

SIG

NA

L_IN

_D[1

3] )

( SIGNAL_IN_D[12] )( SIGNAL_IN_D[9] )( SIGNAL_IN_D[11] )GndTDO( SIGNAL_IN_D[8] )( SIGNAL_IN_D[7] )( SIGNAL_IN_D[6] )( SIGNAL_IN_D[5] )( SIGNAL_IN_D[1] )( SIGNAL_IN_D[4] )( SIGNAL_IN_C[10] )( SIGNAL_IN_C[9] )3V3Gnd( SIGNAL_IN_C[11] )( SIGNAL_IN_C[8] )( SIGNAL_IN_C[7] )( SIGNAL_IN_C[12] )TCK( SIGNAL_IN_C[3] )( SIGNAL_IN_C[6] )( SIGNAL_IN_C[2] )Gnd( SIGNAL_IN_C[5] )( SIGNAL_IN_C[4] )( SIGNAL_IN_C[1] )POLARITYCD_MUX[2]

Gnd3V3( SIGNAL_IN_D[0] )

3V3

( S

IGN

AL_

IN_C

[13]

)(

SIG

NA

L_IN

_C[1

4] )

( S

IGN

AL_

IN_C

[15]

) S

IGN

AL_

OU

T[1

5]S

IGN

AL_

OU

T[1

4]S

IGN

AL_

OU

T[1

3]S

IGN

AL_

OU

T[1

2]S

IGN

AL_

OU

T[1

1]S

IGN

AL_

OU

T[1

0]S

IGN

AL_

OU

T[9

]S

IGN

AL_

OU

T[8

]S

IGN

AL_

OU

T[7

]S

IGN

AL_

OU

T[6

]3V

33V

3G

ndS

IGN

AL_

OU

T[5

]S

IGN

AL_

OU

T[4

]S

IGN

AL_

OU

T[3

]S

IGN

AL_

OU

T[2

]G

nd3V

3G

ndS

IGN

AL_

OU

T[1

]S

IGN

AL_

OU

T[0

](

SIG

NA

L_IN

_C[0

] )(

SIG

NA

L_IN

_D[2

] )G

nd(

SIG

NA

L_IN

_D[3

] )

CD

_MU

X[0

]C

D_M

UX

[1]

CD

_A

123456789101112131415161718192021222324252627282930313233343536

144

143

142

141

140

138

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

TQFP 144Top view

10 October 2004

DELAY_50

108107106105104103102101100

999897969594939291908988878685848382818079787776757473

37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72



7.4. « DELAY_50 » VHDL description

--========================================================================

--

-- Design Units : G0 experiment

--

-- File name : delay.vhd

--

-- Purpose : This CPLD generate a delay ( 10 to 50 ns ) on a 16 bit data bus.

--

-- Notes :

--

-- Limitations :

--

-- Errors :

--

-- Library :

--

-- Dependencies :

--

-- Author : Joel BOUVIER

-- Laboratoire de physique Subatomique et de cosmologie

-- 53 Avenue des Martyrs

-- 38026 Grenoble Cedex, FRANCE

--

--============================================================================

-- Revision List

-- 2.0 31/03/2005 The polarity of the “polarity” signal are inverted

-- 1.0 17/09/2004 delay is encreased to 50 ns

-- 0.0 08/09/2004 Initial version ( delay 10 to 30 ns )

--============================================================================

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.”+”;

entity DELAY is

generic ( bus_width : natural :=15 );

port (

POLARITY : in std_logic ; -- Control input polarity

signal_in : in std_logic_vector(bus_width downto 0);-- Data in

CD_A : in std_logic ; -- Must be connect to 0

signal_in_a : inout std_logic_vector(bus_width downto 0);-- Intermediary signal

signal_in_b : inout std_logic_vector(bus_width downto 0);-- Intermediary signal

signal_in_c : inout std_logic_vector(bus_width downto 0);-- Intermediary signal

signal_in_d : inout std_logic_vector(bus_width downto 0);-- Intermediary signal

cd_mux : in std_logic_vector(2 downto 0); -- Ouput Delay signals

oe_signal : in std_logic ; -- Output is ‘Z’ when ‘0’



signal_out : out std_logic_vector(bus_width downto 0) ); -- Output signal

end DELAY ;

architecture behave of DELAY is

signal signal_int : std_logic_vector(bus_width downto 0);

signal signal_out_int : std_logic_vector(bus_width downto 0);

begin

signal_int <= signal_in when POLARITY =’0’ else ( not signal_in );

signal_in_a <= signal_int when CD_A =’0’ else ( others => ‘Z’ );

signal_in_b <= signal_in_a when cd_mux(2) =’1’ else ( others => ‘Z’ );

signal_in_c <= signal_in_b when cd_mux(1) =’1’ else ( others => ‘Z’ );

signal_in_d <= signal_in_c when cd_mux(0) =’1’ else ( others => ‘Z’ );

signal_out_int <= signal_in_d when cd_mux = “111” else

signal_in_c when cd_mux = “110” else

signal_in_b ;

signal_out <= signal_out_int when oe_signal = ‘0’ else ( others => ‘Z’ );

end behave ;



Annex 1 : board picture



Annex 2 : Generic pinout connector

designation Name Pin pin Name designation Input 0

( positive polarity ) INA[0]+ 1 2 INA[0]-

Input 0 ( negative polarity )

Input 1 ( positive polarity )

INA[1]+ 3 4 INA[1]- Input 1

( negative polarity ) Input 2




INA[3]+ 7 8 INA[3]- Input 2





INA[5]+ 11 12 INA[5]- Input 5





INA[7]+ 15 16 INA[7]- Input 7





INA[9]+ 19 20 INA[9]- Input 9





INA[11]+ 23 24 INA[11]- Input 11





INA[13]+ 27 28 INA[13]- Input 13





INA[15]+ 31 32 INA[15]- Input 15

( negative polarity ) Gnd 33 34 Gnd

designation Name Pin pin Name designation


OUTA[0]+ 1 2 OUTA[0]- Input 0


( positive polarity ) OUTA[1]+ 3 4 OUTA[1]-























OUTA[10]+ 21 22 OUTA[10]- Input 10





OUTA[12]+ 25 26 OUTA[12]- Input 12





OUTA[14]+ 29 30 OUTA[14]- Input 14




Gnd 33 34 Gnd



Annex 3 : Board scheme

10 K

136 P

1,2 K

1/2 MC10192

En

AB

/SASA/SBSB

680

A01

A00A

5

61

SELORAB

TRIGAB

A01

A00A

3

42

SELORBB

TRIGBB1/4 10H158 1/4 10H158

2 x 680

VEE

9

14151213



OPA656

330

330

51

47K



15P

15P

22P

22P



Annex 4 : board representation ( component side )

R2

PO1

C14

U2

C7

C3 C4

C13

P5 P4 P3

J1_1

C6 C2

D1

P2

P1

M1

C5

C1

J1_2

M1_1 M3_1 M2_1 M7_1 M5_1

RS1_1 RS2_1

M4_1 M6_1

RS4_1 RS3_1

M1_2 M3_2 M2_2 M7_2 M5_2

RS1_2 RS2_2

M4_2 M6_2

RS4_2 RS3_2

M1_

1_1

M1_

2_1

M1_

3_1

M1_

4_1

M1_

5_1

M1_

6_1

M1_

7_1

M1_

8_1

M1_

1_2

M1_

2_2

M1_

3_2

M1_

4_2

M1_

5_2

M1_

6_2

M1_

7_2

M1_

8_2

M2_

1_1

M2_

2_1

M2_

3_1

M2_

4_1

M2_

5_1

M2_

6_1

M2_

7_1

M2_

8_1

M2_

1_2

M2_

2_2

M2_

3_2

M2_

4_2

M2_

5_2

M2_

6_2

M2_

7_2

M2_

8_2

R4_1_1 R4_2_1 R4_3_1 R4_4_1 R4_5_1 R4_6_1 R4_7_1 R4_8_1 R4_1_2 R4_2_2 R4_3_2 R4_4_2 R4_5_2 R4_6_2 R4_7_2 R4_8_2

R15_1_1 R15_2_1 R15_3_1 R15_4_1 R15_5_1 R15_6_1 R15_7_1 R15_8_1 R15_1_2 R15_2_2 R15_3_2 R15_4_2 R15_5_2 R15_6_2 R15_7_2 R15_8_2

Q8

_1_

1

Q5

_1_

1Q

8_

2_1

Q5

_2_

1

Q8

_3_

1

Q5

_3_

1

Q8

_4_

1

Q5

_4_

1

Q8

_5_

1

Q5

_5_

1

Q8

_6_

1

Q5

_6_

1

Q8

_7_

1

Q5

_7_

1

Q8

_8_

1

Q5

_8_

1

Q8

_1_

2

Q5

_1_

2

Q8

_2_

2

Q5

_2_

2

Q8

_3_

2

Q5

_3_

2

Q8

_4_

2

Q5

_4_

2

Q8

_5_

2

Q5

_5_

2

Q8

_6_

2

Q5

_6_

2Q

8_

7_2

Q5

_7_

2Q

8_

8_2

Q5

_8_

2

C3_1_1 C6_1_1

C5

_1

_1

R16_1_1

C3_2_1 C6_2_1

C5

_2

_1

R16_2_1

C3_3_1 C6_3_1

C5

_3

_1

R16_3_1

C3_4_1 C6_4_1

C5

_4

_1

R16_4_1

C3_5_1 C6_5_1

C5

_5

_1

R16_5_1

C3_6_1 C6_6_1

C5

_6

_1

R16_6_1

C3_7_1 C6_7_1

C5

_7

_1

R16_7_1

C3_8_1 C6_8_1

C5

_8

_1

R16_8_1

C3_1_2 C6_1_2

C5

_1

_2

R16_1_2

C3_2_2 C6_2_2

C5

_2

_2

R16_2_2

C3_3_2 C6_3_2

C5

_3

_2

R16_3_2

C3_4_2 C6_4_2

C5

_4

_2

R16_4_2

C3_5_2 C6_5_2

C5

_5

_2

R16_5_2

C3_6_2 C6_6_2

C5

_6

_2

R16_6_2

C3_7_2 C6_7_2

C5

_7

_2

R16_7_2

C3_8_2 C6_8_2

C5

_8

_2

R16_8_2

M10

_1

M9_

1 M12

_1

M24

_1

M3

M2C11_1

C10_1

J3_1

J4_1 J5_1

J2_1

S1

S2

P10_1

C1

_1

R23_1

R22_1

R1

26

_1

R1

25

_1

M10

_2

M9_

2 M12

_2

M24

_2

C11_2

C10_2

J3_2

J4_1 J5_2

J2_2

P10_2

C1

_2

R23_2

R22_2

R1

26

2R

12

5_

2

M4

S3

S4

S5

S6

C1

2

M21_1 M22_1 M23_1

J8_1

M20

_1

M17_1 M18_1 M19_1

J7_1

M16

_1

M13_1 M14_1 M15_1

J6_1

R102_1 R101_1 R110_1 R109_1 R118_1 R117_1

R9

4_

1R

93

_1

R86_1 R85_1

R6

2_

1R

61

_1

R78_1 R77_1R70_1 R69_1

R38_1 R37_1 R46_1 R45_1 R54_1

R53_1

M21_2 M22_1 M23_2

J8_2

M20

_2

M17_2 M18_2 M19_2

J7_2

M16

_2

M13_2 M14_2 M15_2

R102_2 R101_2 R110_2 R109_2 R118_2 R117_2

R9

4_

2R

93

_2

R86_2 R85_2

R6

2_

2R

61

_2

R78_2 R77_2R70_2 R69_2

R38_2 R37_2

R46_2 R45_2 R54_2 R53_2

J6_2

PX2PX3PX1R24

R19

Q9

R21Q6Q6Q7

R16

R22

R17

R23Q8

R18R15

R20Q5

PX5PX4



Annex 5 : board representation ( sold side )

R1

R3

R1

5_

1

R1

4_

1

R16_1

R13_1

C2_1

R1

_1

R2

_1

C3_1 C4_1 C5_1

R1

9_

1

R1

8_

1

R20_1

R17_1

C6_1 C7_1

R7

_1

R6

_1

R8_1

R5_1

C8_1 C9_1

R1

1_

1

R1

0_

1

R12_1

R9_1R3

_1

R4

_1

R1

5_

2

R1

4_

2

R16_2

R13_2

C2_2

R1

_2

R2

_2

C3_2 C4_2 C5_2

R1

9_

2

R1

8_

2

R20_2

R17_2

C6_2 C7_2

R7

_2

R6

_2

R8_2

R5_2

C8_2 C9_2

R1

1_

2

R1

0_

2

R12_2

R9_2R3

_2

R4

_2

R21_1

M8_1

M11_1

R26_1

R25_1

R24_1R27_1

R28_1

R29_1

R30_1

C8

R7

C44_1

C36_1

R12

R6

C9

R5

R4C10

R8

R13

C11

R21_2

M8_2

M11_2

R26_2

R25_2

R24_2R27_2

R28_2

R29_2

R30_2

C44_2 C36_2

R11

R9

R10

R14

Q2

Q4

Q1

Q3

R122_2

R120_2

R121_2

R119_2

R124_2

R123_2

C24_2

C40_2R113_2R112_2C37_2R105_2R104_2

R111_2R114_2C31_2R103_2R106_2

C32_2

C17_2

C38_2

C16_2

R97_2

R95_2

R96_2

R98_2

C39_2

R122_1

R120_1

R121_1

R119_1

R124_1

R123_1

C40_1R113_1R112_1C37_1R105_1R104_1

R111_1R114_1C31_1R103_1R106_1

C32_1C38_1

C16_1

R97_1

R95_1

R96_1

R98_1C39_1

C17_1

C24_1

R92_1

R91_1

C47_1 R100_1 R99_1 C46_1 R108_1 R107_1 C45_1 R116_1 R115_1

R81_1R80_1C25_1R73_1R72_1

R79_1R82_1C19_1R71_1R74_1

C20_1C26_1

C43_1

R65_1

R63_1

R64_1

R66_1C27_1

C28_1

C35_1 R68_1 R67_1 C34_1 R76_1 R75_1 C33_1 R84_1 R83_1

R49_1R48_1C13_1R41_1R40_1

R47_1R50_1C29_1R39_1R42_1

C14_1

C30_1

R33_1

R31_1

R32_1

R34_1C15_1C18_1

C23_1 R36_1 R35_1 C22_1 R44_1 R43_1 C21_1 R52_1 R51_1

R60_1

R59_1

C42_1

R58_1

R56_1

R55_1

R57_1

C41_1

C12_1

R90_1

R88_1

R87_1

R89_1

R92_2

R91_2

C47_2 R100_2 R99_2 C46_2 R108_2 R107_2 C45_2 R116_2 R115_2

R81_2R80_2C25_2R73_2R72_2

R79_2R82_2C19_2R71_2R74_2

C20_2C26_2

C43_2

R65_2

R63_2

R64_2

R66_2C27_2

C28_2

C35_2 R68_2 R67_2 C34_2 R76_2 R75_2 C33_2 R84_2 R83_2

R49_2R48_2C13_2R41_2R40_2

R47_2R50_2C29_2R39_2R42_2

C14_2

C30_2

R33_2

R31_2

R32_2

R34_2

C15_2

C18_2C23_2

R36_2

R35_2 C22_2 R44_2 R43_2 C21_2 R52_2 R51_2

R60_2

R59_2

C42_2

R58_2

R56_2

R55_2

R57_2

C41_2

C12_2

R90_2

R88_2

R87_2

R89_2

Q10

C18

R25 Q13

C19

R28

C17 Q12R27

C16

R26Q11C15 Q14

R29

R6_1_1

R2

_1

_1

Q2_1_1

R5

_1

_1

C2

_1

_1

C1

_1

_1

R3

_1

_1

R1

_1

_1

Q1_1_1

C4_1_1

R6_2_1

R2

_2

_1

Q2_2_1

R5

_2

_1

C2

_2

_1

C1

_2

_1

R3

_2

_1

R1

_2

_1

Q1_2_1

C4_2_1

R6_3_1

R2

_3

_1

Q2_3_1

R5

_3

_1

C2

_3

_1

C1

_3

_1

R3

_3

_1

R1

_3

_1

Q1_3_1

C4_3_1

R6_4_1

R2

_4

_1

Q2_4_1

R5

_4

_1

C2

_4

_1

C1

_4

_1

R3

_4

_1

R1

_4

_1

Q1_4_1

C4_4_1

R6_5_1

R2

_5

_1

Q2_5_1

R5

_5

_1

C2

_5

_1

C1

_5

_1

R3

_5

_1

R1

_5

_1

Q1_5_1

C4_5_1

R6_6_1

R2

_6

_1

Q2_6_1

R5

_6

_1

C2

_6

_1

C1

_6

_1

R3

_6

_1

R1

_6

_1

Q1_6_1

C4_6_1

R6_7_1

R2

_7

_1

Q2_7_1

R5

_7

_1

C2

_7

_1

C1

_7

_1

R3

_7

_1

R1

_7

_1

Q1_7_1

C4_7_1

R6_8_1

R2

_8

_1

Q2_8_1

R5

_8

_1

C2

_8

_1

C1

_8

_1

R3

_8

_1

R1

_8

_1

Q1_8_1

C4_8_1

R6_1_2

R2

_1

_2

Q2_1_2

R5

_1

_2

C2

_1

_2

C1

_1

_2

R3

_1

_2

R1

_1

_2

Q1_1_2

C4_1_2

R6_2_2

R2

_2

_2

Q2_2_2

R5

_2

_2

C2

_2

_2

C1

_2

_2

R3

_2

_2

R1

_2

_2

Q1_2_2

C4_2_2

R6_3_2

R2

_3

_2

Q2_3_2

R5

_3

_2

C2

_3

_2

C1

_3

_2

R3

_3

_2

R1

_3

_2

Q1_3_2

C4_3_2

R6_4_2

R2

_4

_2

Q2_4_2

R5

_4

_2

C2

_4

_2

C1

_4

_2

R3

_4

_2

R1

_4

_2

Q1_4_2

C4_4_2

R6_5_2

R2

_5

_2

Q2_5_2

R5

_5

_2

C2

_5

_2

C1

_5

_2

R3

_5

_2

R1

_5

_2

Q1_5_2

C4_5_2

R6_6_2

R2

_6

_2

Q2_6_2

R5

_6

_2

C2

_6

_2

C1

_6

_2

R3

_6

_2

R1

_6

_2

Q1_6_2

C4_6_2

R6_7_2

R2

_7

_2

Q2_7_2

R5

_7

_2

C2

_7

_2

C1

_7

_2

R3

_7

_2

R1

_7

_2

Q1_7_2

C4_7_2

R6_8_2

R2

_8

_2

Q2_8_2

R5

_8

_2

C2

_8

_2

C1

_8

_2

R3

_8

_2

R1

_8

_2

Q1_8_2

C4_8_2

R17_1_1

Q7_1_1

R1

3_

1_

1

Q3_1_1

R1

1_

1_

1C

7_

1_

1

R9

_1

_1

R7

_1

_1

R8

_1

_1

R1

0_

1_

1

C8

_1

_1

Q4_1_1

R1

4_

1_

1

Q9_1_1

R18_1_1

Q6_1_1 Q10_1_1

R1

2_

1_

1

R17_2_1

Q7_2_1

R1

3_

2_

1

Q3_2_1

R1

1_

2_

1C

7_

2_

1

R9

_2

_1

R7

_2

_1

R8

_2

_1

R1

0_

2_

1

C8

_2

_1

Q4_2_1

R1

4_

2_

1

Q9_2_1

R18_2_1

Q6_1_1 Q10_1_1

R1

2_

2_

1

R17_3_1

Q7_3_1

R1

3_

3_

1

Q3_3_1

R1

1_

3_

1C

7_

3_

1

R9

_3

_1

R7

_3

_1

R8

_3

_1

R1

0_

3_

1

C8

_3

_1

Q4_3_1

R1

4_

3_

1

Q9_3_1

R18_3_1

Q6_1_1 Q10_1_1

R1

2_

3_

1

R17_4_1

Q7_4_1

R1

3_

4_

1

Q3_4_1

R1

1_

4_

1C

7_

4_

1

R9

_4

_1

R7

_4

_1

R8

_4

_1

R1

0_

4_

1

C8

_4

_1

Q4_4_1

R1

4_

4_

1

Q9_4_1

R18_4_1

Q6_1_1 Q10_1_1

R1

2_

4_

1

R17_5_1

Q7_5_1

R1

3_

5_

1

Q3_5_1

R1

1_

5_

1C

7_

5_

1

R9

_5

_1

R7

_5

_1

R8

_5

_1

R1

0_

5_

1

C8

_5

_1

Q4_5_1

R1

4_

5_

1

Q9_5_1

R18_5_1

Q6_1_1 Q10_1_1

R1

2_

5_

1

R17_6_1

Q7_6_1

R1

3_

6_

1

Q3_6_1

R1

1_

6_

1C

7_

6_

1

R9

_6

_1

R7

_6

_1

R8

_6

_1

R1

0_

6_

1

C8

_6

_1

Q4_6_1

R1

4_

6_

1Q9_6_1

R18_6_1

Q6_1_1 Q10_1_1

R1

2_

6_

1

R17_7_1

Q7_7_1

R1

3_

7_

1

Q3_7_1

R1

1_

7_

1C

7_

7_

1

R9

_7

_1

R7

_7

_1

R8

_7

_1

R1

0_

7_

1

C8

_7

_1

Q4_7_1

R1

4_

7_

1

Q9_7_1

R18_7_1

Q6_1_1 Q10_1_1

R1

2_

7_

1

R17_8_1

Q7_8_1

R1

3_

8_

1Q3_8_1

R1

1_

8_

1C

7_

8_

1

R9

_8

_1

R7

_8

_1

R8

_8

_1

R1

0_

8_

1

C8

_8

_1

Q4_8_1

R1

4_

8_

1

Q9_8_1

R18_8_1

Q6_1_1 Q10_1_1

R1

2_

8_

1

R17_1_2

Q7_1_2

R1

3_

1_

2

Q3_1_2

R1

1_

1_

2C

7_

1_

2

R9

_1

_2

R7

_1

_2

R8

_1

_2

R1

0_

1_

2

C8

_1

_2

Q4_1_2

R1

4_

1_

2

Q9_1_2

R18_1_2

Q6_1_1 Q10_1_1

R1

2_

1_

2

R17_2_2

Q7_2_2

R1

3_

2_

2

Q3_2_2

R1

1_

2_

2C

7_

2_

2

R9

_2

_2

R7

_2

_2

R8

_2

_2

R1

0_

2_

2

C8

_2

_2

Q4_2_2

R1

4_

2_

2

Q9_2_2

R18_2_2

Q6_1_1 Q10_1_1

R1

2_

2_

2

R17_3_2

Q7_3_2

R1

3_

3_

2

Q3_3_2

R1

1_

3_

2C

7_

3_

2

R9

_3

_2

R7

_3

_2

R8

_3

_2

R1

0_

3_

2

C8

_3

_2

Q4_3_2

R1

4_

3_

2

Q9_3_2

R18_3_2

Q6_1_1 Q10_1_1

R1

2_

3_

2

R17_4_2

Q7_4_2

R1

3_

4_

2

Q3_4_2

R1

1_

4_

2C

7_

4_

2

R9

_4

_2

R7

_4

_2

R8

_4

_2

R1

0_

4_

2

C8

_4

_2

Q4_4_2

R1

4_

4_

2

Q9_4_2

R18_4_2

Q6_1_1 Q10_1_1

R1

2_

4_

2

R17_5_2

Q7_5_2

R1

3_

5_

2

Q3_5_2

R1

1_

5_

2C

7_

5_

2

R9

_5

_2

R7

_5

_2

R8

_5

_2

R1

0_

5_

2

C8

_5

_2

Q4_5_2

R1

4_

5_

2

Q9_5_2

R18_5_2

Q6_1_1 Q10_1_1

R1

2_

5_

2

R17_6_2

Q7_6_2

R1

3_

6_

2

Q3_6_2

R1

1_

6_

2C

7_

6_

2

R9

_6

_2

R7

_6

_2

R8

_6

_2

R1

0_

6_

2

C8

_6

_2

Q4_6_2

R1

4_

6_

2

Q9_6_2

R18_6_2

Q6_1_1 Q10_1_1

R1

2_

6_

2

R17_7_2

Q7_7_2

R1

3_

7_

2

Q3_7_2

R1

1_

7_

2C

7_

7_

2

R9

_7

_2

R7

_7

_2

R8

_7

_2

R1

0_

7_

2

C8

_7

_2

Q4_7_2

R1

4_

7_

2

Q9_7_2

R18_7_2

Q6_1_1 Q10_1_1

R1

2_

7_

2

R17_8_2

Q7_8_2

R1

3_

8_

2

Q3_8_2

R1

1_

8_

2C

7_

8_

2

R9

_8

_2

R7

_8

_2

R8

_8

_2

R1

0_

8_

2

C8

_8

_2

Q4_8_2

R1

4_

8_

2

Q9_8_2

R18_8_2

Q6_1_1 Q10_1_1

R1

2_

8_

2



Annex 6 : component value ( component board side )

NE5532

10K

10NF

10µF

10µF 10µF 10µF 10µF

10µF

10µF10NF

30S6

UGB8T

HE10_34 HE10_34

10H

115

10H

115

10H

115

10H

115

10H

109

10H

109

10H

109

1KΩΩΩΩ

100Ω100Ω100Ω100Ω 100Ω100Ω100Ω100Ω 100Ω100Ω100Ω100Ω 100Ω100Ω100Ω100Ω

10H

115

10H

115

10H

115

10H

115

10H

109

10H

109

10H

109

100Ω100Ω100Ω100Ω 100Ω100Ω100Ω100Ω 100Ω100Ω100Ω100Ω 100Ω100Ω100Ω100Ω

10H

131

10H

131

10H

131

10H

131

10H

131

10H

131

10H

131

10H

131

10H

131

10H

131

10H

131

10H

131

10H

131

10H

131

10H

131

10H

131

10H

101

10H

101

10H

101

10H

101

10H

101

10H

101

10H

101

10H

101

10H

101

10H

101

10H

101

10H

101

10H

101

10H

101

10H

101

10H

101

32 x BFR93

16 x 10K ΩΩΩΩ

16 x 10K ΩΩΩΩ

16 x 10NF

16 x 10NF

16 x 10K ΩΩΩΩ

10KΩΩΩΩ HE10_20

HE10_20

HE10_10 HE10_10

10µF

10µF

EPM3256A

SN

10K

HT

5541

SN

10K

HT

5541

1KΩΩΩΩ

100ΩΩΩΩ

10K ΩΩΩΩ HE10_20

HE10_20

HE10_10 HE10_10

10µF

10µF

EPM3256A

SN

10K

HT

5541

SN

10K

HT

5541

1KΩΩΩΩ

100ΩΩΩΩ10H

131

10H

101

10NF10

H12

52 xHE10_2

HE10_2

HE10_2

HE10_2

HE10_2

10NF10NF

10H124 10H124 10H124

10H

124

2 x680ΩΩΩΩ

6 x 680ΩΩΩΩ

10H124 10H124 10H124

2 x680ΩΩΩΩ

6 x 680ΩΩΩΩ

10H

124

HE10_34

10H124 10H124 10H124

10H

124

2 x680ΩΩΩΩ

6 x 680ΩΩΩΩ

HE10_34

10H124 10H124 10H124

10H

124

2 x680ΩΩΩΩ

6 x 680ΩΩΩΩ

HE10_34

HE10_34

10H124 10H124 10H124

10H

124

2 x680ΩΩΩΩ

6 x 680ΩΩΩΩ

HE10_34

HE10_34

10H124 10H124 10H124

10H

124

2 x680ΩΩΩΩ

6 x 680ΩΩΩΩ

R19

LEMOSIMPLE

4 x LEMO DOUBLE

BFR93BFR93BFR93BFR93

BFR93

680ΩΩΩΩ

680ΩΩΩΩ

680ΩΩΩΩ

680ΩΩΩΩ

680ΩΩΩΩ

680ΩΩΩΩ

680ΩΩΩΩ680ΩΩΩΩ

680ΩΩΩΩ

680ΩΩΩΩ



Annex 7 : component value ( sold side )

1KΩΩΩΩ

100ΩΩΩΩ

16 x 10 NF

40 x 680 ΩΩΩΩ

16 x 10 K ΩΩΩΩ16 xBFR9316 x 100 ΩΩΩΩ16 x 10 ΩΩΩΩ16 x 15 pF

16 x 10 ΩΩΩΩ16 x 15 pF

16 xBFR9316 x 100 ΩΩΩΩ

16 x 10 NF16 x 680 ΩΩΩΩ

16 x 680 ΩΩΩΩ16 x 22 pF

32 x 680 ΩΩΩΩ32 x 680 ΩΩΩΩ

16 x 22 pF

16 x 680 ΩΩΩΩ

51 ΩΩΩΩ

32 xBFR93

MAX9691

MAX17931 KΩΩΩΩ

1 KΩΩΩΩ

1 K ΩΩΩΩ

10 KΩΩΩΩ

10 KΩΩΩΩ10 KΩΩΩΩ

10 KΩΩΩΩ

51 ΩΩΩΩ

MAX9691

MAX17931 K ΩΩΩΩ

1 K ΩΩΩΩ

1 KΩΩΩΩ

10 KΩΩΩΩ

10 KΩΩΩΩ10 KΩΩΩΩ

10 KΩΩΩΩ

10 NF 10 NF 10 NF 10 NF

10 NF

680 ΩΩΩΩ

10 NF 680 ΩΩΩΩ

680 ΩΩΩΩ680 ΩΩΩΩ

680 ΩΩΩΩ

1,2 KΩΩΩΩ 68 pF

68 pF

680 ΩΩΩΩ

680 ΩΩΩΩ

6 x 680 ΩΩΩΩ 6 x 680 ΩΩΩΩ

4 x 10 NF

4 x 10 NF

6 x 680 ΩΩΩΩ 6 x 680 ΩΩΩΩ

4 x 10 NF

4 x 10 NF

6 x 680 ΩΩΩΩ6 x 680 ΩΩΩΩ

10 NF10 NF10 NF 10 NF

18 x 680 Ω Ω Ω Ω et 8 x 10 nF 18 x 680 Ω Ω Ω Ω et 8 x 10 nF



10 NF

10 NF10 NF10 NF10 NF

680 ΩΩΩΩ

680 ΩΩΩΩ

680 ΩΩΩΩ680 ΩΩΩΩ680 ΩΩΩΩ

BFR93

BFR93

BFR93

BFR93BFR93



Annex 8 : bill of materials

Circuits logique :

MC10H101_dip 17

MC10H109_dip 6

MC10H115_dip 8

MC10H124_dip 24

MC10H125_dip 1

MC10H131_dip 17

MC10H158_dip 1

MC10192_dip 1

SN10KHT5541_dip 4

EPM3256A-10 PQF144 2

MAX1793 2

MAX9691 2

NE5532_dip 1

OPA656_SO 2

Transistor & diodes :

Transistor :

BFR 93 106

Diode :

30S6 1

UGB8BT 1

Résistances :

10 ( 1206 ) 32

51 ( 1206 ) 3

100 ( 1206 ) 35

330 ( 1206 ) 2

680 ( 1206 ) 398

1 K( 1206 ) 10

1,2 K( 1206 ) 1

10 K( 1206 ) 57

47 K( ¼ W ) 2

Reseau :

100 ( SIL8 ) 8

Potentiometre :

10 K ( 10 tours ) 4

Capacites :

10 NF ( 0805 ) 148

15 pF ( 0805 ) 32

22 pF ( 0805 ) 32

68 pF ( 0805 ) 2

10 MF 25V 7

10 MF 25V droites 4

Connecteurs :

HE10-2 male male 5

HE10-10 male male 4

HE10-20 male male 4

HE10_34 droit 6

HE10_34 coudes 2

HE10_34 à sertir 6

HE10_34 à sertir face avant ) 6

Strap 2,54 7

LEMO coude simple 1

LEMO coude double 4



Annex 9 : MC10192 data sheet ( ON semiconductor documentation )



Annex 10 : MC10H158 data sheet ( ON semiconductor documentat ion )



Annex 11 : OPA656 data Sheet ( Burr Brown documentation )



Annex 12 : Documentation update

Draft ( July 2005 ) : initial version

Version 1 ( August 2005 ) :

Annex : Generic pinout connector Modify name

« SPLITTER & TRIGGER » board Diagram ( Add MUX component MC10H158 ) Modify

Add Annex 3 : Board scheme Add

Add Annex 4 : board representation ( component side ) Add

Add Annex 5 : board representation ( sold side ) Add

Add Annex 6 : component value ( component board side ) Add

Add Annex 7 : component value ( sold side ) Add

Add Annex 8 : bill of materials Add

Correct “Switches and setting” chapter ( delay generator switch were wrong ) Modify

Add TABLE OF CONTENTS Add

Add data sheet MC10192, MC10H158, OPA656 component Add

Version 2 ( September 2005 ) :

Board scheme up to date Update

Version 3 ( October 2005 ) :

Upgrade the “SPLITTER & TRIGGER board diagram” chapter 3 Update

In Inputµ/output chapter ( chapter 2 ) add time duration of the MULTA MULTB signal Add

In Inputµ/output chapter ( chapter 2 ) add time duration of the TRIGGER0,TRIGGER1 signal Add



TABLE OF CONTENTS

1. Overview ......................................................................................................................................................................... 1

2. Input / output ................................................................................................................................................................... 1

3. « SPLITTER & TRIGGER » board Diagram.................................................................................................................... 2

4. « SPLITTER & TRIGGER » Front view........................................................................................................................... 3

5. Switches and setting ....................................................................................................................................................... 5

6. Board Power consumption .............................................................................................................................................. 5

6.1. Maximum Value :..................................................................................................................................................... 6

6.2. Typical Value : ......................................................................................................................................................... 7

7. DELAY_50 Component ................................................................................................................................................... 8

7.1. EPM3256A I/O and dedicated Pin-outs ................................................................................................................... 8

7.2. « DELAY_50 » Component pin report ..................................................................................................................... 8

7.3. « DELAY_50 » Component Pinout ........................................................................................................................ 10

7.4. « DELAY_50 » VHDL description.......................................................................................................................... 11

Annex 1 : board picture ..................................................................................................................................................... 13

Annex 2 : Generic pinout connector .................................................................................................................................. 14

Annex 3 : Board scheme................................................................................................................................................... 15

Annex 4 : board representation ( component side ) .......................................................................................................... 20

Annex 5 : board representation ( sold side )...................................................................................................................... 21

Annex 6 : component value ( component board side ) ...................................................................................................... 22

Annex 7 : component value ( sold side ) ........................................................................................................................... 23

Annex 8 : bill of materials .................................................................................................................................................. 24

Annex 9 : MC10192 data sheet ( ON semiconductor documentation ) ............................................................................. 25

Annex 10 : MC10H158 data sheet ( ON semiconductor documentation ) ......................................................................... 26

Annex 11 : OPA656 data Sheet ( Burr Brown documentation )......................................................................................... 27

Annex 12 : Documentation update .................................................................................................................................... 29

splitter trigger board - board which split a bus of 32

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