sse 2010-soi versus bulk-silicon nanoscale finfets

8/3/2019 SSE 2010-SOI Versus Bulk-silicon Nanoscale FinFETs

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SOI versus bulk-silicon nanoscale FinFETs

Jerry G. Fossum a,*, Zhenming Zhou a, Leo Mathew b, Bich-Yen Nguyen c

a Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL 32611-6130, USAbApplied Novel Devices, Inc., Austin, TX 78717, USAc Soitec USA, Inc., Austin, TX 78746, USA

a r t i c l e i n f o

Article history:Received 20 April 2009

Received in revised form 4 July 2009

Accepted 20 August 2009

Available online 23 December 2009

The review of this paper was arranged by

Prof. O. Engstrm

Keywords:

Double-gate MOSFET

Nanoscale CMOS

Pragmatic FinFET

a b s t r a c t

Our previously proposed concept of pragmatic FinFET design is overviewed, with new insights given,prior to presenting results of an assessment of nanoscale FinFETs on SOI versus bulk silicon (Si). The

assessment is supported by 3-D numerical simulations of FinFETs for a comparison of the electrical prop-

erties of the SOI and bulk-Si FinFETs, and it includes a discussion of serious processing issues for the lat-

ter. The SOI FinFET is thereby suggested to be viable, whereas the bulk-Si FinFET (as currently defined) is

not.

2009 Elsevier Ltd. All rights reserved.

1. Introduction

The quasi-planar FinFET, illustrated in Fig. 1 on SOI, will most

likely become the mainstream CMOS device in the future, enabling

the technology to be scaled to the end of the SIA ITRS (roadmap) [1]

where gate lengths (Lg) are projected to be


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The noted bulk inversion is significant for strong- as well as

weak-inversion conditions [8]. It is a result of the (relatively) low

transverse electric field in the undoped (symmetric) DG FinFET.

Whereas it can thus lead to increased mobilities, it is predomi-

nantly a negative effect in undoped channels since it reduces the

effective gate capacitance (CG) in strong inversion, and hence low-

ers Ion. This effect can be characterized (classically, for low VDS) by

integrating Poissons equation over half of the Si body/channel

thickness (tSi), and expressing the (total) inversion charge density(for an n-channel DG FinFET) as [13]

Qi 2Cox

1 eoxxi

eSitox

2664

3775VGS Vt 1

where Cox = ox/tox is the oxide capacitance (per unit area) and xi is

theaverage depth of theinversion electrons in each half of thechan-

nel. Bulk inversion increases xi and thereby lowers the inversion-

layer capacitance, yielding lower Qi, CG [the (VGS Vt) coefficient

in (1)], and Ion. And, energy-quantization further increases xi. We

note from (1) that bulk inversion in the FinFET also renders Qi less

dependent on the oxide thickness tox. This is why keeping tox prag-

matically thick, and avoiding a high-k dielectric [9], is not so detri-mental to CG and Ion, and is thus feasible for the nanoscale FinFET.

Further, thicker SiON reduces parasitic GS/D fringe capacitance

[14], which can improve speed performance significantly [3,9].

The GS/D underlap [10], which yields Leff > Lg in weak inversion

for control of short-channel effects (SCEs), while Leffffi Lg in strong

inversion, is crucial for ultimate undoped FinFET-CMOS scaling.

Further, it reduces parasitic GS/D fringe capacitance [14], and

can enable device design flexibility for different applications, e.g.,

SRAM [15]. As illustrated and explained in Fig. 2, the underlap is

effected by design of the lateral doping profile in the S/D exten-

sions, NSD(y), which must be controlled in the S/D processing. This

processing must also be defined to retain high mobilities for short

Lg [11]. And, we note a third significance of this processing and

NSD

(y). Limited S/D dopants can be allowed in the channel, near

the S/D extensions, for Vt adjustment [12]. The key to such design

is that the weak-inversion Vt, which correlates with Ioff, depends

on NSD near the center of the channel, whereas the strong-inver-

sion Vt, which correlates with Ion, depends on the average of NSDover the entire channel. Thus, a low-power FinFET design, with

negligible NSD throughout the channel, would give high Vt and long

Leff for low Ioff, all relative to a high-performance FinFET design,

with negligible NSD near the center of the channel but significant

NSD near the ends of the channel, for lower Vt, shorter Leff, and high-

er Ion, without significant Ioff sensitivity to NSD [12].

3. SOI versus bulk Si

Future FinFETs on bulk Si [4,5] are of interest mainly because oflower wafer cost. However, this advantage must be traded-off with

possible disadvantages of the bulk-Si FinFET associated with the

fabrication process as well as the electrical performance. To assess

the viability of bulk-Si FinFETs, we first use 3-D numerical simula-

tions to compare their electrical properties with those of SOI Fin-

FETs, assuming quasi-controlled processing, and then we check

the effects of the real, non-pragmaticprocessing on bulk Si.

3.1. Electrical properties

We use Taurus [16] for 3-D simulations of nanoscale SOI and

bulk-Si nFinFETs (Lg = 28 nm, wSi = 14 nm, hSi = 56 nm, tox = 1 nm,

undoped UTB, midgap gate), as illustrated in Fig. 3. For the bulk-

Si device, we use the Taurus domain shown in Fig. 4, and we focus

on the lower, ungated part of the Si fin, which can result in signif-

icant SD punch-through if left undoped (like the upper fin-chan-

nel). For punch-through stopping (PTS), we assume a uniform

25 35 45 55 65 75 85 95

y [nm]

1015

1016

1017

1018

1019

1020

NSD[

cm

-3]

LgateLext Lext

y

LeSD

Leff

NSD(y)

LeSD

L Abrupt NSD(y)

LeSDw/ LeSD=0

Abrupt NSD(y)

w/ effectiveLeSD0

Fig. 2. Illustrationof how varying the lateral doping density profile NSD(y) inthe S/D

extensions of the undoped DG FinFET changes the weak-inversion effective channel

length, as characterized by the effective GS/D underlap LeSD indicated. The SCEs aregoverned by LeSD, which is defined (implicitly) by the peak doping density in the S/

D, the (gaussian) NSD(y) straggle rL (that defines the degree of penetration of S/D

dopants into the extensions), the extension length Lext, and the fin width wSi, as

described in [10] and [15].

Gate

SiO2

Si Substrate

BOX

Si Fin

SOI FinFET

Lower

Fin

Gate

SiO2

Si Substrate

Isolation

Oxide

x

z

wSi

hSi

Bulk-Si FinFET

Fig. 3. The basic structures of the SOI and bulk Si FinFETs, viewed along the

channels. The lower, ungated portion of the bulk-Si fin is indicated, as are thedimensions of the gated fin (which are the same for both devices).

n+

Source

n+

Drain

Gate

n+

Source

n+

Drain

Gate

BOX

Fig. 1. The basic quasi-planar nFinFET structure on SOI.

J.G. Fossum et al. / Solid-State Electronics 54 (2010) 8689 87


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p-type doping density (NAL) in the lower fin, under the S-UTB-D

structure as noted in Fig. 4. Also, we allow for possible over-diffu-

sion of the S/D junctions (Dzj) into the PTS region as indicated in

Fig. 4. The Ioff predictions plotted in Fig. 5, versus NAL for varying

Dzj, reflect the significance of punch-through leakage current for

low NAL and finite Dzj. A realistic, finite Dzj > 0, which results in a

direct SD punch-through path under the channel, clearly necessi-

tates an optimal NAL$ 1018 cm3 to stop the punch-through. How-

ever, the PTS doping, assumed to underlie the S/D regions as well as

the fin-UTB as noted, results in significant drain-junction tunneling

current for NAL > 1018 cm3 as evident in the figure. Control of NAL

is thus crucial, and this portends a significant doping-sensitivity is-

sue for the bulk-Si FinFET. Of course, this is not an issue for SOI Fin-

FETs because of the underlying BOX.

Another issue for the bulk-Si FinFET is the possible up-diffusion

of the underlying PTS doping into the fin-channel. Simulations,

based on assumed gaussian NAL(z) profiles, show, in Fig. 6, that

the up-diffusion, for typical vertical straggle (rV), effectively re-

duces hSi (the gate width), and hence increases Vt and lowers Ion

relative to the SOI FinFET. Note also that similar effects will occur

for under-diffusion of the S/D junctions, i.e., ifDzj < 0. Further, up-

diffusion of the PTS doping into the S/D extensions, as well as the

channel, can undermine control of NSD(y), and hence of the GS/D

underlap, the adjusted Vt, and possibly carrier mobility as we dis-

cussed in Section 2.

The speed performance of bulk-Si-FinFET CMOS is degraded by

the added S/D-junction capacitance due to the PTS doping, but not

excessively. For 28 nm devices designed as noted, with optimal PTS

doping, UFDG [17]/Spice3 ring-oscillator simulations predict only

about a 5% increase in delay relative to the counterpart SOI-FinFET

CMOS.

3.2. Processing issues

Whereas the noted electrical properties (at least for assumed

quasi-controlled processing) of the bulk-Si FinFET do not clearly

negate its viability, we believe that the processing issues do. Con-

trol of the fin and isolation-oxide heights require multiple pro-

cesses not needed for the SOI FinFET. And, clearly, the processing

needed to get optimal NAL (Fig. 5) in the lower fin, with minimal

Dzj and the needed isolation oxide (Figs. 3 and 4), is very complex

relative to that of the pragmatic SOI FinFET. For the current imple-

mentation proposed for the bulk-Si FinFET [4,5], the PTS implant

should be nearly vertical for tight fin pitch, necessitating subse-

quent lateral dopant diffusion under the fin and up the lower finduring anneal. Direct implant to the base of the fin through the

channel results in prohibitive doping in the channel due to subse-

quent anneals and finite straggle in the profile. Clearly, the reliabil-

ity of the noted multi-directional PTS diffusion in a nanoscale

structure is questionable (like that of the channel doping which

is now stopping conventional bulk-Si CMOS scaling); the resulting

NAL in the lower fin, and in the fin-channel, will be random. Fur-

ther, this randomness is exacerbated by varying fin features for dif-

ferent applications on a CMOS chip (e.g., for SOC design). For

example, Fig. 7 illustrates how the efficacy of the PTS implant/dif-

fusion process depends on the fin width (wSi). Clearly, the same

process, which is hardly viable for fixed wSi, cannot be used for dif-

ferent wSi. Thus, since varying wSi is desirable (and even essential)

in different applications to enable different oxide thickness (with-out undermining tSi) or variable SCE control (via wSi/Lg) for Vt and

Fig. 4. The Taurus 3-D domain assumed for the bulk-Si FinFET. The lower fin is

doped uniformly (NAL for PTS, which is p-type for the nFinFET) everywhere under

the S-UTB-D structure. The possible S/D-junction over-diffusion (Dzj) into the PTS

region is indicated; under-diffusion is also possible, for which Dzj < 0.

1015 10

1610

1710

1810

19

10-10

10-9

10-8

10-7

10-6

10-5

zj=0nm

zj=6nm

zj=10nm

NAL (cm-3)

Ioff

(A/fin)

Fig. 5. Taurus-predicted off-state current in the 28 nm bulk-Si nFinFET, versus theunderlying PTS doping density and the S/D over-diffusion.

20

40

60

80

100

120

Ion(bulk)/Ion(SOI)(%)

0 5 10 15

V (nm)

0

20

40

60

80

100

Vt(mV)

NAL=1e18cm-3

NAL=1e19cm-3

Fig. 6. Taurus-predicted increase in threshold voltage and decrease in on-state

current in the bulk-Si FinFET, relative to Vt and Ion of the SOI FinFET, versus the

vertical straggle rV of the PTS doping for two different underlying peak doping

densities. The values of NAL indicated are the peak, uniform densities in the

underlying PTS region, and rV defines the assumed gaussian upward fall-off of the

doping density in the fin-channel.

88 J.G. Fossum et al./ Solid-State Electronics 54 (2010) 8689


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Ion/Ioff adjustment, SOC design with bulk-Si FinFETs is severely

limited.

Other bulk-Si-FinFET processing issues relate to etching the fin

and the deposited isolation oxide, and its effects on the device per-

formance. The bulk-fin height must exceed the SOI-fin hSi signifi-

cantly because of the need for the isolation oxide (Figs. 3 and 4).

The fin is thus unavoidably tapered, implying uncontrolled wSi,

and control of the gated fin height (hSi

) is undermined by tapering

of the oxide up the fin, as illustrated in Fig. 8. Control ofhSi and wSiin SOI FinFETs is much easier.

4. Summary

We summarize briefly with two educated, personal opinions

that follow from our study described herein.

(1) The pragmatic DG FinFET on SOI is viable, and is potentially

scalable to the end of the SIA roadmap (where Lg < 10nm).

(2) The bulk-Si FinFET (as currently defined) is not viable.

(3) We further note that the FinFET-on-SOI technology, as

opposed to on bulk Si, will enable integration of floating-

body (e.g., 1T) DRAM [18], which can be a viable, essential

embedded memory technology in the future.

Acknowledgment

This work was supported in part by Soitec.

References

[1] The international technology roadmap for semiconductors. Austin (TX):

Semiconductor Industry Assoc.; 2005.

[2] Fossum JG. Physical insights on nanoscale multi-gate CMOS design. In:

EUROSOI 2006 Conf Proc; March 2006. p. 112.

[3] Fossum JG. Physical insights on nanoscale multi-gate cmos design. Solid-State

Electron 2007;51(February):18894.

[4] Okano K et al. Process integration technology and device characteristics ofCMOS FinFET on bulk silicon substrate with sub-10 nm fin width and 20 nm

gate length. IEDM Tech Dig 2005(December):73942.

[5] Inaba S et al. Direct evaluation of DC characteristic variability in FinFET SRAM

cell for 32 nm node and beyond. IEDM Tech Dig 2007(December):48790.

[6] Chowdhury MM, Trivedi VP, Fossum JG, Mathew L. Carrier mobility/transport

in undoped-UTB DG FinFETs. IEEE Trans Electron Dev 2007;54(May):112531.

[7] Chouksey S, Fossum JG. DICE: a beneficial short-channel effect in nanoscale

double-gate MOSFETs. IEEE Trans Electron Dev 2008;55(March):796802.

[8] Kim S-H, Fossum JG, Trivedi VP. Bulk inversion in FinFETs and implied insights

on effective gate width. IEEE Trans Electron Dev 2005;52(September):19937.

[9] Agrawal S, FossumJG. On the suitability of a high-kgate dielectric in nanoscale

FinFET-CMOS technology. IEEE Trans Electron Dev 2008;55(July):17149.

[10] Trivedi V, Fossum JG, Chowdhury MM. Nanoscale FinFETs with gate-source/

drain underlap. IEEE Trans Electron Dev 2005;52(January):5662.

[11] Cros A et al. Unexpected mobility degradation for very short devices: a new

challenge for CMOS scaling. IEDM Tech Dig 2006(December):6636.

[12] Chouksey S et al. Threshold voltage adjustment in nanoscale DG FinFETs via

limited source/drain dopants in the channel. IEEE Trans Electron Dev

2009;56(October):234853.[13] Lpez-Villanueva JA et al. Effects of inversion-layer centroid on the

performance of double-gate MOSFETs. IEEE Trans Electron Dev

2000;47(January):1416.

[14] KimS-H, FossumJG, Yang J-W. Modeling andsignificanceof fringe capacitance

in nonclassical CMOS Devices with gate-source/drain underlap. IEEE Trans

Electron Dev 2006;53(September):214350.

[15] Kim S-H, Fossum JG. Design optimization and performance projections of

double-gate FinFETs with gate-source/drain underlap for SRAM application.

IEEE Trans Electron Dev 2007;54(August):193442.

[16] Taurus-2006. Users manual. Durham (NC): Synopsys, Inc.; 2006.

[17] UFDG-3.7. Users guide. Florida: SOI group, Univ.; 2007.

[18] Okhonin S et al. Ultra-scaled Z-RAM cell. IEEE Int SOI Conf Proc

2008:1578.

Fig. 7. Illustrations of how the efficacy of the PTS implant/diffusion in a bulk-Si

FinFET depends on fin width (wSi), showing that a universal process for different

applications on a chip (i.e., SOC) cannot be utilized.

Fig. 8. Illustration of issues relating to etching the fin and the isolation oxide of the

bulk-Si FinFET. Control of the gated fin is undermined by variations in the isolation

oxide between fins and by tapering of the oxide up the fin.

J.G. Fossum et al. / Solid-State Electronics 54 (2010) 8689 89

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