cmos scaling beyond finfets: nanowires and tfets · • better electrostatic control • multiple...
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Accelerating the next technology revolution
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CMOS Scaling Beyond FinFETs: Nanowires and TFETs
Chris Hobbs, Wei-Yip Loh, Kerem Akarvardar, Paul Kirsch, and Raj JammyJune 22, 2010
SEMATECH SymposiumJune 23, 2011
Tokyo
Outline
• Advanced CMOS Scaling Overview• Nanowires• TFETs• Summary
14 June 2011 2
14 June 2011 3
Device scaling optionsI d
,sat
Vg
14 June 2011 4
Device scaling optionsI d
,sat
Vg
14 June 2011 5
Device scaling options
• Very high mobility/high injection velocity• SiGe, Ge, InGaAs• Graphene [e ~15000 cm2/V-s at RT]
I d,s
at
Vg
1
14 June 2011 6
Device scaling options
• Very high mobility/high injection velocity• SiGe, Ge, InGaAs• Graphene [e ~15000 cm2/V-s at RT]
• Better electrostatic control• Multiple gates + more channel area• FinFETs, nanowire FET
12
I d,s
at
Vg
Why are Multi-Gates beneficial?
• Thin silicon channel with gate on both sides helps maintain channel control.
Gate
Well
Source DrainExtensionHalo
Channel
Source and drain are much closer…Gate looses control of channel region
Conventional MOSFET Scaling to improve performance
Source Drain
Dou
ble
Gat
e D
evic
e
Gates on both sides
ThinSiliconChannel
Sing
le G
ate
Dev
ice
GateFinFET
Si Wafer Surface
Gate can’t control down here, so drain leaks to source
Fin
Drain
Source
714 June 2011
Lg
Source Drain
GateNanowire
Drain
Source
4-G
ate
Dev
ice
Performance and power tradeoff
8
Typical Ion-Ioff for CMOSFETs
• Same transistor with specifications tuned for performance or power @ cost.14 June 2011
Performance and power tradeoffAll F
ace T
rans
istor
Sca
ling I
ssue
s (ne
ed ne
w
materia
ls/ar
chite
cture
s/nov
el pr
oces
ses)
9
Typical Ion-Ioff for CMOSFETs
• Same transistor with specifications tuned for performance or power @ cost.14 June 2011
MOSFET scaling trends
2009 2009 2011 2013 2015
Planar
Non planar2007
High-K45nm
(Production)Intel IEDM 2009
32nm
(Production)Intel IEDM 2007
Nano-wire(LETI IEDM’08)
NXP FINFET, VLSI 2007
Intel Tri-Gate, VLSI 2006
SEMATECH, IEDM 2009
IBM, IEDM 2009 6nm LengthB. Doris IEDM 2002
22nm? 16nm?
Si-Ge Device
SEMATECH, VLSI 2009
New materialsIII-V Device
12nm+
Intel, IEDM 2007,9
SEMATECH, IEDM 2010
• Past: Performance improved by scaling device dimensions.
• Now: Performance improved by Novel Materials and Architectures.
• Planar CMOS and Beyond:A continuous spectrum of devices.
14 June 2011 10
Non-planar devicesMotivation:
– Gate wrap-around helps control short channel effects in scaled devices
– High mobility channels enables higher drive currents
High w and w/o 3rd gate ?
High Bulk vs SOI
OR
OR
Scaling Pathways
Hom
gene
ous
Het
erog
eneo
us
11
Si
SiN HM
TiNHfO2
BOX
14 June 2011
Critical FinFET/Trigate/Nanowire Modules
Fin Scaling and smoothness Gate etchSource/Drain
SEG, doping and silicide
Group IVchannel material
Spacer etch and process schemes
Processing and integration
FinFET/Trigate
Si
SiSiGe SiGe
SiGe SiGeSi
BOXSi
Processingandintegration
Nanowire
NW Scaling and smoothness
Group IVchannelmaterial
Gate etchSource/Drain SEG, doping and silicide
Spacer etch and process schemes
• Most nanowire module issues are similar to FinFET module issues with added degree of integration complexity.
1214 June 2011
Silicon Nanowires
450 nm
Wmask = 50 nm
450 nmsource
drain
suspended wires
Wmask = 50 nm
VGS (V)
I D(A
/um
)
Single Si Nanowire Silicide Data
10 nm10 nm
SiMGHiK
|VD| = 50 mV|VD| = 1 V
NFETPFET
Gate length = 40 nmNW width = 50 nmNW height = 20 nm
14 June 2011 13
Lmask (nm)
DIB
L (V
/V)
Sw
ing
(V/d
ec)
Omega GateFinFET
VDS = -50 mV
Gate wraparound improves rolloff
• Nanowire device has smaller rolloff compared to FinFET.– Wrapping gate around channel
improves short channel control.
• Long channel SS is similar for Omega-Gate and FinFET.– Vdd scaling limited by SS.– Different device structure needed
to reduce Vdd. TFET!
• Gate-All-Around (GAA) Device:– Total current in nanowire limited
by crossectional area.– Multiple GAA nanowires to meet
ITRS targets.– In contrast, total current in FinFET
can be increased with taller fins.
Si
SiN HM
TiNHfO2
BOX
14 June 2011 14
PFET
PFET
14 June 201114 June 2011
Stacked Si nanowire formation using SiGe
200 nm200 nm
BOX
Si
SiSiGe
SiSiGe
SiSiNPt
SiSiGe
SiSiGe
Si
BOX
BOXSiSi
Si
SiGe
SiGe
BOXSi
Si
SiSiGe
SiGe
Si
Si
Si
SiGe
SiGe
Suspended NWs
SiGe/Si Superlattice Fin etch Selective SiGe etch
• Stacking nanowires helps increase total drive current to meet ITRS targets.15
High mobility SiGe FinFETs/nanowires
• SiGe PFETs have higher mobility than Si fins.• Potential for performance > strained Si in non-planar devices
Extracted bySplit CV Method
0 1x1013 2x10130
50
100
150
200
250
300
350 SiGe {110}<110> SiGe {100}<100> Si {110}<110> Si {100}<100> (100) universal
eff (c
m2 /V
-s)
NINV (#/cm3)
(110)
(100)
Si fin (Tinv = 1.2nm)
SiGe fin (Tinv= 1.8nm)
Universal (100)
shell/core fin (Tinv=1.5nm)
14 June 2011 16
Outline
• Advanced CMOS Scaling Overview• Nanowires• TFETs• Summary
14 June 2011 17
14 June 2011 18
Device scaling options
• Very high mobility/high injection velocity• SiGe, Ge, InGaAs• Graphene [e ~15000 cm2/V-s at RT]
• Better electrostatic control• Multiple gates + more channel area• FinFETs, nanowire FET
• Improve on-off ratio• Tunnel FET
• Very steep ∆SS << 60 mV/dec• Low bias voltages (<< 1V)
• Nano Electro Mechanical switch (NEMS)• Hybrid: Ion by CMOS + Ioff by NEMS• Zero Leakage Power
12
I d,s
at
Vg
14 June 2011 19
Device scaling options
• Very high mobility/high injection velocity• SiGe, Ge, InGaAs• Graphene [e ~15000 cm2/V-s at RT]
• Better electrostatic control• Multiple gates + more channel area• FinFETs, nanowire FET
• Improve on-off ratio• Tunnel FET
• Very steep ∆SS << 60 mV/dec• Low bias voltages (<< 1V)
• Nano Electro Mechanical switch (NEMS)• Hybrid: Ion by CMOS + Ioff by NEMS• Zero Leakage Power
12
3
I d,s
at
Vg
(P. Packan (Intel), 2007 IEDM Short Course)(B. Meyerson et al., , IBM, Semico Conf., 2004)
• Passive power has shown continuous increase due to VDD scaling limit.• VCC scaling limited by VT and subthreshold slope (which is kT/q limited)
need “green” devices not governed by kT/q ~ 60mV/dec limit.
Pow
er D
ensi
ty (
W/c
m2 )
1E-05
1E-04
1E-03
1E-02
1E-01
1E+00
1E+01
1E+02
1E+03
0.01 0.1 1Gate Length (μm)
Passive Power Density
Active Power Density
VCC scaling for “green” electronics
14 June 2011 20
Working mechanism of TFET
0.0 0.2 0.4 0.6 0.8 1.0
Log
I D
0.0 0.2 0.4 0.6 0.8 1.0
Log
I D
MOSFET
Band-to-Band Tunneling, SS < 60mV/dec
)exp( GSdepox
oxDS V
kTq
CCCI
Ec
Ev
COX
CDEP
φS
VG
20 30 40 50 60 70-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
ON
Ener
gy [
eV]
X [nm]
OFF
LowION
HighIOFF
TFET
EC
EV
14 June 2011 21
OperationRange
MOSFET:• For Narrow On/Off
Voltage Range:– Low Ioff Low Ion– High Ion High Ioff
• Electrons go over thermionic energy barrier
• Boltzmann distribution of carriers causes leakage.
TFET:• Carriers go through
the energy barrier.
Several types TFETs with Si PIN, Metal Schottky PIN and Si-pocket PIN have been demonstrated.
Ultra-low subthreshold of < 50 mV/dec has been achieved over 103 order of drive current.
Very Low SS, need more Ion.
Si PIN tunneling FETs
14 June 2011 22
-2.0 -1.5 -1.0 -0.5 0.010-1410-1310-1210-1110-1010-910-810-710-610-5
I D [
A/u
m]
VG [V]
46mV/dec-2.0 -1.5 -1.0 -0.5 0.00
1x10-6
2x10-6
3x10-6
4x10-6
5x10-6
VG=-1.0V
VG=-1.5V
VD [V]
VG=-2.0V
SEMATECH-UCB DARPA STEEP Project
ND activation for high Ion Si TFET
Lg = 56nmSiNspacer
Metal gate
NiSiNiSi 80nm Si
High-K
n+
p+
Lg = 56nmSiNspacer
Metal gate
NiSiNiSi 80nm Si
High-K
n+
p+
-2.0 -1.5 -1.0 -0.5 0.0 0.510-9
10-8
10-7
10-6
10-5
10-4
10-3 Experimental Sim. Overlap 10nm Sim. Overlap 5nm Sim. Overlap 0nm
I D (
A/
m)
Vgate-VBT (V)
-0.2 0.0 0.2 0.4 0.610-11
10-10
10-9
10-8
10-7
10-6
I drai
n (A
/m
)
Vds (V)
Temp = 213K~313Kin step of 20K
Lg ~ 46 nmVg = 0V
IThermonicITunnel
• Highest Ion (~ 109 A/m)at Vcc = 1.0V for Si TFET using optimized flash anneal for Nd activation.
• Good Ion, poor SS.[1] IEDM Tech. Dig. 2009, p.949. [2] IEDM Tech. Dig.2008, p. 947. [3] IEDM Tech. Dig. 2008, p. 163. [4] IEEE Trans, ED., vol 51(2), p. 279, 2004. [5] IEEE EDL, vol. 28(8), p. 743, 2007. [6] 40th ESSDERC 2010, p162
References Channel Material
SS (mV/dec) @ RT
Ion1
(A/m) Vds (V) Ion/Ioff1
S. Mookerjea [1] InGaAs 150~290 20 0.75 > 103
T. Krishnamohan [2] Ge 50 ~ 60 10 1.00 106
T. Krishnamohan [2] Si 460 10-4 1.00 > 102
F. Mayer [3] Ge >400 4 0.80 > 102
F. Mayer [3] Si 42 ~ 200 0.04 0.80 105
K. K. Bhuwalka [4] Si 285 0.1 1.50 104
W. Y. Choi [5] Si 52.8 12* 1.00 104
84 0.70 >105
109 1.00 >104
1Ion is taken at overdrive of Vg-VBT = 2.0V except for *. Ioff taken at onset of BT-BT, VBT
120 ~ 250This work Si[6]
14 June 2011 23
SEMATECH-UCB ESSDERC 2010
Eg engineering : H-TFET• Effective Eg can be engineered by
using heterostructure (e.g. Ge on Si)• Ge % from 25 ~ 50% Bandgap
engineering to enhance tunneling• Abrupt doping gradient by in-situ B-
doped SiGe and post annealing
g g g g
Much lighter Hole mass
Ec offset and bandgap narrowing for high tunneling
14 June 2011 24
Heterostructure TFET
Gate
Heterostructure TFET
Gate p+Ge(Source)
n+ Si(Drain)
i-Si
SEMATECH-UCB DARPA Joint Project
III-V tunnel FETs
• Tunneling is a strong function of bandgap.
• III-V has smaller bandgap and heterostructures (e.g. InAs/AlxGa1-xSb)have staggered or even zero bandgap direct tunneling.
• Preliminary InGaAs TFETs results indicates further optimization is needed to improve the poor SS, high Ioff, high Dit and poor Rco.
(Ge) Eg=0.69eV, Vd=0.5V
Dra
in C
urre
nt
(A/µ
m)
1E-03
0.0 0.2 0.4 0.6 0.8 1.0
(InAs) Eg=0.36eV, Vd=0.2V
(Si) Eg=1.1eV, Vd=1V
Gate Voltage (V)
1E-06
1E-09
[C. Hu et al, VLSI-TSA, pp.14-15, 2008]
-2.0 -1.5 -1.0 -0.5 0.0 0.51011
1012
1013
CB edge
Vgate (V)
Dit (#
/cm
2 /eV
n-Typep-Type
VB edge
In0.53GaAs
High Dit
-1.0 -0.5 0.0 0.5 1.010-7
10-5
10-3
10-1
101
103
1st lot 2nd lot
I diod
e (A
/cm
2 )
Vdiode (V)
n+i-p+ In0.53GaAs Diodes
Junction Leakage
14 June 2011 25
Novel design: pocket structure TFET
• Large field, good capacitive coupling btw gate & pocket• Abrupt turn-on due to overlap of valence/conduction bands• Tunable turn-on voltage
N+ Source P+ Drain
Buried Oxide
P+ Pocket
P-
[ C. Hu et al, VLSI-TSA, April, 2008 ]
14 June 2011 26
Dopant-segregated Si-pocket TFET
• Achieved sub-60 mV/dec (46mV/dec) with 30% dies showing sub-60mV/dec Si TFET with high-K/MG
0.00.10.20.30.40.50.60.70.80.9
20 60 100 140 180 220
Schottky-Source P-I-N
Subthreshold Swing [mV/dec]
Prob
abili
ty
Silicon TFETSilicon TFET
-1.5 -1.0 -0.5 0.010-1410-1310-1210-1110-1010-910-810-710-610-510-4
Measured Sim. w/ pocket Sim. no pocket
I D [
A/
m]
VG [V]
Gate
SiNiSi
BOX N+< Pocket >
Gate
SiNiSi
BOX N+< No Pocket >
100nm
BOX
NiSi
Gate
SiNiSi
BOX
N+Gate
SiNiSi
BOX
N+
14 June 2011 27
SEMATECH-UCB VLSI Symp. 2010
S-MLD pocket InGaAs pocket TFETs
0 .5 1 .0 1 .5 2 .0
1
2
3
4
C o n tro l
PV
CR
V g a te (V )
p o cke t
3 0 0 K
• N+/p- pocket structure achieved on InGaAs TFET.
• Enhanced drive current obtained due to enhanced vertical field at gated pocket n-p+ junction.
• Improved gate coupling and Dit observed.
-1.0 -0.5 0.0 0.5 1.010-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
Vg-VBT = 0.2 V to 1.5 Vin step of 0.1 V
I drai
n (A/
m
Vdrain (V)
Lg = 100 nm
Control
-2.0 -1.5 -1.0 -0.5 0.0 0.51011
1012
1013
CB edge
Control Pocket
Vgate (V)
Dit (#
/cm
2 /eV
n-Typep-Type
VB edge
N+P++ P+
n+AlOx
Tunneling Front P++ P+ N+
AlOx
Control TFETTFET with pocket
i i
14 June 2011 28
Simulation of TFETs
0.0 0.2 0.4 0.6 0.8 1.010-11
10-9
10-7
10-5
10-3
Si TFET Ge TFET Si MOSFET
Ge/Sipocket [1]
Ge-sourceSi NW [3]
Ge NW [3]
Ge UTB [4]
Si PNPN [5]
Si pocket [1]
Gepocket [1]
I drai
n (A/
m
Vgate (V)
s-Ge/s-Si [2]
60 mV/dec
Si NW [3]
Intel 32nm LPIEDM 2009 [9]
IV TFETs (Simulation) IIIV TFETs (Simulation)
[1] C. Hu et al. (invited), VLSI-TSA 2008 [2] O.M. Nayfeh et al., EDL, 1074, 2008.[3] A.S. Verhulst et al., APL, 104, 064514, 2008. [4] Q. Zhang et al., Solid-State Elect. 30, 2009. [5] V. Nagavarapu et al., TED, 1013, 2008. [6] M. Luisier et al., EDL, 602, 2009. [7] M. Luisier et al., IEDM, 913, 2009. [8] S. Mookerjea et al., IEDM, 949, 2009.
0.0 0.2 0.4 0.6 0.8 1.010-11
10-9
10-7
10-5
10-3GaSb-InAs UTB [7]
InSbUTB [7]
InGaAs [8]Eg = 0.72 eV
InSb NW [7]Eg = 0.17 eV
InAs NW [6]Eg = 0.37 eV
I drai
n (A/
m
Vgate (V)
GaSb-InAs NW [7]
60 mV/dec
Intel 32nm LPIEDM 2009 [9]
SG PocketEg =0.36 [1]
14 June 2011 29
Current TFET performance
0.0 0.2 0.4 0.6 0.8 1.010-11
10-9
10-7
10-5
10-3
Ge-sourceTFET [15]Lg = 5m
In0.53GaAsTFET [8]Lg = 100nm
In0.7GaAsTFET [13]Lg = 100nm
I drai
n (A/
m
Vgate (V)
60 mV/dec
PNPNSi TFET [5]Lg = 1m
GeOITFET [14]Lg = 0.4 m
n-channel
Si TFET[12]Lg = 70nm
32nm nFET
• Experiments show higher sub-threshold slope than simulations.
• No physical demonstration of TFET with both high Ion > 100 A/mand SS < 60 mV/dec has been demonstrated so far.
-1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.210-11
10-9
10-7
10-5
10-3
60 mV/dec
SOITFET [14]Lg = 100 nm
DSSSi TFET [17]Lg = 20 m
I drai
n (A/
m
Vgate (V)
Si TFET [16]Lg = 56 nm
p-channel32nm pFET [9](LP)
P-TFET (experimental) N-TFET (experimental)
14 June 2011 30
Summary
• Power Constrained CMOS Scaling requires new materials and device structures to enable continued scaling.
• Nanowires: – Better short channel control than FinFETs with added degree
of integration complexity
• TFETs:– Band to band tunneling transport mechanism allows for sub-
60mV subthreshold slope
Vcc reduction lower power consumption– TFETs simulations show promise for Vcc reduction and
additional process improvements are needed to improve device performance.
14 June 2011 31