stacked-die chip scale packages adeel baig. microsystems packaging objectives define stacked-die...
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![Page 1: Stacked-Die Chip Scale Packages Adeel Baig. Microsystems Packaging Objectives Define Stacked-Die Chip Scale Packages (S- CSP) Explain the need for S-CSP](https://reader035.vdocument.in/reader035/viewer/2022062308/56649d6b5503460f94a4aef3/html5/thumbnails/1.jpg)
Stacked-Die Chip Scale Packages
Adeel Baig
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Microsystems Packaging
Objectives
Define Stacked-Die Chip Scale Packages (S-CSP)
Explain the need for S-CSP Define the challenges faced Present strategies for improving the electrical
performance and yield of wire bound S-CSP
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S-CSP
S-CSP refers to a type of multi-die package in which the die are stacked vertically and interconnected electrically via wire bonding in most cases.
Microsystems Packaging
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S-CSP
Microsystems Packaging
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Why Wirebonding?
AdvantagesGreater flexibilityMore cost effective
Microsystems Packaging
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Why S-CSP?
For many hand held devices, there is a need for greater functionality crammed into a smaller package.
These features require Greater memory capacity Smaller footprint Thinner profile Lower package cost
Microsystems Packaging
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Functions Added to Cell Phones
Microsystems Packaging
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Sensors in Cell Phones MECHANICAL (Accelerometer)
Joystick games Shock detectors
CHEMICAL Pollution Alcohol
OPTICAL Imaging Optical mouse
CAPACITIVE Fingerprint detection
Microsystems Packaging
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Worldwide Cell Phone Sales(Millions)
Microsystems Packaging
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Challenges Faced
Increasing wire bond density Additional space and height requirements for wire
looping
Yield Issues Wire shorting is the main cause of low yield in high-
density packages
If one die fails, all of the other stacked and assembled dies are lost as well
Microsystems Packaging
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Key Factors
Wire Sweep Bonded wires are misaligned in the horizontal plane.
Problems Created The mutual inductance of adjacent wires can be
altered and simultaneous switching noise can be created
An electrical short can occur when the wires touch.
Microsystems Packaging
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Key Factors
Wire Spacing Distance between adjacent wires
Problems Created If there is not adequate space between the wires, the
risk of an electrical short is greatly increased. If the wires are more likely to touch and short, a lower
yield will result.
Microsystems Packaging
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Optimizing Design
Minimize Wire Length With increased wire length, there is a greater
possibility that wire sweep problems will develop
Greater wire length has an adverse effect upon electrical performance
The impedance will be increased Inductive coupling will be more likely to occur The package operating speed will be reduced
Microsystems Packaging
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Optimizing Design
By shifting the die location or moving the die with respect to another die, it is possible to reduce wire length while achieving greater die to die bonding Option B results in lower wire length
Microsystems Packaging
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Optimizing Design
Die Setup There are two main factors in the design
process1. Location of the die
2. The manner in which they are stacked.
Microsystems Packaging
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Optimizing Design
Optimizing performance by shifting die position.Figure (b) eliminates a bond wire to pad short
Microsystems Packaging
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Optimizing Design
The die that has more stringent performance requirements should be placed on the bottom of the stack
Microsystems Packaging
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Wire Encapsulation
In order to maximize yield, it has been necessary to inspect wires for shorts and eliminate them.
Wire spacing is not an issue with this encapsulation technology. Experiments show that using this method can reduce
wire sweep and separate electrically shorted wires.
Microsystems Packaging
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Wire Encapsulation
A silica filled liquid polymer is dispensed onto the wires following the wire bonding process.
This material has many qualities that allow it to remain functional and reliable during the manufacturing process. Adheres well Has low moisture absorption Minimized CTE mismatch that help to enhance
reliability
Microsystems Packaging
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Wire Encapsulation
Microsystems Packaging
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Wire Encapsulation
Ring Lock method is superiorThe amount of encapsulant material utilized
can be greatly reduced by 80-95%Less time is needed in the dispensing
procedure
Microsystems Packaging
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Wire Encapsulation
Encapsulant can help fix wire shorts
Microsystems Packaging
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Wire Encapsulation
Results show that wire encapsulation increases yield
Microsystems Packaging
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Conclusion
Although flip chip technology seems superior, wire bonding is still widely used in the packaging and manufacturing industry.
Challenges faced in wire bonding S-CSP are becoming more complicatedBy utilizing the two approaches (Design and Wire
Encapsulation) jointly, it is possible to overcome these obstacles.
Microsystems Packaging