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Standards for 3D Stacked Standards for 3D Stacked Integrated Integrated CircuitsCircuitsIntegrated Integrated CircuitsCircuits

9/20/20119/20/2011Richard Allen

NIST/SEMATECH

[email protected]

Server Memory Forum 2011International SEMATECH Manufacturing Initiative, and ISMI are servicemarks of SEMATECH, Inc. SEMATECH, and the SEMATECH logo are registered servicemarks of SEMATECH, Inc. All other servicemarks and trademarks are the property of their respective owners.

SEMATECH 3D Enablement CenterSEMATECH 3D Enablement Center» Overview of Activities

3D Standards and Reference Flow3D Standards and Reference Flow3D Wiki Site

» Wiki Site Demonstration

3D TSV 3D TSV OutlookOutlook3D TSV 3D TSV OutlookOutlook

• Near future (2011−2013)I t d t

Source: Xilinx Source: Nokia

– Interposer products – Wide IO DRAM (mobile)

• Performance, power, footprint & cost footprint & cost

• Future (2013−2017)H t i t ti (b d l i )– Heterogeneous integration (beyond memory on logic)

– Higher (>5 stacking levels)– Smaller (<5 micron wide, >10 aspect ratio)

• Far future (2017−2025)– Beyond CMOS (photonics, sensors, etc.)

3D Enablement Center3D Enablement Center• Program announced December 2010 by SEMATECH, SIA, and SRC

• Designed to meet diverse needs of SIA members: high performance, mobile, analog, mixed signal, MEMS, fabless, fablite, IDMs

• Address gaps identified in SEMATECH industry-wide surveyg p y y

• Mission:• Mission: • Enable industry-wide ecosystem readiness for cost-effective TSV-based 3D

stacked IC solutions• Members:

• Enablement Center: ASE, Altera, ADI, LSI, NIST, ON Semi, and Qualcomm• 3D Program: Hynix• SEMATECH Core: CNSE, GLOBALFOUNDRIES, Hewlett Packard, IBM, Intel,

Samsung, TSMC, and UMC• New members welcome!

3D Enablement Center3D Enablement Center3D Enablement Center3D Enablement Center

• Initial focus is on wide IO DRAM for mobile applicationsapplications

• Provide clarity to help identify gaps in standards, specifications, technologies

• Also explore high performance computing, others

• Inaugural activity– Industry survey

SEMATECH SEMATECH Survey ResultsSurvey ResultsGaps Gaps in the Viain the Via--Mid EcosystemMid Ecosystem

• 12 companies surveyed Aug-Sep 2010: IDMs foundries fabless OSATs12 companies surveyed Aug Sep 2010: IDMs, foundries, fabless, OSATs• High density via-mid applications including interposers, heterogeneous stacking, logic on

logic, memory on memory; 2011-2014 timeframe• Addresses all aspects of via-mid: wafer processing, assembly, reliability,

inspection/metrology design test

Gaps in Standards and Specifications• EDA Exchange Formats

Technology Development and Cost Reduction

inspection/metrology, design, test • Highest priorities for heterogeneous stacking (e.g., wide IO DRAM) shown below

• EDA Exchange Formats– Partitioning and floorplanning; logic

verification; power/signal integrity analysis; thermal analysis flow; stress analysis flow; physical verification; timing analysis

• Reliability– Reliability test methods

Reduction

• Reliability– Criteria; test methods; ESD

• Temporary bond/debond cost reduction– Materials and release mechanisms cost reduction;

Equipment cost reductionReliability test methods• Test

– DFT test access architecture• Inspection/metrology

– TSV voids, defect mapping, microbumpinspection and coplanarity

• Chip Interface

Equipment cost reduction• TSV

– Keep out distance/area• Microbumping and bonding

– Pad metallurgy and layer thickness; bump metallurgy

• Chip Interface– Stackable memory pin assignment; stackable

memory physical pinout• TSV

– Keep-out area, fill materials, dimensions• Thin wafer handling

• Inspection/metrology– Microbump inspection and coplanarity; TSV voids;

BWP voids• Test

– Probing microbumps cost reduction

– Universal thin wafer carrier

3D Enablement Center 3D Enablement Center ( )( )Ongoing Activities (I)Ongoing Activities (I)

• Develop reference flows to identify needed standards (and technologies)

• SEMI® standards and standards orchestration orchestration – Leadership: NIST assignee to SEMATECH co-

chairing 3DS-IC NA committee, chairing BWS task force and co-chairing Bonded Wafer Task task force, and co chairing Bonded Wafer Task Force in MEMS/NEMS committee

– Providing wafers to supporting task forces • D5270: Guide to Measuring Voids in Bonded Wafer • D5270: Guide to Measuring Voids in Bonded Wafer

Stacks• D5175: Guide for Multi-Wafer Transport and Storage

Containers for Thin Wafers

3D Enablement Center 3D Enablement Center ( )( )Ongoing Activities (II)Ongoing Activities (II)

• Development of inspection/metrology specifications

• Microbump/bond metallurgy specifications• Near term university research (SRC)• Near-term university research (SRC)• Design exchange formats• Development of an easy to use public • Development of an easy to use public

website for standards related to 3D ICs

3D Enablement Center 3D Enablement Center Future ActivitiesFuture Activities

• Future programs under consideration:• Future programs under consideration:• Pathfinding• EDA tools• Test vehicles• Test vehicles

Reference FlowsReference Flows

• Objective: identify and prioritize needed standards, p ,specs, and technologies

• Initial focus: Mobile Wide IO DRAM

• Second focus: High • Second focus: High Performance Wide IO DRAM

• Approach– Survey member companies

t d fi i tto define requirements– Compare pros and cons of

various reference flow optionsId if d d d d 1200 bumps;– Identify needed standards, specs, and technologies

1200 bumps;40x50 µm pitch

Comparison of Mobile and High Comparison of Mobile and High P f Wid IO A li ti P f Wid IO A li ti Performance Wide IO Applications Performance Wide IO Applications

Computing Wide IO Mobile Wide IO(High Performance)

Structure Limitation Thermal Package HeightCost Dependent on design, SeriousCost Dependent on design,

technology and cooling technique

Serious

Data Band Width (Speed) ≤ 64 GB/s ≤12.8 GB/sPower 10-150W 2-20WInterposer Can be used Not UsedStructure for Thermal Use heat sink and TIM -

Structure memorymemorymemorymemory

Logic

memorymemoryLogic

Si TSV interposer

memorymemory

Heat Sink and TIM

Mobile Wide IOMobile Wide IO Reference FlowReference FlowMobile Wide IOMobile Wide IO Reference FlowReference Flow• Case 1: Logic TSV (DtS)=>Memory cube to Logic TSV

(DtD)=>Backend (molding/BA/singulation)

Tier 2 die to tier 1 die attach processLogic die (C4 bump face down)

C4 process for Tier 1 Molding, etc.

C 2 L i TSV t M b (DtD) M b L i t b• Case 2: Logic TSV to Memory cube (DtD)=> Memory cube+Logic to sub => Backend (molding/BA/singulation)

Flip overFace up

Molding etcMemory + logic die attach processLogic die bonding to Flip over

Carrier

De bonding

Molding, etc. Memory logic die attach processmemory cube (C4 bump face down)

FrontFront--ToTo--Back 3D Design/Back 3D Design/MfgMfg FlowFlowFrontFront ToTo Back 3D Design/Back 3D Design/MfgMfg FlowFlow

3D Stack Planning Tier Design/Manufacturing

Architecture Planning

Partitioning

Electrical

Design/Verif

Physical

Design/Verif

Chip Finishing, Extraction, DRC LVS

3D PDK

Mask Creation, DFM, Data Foundry

Package Planning

Physical Planning

Design/Verif DRC, LVS ,Prep

Thermal/MechAnalysis

3rd Party Tier IP Packaging & Test

Tier Integration

3 Party Tier IP Packaging & Test

Slide Courtesy of Sumit DasGupta, Si2

Consortia Landscape Across 3D FlowConsortia Landscape Across 3D FlowConsortia Landscape Across 3D FlowConsortia Landscape Across 3D Flow

3D Stack Planning Tier Design/Manufacturing


Partitioning

Electrical

Design/Verif

Physical

D i /V if

Chip Finishing, Extraction, 3D

PDK

Mask Creation, DFM Data Foundry

Industry Focus/Interest GroupIndustry Focus/Interest Group

ResearchResearchResearchResearchResearchResearch

ResearchResearchResearch

Package Planning

Physical Planning

Design/Verif DRC, LVSPDK DFM, Data Prep


St d dSt d dSt d d

ResearchResearchResearch

ResearchResearchResearchDesign StandardsDesign StandardsDesign StandardsDesign Standards

Packaging & Test3rd Party Tier IP

Tier Integration

StandardsStandardsStandards

StandardsStandardsStandardsStandardsStandardsStandardsStandardsStandardsStandards

Packaging & Test3rd Party Tier IP

Design StandardsDesign Standards

StandardsStandards


Required Design Flow Standards For 3D: Required Design Flow Standards For 3D: Required Design Flow Standards For 3D: Required Design Flow Standards For 3D: Top LevelTop Level

3D Stack Planning Tier Design/Manufacturingg


g / g

Partitioning

Electrical

Design/Verif

Physical Chip Finishing, E t ti3D

Mask Creation, F d

Package Planning

Physical Planning

y

Design/VerifExtraction, DRC, LVSPDK

,DFM, Data

Prep

Foundry


Tier Desc& Models

Tier Desc& Models

Tier Integration

Ti D

Stack Desc& Models

& Models

Stack Desc& Models

Packaging & Test3rd Party Tier IPTier Desc& Models


Specific Potential 3D Design Flow StandardsSpecific Potential 3D Design Flow StandardsSpecific Potential 3D Design Flow StandardsSpecific Potential 3D Design Flow Standards

3D Stack Planning Tier Design/ManufacturingMulti‐tier

power networks

Multi‐tier parasitic networks

Multi‐tier thermal estimation


Partitioning

Electrical

Design/Verif

Physical Chip Finishing, Extraction, 3D

PDK

Mask Creation, DFM D t Foundry

Package Planning

Physical Planning

Design/Verif,

DRC, LVSPDK DFM, Data Prep

y


d

Tier Integration

TSV, interposer RLC models,

Partitioning and floorplanningconstraints

Packaging & Test3rd Party Tier IPp

properties

API between EDA , T/M tools

RLC models, RDL layers, u‐bumps

Thermo‐mechcorner conditionsChip‐chip & chip‐

package desc EDA , T/M toolspackage descSlide Courtesy of Sumit DasGupta, Si2

Standards & 3D Reference FlowStandards & 3D Reference FlowStandards & 3D Reference FlowStandards & 3D Reference FlowNeed to start with the elements:

Face up

Flip overFace up

Carrier

Molding, etc. Memory + logic die attach processLogic die bonding to memory cube

Flip over (C4 bump face down)

Standards & 3D Reference FlowStandards & 3D Reference FlowStandards & 3D Reference FlowStandards & 3D Reference Flow

Memory Cubeor

Logic Chip


Memory Cube

JEDEC JC-11: Wide IO Mobile Memory Mechanical Outlines

JC-42: Wide IO DRAM Memory Specification – Low Power DRAM

or

Logic Chip

Si2: Open3D Technical Advisory Board (TAB) Develop standards to

• Define the necessary formats/interfaces/APIs to enable the transfer and sharing of design and model data throughout 3D IC design flowsthroughout 3D IC design flows

• Enable the transfer of required design data from the 3D IC design system to package design systems for the design of packages for the 3D ICs


SEMI D5268 G id f T i l

Memory Cube

SEMI D5268: Guide for Terminology for Measured Geometrical Parameters of Through-Silicon Vias(TSVs) in 3DS-IC Structures

or

Logic Chip


Memory Cube SEMI MS1-0307: Guide to Specifying Wafer-Wafer Bonding

or

Logic Chip

Specifying Wafer-Wafer Bonding Alignment Targets


SEMI D5270: Guide to Measuring Voids in

Memory Cube

gBonded Wafer Stacks

SEMI MS5-0310: Test Method For Wafer Bond Strength Measurements Using Micro-Chevron Test Structures

or

Logic Chip

Chevron Test Structures


Memory CubeSEMI D5173: Specification for Parameters for Bonded Wafer Stacks

or

Logic Chip

SEMI D5174: Specification for Identification and Marking for Bonded Wafer Stacks


Memory Cubeor

Logic ChipSEMI D5175: Guide for Multi-Wafer Transport and Storage Containers for Thin Wafers


IEEE P1838: Test Access Architecture for Stacked 3D-ICs

Memory Cube

Points for Testing Pre- and Post-bonding

JEDEC JC-14: 3D-ICs Packaged and Unpackaged Evaluations and Qualifications (qualification and evaluation test methods)or

Logic Chip

test methods)

JC-42: 3D Memory Stack for DDR3 and DDR4 using TSV

JC-63: 3D Stacked Mixed Technology


Face up

Flip overFace up

Carrier




Face up

Flip overFace up

Carrier

D5270: Guide to Measuring Voids



MS1-0307: Guide to Specifying Wafer-Wafer Bonding Alignment Targets

D5270: Guide to Measuring Voids in Bonded Wafer Stacks IEEE P1838: Test Access Architecture for

Stacked 3D-ICs Points for Testing Pre- and Post-bonding

Wafer Bonding Alignment Targets

MS5-0310: Test Method For Wafer Bond Strength Measurements Using Micro-Chevron Test Structures

Standards & 3D Reference FlowStandards & 3D Reference Flow

Face up

Standards & 3D Reference FlowStandards & 3D Reference Flow

Flip overFace up

Carrier

JEDEC JC-14: 3DS-ICs Reliability Test Methods

JEDEC JEP158: 3D CHIP STACK WITH

JEDEC JC-14: 3D-ICs Packaged and Unpackaged Evaluations and Qualifications (qualification and evaluation test methods)

JEDEC JC-40: 3D Stack Buffer/Register



JEDEC JEP158: 3D CHIP STACK WITH THROUGH-SILICON VIAS (TSVS): Identifying, Evaluating and Understanding Reliability Interactions

JEDEC JC 40: 3D Stack Buffer/Register Support

JEDEC JC-42: General Memories and TSVs

3D IC 3D IC Standards Landscape Standards Landscape (“dashboard”) Objectives(“dashboard”) Objectives(“dashboard”) Objectives(“dashboard”) Objectives

• Develop an easy to use public website for standards related to 3D ICs:3D ICs:– Define, track, get status, find milestones – Identify risk areas

D t i l t d t ll 3D IC t d d – Determine gaps related to all necessary 3D IC standards

• Provide a single monitor/coordinator function– To accelerate the development and adoption of standards – To promote the optimal use of resources – To avoid confusion

• Domains– Design exchange formats, test, design, verification, process,

handling, metrology, reliability, materials

Dashboard ReleaseDashboard Release

• Announcement to Working Group– June 22, 2011

• Public Announcements – July 12, 2011: SEMI 3DS-IC Committee meeting– July 12, 2011: SEMI Standards 3D Workshop– September 23, 2011: 3D-Test Workshop

(top half)

(bottom half)

STANDARDS DASHBOARDSTANDARDS DASHBOARDSTANDARDS DASHBOARDSTANDARDS DASHBOARD

• One-stop location to identify ongoing standards activities– 3D standards activities are currently spread

across a wide range of SDOs

O f bli d t• Open for public access and comment– Open dialog among members of the

standards communitystandards community– Help identify unmet standards needs– Encourage participation in standardsg p p

A Wiki’s value A Wiki’s value isis its its A Wiki s value A Wiki s value isis its its community… Please join our community… Please join our

con ersation atcon ersation atconversation atconversation atwiki.sematech.orgwiki.sematech.org

AcknowledgementsAcknowledgements

• Dashboard Data Compilation– Moises Cases, Cases Group

• SDO Representatives– Erik Jan Marinissen, IMEC (IEEE)– Sophie Dumas, ST Ericsson (JEDEC)– Paul Trio, SEMI– Sumit DasGupta, Si2

• Web Site Developmentp– Susan Rogers, SEMATECH– Zack Fantauzzi, SEMATECH

• SEMATECH 3D Enablement Center TeamSEMATECH 3D Enablement Center Team– Larry Smith– Minsuk Suh– Andy RudackAndy Rudack

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