stanford univ calif di6ital systems lab f/g 9/5 sprint ... · stanford univ calif di6ital systems...
TRANSCRIPT
AD-AUH5 t>t>3
UNCLASSIFIED
STANFORD UNIV CALIF DI6ITAL SYSTEMS LAB F/G 9/5 SPRINT - AN INTERACTIVE SYSTEM FOR PRINTED CIRCUIT BOARD DESIGN—ETC(U) JUN 77 W M VANCLEEMPUT» T C BENNETT» J A HUPP N0001U-75-C-0601
DSL-TR-lt3 NL
I *2 AD4045953
ADA045 653
C and F were left undefined.
CO [ DIGITAL SYSTEMS LABORATORY
lO STANFORD ELECTRONICS LABORATORIES «>•> DEPARTMENT OF ELECTRICAL ENGINEERING ^ STANFORD UNIVERSITY • STANFORD. CA 94305
0 SPRINT - AN INTERACTIVE SYSTEM FOR
< PRINTED CIRCUIT BOARD DESIGN
§ USER'S GUIDE
W.M. vanCleemput T.C. Bennett J.A. Hupp K.R. Stevens
/
Technical Report No. 143
g-June 1977 CD CJ>
D D C (^©EDllflJZjj1'
OCT 19 197T
mnrm A -
Pürtrihuöos t*rJuc;t ••
This work was supported by the U. S. Energy Research and Development Administration under contract E4-76-C-03-0515 and by the Joint Services Electronics Program under contract N-00014-75-C-0601.
Also published by Stanford Linear Accelerator Center, Stanford, California, as Computation Research Group Technical Memorandum CGTM-187.
1 ay
SPRINT - An Interactive System for
Printed Circuit Board Design
User's Guide , /
' - / \ W.M./vanCleemput, T.C./Bennett, / J.A./Hupp
K. R./Stevens
m Technical jtep*rt fo. 143
V)
njj J«M77 / Q::\ J5-f' •. -
(Digital Systems Laboratory Departments of Electrical Engineering and Computer Science
'J&anford University Stanford, California 94305
This work was supported by the U. S. Energy Research and Development Administration under contract E4-76g£«Q3«fl515 ap^ hy tba Jalflft Saotlcas _ Electronics Program under contrac±/(Cpödl4-75-C-Ö6dl. E*j- 74- g _ 4 \ _ 7/ /
Also published by Stanford Lineaf Accelerator Center," StänfördT California, as Computation Research Group Technical Memorandum CGTM-187.
// • /
SPRINT - An Interactive System for
Printed Circuit Board Design
User's Guide
W.M. vanCleemput T.C. Bennett J.A. Hupp K.R. Stevens
Technical Report No. 143
June 1977
Digital Systems Laboratory Departments of Electrical Engineering and Computer Science
Stanford University Stanford, California 94305
ABSTRACT
The SPRINT system for the design of printed circuit boards is a collection
of programs that allows designers to interactively design two-sided boards
using a Tektronix 4013 graphics terminal. The major parts of the system
are: a compiler for SDL, the Structural Design Language, an interactive
component placement program, an interactive manual conductor routing pro-
gram, an automatic batch router, a via elimination program and a set of
artwork generation programs.
INDEX TERMS: printed circuit board design, computer-aided design,
design automation
This work was supported by the U. S. Energy Research and Development Administration under contract E4-76-C-03-0515 and by the Joint Services Electronics Program under contract N-00014-75-C-0601.v/
Also published by Stanford Linear Accelerator Center, Stanford, California, as Computation Research Group Technical Memorandum CGTM-187.
SPRINT - An Interactive System for
Printed Circuit Board Design
User's Guide
0. Introduction 1 1. System Overview 3 2. The Description of Circuits in SDL 5
2.1 SDL Language 5 2.2 An Example 13 2.3 How to Run SDLCOMP 16 2.4 Error Messages 17 2.5 SDL Object Language Format 21 2.6 Sample Output of the SDL Compiler 25
3. Logical and Physical Libraries 35 3.1 Logical Library 35 3.2 Physical Library 39 3.3 How to Add a Component to a Logical Library 42 3.4 Board Description 43
4. Design File Generation 45 4.1 Introduction 45 4.2 How to Run SDLPCGEN 48 4.3 How to Run LOADFILE 50 4.4 Error Messages 51
5. Interactive Placement Program (PLACER) 56 5.1 The Placement Process 56 5.2 Using PLACER 58 5.3 Error Messages 70
6. Manual Prewiring of Critical Connections (MWIRE) 76 6.1 Introduction 76 6.2 Using MWIRE 76 6.3 Error Messages 81
7. Batch Routing Program (HIWIRE) 85
7.1 Introduction 85
7.2 Using HIWIRE 87
7.3 Error Messages 96
8. Via Elimination 99
8.1 Introduction 99
8.2 Running VIAELIM 100
8.3 Error Messages 102
9. Output Plot Generation 104
9.1 PLOT 104
9.2 ARTWORK 106
10. Utilities 122
10.1 DUMP and RESTORE 122
10.2 PRINT 123
10.3 Running DUMP and PRINT 123
10.4 Running RESTORE 124
11. Future Enhancements 127
ii
0. INTRODUCTION
The objective of this system is to allow interactive computer-
assisted design of printed circuit boards. The SPRINT system allows
for the manual placement of critical components and for automatic
placement of certain other components such as 14 and 16-pin dual-
in-line packages. The interconnection routing module allows for
manual routing of critical connections and for automatic routing
of non-critical connections. The current system is limited to
two signal layers, but a future expansion to multilayer boards has
been planned.
The input to the system is in the form of an input language
called the Structural Description Language (SDL). In the future
the SDL description will also be used as the input to a logic
simulator, to a fault test generation/simulation system and to an
automatic logic diagram generation capability.
The current system is implemented in MORTRAN and FORTRAN IV
on the IBM 370 system at SLAC and makes use of a Tektronix 4013
terminal. The SDL compiler is implemented in SPITBOL, a SN0B0L
dialect. Currently, the output of the system is in the form of
a Calcomp plot, from which the artwork has to be generated manually.
Future enhancements will be discussed in section 11. In order
to illustrate the working of the system a small example will be
used consistently throughout this manual. (Figure 0.1).
- • i i - HWMHWMMMMIMlMfa
INTET
(B) L0G2T
H BREQ
BUSCL
CREJ
J 08 ^8 BREQ(H) C04
NRBREQ
GRACK ,RpRB06
AIO £ 5 12
rfr>-
5 R!° 12
IrNRREO 3
AVAILIN 3 BN
fr* NAVA
II
UM 1
üo s
D Q
74C03 C Q
R
8
13
NREQ
NBUSGO
BUSGO (F)
BUSGO
10 V8 AVAILOUT
Figure 0.1
2
.—. • •• miinMii
1. SYSTEM OVERVIEW
The current release of the system consists of the following
major programs:
1) SDLCOMP: The SDL compiler translates the circuit description
provided by the user into an internal format. It makes
use of a logical library. This logical library contains
information for each component type used. For the purpose
of printed circuit board design only the pin names for
every component type are retrieved from this library.
2) SDLPCGEN: This program takes the sequential output file,
generated by the compiler, and combines it with information
retrieved from the physical library and the board description
file. The output is a sequential file containing all the
information necessary to initialize the design file.
3) LOADFILE: This program initializes the direct access
design file using the output generated by SDLPCGEN.
4) PLACER: This is an interactive subsystem that allows the
user to place components on the board.
5) MWIRE: Interactive subsystem for routing critical and
multiple width wires manually.
6) HIWIRE: Batch router for automatic routing of non-critical
connections.
7) VIAELIM: Batch program for elimination of unnecessary
via holes.
1 •• •"• 1 ' n^^^K^^^t^
The overall structure of the system is illustrated in
Figure 1.1.
, . C LOGICAL^ (SDL) V LIB J
SDLCOMP
1 f PHYSICAL^
(^"BOARD ) S0LPC6EN
Figure 1.1
•MH^^^HB^^H^B^^H^M
2. THE DESCRIPTION OF CIRCUITS IN SDL
2.1 Language Definition
The SDL language allows for format-free entry of a circuit.
It performs checking of the input wherever possible. The SDL
language removes all blanks from statements before processing.
Therefore embedded blanks have no meaning, although they may be
inserted in the source text in order to enhance readability.
The sequence of groups of statements has to be adhered to.
The following description defines this sequence. Some statements
are mandatory while others are optional. For each statement it
will be indicated whether or not it is optional.
In general, names (identifiers) in the system may consist
of the letters A-Z, the digits 0-9, the slash (/), the underscore
(_) and angular brackets (<and>).
1) User Identification
USER: <name>;
where name is a character string of at most 20 characters.
Example: USER: TBENNETT;
This declaration is mandatory.
2) Project Identification
NAME: <projectname>;
where <projectname> is a character string of at most
20 characters.
-
—*—
Example: NAME: CAMACEXAMPLE;
This declaration is mandatory and should follow the
USER identification.
A preferred naming convention in the system is of the form:
<Purposename>. <level name>. <Project name>
For PC layout
<Purposename> = PCBGEN
and <level name> = BOARD
The reason for this naming convention is the possibility of
logic macro expansion which will be available in a future
release of the system. However, if the description will be
used for PC layout only you may use any name. If you do so
a warning message will be issued.
3) Purpose Definition
PURPOSE: <purposename>;
where <purposename> is a string of at most 20 characters.
In general, the purpose of the description should be
stated here.
For printed circuit board design this purpose is always
defined as: PCBGEN.
This declaration is mandatory.
4) Level Definition
LEVEL: <levelname>;
where <levelname> is a valid identifier.
In general, the level of a description has to be specified
before doing a macro expansion.
For printed circuit board design two levels are of interest:
1) COMP (the component level) which should be used to
describe the board in terms of components and connections.
2) END (the lowest level) which should be used to describe
component types to be entered in the logical library. The
basic purpose of such a description is to associate names
with each of the pins of a given component type.
"'•'" """ in i.i. ii u i. n »IIII.III... urn ,i ..!.. ii. .i i ... . i. .1 . inn—in».^-
5) Declaration Of All Logical Types Used
TYPES: <namelist>;
where <namelist> consists of a single logical type name
or of several names separated by commas.
It is necessary to declare explicitly all logical component
types used in the circuit being described.
Example: TYPES: AND, OR, 54180, 8080, SN7474, DFLIPFLOP;
The name of a type is restricted to 20 significant
characters.
NOTE: The type EXT is implicitly defined and reserved for
specifying the external connectors. Therefore, EXT is a
reserved type name and should not be redefined.
6) Definition of External Connectors
a) EXT: <cname> : <namelist>;
This declaration is necessary for every external
connector.
A <cname> is the name of that connector while <namelist
is a list of all the terminals of that connector in thp
order in which they appear. All terminals that are
connected should have distinct names. When a terminal
is unconnected and unnamed, this may be indicated by
using the reserved name DUMMY.
Example: EXT: C0NNECT0R1: A, B, C, DUMMY, D, E, F;
This declares a connector called C0NNECT0R1 with 7
• • ' —
terminals with terminals 1-3 called A, B, C and
5-7 called D, E, F.
Terminal 4 is unconnected and without an actual name.
Again, the name of a connector and of terminals is
limited to 20 characters without embedded blanks.
Every external connector implicitly defines a logical
type and a component with the same name (i.e. a <cname>),
b) INPUTS: <tnamelist>;
OUTPUTS: <tnamelist>;
A terminal of a connector may be defined as either an
input or an output terminal or both or it may be left
undefined.
The order in which these terminals appear in the
INPUTS or OUTPUTS declaration is not important.
A <tnamelist> is either a single <tname> or several
<tname>'s separated by commas.
A <tname> consists of a connector name followed by a
period (.) followed by a terminal name. Both names
are limited to 20 characters without embedded blanks.
Example: INPUTS: C0NNECT0R1.A, C0NNECT0R1.B;
C0NNECT0R2.A, C0NNECT0R1.E; OUTPUTS: C0NNECT0R1.D, C0NNECT0R1.E;
In this example, terminals A, B of C0NNECT0R1 were
defined as inputs only, terminal D as output only,
terminal E is both input and output, while terminals
8
•iffl^.».^^.^!!.,.! . ....»«wauMmBIW.» m
C and F were left undefined.
7) Component Declarations
<typename> : <cnamelist>;
where <typename> is a previously defined logical type and
<cnamelist> is a list of component names.
Component name may be up to 20 characters long
Example: AND: Cl, C5, TPX, 8080, PI;
Note that external connectors should not be declared as
components here since this has been implied by the EXT
statement(s).
8) Net Declarations
Each net is specified by the following declaration:
<netname> = <tnamelist>;
where <tname> is of the form: component name, followed
by a period (.), followed by a terminal name.
e.g.: NET! = C1.IN1, C0NNECT0R1.A; NET2 = C1.IN2, C0NNECT0R1.B; NET3 = Cl.OUT, C2. INI, C3.IN2; NET4 = C2.0UT,C3.0UT, C0NNECT0R1.C;
The net descriptions are followed by an END; statement.
Some users may prefer to encode a signal 1« more than one
statement. This is, e.g., the case when a logic diagram that
is being encoded is spread out over several sheets.
Since allowing this removes some of the error-checking capa-
bility of the system, a warning message will be issued for
multiply-defined nets.
9) Crosschecking of the Net Declarations
It is frequently desirable to input the net declarations
in their dual form, i.e., for every component, one can enter
the net each pin is connected to. The option here is:
9
NO CROSSCHECK; or
CROSSCHECK;
In the second case, the following input is expected:
<cname> : <nnamelist>;
where <nname> consists of the netname followed by a
period (.) followed by the pinname.
If crosscheck is specified, a complete netname list has
to be provided for every component. The order in which
these statements appear is not critical. The description
is terminated by an END; statement,
e.g.: CROSSCHECK; Cl C2 C3
NET1.INL, NET2.IN2, NET3.0UT; NET4.0UT, NET3.IN1; NET3.IN2, NET4.0UT;
C0NNECT0R1: NET1.A, NET4.C, NET2.B;
Although the use of crosscheck will require twice the
encoding work, it allows to detect otherwise difficult-
to-find mistakes.
It is highly recommended to use the crosscheck option.
Although it requires the logic diagram to be encoded twice,
it ensures a more correct input and may eliminate some
unnecessary layout runs.
10) CEND Statement
The circuit description is terminated by a statement of
the form: CEND;
11) Definition of Obstructions
An obstruction is a physical component that completely
occupies one or more layers of a board. The normal
10
— • • • — - - ••••.—.. -. .. _ .
components that were defined before may, under certain
conditions, be obstructions. Since this is to be considered
a physical property, this information will be provided in
the physical description library. It will sometimes be
necessary to declare physical obstructions that do not have
any external connections. An example of this is a hole
in the board.
It will be necessary to declare this hole as a component
and to associate a logical and physical type with it.
This will then require the appropriate entries in the
logical and physical libraries.
12) In some cases, a designer may have special components that
are not general enough to be placed in the normal component
library. When this is the case, he can specify a user
library as following:
USERLIB : <name>;
This statement has to follow the TYPES declaration. The
library used has to be referred to in the JCL (this is
taken care of by the #RUNC0MP exec file).
The name of the library is checked against the name in the
leader record of the library. The generator of a library
is discussed in Section 3.3.
13) In some cases, e.g., the generation of a user library, it
may be desirable to compile several circuits in a single
run. This is permitted in the current version of the
compiler. Note that the CEND; statement determines the
11
"-"-"••M*^-jL-"—1-j-t- - .-....- ,— .... ... . - -.... .- .... . ^ _ - -. . _ . , .J.. . - _.....
1
end of the Input deck. The USER statement should only
appear once, i.e., is the first card. A typical batch
may look as follows:
USER : WMVC;
NAME : CIRCUIT1 ;
NOCROSSCHECK;
NAME : CIRCUIT2 ;
CROSSCHECK;
END; (end of crosscheck list)
NAME : CIRCUIT3;
NOCROSSCHECK;
CEND;
12
•-• -• • • - -
' •'••
11 2.2 An Example
The following simple example illustrates the use of SDL
for describing a circuit. The logic diagram for the circuit in
this example is given in Figure 0.1.
Note that every signal has to be given a distinct name. It
is possible to describe a signal net using more than one net
declaration, e.g., signals LOGIT, BUSGO, BREQ and ISIG in the
example.
Note that pins in such a declaration may be specified only once.
The compiler will merge all net declarations with the same name.
In order to prevent accidental errors, a warning message will be
issued for every duplicate net name encountered.
13
USER: WMVC; NAME:EXA"PLE1; PURPOSE:PCBGEN; LEVEL:COMP; TYPES:7400,7402,7408,7433,7410,7474,7404,7416,RES,CAP; EXT:CONN20A:A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P,Q,R,S,T; 7400.-C01; 7474:C02,C03; 7408:C04; 7402:C07; 7416:A10; 7433:B03; 7410:C11; 7404:B11; RES:R1,R2; CAP.-C1; INTET=CONN20A.A,C01.1,C01.2; INTE=C01.3,C04.10; LOG2T=CONN20A.B,C0 2.10; DIVCLK=CONN20A.C,C0 2.3; HBT=CONN20A.D,C02.1; MCLR=CONN20A.E,C07.12; BUSGO=CONN20A.F,C04.4; AACK=CONN20A.G,C04.5; LOG2T=C03.4,C03.10; BREQ=CONN20A.H,C03.2,C03.13; BUSCL=CONN20A.I,C0 3.3; CREJ=CONN20A.J,C04.1; AVAILIN=CONN20A.K,B11.3; C02Q=C02.9,C04.9; C02QB=C02.6,C02.2,C02.4; DIVQ1=C02.5,C02.11; NINTDIS=C07.13,C02.13; GRACK=C04.6,C07.11; REQ=C0 3.5,C03.12,B0 3.2; BUSGO=C03.9,B03.3,B03.8,B03.9,B03.11,B03.12; NX=C0 3.8,C11.9,A10.13; NREQ=C03.6,C11.10; NAVAILIN=B11.4,C03.11,C11.11; BREQ=C04.8; ISIGT=B0 3.4,CONN20A.P; ISIG=A10.12,R2.2,B0 3.5,B03.6; ISIG=C1.1; REQUSGT=B0 3.1,CONN20A.O; D8 0 6=B0 3.10,CONN20A.N;
14
-•—
D802=B0 3.13,CONN20A.M; AVAILOUT=Cll.8,CONN20A.L; PLUS5=R1.1,R2.1; GND=C1.2,Rl.2,C02.12; END; CROSSCHECK; C01:INTET.1,INTET.2,INTE.3; C0 2:HBT.1,NINTDIS.13,C02QB.2,DIVCLK.3,C02QB.4,DIVQ1.5,C02Q.9,
C02QB.6,LOG2T.10,GND.12,DIVQl.ll; CONN20A:INTET.A,LOG2T.B,DIVCLK.C,HBT.D,MCLR.E,BUSGO.F,AACK.G,
BREQ.H,BUSCL.I,CREJ.J,AVAILIN.K,AVAILOUT.L,D80 2.M, D806.N,REQUSGT.O,ISIGT.P;
C0 3:BREQ.2,BUSCL.3,LOG2T.4,REQ.5,NREQ.6,NX.8,BUSGO.9,LOG2T.10, NAVAILIN.11,REQ.12,BREQ.13;
C04:BUSGO.4,CREJ.1,AACK.5,GRACK.6,BREQ.8,C02Q.9,INTE.10; C07:GRACK.11,MCLR.12,NINTDIS.13; A10:ISIG.12,NX.13; B0 3:REQUSGT.1,REQ.2,BUSGO.3,ISIGT.4,ISIG.5,ISIG.6,BUSGO.8,
BUSGO.9,D806.10,BUSGO.11,BUSGO.12,D8 0 2.13; Cl1:AVAILOUT.8,NX.9,NREQ.10,NAVAILIN.11; B11:NAVAILIN.4,AVAILIN.3; R1:PLUS5.1,GND.2; R2:PLUS5.1,ISIG.2; C1:ISIG.1,GND.2; END; CEND;
15
»~_ ummummt* n »m f "<
2.3 How to Run SDLCOMP
The SDL compiler reads and checks an SDL source file for
syntax errors and logical inconsistencies. If the compilation is
successful SDL object language will be output. The logical library
will contain circuit descriptions in the form of SDL object. All
application programs (PC generation, logic diagram generation,
IC layout etc.) will use the SDL object file of a circuit together
with an application-oriented library to create input for the appropriate
subsystem.
In order to simplify the use of this compiler, a Wylbur
exec file (LIB#RUNCOMP under account number PCB$CG) has been created.
It can be used as follows:
exec from Iruncomp user pcb group eg THIS FILE RUNS THE SDL COMPILER. <CR> CLEAR ACTIVE?
<CR> clears your active file otherwise use break to save it.
'ACC0UNT?= CG.PCB?' ENTER? cg.wmv
Enter the account number that will be used as a prefix
for all files e.g. cg.wmv
'SDL SOURCE FILE = SDLINPUT?' ENTER? exl
Enter the name of the Wylbur format file containing your
SDL source input. Two forms are possible:
a) for sequential files use the file name
b) for library members use the form libname (membemame)
16
•fc i — Hl IM—«—111 II I II mimtmmmmmlm
'SDL OBJECT OUTPUT FILE = SDLOBJ?' ENTER? objl
Enter the name of the Wylbur format file into which the
object language output will be written. <CR> will give
you the default name SDLOBJ.
'VOLUME = SCFEV9? ENTER?
Enter the volume on which the SDL object file is to be
placed. <CR> will give you a scratch volume (i.e. SCFEV9),
'USER LIBRARY? <CR>=N0NE' ENTER? xlib
Enter the name of the user library if you have one,
otherwise reply with a <CR>.
THE JCL IS NOW IN YOUR ACTIVE FILE READY TO RUN -> EXE F PAU
Issue a run command to submit the job.
2.4 SDLCOMP Error Messages
The following list explains all error messages that are
currently generated by the SDL compiler. A severity less than 4
is a warning; severity 4-7 are serious errors which need correction;
severity 8 is a fatal error.
Depending on the nature of error the following actions are
recommended:
1) correct the error and run the program again
2) keep your output and a copy of the input file and contact
the person responsible for maintaining the compiler
17
....-...
"••'•' • < " "• •• — ' ••
3) contact
library.
the person responsible for maintaining the component
error number severity action message
1 8 missing circuit name
2 8 missing or incorrect EXT declaration
3 8 missing or incorrect TYPE declaration
4 4 undefined type
5 8 missing type in component declaration
6 4 maximum name length exceeded
7 4 expecting net definition or END but other statement found
8 8 3 missing header in logical library
9 8 3 syntax error in logical library
10 8 3 not all types in logical library
11 4 1 invalid pin name
12 4 1 previously defined type
13 4 1 undefined component
14 8 1 missing crosscheck statement
15 8 3 missing or incorrect PINS record in library
16 8 3 user library name conflict
17 4 1 undefined component
18 4 i undefined netname
18
error number severity action message
19 4
21 4
22 4
23 8
24 8
26 4
27 8
28 4
29 4
30 8
31 8
37 8
38 8
39 8
40 8
41 8
42 8
43 4
44 8
45 8
1 or 3
3
3
3
3
3
3
1
3
3
undefined pinname
previously defined component
previously defined pinname
missing user name
syntax error in EXT declaration
undefined component type
invalid netlist
invalid terminal name
syntax error
incomplete crosscheck list
missing END statement
missing or incorrect NTYP record in logical library
missing or incorrect NCOM record in logical library
missing or incorrect TNPN record in logical library
missing or incorrect NNET record in logical library
missing or incorrect TYPE record in logical library
missing or incorrect COMP record in logical library
error detected during processing of crosscheck information
invalid name in logical library
missing or conflicting purpose in logical library
19
-•'•- • -' ••" •••
IIIIIMIIII III «11^*91 J|WÄ|J|I,II1*HPU I "
error number severity action message
46 8 3 missing or conflicting level in logical library
47 2 - previously defined netname
48 8 2 one of the systems limit was exceeded
49 8 3 error in alias directory of logical library
50 4 1 pin connected to two different nets
57 2 - unconnected pin
20
—
IWJ 'i .inuivmiuuuiBi '!• (»»II...I. Fl I" lll.I HI«!,!".!, in .iuj.il. -I. • .- Jin . .11.11 ll i. . ji.iijuui. I.I l.l .ill ll ll>,-l|il nil IIP i i , i -.-!•! n p..
2.5 SDL Object Language Format
As indicated in section 2.3, the SDL compiler generates an
intermediate input in the form defined below. This format is
used
1) by each subsystem (printed circuit design, integrated
circuit design, logic simulation etc..) together with a
special library to create a specific design file (the
printed circuit design file generation is discussed in
detail in section 4).
2) in the logical library
3) by the macro-expansion facilities that will be available
in the future.
The user need not be aware of the rest of this section. Nevertheless,
it is included for the sake of completeness.
The SDL object language consists of records of length 80
with columns 1-5 reserved for a record type indicator. The following
description gives these records in the order in which they will occur.
All records are fixed-format to make them easy to read from
Fortran.
1) USER:
1 record
username: col. 6-25
2) NAME:
1 record
project name: col. 6-25
21
3) PURP:
1 record
purpose name: col. 6-25
4) LEVL:
1 record
level name: col. 6-25
5) NTYP:
1 record
# of logical types: col. 6-10
6) NCOM:
1 record
# of components: col. 6-10
7) TNPN:
'i record
total # of pins: col. 6-10
8) NXPN:
1 record
# of external pins: col. 6-10
9) NNET:
1 record
# of nets: col. 6-10
10) XPIN:
1 record per external pin
pinnumber: col. 6-10
pinname: col. 11-30
22
-.--••••-•••• •••-•• —i^^^^^^^—
11) TYPE:
1 record per logical type
typenumber: col. 6-10
typename: col. 11-30
# of pins: col. 31-35
external flag: col. 36-40
12) COMP:
1 record per component
component #: col. 6-10
componentname: col. 11-30
# of pins: col. 31-35
logical type: col. 36-40
external flag: col. 41-45
13) PINSi
directly follows COMP: record
1 record for every pin of the component
pin #: col. 6-10
pinname: col. 11-30
14) HNET:
1 record for every net
net #: col. 6-10
netname: col. 11-30
# of pins: col. 31-35
23
-—• - • ...
15) PNET:
directly follows HNET: record
1 record for every pin in the net
component #: col. 6-10
pin #: col. 11-15
16) ENDC:
terminates the SDL object file
24
1
i. cu
o
co a» +->
3 O
f
CM
< •»
w co co - OS OS
»ft *
i-H ft •* c-
<s> Z ^ •. r- T % *».
r>» •.
r- «.
<s •>
* ft r» x
ft ft ro CJ PO -
r-~ » ft u
ao - <s Q ^ ft r» u
co •ft J U ft. > s s < £ X
CO • • •• OS u cj s: w < => z
Z S CO * O r» CQ «ft ft
•• O *• co U r» w •• •• O J w cu co w OS > ft. DU>n a, J H
CQ
• •
<s fM •« Z ^H Z <a O U u •• .. s
E-t Si x •» co r»
EH (N
8 J
CO s < z EH CO z Q CO z l-l Cb CO Q
5H a CO s o M > CO OS Q,
* •ft * •» * CM * CO * •
-1 * rH
• X « r^ ro •* •% u u Ml •% ^f IS CO *f EH ft ES no • •ft • ft u — • •
CO CO rH H • <N *r .> O «. n •« rH CM M Cb • • (N •ft ^H • in Z (N • rH rH IS J i-H (N S rH • * • • - M • O • CO U •»
Sä <S »ft <S u • r» <s «a> SI Z <*"> S) ^P ft ft r-1 UBU CN IS CJ CB rH OS S US t£ i«NH
< ftiH W u ea U ftU • <CJ »CJ •• • • II OS < • CQ • u •fc Cb ft CO EC ftM »< • N (N
CQ • ^< • < ft CO • US rn • rj s •*»* s is CO M •ft <S<SQ • < • CJ * •< • <N <S O O r J n IS CJ CB CM • < s < A < s <; z cj - - < • CM ft (N z <0<NS<T OiSIMSZ » VD en Z Cb
o u •. Z^ZZeacNZtN CN Z •ZOtNZZZ OS O^HOUZZOZ
• CO
IMZNO* • • OZZZCJ «(NiTM UZOZ HfMcais (NIT^ISrOHH ts»
OS Q SCaSHBHH ft •- CJ ea u II ZOCjOCJJOCJOZiSCJU
2 CO CQ
CJ CJ U < CO U CO OS U EH II •• •• CO CO
II « o u c_« . 1 r i II
II u O II O MS
II Q U II U w U II II C_i rr\ II . 1 II . 1 II n-\ i
f 00 (N VO l*) S * (N u II OS CNJ O U <~i M O O O M « r- co <s iH <*> IH CB W ftt EH EH 8 > EH J en u 8 « C0t0C0i<<N(N> •J « tj* Tf Tf TJ ^ Tj Tf co 2 z Z tH (DOO< * OSDOS>SSH
* M^M^r-M^KUHH iJQOBSCQ<J* CQ CO CJ < CJ CJ Q
25
o o o o tn u M
3 OS tn CQ QQ M
W W DJ oos tn EH £ £ £ • • • • «C < < < < < < 2 2 2 SSSS tSrHCMrO'* TT
H EH EH CMCMCMCM^invOr^COCPlrHrHrHrHrHr^COrHrH
DJ DJ DJ
Z 2 2 222ZrHrHrHrHrHrHrHrHrHrHrHCMCMCMrO OOOOsssiisisssissiasssisis
Q Q Q CJCJCJCJCJCJCJCJCJCJCJCJCJCJCJCJCJCJCJ U 2
•«• M
U 2 M
DJ
2 M 222ZZZ222222Z2Z222Z
CM Du Cn D_ HHHHHHHHHHHHHHHHHHH .-1 U CO DJ puCUOnCuO*OuOüQiOnOLifaO*OLiCLiOLiOL,Clja,(±i
• Q Q a co QQQDQQQQQQQQQQQQPQQ S >H X >4 DJDJDJDJDJDJDJDJDJDJDJDJDJDJDJDJDJDJDJ tn J 3 J EHEHHEHEHEHEHEHEHEHEHEHEHEHEHEHEHEHEH *tn to to UUUCJUOUUUUUUCJUUUUCJU
rH O 3 3 DJDJDJDJDJDJDJUDJDJDJDJDJDJDJDJDJDJDJ rH 1 O O 222Z2ZZ22222Z222Z22
* iH M M 22222ZZZZZZZZZZZZZZ n > > > ooooooooooooooooooo (S DJ DJ u CJCJCJCJCJCJCJCJCJCJCJCJCJCJCJCJCJCJCJ m os OS OS zzzzzzzzzzzzzzzzzzz oT*
O. CD DOa3D0333DOOD300to=)n • « ^H « kO * *-»**-K**-K*-k-K***-K****
ro * rH * • * «««*««««««««««««««* ts * • * ro * **-K-K********-r:**-t<***
CO ^H (S Ml
»r~ ^H r~ CQ r- •^ J r»r-r-r~r^r~r~r--r~r-r~r»r~r»r«-r~r--r~r~ •* CO ^ U TT % T o • iniriiriiriLriirii/iiriiniriirii/iinirii/iirtLniriLn
M CM • • * » M in • • •• •». f£ ro • nu ro rH O 0. • O < 2 £ is •«• Ut3UU(3ü(3ÜÜUm3ÜUUU!5l3U •—I ro is 2 rH rH 2 • ro 2 is • • CM CM ZZZZZZZZZZZZZZZZZZZ
• •« S CQH • • M «C IS M CM < < z <-H MrHrHMrHrHMMMrHrHMrHMIHrHrHrHIH CM rH CQ -2 S Mi ro 2 s> CQ 2 2 IS IB 2 • ZZZZZZZZZZ222222222 S ^H »no; .-I IS (S OS CM n OS 2 fN CM O CM 0S0S0SQS0S0SQS0SQS0S0S0S0S0S0S0SOSQS0S CJ • CN • < < ,—i U <ZN < O 2 2 U •% rs <<<<:<<:<<<<<:<<<<<:«£<< »r~ rH ro ;$ «> • K 3 2 • X CJ 2 2 V i—1 CJ 223SSE322322223S2222
on cs • cs a\ .—• TT O <N » O O 00 • K
rH U ro CO * • .H • * U OS « •-t u u • CM CM ««««ft«««««*«««««««« • »» <s - rH u f-H *t fe • fe *. .-1 OS •
r- ^o U<J>Q< ^H • f-4 M Q, TT CM Cu ro IS ro rH • rH cucuCDCDQ<CDCMaii^a,a,CDCDCDCDa.CDCua, is • * • £ CJ VO CQ 00 £ • ^H • « £ s» <-* i-l u rH OS £££££££££££££££££££ CJ ^r in ro O k • II « O ro • rH O CQ • • II • * OOOOOOOOOOOOOOOOOOO II s • S(JOD ro z T CJ s IS « U II ro ro EH rH CM CJCJCJCJCJCJCJCJCJCJCJCJCJCJCJCJCJCJCJ tn CJ nuJ • IS •H IS JCQHH •J hss 3 OS • JJJJJJJJJJJJJJJJJJU M II IS II QrocjJOQ II < U Q U CQ CQ O II rH QQQQQQQQQQQQQQQQQaa Q *: UOM IS II •H II tn H II II to to II II J in u tntntotntntntntntotototntntniotntntntn i-> U II o U OK O oou 3VON •H tn II •• 2 < a tn * ll U > DJ * rH n H * a« is < 3 a a • •»i*****************
H OS U3« X 05 < os * en tn tn « DJ co co > j 2 2 ******************* 2 o OS CD * 2 2 2 CQ * (-1 •H l-H * as a a < cu o u *******************
26
I I — •:• . 1
ro«^^«»^«"*«»^«^^ f— t— i— i— p^r^r^r^r^r^issssssssssssromr—ti—ii—it—1>—ii—i SSSSSSSSSSSSSSSSSSSSHHHHHHHHHHHHSSHi-IHHHH UUUUUUUUUUUUUOOUUUUU<<<<<<<<<£<<<CQCaUCJUC>UCJ
zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz Z Z
QQQQQQQQQQQQQQOQQDQQQQQQQQQQaQQQQQQQQCiQO
OOOOUUOUOOUUOUUUUUUUUUUUUUUUUUCJUOCJUUUOUU CdWWUWUUUWWWUUUWiaW&JUWUWUWCawWUUUWM zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz oooooooooooooooooooooooooooooooooooooooo UUUUUUOUUUUUOUUCJUUCJUUUUUUUUUUUUOUUUCJUUUU zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
**************************************** **************************************** ****************************************
ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ^'Z ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZT^nz ix a x a QJ es a: a a x x a a x x x a a a; x x a; a x x a a a a; x a; «XXQSIXXXXX <<<<<<<<<<:<<<<<<<<<<<<<<<<<<<<<<<<<<:<:< <<
************************************»>•»
_ o o u u u u u u u
Q Q rn to
*************************************>•»•
**************************************«. ************************************»»>.*
27
w
II . I I • I "-•*-•"•-•*•"• -'
r- CM .—1
CO .—1 f—1 r-{ (N in vo r» 00 CM r-l
r-H rH
CM r-l
co «* rH rH
r-t ^H ^H <-i •—1 .-1 i-n .—i i—1 1—I r-l i-H i-H .—1 rH rH
u o u u CQ CD CQ CQ CQ CQ CQ CQ CQ CQ CQ CQ
ZZZZZZZZZZZZZZZZ 1-lrHI-lrHrHrHrHrHrHrHI-trHrHI-II-ll-H
Q Q CO CO H E-< u u co co z z z z o o u u z z
a a u u CJ U CO CO z z 2 2 o o u cj 2 2
a a u co E-< En U U to to 2 2 2 2 O O u u 2 2
Q Q CO CO EH EH CJ U CO CO 2 Z Z 2 o o cj u z z 3 O
a a CO CO in H u cj CO CO z z 2 Z o o u cj z z
Q Q CO CO EH EH CJ CJ CO CO z z z z o o u cj Z 2
Q Q CO CO in in V u CO CO 2 2 2 2 O O cj u z z 3 O
Q Q CO CO in in u u CO CO Z 2 2 2 O O u u 2 2 D 3
CM
O CM <a u in
0> >
CQ o 5) u CO
cj * u < <
Ik
CL, • o o en
CQ
CO * QS .-) u
CN
00 Q
**************** **************** **************** r~r~r*-r-r»-r"»r-r»t--r~r"»r--r-~r-«i^r~ inmininminmininmininmininin
22ZZZZ22222ZZZZZ Mt-HMMMMI-HMt-HMMMI-Ht-HMM CM i—I ZZZZZZZZZZZZZZZZ
<<<<<<<<«<<<<<<•<*: EH
CO EH
Z **************** M
SU rH CQ j • ac CJ rH *• > otu l-H > • Q <n be »Q J
CM »CJ • CM >
OHH O • Q (N Q > <S 2 CD CJ cj •
» »EH CO ® CM
H O • o
EH J CM
O o
EH CM U •« O <s •H* i-H
CO rH
Q E< Z
EH
O •H t-H
< > <c
z rH J M < > O, <c •
»EH
rs co CO M os - u o
. cj _J to CJ 3 CO O 3 CO CQ OS
en •
O U co D CQ
GO •
x z
• o CO IX 2
in
CO EH
2 M
lb
• o CM <a u
Mi
oo •
O» CO a CQ
lb
VO
< »
Cu Cu Cb Cu T. ar sr r o o o o uuuu J J j J Q a Q Q w to (A to
•H Z a.cwQjCuQ-.a.aiacD-iQuCucu
OOOOOOOOOOOOUEH CJCJCJCJCJCJCJCJCJCJCJCJCOCO
QQQQQQQQQQQOUZ COCOCOCOCOCOCOCOCOCOCOCOCORH
CO •• ****************O^H **************** K is **************** u CJ
H CO
VO EH
• z HfflH
• Ot •• t^ CM < CQSS X CJ CN
z CM 2 s O U U
• EC Z
co <a 05 CO CQ Q
. .« « CO OICO CJ tH CO .-H < • OS . OS CO «OÜH
T* co -a . os in in
EH OQ .2 CM » •&. t-H
U CM CJ Z O <H < » J • < CM
»• O »i-t CO CO t-H •
• os «os •J »T> j UHMU co ^H o: ac o . u •> m 2 »fH
CM J . . • HO«
OK O U CO > CO < os < o os CQ 2 CQ CJ
CO •
o o CO
CQ
t-H •» co co
in CM • is
O oo t-H Q CO - M CM
»i-H «* •
• o in O cj co M a CO CQ
2 I-H J I-H
< > 2
MHB
O O Ü o CO CO O D CQ CO
CM S •» • i-H
co a • rH CO ^D
• OS s X »oo 2 »"I Q
CM E-l CM r-l O •
• Ü1 O O D CJ M O CO co co a i-H OS CQ
CO
CJ is ts> U U
•S CO rH (S < CQ
a ro Cd • OS z Z M »•J
CTl M . <
X > -CM Z < CM • M
» •» • U CM OO« Q H •
• • 2 CO Q EH Z ü M 2 a M » »u O JHH «.
H <m in • < > CO CO CJ > «C 3 3 M < 2 J J CO •• •• Cli CXi rH •*
•-n rn Q rH i-H t-H CN i-H Z
CJ CQ OS OS CJ CO
CM CO rH f-l
z II CO
CL<
o
28
o*
co z oi a, in
< II z 3 to u Z E-"
cu u
Cu Cu o o
• • w a «e Q sNoons'*««oidBj<« w w i'i">f*fl"<j^'rQ;uMa< s r*r*r»t^r>-r^r»r» ZM
Z Q CO O U O 0.
<N
CO Cd
CO
Cd z o a, z o u Cd 33 EH
HNn*miOM»«SH(S CO a, z o CJ z
CM in
CO z
(*1 Cu -I o
E-« O EH
Cd
< CO EH Z Cd Z o a, z o u Cd X EH
HHvevoMNoo^ifir^wws
>aCiHr<ir»i^*r»<s',o^Hi-i^Hfsii-H ssssssi-HSn-ir-iaschCj Nuuuuu<muin z z o u
H(N(«i*in(or»flOCAsH(Nn
29
CM •
CM IS
r-t r-t
CM m
00
OS
00
co
CO
GO
ao
in
co CM CO
*3* • • • CO • *f ^p CO co co p*
es CM r-t • i-HrHMCMfS HciHrt^inoin • ts c* CM rH » r-t r-t a\ r-t
• •••••• »LTlrH •••CO •••• cococovoinin^"^ m co co vo^cncn
<s i-t co cMco^"invor»cocT>rHrHcnvomrHvomoo\o
CM COCOVOin^^^rH
VO •
r-t co
CM •-( in rH • • •
C* oo CO
i-l CM •«r CO r-t CM H* • in r-t rH CM • • • r-t CM
r-t rH
• • rH CM r-t
T CM <B CO r-t CM • * r-t •H rH r-^ 00 • •
r-t CO rH r-t r-H oo r-» oo oo co o\
COCNl^CMCMCMOOCMTrCMCMCMCNCOCMCNlCMCOCOCMCOCMinCMCMCMCMCMCO
SI en < CM
w II EH
U W z H u u z ac z H
rH CM CO * mvor»ooc*<BrHCMco^mvor-ooc*^rHCMco^,invor>-cocT\ r-tr-tr-tr-tr-tr^r^r-tr-tr-tC^t<>iC4C^C>iC>i(>iCHC^C^
30
r~ •
co ^r
T VO .-i
• c"> (N •
VO PO H (N
CM CO
(N
CM VO
CM VO
CM LO
S CO i—I i-H
• • CM in
ON CM • f-<
CM • in
oo . ^
CM tH
r-» in
CM r-
vo in
<N en
CM CM
^ in •
CM •** i-H
<S • ••(Nrr CO • 2 <-• r- M • Ck ON <t
Q • i-H Cd -H . E-« "* CJ 00 M «-H • z • >-H Z H • O co U r- Z "H CO o • •
cs ea p- -vor- s i-H i-t » T* a iH • CM P- 00
P» i-H S • VO • VO CM VO 1" •
ON St • • i—I S • i-t CM i-H V© • <-t
r~ • r~ *in»io in
OOH «H i-H • • «CM • IT) i—I St
P» ON r-| . . rH *»• vo p»
p» co • oo CM • rH CM rH "IT S •
P"* • • tHS ON *r <-t vo .i—i
vo >-t p~ • CM • P» CO i-H
p^ s H • ^ • rH rH • VO .IS
in • i-H r* iH • ON CO CM
r~ »-H *J* • co ^* P» • rH VO • r-i
*& • IS • p* • • ON i—( CO i-H ON
p~ • p» VO CM CO VO »CO
CO • i-H P~ rH • ON • »Jl • ^1
P- S3 iHkO*H m i-H co • • •
CM • in r~ CM si •WHP> I-H rH
p» i-H • co in • ^* • CO i-H • ON CO
rH • IS • P» i-H • er« rH ^ m p» •
p» t-i «•? • a CO IS «CM ON rH
T • rH CM rH H * • • • 10 CM
• ea co m p» • i—i VO CM rH rH ON •
• • i-H CO S St ON ON CM >-H .001-1 f—i • • p^ • iHSCMlfl ON >-H
VO • rH i-H CM i-H ON . r- • •»* .
ON 00 CM • p» • • ^ • in en si
VO I-H S I-H i-t i-H • i-H rH CO «CO
oo oo * • r^ • s • r» CM in ON rH
vo p» • ^ • • S SI CM rH CM St
P-00i-HiH • • «rH • • in vo ON
VO <*• vo CM ON ^H • ^>S H t
VO <s WI-IH «St • p» i—I • • . <Ti i—I
vo CM ^" vo rH in ^ oo
IflH tOO P-OA H • • •SI ••• • S)
VOr»HN^vO00H
CO
U U Z u w Cu u as
w CO
u EH U Z I u o Q O 3E
EH
Cd
< S3 CM Z z o o
z
EH
H EH EH H J ZUNU UHU> Z Z O M O M J Q rV| ac rH co ^ o U rH CM CO
E-< z a E-i MO e> J J CO EH
J^HHNVBDÜ O UU<«£QISC"H
KUKOino:>>ipoouin hJUUUDU<4QQKH £DUD<«(2 sa x ta < fa H N p-vo m * N
SlrHrHCMCMCMCMCM in VO P- CO ON rH
si rH CM co «* in VO ^•invOP^CDCni-lrHrHrHrHrHrH
< EH
vo
Cd Cd CU Cfc
e e rH CM Si a U u II ii
Cd Cd S X < < z z
CD iC CO E-t EH EH EH O" J O Z Cd Cd Cd z CM C_) CM Cd EH EH EH Cd E-> S > s z z z z z CO U rH CJ O M M l-H o X Q ft. Cu rt ^< X H "-H CM T. U1H ^H o O CJ rH CM CO u i-H CM CO ^r
31
_. „•I,.«.,,,».!.,,., ,. - j
r
n
II
u
u
u £ i in
1 EH 1 CM 00
II II
U u
E «a
< II II
2 2
VO r~
en r-H Q
H OQ H O H ooo (N > O Z > (M CM 8 l-l 2 I-H
H «S3 • Q U Z Q U U J
in C\ vO IT) Tf p*> m <-< CM <-t >-H H ^H
ra r—1 CM CO in ^) ^ .—i H ^H rH
J EH < EH CJ EH O 0<N>OtO ZOIAINOU OU<WW UUDUUBXUIOZKB; ZKfflOKZZDJ 00 O 03 J HI HOO Cu s oo OB a\ mrsii-HCn
CJ<NrO^"lTIVO000n^(rHi-lr-(
EH <r> O 2 W O u os co z o a o CO
B rH r» oo O
M u oca M < O• EH UBIUSZ < U OS U M < CO
r» m rvi .-I ON ,-H
• m vo oo eft i-t
CO M
••»• M Q U EH
EH < 06 Z 2K JH H u o z Z £ o r» vo Oi ^H VO H
OHNfO UHHH
u EH t-i Z CO X Cd M Z z O fJ ON O.NH
O N It CJ H iH
32
1
I EH
U a, e CO
CD
II
U
I
o o U < < C3 O < EH EH g 3
EH EH
in r~ IS <T\ CM rH
II II II n II
w w a, a. ca H U
D B a.
i-H •-H rH •H rH CN rH o ca « 05 u II ii II II II
M u w u u x < s 3 & x
< 2 2 2 2 2
ON CM
EH EH HI 2
2 M * U =*o M *H J =«* =•*: **
CO EH UOOIN •9 CK J M in in H3 OOUUOO«UU<s EH t-i u > BH< EH en EH CO CJ H O ZOOÜHHHÜU9WW» 2 < a < 2 < > 2 O Q 2 3 M Z M Q UUUU)(/lU)taiAUlQ3DQ eg > x 2 z W > < W J 2 UJtO u en 2 ZKOiSHMHDD OQCQ 2 < 2 2 < 2 2 OH O ZHH ZH(J O cQ co cQ m vo O CS rH O O o O a, T ao (Nrnn <N r^ r~ <N o, r» ON <N <N 04 CN r-i a. oo CM CM 00 c» CU ro CM X<>>*'-Hr~<N<MfNr~r~ X <N rH SH(N X <N CN X <N <N X CM <N O SHINfO o «S i-H o o O o UHCNfO*l/1lO«*HHHH CJ 00 Ch •H rH CJ m TT CJ i-H (N CJ rH <N CJ rH <N
33
. A
..I». II III ..11,11 J..I..I .1 „I.....,,.,.--.. ..
* * « a. T. ^ O u o
J •3 a a £ w «* X fa Cd o * 2 * O « M
E-» E- < M Z 3 M U z a B M M u E->
Cb •J o «C
JC a B z o u •-Z
Q « Z * * u « « o *
34
3. LOGICAL AND PHYSICAL LIBRARIES
3.1 Logical Library
3.1.1 Logical Library
The library name definition record is specified as
fol1ows:
LLIB:<1ibrary name>;
3.1.2 Alias Directory
The alias directory consists of a number of alias
definitions followed by: END;
An alias definition has the form
<typename1> = <typename2>;
where <typenamel> is declared to have the same attributes
as <typename2>. This requires the second type to be fully
defined in the body of the library.
3.1.3 Library Body
This part consists of a number of SDL object format
descriptions of various components. The format is identical
to what given in section 2.5 except for the lack of a USER
record.
3.1.4 End of Library
The end of the library is signalled by a record containing
'LEND' in col. 1-4.
35
••, , I I.IIIWW ••!••• « III..WP|,W.....li..|IH ..WMLI^I) •!•!• •">•"•• 'WW —'*-»»"'«^"—--"W——
1
Q-
X
CO
u
H(NrO*lfHOt*00»SH(Nri* i-t CM PO ^" If» «Ä
03 M
* * ^" »o f-t »H i-t f-l a, di Q, 04
*r 2 D rH U 2
M OQ Q U • 0M
8 o u • 2 Cd
OQ U b
Q Q Q Q II II II H SHNfO
« s s a co CD CO CO CO CO M J J «J J
Jr-r~r-r~w2enJ22
i-H iH i-l rH i-l rH rH
££ •JCk«Z22EH22222Z22222222 >SHO0*CUWMHtMMMMMMMMMMWM
UPuCOCOCOCOCOCO QHSEZ2Z222 z<buhuzxzp<aihciiai0iaiBiCvciiCiiiiiDiBi><OHHHHHH
E-i22XXXXXXXXXXXXXXE-<Uaia,a40.a.04
36
k.
X Cd
VO
r- CO a\ IS <-l CM ^CMro^invpr-oo^sii-icMro TT m \o rH <N
vo Z Q <H W Z cu o u M 00 Q U • On
M»»SH(Nrt*
Z Cd
o HH»c«SH(Nrn*irno^oo*SH(Nn*iniOHHH(N
u)cncncncncocotfl(jcdOiiJCk.zzzHzzzzzzzzzzzzzzzzcd04U}io ZZZZZZZZOZO;>»HOCUCViCdMMI-IMI-IMMMMMMh-IMMI-IM(Xi£ZZ HHHHHHHHZ<3UhuzxZBiBiaiBiBiOiaiiiil>iBiii<bi>ialaa><OHH C^CfcCua.AO.a.a.WZft.JZZEHZZXXXXXXXXXXXXXXXXi-iOQ.Q,
37
ro^invor^oowsiHtNPO^invo
w»i/i\fiMS»SHNn^i/ne
UUltOIOCAt/lUlUlUlUlUlIOUUlUQ ZZZZZZZZZZZZZZOZ t-tl-ll-IMMt-tk-tMt-tl-IMMt-IMZW a.o.a,a.a.Q.CL,a.a,a,ixa<aiaiCüi-j
7fi
-
3.2 Physical Library
The physical component library is stored as a sequential file
with the following format:
3.2.1 Header Record:
PHYSICAL LIB: <name>;
3.2.2 Logical Type/Physical Type Associations
a) for every association there will be a statement of
the form:
<logicaltypename> • <physicaltypename>;
b) END;
3.2.3 Physical Type Description:
a) NAME: <physicaltypename>;
b) NPINS: <number>;
Defines the number of pins for this type.
c) OFFSET: <offset1ist>;
Defines for every pin its offset w.r.t pin 1, the
reference pin.
An <offsetlist> consists of a single <offset> or of
several <offset>'s, separated by comma's. An <offset>
is specified as follows: xoffset.yoffset. Both x
and y offset are integer numbers expressing the offset
in mils.
d) OBSTRUCTION: <n>;
Where <n> = NONE if no obstruction.
• COMPONENT if obstruction on component side.
39
= SOLDER if obstruction on solder side.
• BOTH if obstruction on both sides.
e) SIZE: <xsize>.<ysize>;
This indicates the physical size of the component in mils.
f) END;
3.2.4 End of Library Indicator
PLEND;
40
3.2.5 Example
PHYSICAL LIB:EXAMPLE; DIP14=DIP14; ICB0X=ICB0X8; NAME:ICB0X8; NPINS:8; OFFSET:100.0,200.0,300.0,400.0,500.0,600.0,700.0,800.0; OBSTRUCTION:BOTH; SIZE:900.1000; END; NAME:DIP16; NPINS:16; OFFSET:0.0,100.0,200.0,300.0,400.0,500.0,600.0,700.0,
700.300,600.300,500.300,400.300,300.300,200.300,100.300,0.300; OBSTRUCTION:NONE; SIZE:700.300; END; NAME:DIP14; NPINS:14; OFFSET:0.0,100.0,200.0,300.0,400.0,500.0,600.0,
600.300,500.300,400.300,300.300,200.300,100.300,0.300; OBSTRUCTION:NONE; SIZE:600.300; END; PLEND;
41
- •••'
3.3 How to Add a Component to a Logical Library
Currently no programs are available for updating the logical
library. However, since its format is rather simple, one can use
Wylbur to perform this task. Two major types of addition are
possible:
1) If you want to add a component for which there is a similar
description already in the library, just insert a line in
the Alias Directory. (Try to keep this directory in alpha-
betical order.)
2) If no similar description exists, then encode the circuit
in SDL and compile it. Remove from the object file the
USER and CEND records and merge this file into the body
of the library.
42
mi '--• — itja^«^».
3.4 Board Description
The board description has to be stored in a file to be used
by the SDLPCGEN program. It consists of the following information:
1) Board Name
NAME:<id>;
2) Physical Outline
PHYSICAL:<point list>;
where every point is specified as <x>.<y>. All dimensions
are expressed in mils. All coordinates are relative to the
lower lefthand corner of the physical board outline (see
figure 3.4.1).
e.g. PHYSICAL:0.0,0.10000,6000.10000,6000,0;
3) Logical Size and Offset
The logical board is the space allowed for placing components
and for routing connections. The logical board is always
a rectangle and is specified by a size (L0GSIZE) and by the
location of its lower lefthand corner (L0G0FFSET). This
is illustrated in figure 3.4.1.
LOGSIZE:<xsize>.<ysize>;
LOGOFFSET:<xoffset>.<yoffset>;
4) External Connectors
NC0NNECT0RS:<n>;
for every connector:
NAME:<id>;
NPINS:<n>;
OFFSET:<point I1st>;
ORIENTATION:<n>;
L0CATI0N:<x>.<y>;
END;
43
m •••»*•• I I «VUW
Example
NAME:CAMAC1; PHYSICAL:0.0,11990.0,11990.4390,10890.4390,10890.5340,
11990.5340,11990.7230,0.7 230,0.0; LOGSIZE:10400.6300; LOGOFFSET.-500.500; NCONNECTORS:1; NAME:CONNl; NPIN3:42; OFFSET:0.000,0.100,0.200,0.300,0.400,0.500,
0.600,0.700,0.800,0.900,0.1000,0.1100, 0.1200,0.1300,0.1400,0.1500,0.1600,0.1700, 0.1800,0.1900,0.2000,0.2100,0.2200,0.2300, 0.2400,0.2 500,0.2600,0.2700,0.2800,0.2 900, 0.3000,0.3100,0.3200,0.3300,0.3400,0.3500, 0.3600,0.3700,0.3800,0.3 900,0.4000,0.4100;
ORIENTATION:0; LOCATION:10 900.600; END;
44
..*„ ^—
4. DESIGN FILE GENERATION
4.1 Introduction
The SDLPCGEN program combines the output of SDLCOMP (the SDL
compiler, as described in section 2.5), the physical library (as
described in section 3.2) and the board description (as described
in section 3.4) and generates a file which contains all the information
necessary to start the PC layout process.
The output of the program is a new sequential file which
consists of the original SDL object description plus the following
information appended to it.
1) NPHT:
1 record
# of physical types: col. 6-10
2) PNTP:
1 record for eyery physical type
type #: col. 6-10
type name: col. 11-30
# of pins: col. 31-35
obstruction type: col. 36-40
3) PSIZ:
1 record for every physical type
xsize in mils: col. 6-iC
ysize in mils: col. 11-15
45
mum^rmcm^nmmimm -*~J .. K»W •••"•'• "'•-'-»«
4) POFF:
1 record for every pin of this type
Xoffset in mils: col. 6-10
Yoffset in mils: col 11-15
5) L6PH:
1 record for every logical type
logical type #: col. 6-10
corresponding physical type #: col. 11-15
6) ENDP:
1 record ending physical information
7) BNAM:
1 record
board type name: col. 6-25
8) BPAR:
1 record
# of points in physical outline: col. 6-10
I of connectors: col. 11-15
logical Xsize in mils: col. 16-20
logical Ysize in mils: col. 21-25
logical Xoffset in mils: col 26-30
logical Yoffset in mils: col. 31-35
9) BPHQ:
one record for every point of the physical outline
X in mils: col. 6-10
Y in mils: col. 11-15
46
„•_, i HI... ...i — .p ,i». MHI.ii.li I» ..••.» ;.nu. • inn MHIimi«,. nil I ill I.« •! mil .Hill ip-a-i '• yn I • n m . I •'» •• • ' "»"• •'
1
10) CONN:
one record for every connector
corresponding physical type #: col. 6-10
orientation: col. 11-15
X location: col. 16-20
Y location: col. 21-25
The sequential file is then transformed by the LOADFILE
program into a direct access design file which will then be used
by the rest of the system.
47
•III. M.wtiip.v
4.2 How to Run SDLPCGEN
An exec file is available for creating the JCL for running the
program. It can be used as follows:
exec from Irunpcgen user pcb gro eg cle THIS FILE FUNS THE SDL PC GENERATION PROGRAM <CR> CLEAR ACTIVE?
A <CR> will clear your active file. Use a break to save if necessary.
'ACCOUNT = CG.PCB?'
ENTER? cg.wmv
Enter your account number in the format shown. This number
will be used as a prefix for your files.
'SDL OBJECT FILE = SDLOBJ?' ENTER? objl
Enter the name of the SDL object file you desire.
A <CR> will give you the default name SDLOBJ
'SDL BOARD DESCRIPTION FILE = BOARD?' ENTER? boardlib(camac)
Enter the name of the file containing the board description
'OUTPUT FILE = PC0UT1?' ENTER?
Enter the name of the output file. A <CR> will give you the
default name PC0UT1. The system will overwrite a file with
this name or it will create a new file if none exists.
'VOLUME = SCFEV9?' ENTER?
Enter the volume on which the output file should be generated.
<CR> will give you a scratch volume (i.e. SCFEV9).
THE JCL IS NOW IN YOUR ACTIVE FILE READY TO RUN +EXE F PAU
Issue a run command to submit the job.
48
I^H^H^
(S a a sss <S ts (S <s ^O ^O ^O ^O ^B <S Q S IS (S s H(NB IS s es
<-< (Ncinn* m vo r»
* * * * * * * * * * * * « « * * * * « * * * « * •K * « * es * * r-> * « CM *
<1> « rH * « * 'S * r- r~ *
E * • r~ ON * (V * £ en ^r * X
* tf-H 05 -~
m * EH
3 d) « C> «B in * a. x: * O ro i-t « z -t-> He cc *• « M s_ * CM 3S «— * o « u * z 4- * Z OS EH « M
+J •It •K
O 3 3 M x a«
* * Cd 3
a 4->
* «
EH 9 < 6u Cd
* * • 3
3 -J: 05 O W * Z o *
Cd J Z H U U Z
* Q M
Z o * U J «C « en J t-H
* Cd > * a < EH « M > * z £ *C * J Cd • * o Z * M J 3E « u M M * Cu • * u -^ s * -H * * 0} CO * « EH * Ed * Cd Cd * 3 Z EH * r-EHvovovoeDoom •K •J EH * CM O O * vo>Hi~»mo>voooiH CM •X Z M < « iH en o\ es <N in co f- ^H •»r £ J « M CO EH * • ON MhHHHZ Cd fN «C < « 05 Z * S3 J (N»0 a X S * CO Cd O * < ro M CM 05 Cd OS * U > U * SE EH £ O O * a. * M < < 05 II z * « u •J u x: 05 « * Cd Cd M > Cd Cd s: « * r "» CU X * * t-. 8 2 II * < * * « EH o as * * Cd tj II Cd Z OQ z « * Z O X Cd M Cd * * O < • t •• •• J Cd < U J u * * M 01 CO CO Cd 3 X z U u * * EH 3 •• Cd EH •J Ct, 2 CM J CM * « * * * * * * *
Sä.. CO J Z CO CO z EH J < -3 U CO «C • • rC CO U Q U Q Z < EH J J Cd • Cd CO HH CO
CM O Cd HHIAtfHU Cd 3 CO JIQKCUZh^U CO « B: OUOEH<00>D 3 05 * uaEuco>uEH<co Oi * CM *
49
iL — . ^
4.3 How to Run LOADflLE
Once again an exec file is available for helping you to run this job.
It can be used as follows:
exec from #runload user pcb gro eg cle THIS FILE RUNS THE SPRINT DESIGN FILE INITIALIZATION <CR> CLEAR ACTIVE?
A <CR> will clear your active file. Use a break to save it
if necessary.
'ACCOUNT = CG.PCB?' ENTER? cg.wmv
Enter your account number in the format shown. This number
will be used as a prefix for your files.
'INPUT FILE = PC0UT1?' ENTER?
Enter the name of the input file i.e., the output from the
SDLPCGEN program. A <CR> will give you the default name PC0UI1.
'DESIGN FILE - DFILE?' ENTER? mydfile
Enter the name you wish to give to the design file. A <CR>
will give you the default name DFILE.
'VOLUME = SCFEV9?' ENTER?
Enter the volume the design file is to be created on.
THE JCL IS NOW IN YOUR ACTIVE FILE READY TO RUN •> EXE F PAU
Issue a run command to submit the job.
50
- ........ -»,1111 , • .I,,,,«
4.4 Error Messages
4.4.1. SDLPCGEN Messages
When the program terminates normally a message
***SDLPCGEN *** NORMAL TERMINATION
will be printed. This message is not to be confused with
the message: NORMAL TERMINATION IN STATEMENT, which is
generated by the SNOBOL compiler and which may occur even
if the SDLPCGEN ends abnormally due to erroneous input data.
Some messages may be generated because of an erroneous
input caused by a compiler run that did not terminate properly.
Therefore, it is important to check successful completion of
the SDLCOMP program before running SDLPCGEN.
51
... Ii* »Ml
- • • -
error number severity action Explanation
1 8 5
2 8
3 8
4 8
5 8
6 8
7 8
8 8
9 8
10 8
11 8
12 8
13 8
15 8 5
16 8 5
17 8 5
18 8 3
19 8 5
20 8 5
21 8 5
22 8 5
23 8 5
24 4 4
25 4 4
Missing circuit name specification
All physical types required not found in library
Missing or invalid board name
Missing or invalid board outline
Missing or invalid logical board size
Missing or invalid logical board offset
Missing or invalid number of connectors
Missing or invalid number of pins
Missing or invalid offset
Missing or invalid connector name
Missing or invalid orientation
Missing or invalid location
Missing end in board description
Missing or incorrect XPIN record
Missing ENDC record in lib
Missing user name
System limit exceeded
Missing or incorrect NTYP record
Missing or incorrect NCOM record
Missing or incorrect TNPN record
Missing or incorrect NNET record
Missing or incorrect TYPE record
Invalid name in input
Missing or conflicting purpose
52
•nl.« in.WiWMimn J
»W"^^"i"» '." " ii ii.PI
error number severity action Explanation
26 8 5
27 8 2
28 8 2
29 8 2
30 8 2
31 8 2
32 8 2
33 8 1
34 8 5
35 8 1
36 4 1
Missing or conflicting level
Missing physical library name
Missing NPINS in physical library
Missing offset in physical library
Missing obstruction in physical library
Missing size in physical library
Missing end in physical library
Invalid connector location
Missing or incorrect NXPN record
Incorrect connector in board file
Pins of connector not in straight line
53
- — • -• • - -*-—•-*-»•••• - - - -
Possible Actions
1. Correct the board description file
2. Contact the person responsible for maintaining the physical
component library
3. System error; contact the person responsible for maintaining
the system
4. Warning only
5. Check the compiler run; if it was correct take action 3
54
.. ._
4.4.2. LOADFILE Messages
All error messages generated by the LOADFILE Program
are fatal in nature. Most of these errors indicate a problem
with the input file. Check the listing of SDLPCGFN that
created this file and correct any errors. If SDLPCGEN finished
with the message *** SDLPCGEff** NORMAL TERMINATION, then
consult the person responsible for maintaining the system.
If LOADFILE is successful, it will print out a message:
DESIGN FILE GENERATION SUCCESSFUL and some statistics about
the usage of records in the file.
A common error occuring when trying to run LOADFILE
is that the new design file to be created already exists,
especially when you use the default name DFILE. If this is
the case, the program will abend with a JCL error. This
is done in order to prevent accidental overwriting of a
valuable existing design file.
55
5. INTERACTIVE PLACEMENT PROGRAM (PLACER)
5.1 THE PLACEMENT PROCESS
In order to allow maximal flexibility in placing components,
this subsystem is highly interactive.
Several algorithms for optimizing the placement can be invoked
by the designer. Depending on the nature of the design and on the
inclination of the designer, placement may be done completely
manually or completely automatically.
Usually the placement process consists of a combination of
both manual placement and algorithmic placement improvement. The
SPRINT system reflects this philosophy in the following four major
steps:
1) placement of critical components. This step is manual
and allows the designer to carefully place components for which
he considers placement to be critical. The so-called 'critical"
components will not be moved by the automatic placement algorithms
although the designer can do so at all times. The remaining com-
ponents will be classified as "automatic" or "discrete" components.
Discrete components, in the context of this system, are resistors
and capacitors for which automatic placement is difficult. An
example of this are decoupling capacitors between power and ground
in TTL logic or termination resistors in ECL.
2) initial placement of the "automatic" components. In this
phase the designer has the choice between three different initial
56
W^^W^'J I ' . w< ' ' ^""j ii • iw i • •
placement methods:
- manual initial placement: Useful if the designer has a
good feeling of how the placement should look.
- constructive algorithm: This algorithm achieves a
suboptimal initial placement.
- Random initial placement: Random initial placement
randomly places the components. This can be useful
for evaluating several runs of the placement improve-
ment algorithms for different starting points.
3) placement improvement: Two different algorithms are
available: a pairwise interchange algorithm and Steinberg's
placement improvement algorithm. The designer can choose between
these two for every iteration. He can also make manual changes
if he deems this necessary.
4) placement of "discrete" components: In this last phase,
the designer manually places all remaining components.
57
5.2 Using PLACER
5.2.1. Running the Placement Program
A) EXEC FROM #RUNPLCR USER PCB GROUP CG CLR
an explanation of the prompts:
1) Design file=DFILE?
a) <cr>:use the default file name
b) enter the name of the design file you wish to
do the placement on
2) Volume=SCFEV9?
a) <cr>:use the default volume
b) enter the name of the volume which the design
file is on
3) The job is now in the active file, type "exec" to
run it
B) Signing on the placement program
1) If the user receives the message:
FROM OPERATOR: (uuuPLCRn) PLACER IS READY,
(where uuu=user id, and n is a single digit integer)
Type "uuuPLCRn" as a WYLBUR command when you want to
do the placement. Then the prompt: WHAT'S THE MAGIC
WORD? Respond: "punt". This will attach your 4013 to
the placement program.
2) If the user receives the message:
FROM OPERATOR: (uuuPLCRn) DESIGN FILE HAS
NOT BEEN INITIALIZED.
58
• - -
, .,,,,,. ,, _-,
then the placement program has found an invalid
design file (it has nothing in it). The user
should check into how the design file was created.
5.2.2. The Different Stages
A) File identification and cross-checking
to the prompts:
USER NAME?
PROJECT NAME?
the user should identify the design he thinks he is
going to work on. If the user doesn't give the correct
names he will not be allowed to modify the current design.
To stop the program if you have the wrong design, type
"$wyl", this will let you out of the program.
B) Restarting previous placements
If the design has been wired you will receive the prompt:
DELETE ROUTING?
<cr> means no. If you respond "no" then the prompt:
LEAVE PLACER?
will appear. Type "yes" to terminate placer. <cr> will
give the prompt:
DELETE ROUTING? again.
If the design has already been placed you will receive
the prompt:
USE OLD PLACEMENT?
to which you may respond <cr> which means YES, or you
59
• - -
may respond "no" which will not allow you to use the
previous placement. If you restart the placement you
will not be asked for the gridsize or cellular definition.
Instead the old placement will be reconstructed and the
following message should appear:
SUCCESSFUL RESTORE
C) Grid size definition
Place the cross-hairs over the appropriate grid size and
hit the space bar. This will give the desired gridsize.
D) Cellular definition
1) To the prompt:
NUMBER OF AUTOMATIC TYPES?
give the number of physically different types you
wish to be defined as automatic. An automatic
component (one whose physical type is defined as
automatic) can be used specially in various parts
of the program.
2) Defining automatic types
You will be given the prompt:
TYPE NO. n?
for each automatic type to be defined. Type the
name of the physical types you wish to be automatic.
By typing "?" all types available will be listed.
Type "go back" to restart the cell definition stage.
3) Defining the cell dimensions
60
- • • • " M
_.—..., . ..I.l.-J. ., • I.I • II. ..I-. ..I— .. .11. MJ.... I..... I ....I ....—.. I, I, I- 1.1... ....... -
You will be prompted for the number cells per row
and column.
4) Alignment
For automatic components a global direction (or
orientation) is defined. To the prompt:
ALIGN VERTICALLY?
the user can respond <cr> which means YES or "no"
which means align horizontally.
5) If the largest automatic type will not fit inside
the defined cells than an error message will be
issued and the user will have to respecify every-
thing in the cellular definition stage.
E) Placement phase 1_ (critical placement)
menu choice explanations
1) PLACE CRITICAL COMPONENTS
Critical placement allows the user to place any
component exactly as desired.
To the prompt:
COMPONENT NAME?
you may respond
a) The name of the component you wish to place.
After the carriage return, indicate the
reference point (usually pin 1) with the cross-
hairs, hit the space bar. The component has
been placed.
61
i,», iLiJiiiiiiim.l.i -»I J. IJII..IH HWli IJIIII » Hi HHI I .•.-!• »Ji .iiJUJi^imn n.l.ll. n ,iu| I .. .J.ilil I Jin . ill lim «wuw .1 III I iipmnpiw.iii»n|.|»j»»..iiii.ni.; — JII.J •• 1 •
b) RULER -- the ruler will be displayed
c) ? -- list the names of all the unplaced components
Components listed as xxx* must be given a board
connector association.
d) ?xxx — where xxx is a searching field. All
components whose names start with xxx will be
listed.
e) LABEL -- label the components
f) *xxx -- place logical connector xxx using a
board connector definition. This gives the
prompt:
CONNECTOR ASSOCIATION?
you may respond:
i) ?-- list names of board connectors
ii) the name of the associated board
connector.
g) MENU — allows the user to leave CRITICAL
PLACEMENT and select something from the menu.
2) RESTART CRITICAL PLACEMENT
Gives the prompt:
DELETE ALL CRITICAL COMPS?
<cr> means don't delete anything, "yes" means
remove all components placed either in CRITICAL or
DISCRETE placement. (Does not affect automatic
components.)
62
MWWIW'J P. — 'iil'H. •••• . HIIIHUMI ••) J.II,...,P'UI....I..IPPI»...
3) RESTART PLACEMENT
Gives the prompt:
DELETE ALL COMPONENTS?
a <cr> means don't delete anything, "yes" means
delete all components
4) GO BACK TO CELLULAR DEFINITION
This allows the user to return to cellular
definition and redefine those parameters. Components
will remain placed, but all automatic components will
become critical.
5) END OF CRITICAL PLACEMENT
Allows the user to proceed to placement phase 2.
6) See general utilities for other menu options.
F) Placement phase 2 (initial placement)
After all automatic components have been placed the
placement progräm will go on to placement phase 3.
menu choice explanations:
1) CONSTRUCTIVE ALGORITHM — not implemented
2) RANDOM INITIAL PLACEMENT
Place all unplaced automatic components into random
cells.
3) MANUAL INITIAL PLACEMENT
Manual initial placement allows the user to place
the automatic components into specific cells. Menu
options:
63
- • -•-•*—'—• • -•• • • -• - -
.
ä) The user will be prompted with an automatic
component to be placed. Indicate the location
by putting the cross-hairs in a cell and hit the
space bar.
b) EXIT MANUAL INITIAL PLACEMENT
Returns the user to placement phase 2
c) See general utilities for other menu options.
4) RESTART INITIAL PLACEMENT
To the prompt:
DELETE ALL AUTOMATIC COMPS?
<cr> means NO, "YES", means delete all components
placed in the initial placement phase.
5) GO BACK TO CRITICAL PLACEMENT
Allows the user to return to placement phase 1.
6) See general utilities for other menu options
G) Placement phase 3 (placement improvement)
menu choice explanations:
1) STEINBERG
Not yet implemented.
2) PAIRWISE INTERCHANGE
This algorithm tries all possible cell inter-
changes in an attempt to reduce the estimated
wire length. Several important statistics are
given:
a) Ratio of successful to tried exchanges
64
„^^-..«„IMI —> i.» «IIWMIIII>> •»•>«.«<—..».nil mmMMmm^mmtitmmmm
,. .11.111-. . i mini • i iwiii- i " » .um.. . — i. "»"»»'•<•••' 1
b) Estimated total wire length (ETWL)
c) Percentage improvement in ETWL
d) Estimated board utilization
After the pairwise interchange is done the
prompt:
PAIRWISE INTERCHANGE AGAIN?
will appear. <cr> will cause the algorithm to be
done again» "no" will let the user exit pairwise
interchange.
3) GO BACK TO INITIAL PLACEMENT
Allows the user to return to placement phase 2.
4) GO BACK TO CRITICAL PLACEMENT
Allows the user to return to placement phase 1.
5) END OF PLACEMENT IMPROVEMENT
Allows the user to proceed to placement phase 4.
6) RESTART INITIAL PLACEMENT
To the prompt:
DELETE ALL AUTOMATIC COMPS?
<cr> means NO, "YES" means delete all components
placed in the initial placement phase.
7) See general utilities for other menu options.
H) Placement phase 4 (final manual changes)
menu choice explanations:
1) PLACE DISCRETE COMPONENTS
Discrete component placement prompts the user
65
with every unplaced component that is left. If
the user doesn't want to place the current
component, the menu response SKIP COMPONENT will
give a new component to place.
2) GO BACK TO PLACEMENT IMPROVEMENT
Allows the user to return to placement phase 3.
3) SKIP COMPONENT
Valid only in DISCRETE placement.
4) END OF PLACEMENT
If all components have been placed the user is
allowed to leave PLACEMENT and update the design.
5) See general utilities for other menu options.
5.2.3. General Utilities (an Explanation of Various Menu Options)
A) DISPLAY
Display allows the user to change the scaling for board
viewing. Menu options:
1) CURRENT SCALE, MAGNIFY xx, REDUCE xx
Change the scaling by this factor. The user
indicates the new center of the screen when the
cross-hairs come up again.
2) See general utilities for other menu options.
B) RESET SCALE
Set the scale such that the entire board can be viewed.
C) LABEL
Write the names of each component over each component.
66
. ,.
.,..,.. ML .•... .1111. WM,!» I«. • •— ••• •.»..•II — •.-LIU •>-••• -.....••
D) RULER
Display the ruler.
E) RESUME
Return to wherever you came from.
F) HELP
A future feature.
G) MANUAL CHANGE
Manual change allows the user to move and delete
components from the board. Menu options:
1) EXCHANGE
Use the cross-hairs to indicate the two components
to be interchanged. All locations are exchanged.
2) DELETE
The component indicated by the cross-hairs will
be removed.
3) MOVE
a) Critical components are moved to the exact
location indicated by the cross-hairs.
b) Automatic components are moved to the cell
indicated by the cross-hairs.
4) CRITICAL MOVE
The component is moved to the exact location
indicated by the cross-hairs.
5) CLEAN
Regenerate the picture on the screen.
67
• - - ••- • -••-—• ••—••• • --•*-*-—— .»•- -••--
_ „*.
• •-[•••i -.«•••••• ,m< »—••'•i ••• .»»•• '• ' 11
6) See general utilities for other menu options.
H) SAVE/RESTORE
To the prompt:
SAVE OR RESTORE?
1) SAVE -- This will update the design file with this
version of the placement. Routing cannot be done
on a placement saved this way. To the prompt:
LEAVE PLACER?
<cr> means "no". A response of "yes" will terminate
the PLACER.
2) RESTORE -- This will reconstruct the placement that
is in the design file. (If no placement has been
put in the design file then that is what will be
reconstructed.)
5.2.4. WAIT INSTRUCTION
Whenever the prompt:
CONTINUE (CR)
appears this means that the user is to hit <cr> to
continue with the program. (If the user responds
"stop" the program will be exited and the design file
will not be updated.)
5.2.5. SPECIAL PROMPT RESPONSES
A) "$wyl" -- Allows user to exit from the PLACER (go
back to WYLBUR). To return to PLACER type "uuuPLCRn"
68
_
IWWPP" » '• fom.mmm • •• IILIIIIJ. •«•»• • i'^» w • ..•—••«• I I ^i • -••» »- • • >W • ' • "•••"- — -1 • •— •• i —..-- —
like was done initially.
B) "comment" -- This allows the user to type directly into
the PLACER log. This is particularly useful if a user
encounters an error he wishes to show to a systems pro-
grammer. After typing "comment" the prompt:
EXPLAIN:
will appear. Tell your problem. To get back to the
original question make the character before the <cr>
a PERIOD (.); this will allow you to stop commenting.
Don't forget to take the output (PLACER log) to some-
one in charge of the SPRINT system.
5.2.6. PLACEMENT LOG
The placement program gives the user a complete log of
his actions during the execution of the program. If
you should encounter a problem:
A) Release the output.
B) Contact the person responsible for the system.
69
*—*•'••""-""'-" "••
5.3 Error Messages
error number severity routine description
5 1 GETGRD
6 1 INITPR
7 1 INITPR
8 2 GETCLL
10
11
GETCMD Menu line selected is not an allowable choice. (Message was written to user.) Fixup: Reprompt
GETINT A non-integer has been entered. (e.g. 7.1 or 7YES) Fixup: Reprompt
GETREL A non-real has been entered, (e.g. 7YES) Fixup: Reprompt
GETREL Multiple decimal points have been entered instead of a real, (e.g. 7.12.8) Fixup: Reprompt
Invalid gridsize entered. Fixup: Reprompt
Incorrect project name. Fixup: Reprompt
Incorrect user name. Fixup: Reprompt
Cells defined by user are too small for type(s) specified. Fixup: Reprompt
SETOBJ Object space range is out of order--PROGRAMMER error.
No fixup. Job terminated.
SETSUB Subject space range is out of order--PROGRAMMER error.
No fixup. Job terminated.
GETCLL Zero components per column is clearly not valid. Fixup: Reprompt
70
—*-" • •"•—•"••-•"•
error number
12
13
14
15
16
18
19
20
21
22
severity
1
1
1
1
24
routine description
GETCLL Zero components per row is not valid. Fixup: Reprompt
GETCLL Type name specified for automatic placement is not on catalogue. Fixup: Reprompt
GETCHA Too many characters typed in. Fixup: Reprompt
IPLCMT Instruction during initial placement cannot be identified. Fixup: Ignore and continue
IPLCMT Assigning more than one automatic component per cell is not valid. Fixup: Reprompt
GETCLL Too many components per column in the cell definition. Fixup: Reprompt
GETCLL Too many components per row in the cell definition. Fixup: Re prompt
GETCMD Invalid menu choice.
MANCHG Component must be indicated when exchanging components. Fixup: Reprompt Invalid delete command.
CPLCMT The component name indicated could not be located either because it had already been placed or the name was invalid. Fixup: Ignore
CPLCMT Placement causes overlap. Fixup: Ignore
71
error number severity routine description
26
27
30
31
32
33
34
35
36
2
5
2
2
MANCHG
DISPSG
DISPLY
MANCHG
REMOVE
GETCLL
GETCMP
GETCEL
GETCLL
37 2 PLACE
38 2 PLACE
39 2 PLACE
40 2 PLACE
41 2 IPLCMT
42 2 MANCHG
Invalid exchange command.
Too many segments to display. PROGRAMMER error.
No fixup. Job terminated.
Invalid menu choice. No message sent to user.
Fixup: Reprompt
Invalid delete command.
The user has not indicated a component with the cross-hairs, and no component was removed.
Fixup: Ignore
The user has indicated more types for automatic placement than are available. Fixup: Get new value (NAUTO)
No more records in comp. list. Probable USER error.
No fixup. Job terminated.
No more records in cellst. Probable USER error.
No fixup. Job terminated.
The user has indicated a type as an automatic type more than once. Fixup: Reprompt.
The same as error #30.
The same as error #30.
The same as error #30.
The same as error #30.
The same as error #30.
The same as error #30.
72
_. . .. ..,..•-—^„„^„^.
IIUWII III II • '•*• ' " ••• '"
error number severity routine description
43
44
45
46
47
49
54
2
6
50 1 DPLCMT
51 1 DPLCMT
53 1 PAIRP
NEWPIC No more space in the graphic element. (Recompile with a larger element.) No fixup. Job terminated.
MANCHG Component was not moved to new location because of overlap. Fixup: Replace component and
reprompt for a new component to move
MANCHG The same as error #21. Invalid move command.
GETCIR Component and net cross listing dynamic lists have been over- flowed. Probable USER error. No fixup. Job terminated.
GETCIR Pin type in net list has an invalid value. Probable USER error. No fixup. Job terminated.
DPLCMT User asked for discrete com- ponent placement while doing discrete placement. Fixup: Ignore
The same as error #1.
The same as error #24.
Component table overflow; Too many dummy components. Fixup: Stop placing dummy
components.
IPRAND Not all automatic types will fit on the board. No more will be placed. Fixup: Continue
73
.. I., . —
error number severity routine description
55
56
57
58
1
8
PAIRP Net list overflow; too many nets involved in component pair interchange. (Recompile with a larger array for common nets in subroutine PAIRP.) No fixup. Job terminated.
GETCIR Too many types, nets, or com- ponents defined. (Recompile with more space for these data fields.) No fixup. Job terminated.
CPLCMT The same as error #1
RESTOR RUN error. PROGRAMMER error. One or more components have replaced on the board in- correctly. No fixup. Job terminated.
59
60
61
PLACE
GETCIR
GETCIR
62
63
The menu instruction "skip" is only valid while in Discrete Placement. Fixup: Ignore
Pointer to the board records is equal to zero. (Invalid design file—bad data.) USER error. No fixup. Job terminated.
Too many type pins defined by design file. (Recompile with more space for type pin definitions.) No fixup. Job terminated.
GETCIR Component names have overflowed the name list. (Recompile with more room for names.) No fixup. Job terminated.
GETCIR Typed names have overflowed the name list. (Recompile wi th more room for names.) No fixup. Job terminated.
74
——-w. .... . «mm .:
error number
64
65
66
67
68
69
71
72
73
74
99
seven' ty
5
3
1
8
2
8
routine description
DISPNB The integer to be displayed is out of range (too big). PROGRAMMER error. No fixup. Job terminated.
PROMPT The prompt to be assigned is too long. Fixup: Truncate to prompt
to the maximum size.
CPLCMT Logical connector has fewer pins than associated board connector. Fixup: Continue
CPLCMT Logical connector has more pins than associated board connector. Fixup: Reprompt
FDUMP NAUTO is greater than 19. Fixup: NAUTO set to 19.
PAIRP No automatic components have been placed. Fixup: Exit pairwise inter-
change
CPLCMT Cannot assign non-external com- ponents to board connectors. Fixup: Reprompt
CPLCMT A non-external component has no physical type. No fixup. Job terminated.
GETCIR A net has no pins. No fixup. Job terminated.
PLACE Must associate all logical connectors with board connectors. Fixup: Go back to Critical
Placement
GETREC No more free records available. Probable USER error. No fixup. Job terminated
75
^ _...„..
6. MANUAL PREWIRING OF CRITICAL CONNECTIONS (MWIRE)
6.1 Introduction
The MWIRE program allows a user to route critical connections
manually, using an interactive graphics terminal. It can also
be used for routing multi-width wires (e.g. for power and ground
connections).
6.2 Using MWIRE
6.2.1 Exec File
An exec file has been provided for using MWIRE. It can
be used as follows
exec from #runmwire user pcb group eg cle THIS EXEC FILE RUNS THE MANUAL WIRER. Type "?" for help.
A reply of ? to any prompt will explain the question.
<cr>=CLR ACT or SAV filename? clr act
A response clr act clears your active file while SAV x
will save it in a file x under your account number.
DIRECT ACCESS FILE=DFILE? dfile21
Enter the name of the design file containing the problem
(in this case the name is DFILE21). The default name
is DFILE.
FILE DFILE21 ON V0L=SCFEV9?
Enter the volume on which the design file is stored.
A <CR> will give you the default volume SCFEV9.
76
... -••«I I I P«WI«W
GROUP.USER = CG.PCB? cg.wmv
Enter your group and user name in the format shown.
6.2.2 Explanation of Menu Commands:
A) SET NET -- SET NET sets the current net. Wires may be
placed and removed only from the current net. You may
set current net for any net. Even nets you have com-
pletely wired. This allows you to wire net A, wire
net B, and then unwire and modify net A.
B) GET PIN -- GET PIN is used to release the pin which you
have pointed to with the cursor. This is useful when
you have pointed to the wrong pin when starting a run.
C) DISPLAY -- DISPLAY allows you to change the board area
on the screen. The options include:
1) RES - reset picture to full board
2) RED - reduce magnification
3) CUR - use current magnification
4) MAG - increase magnification
Options 2, 3 and 4 require a second 'hit' with the cursor
to indicate the center of the sew screen image.
D) SET SIDE -- SET SIDE allows you to explicitly define the
side on which the wires are placed. Options include:
1) H - put wires on horizontal side (auto router)
2) V - put wires on vertical side (auto router)
3) C - put wires on component side
77
" I .1.—I — - ' «»•• •' •
4) S - put wires on solder side
5) BOTH - put wires on horizontal and vertical to
match the auto router.
Note that H and V will be paired with C and S thus
showing the auto router's preferred alignment. Wires
placed on the wrong side (with respect to the auto
router) are obstructions to the auto routing process and
should therefore be used cautiously. The BOTH option
will automatically choose the correct side for each
wire placed and should therefore be used whenever
possible. The current side set can be seen with the
show status command.
E) SHOW STATUS — the SHOW STATUS command displays the
following useful information:
1) current wire width in grids
2) current side mode (see SET SIDE)
3) current net (see SET NET)
4) number of unwired pins in current net (if set)
This command should be used whenever such information
would be helpful.
F) REMOVE SEGMENTS-- this command allows you to 'pop'
segments off the net stack. You will be asked for the
number of segments to remove. A response >= the current
number of segments for the net will remove all segments.
78
.- , ...
NJIlllllll Piling IWII —
Note that multi-width segments are considered as
single segments.
6) Set wire width -- this command causes the prompt
wire width in grids?
to be issued. An answer of 1 will allow all wires to
be placed single width from pin to pin or pin to segment.
If a width of > 1 is given then you will be placed in
multi-width mode. In multi-width mode you will not be
allowed to intersect with pins and therefore wire from
point to point or point to existing wire (point being a
place on the board free from wires and pins).
** NOTE ** When in multi-width mode you are required to
give three cursor 'hits' for each segment. They are:
1) starting point (not at pip or wire)
2) finishing point (to or through intersecting wire
is allowed and wire will be trimmed)
3) direction of width (high or low from base line)
In single width mode wires require:
1) a hit at origin pin of run (only for first segment
of run)
2) a 'hit' at every corner of run (to or through wire
or segment; intersections will be trimmed).
It is generally recommended that all multi-width wires
be placed early. After all multi-width wires are placed it
79
.. ....
• •• • '• i* '' •"• ••'• ' •'•••' • . • II • '• 1 •• Uli uuii ,l}m •jp.miiin •! •• !• • '•• •
is very simple to reset width to 1 and connect all the
multi-width wires to pins with single width wires.
H) SKOWUNWIRED PINS -- this command will flash the unwired
pins on the screen. Note that this command is only
valid if the current net is set.
I) LABEL COMPONENTS — LABEL COMPONENTS simply labels each
component on the current screen image.
J) END MANUAL WIRING — this command allows you to exit the
manual routing program. If you have placed any segments
you will be asked to ok the exit. This is just a safety
in the case that you don't want to exit. By responding
with anything but 'yes' you will be returned to the
wiring mode. Typing 'yes' will end the interactive session
and update the design file with all new segments and vias.
6.2.3 Starting Sequence
When the interactive subsystem is active you will
be asked for your name and the project name. This is
to be sure you are using the correct design file. The
prompts will be repeated until they are answered correctly.
If you are not sure of the project name then type '$WYL' and
cancel the job.
** NOTE ** If the design file has any wires in it
(either from previous manual wiring or auto routing) then
the prompt: 'board wired, type "yes" to start over'
80
will be issued. Should you not wish to remove all the
old wires then answer '$WYL' and cancel the job. If you
want to start over then answer'yes' as instructed.
** NOTE ** A response of 'yes' to 'board wires, type
"yes" to start over' will not remove the old wires until
the end of the job. If you respond yes and then later
cancel the job abnormally then all wires will be left
as before the job started.
It is possible to simply remove all the wires from a
board by responding yes to the start over question and
then not placing any manual wires. This will clean the
board for the auto router.
6.3 Error tessages
error number severity procedure cause action
101 1 wident wrong user name retry
102 1 wi dent wrong project name retry
103 6 wident board not placed abend
104
105 7 wloadc rec #1 comp ptr <=0 abend
106 7 wloadc rec #1 board ptr <=0
abend
107 7 wloadc rec #1 net ptr <=0 abend
108 2 wire invalid cursor command
ignored
81
" " '• •'••PI II •») • • •..»»••.! -—... • •"••—"~——-—r—
error number severity procedure cause action
109 2 wire "show unwired pins" before set net
ignored
no 2 wire "remove segments" before set net
ignored
in 2 wire "start net" with an open run
ignored
112 2 wire invalid net name given
reprompt
113 2 wire "get pin" before start net
ignored
114 2 wire "get pin" with an open run
ignored
115 2 wire invalid pin pointed to by cursor
retry
116 2 wire cursor off board retry
117 2 wire pin intersection on multi-width
retry
118 2 wire invalid via this segment
wire not placed
119 2 wire pin intersect with different net
wire not placed
120 2 wire pin intersect causes loop
wi re not placed
121 2 wire subnet formed on pin intersection
wi re not placed
122 2 wire wire intersect with di fferent net
wi re not placed
123 2 wire wire intersection causes loop
wire not placed
82
J
error number severity procedure cause action
124 2 wire "end manual wiring" with open run
ignored
125 5 putseg no more room for segments
abend
126 8 getrec no free records in design file
abend
127 2 wire "set wire width" with an open run
ignored
83
-• -
***WARNING*** Special care must be taken when routing
multi-width wires to avoid later errors in HIWIRE. In
particular, if multi-width segments are used in a net they
must form a single connected network branching out from
one or more pins in that net. This is a special case of
a general requirement: all prerouted segments in a net
must be electrically common with each other and with a
pin in the net. This requirement is enforced when wiring
single-width segments but unfortunately has not been for
multi-width segments. Failure to connect to at least one
pin (with a single-width segment) will cause an error halt
in HIWIRE; failure to keep all segments connected will
result in disjoint path? for the net in the final routed
board.
84
-• • • - •••-•-•
WP...W,..«,.— >..*. K«*«l -I • • •• I— Uli UM! ••• I ll»l •.»•»«U • J.lll II INPII I-!P^—- .—T!.P«F<.^»"»^- P"- • Hi-" -.,•.,,.•,,-,— »-.--11.1
7.1 BATCH ROUTING PRuGRAM (HIWIRE)
7..1 Introduction
7.1.1 Purpose
HIWIRE is an automatic batch router using a modified
version of Hightower's algorithm to route two-sided PC
boards. The algorithm provides a relatively high connection
completion rate using relatively small amounts of computer
time. It is, however, only a heuristic, and will not necessary
find the optimal path between two pins or even find a path at
all when one might exist. A fair amount of optimization is
done by the program, though, to maximize the chance of
finding a good path.
7.1.2 General Use
HIWIRE uses the design file for input and output.
PLACER must have been run on the design file to provide pin
locations for the networks, and MWIRE may have been run to
route multi-width busses or critical wires, and to insert
wiring obstructions. After routing is completed (as far as
possible), the design file is updated by inserting information
about the segments and vias. This information can then be
used by VIAELIM to minimize the number of vias or be output
on the plotter. In addition to the design file output, HIWIRE
produces a listing of all connections it has made for each net,
a list of pins it has been unable to connect and the paths it
85
M-"-"' • - - —**—*-»-—^——-^— - .... • .—^..~.
••• —• -»•—?-^«•—••'••• JPP..P» m.. •!•• jii.miiwHPi
1
tried, and general information about the design file and the
job. This information may be printed, if desired.
7.1.3 Applicability
As stated above, HIWIRE can only handle boards with
two signal planes at the present time. Routing is done with
all horizontal segments on one plane and all vertical segments
on the other, though VIAELIM will try to bring as much of each
path on one side of the board as possible. The board size,
number of pins, number of nets, etc., which can be handled
is fairly arbitrary; most parameters can be set at run time
instead of being fixed in the program. Another factor in applicability
is the quality of the routing obtained for a given circuit.
All that can be said here is that HIWIRE will do the best it
can with the placement it is given. Care must be taken to
avoid producing overly congested areas on the board (e.g.,
near an external connector) or manually routing too many (or
too long) 'wrong' side wires (which act as obstructions to
HIWIRE). With experience, you will probably develop your own
estimation of what will and will not be routable at an acceptable
level of completion. The ease with which a placement can be
modified, combined with the relatively fast execution of
HIWIRE provide a system for adaptively improving the router's
86
' ' ' "imp m ii in JI
performance on a given board. Hopefully, all connections can
be completed or few enough will be left that only minor editing
by hand will be necessary.
7.2 Using HIWIRE
A) An exec file is provided to help you run the router. To
use it type:
exe fro #runroute use pcb gro eg clr
After an introduction, the exec file will prompt you for
information needed to run the job. The prompts are:
1. <CR>=CLR ACT or SAV filename?
Typing a carriage return will clear the active
file. If there is something there you want to
keep, type a save command to put it into a file.
2. FILE ACCOUNT = CG.PCB?
Type the account under which the design file is
stored. The format is group.user. Type a carriage
return if under the default account.
3. DIRECT ACCESS FILE = DFILE?
Type the design file name or <CR> for default
filename.
4. (FACC).(DAFNAME) ON VOLUME = SCFEV9?
Type the name of the volume on which the previously
specified design file is to be found (<CR~> for default)
87
taM i—i
. i i .wiwwwp
^
5. TIME = 4?
Specify the length of time you wish to let the
job run. The default time of four minutes should
be adequate for most boards. If the board is small,
you may be able to get by with as little as half
that much, and by specifying a smaller time limit
you can increase the job's priority and shorten
your wait time. Some very large boards (or fairly
large boards with a bad placement) may take more
than 4 minutes, but if you must specify a larger
time limit, be forewarned that the job's priority
will go down drastically and you may have a long
wait ahead of you. Still, it is always best to
be sure you have given the job enough time to run;
a partially run job is of no use and in the worst
case you may leave the design file in a partially
altered state. The answer to this prompt should
be <CR> for the default time, a single digit for
a time limit in minutes, or something of the form
'(m.ss)' for a time limit in minutes and seconds.
6. OUTPUT LEVEL = 1?
Not all of the output HIWIRE is capable of pro-
ducing may be useful every time the program is
run. This prompt allows you to select the amount
88
. i ii.
, .,.,.,, ...... ..: ..
of output generated. Available levels are:
0 - Overall statistics and error messages only
1 - Level 0 plus an indication of unconnected
pins for each net.
2 - Level 1 plus a list of what pin-to-pin
connections were attempted and whether or
not they were successful.
3 - Level 2 plus lists of endpoints for each
successful path.
4 - Level 2 plus detailed information (dis-
cussed below) about the unsuccessful
connection attempts.
5 - All possible output (Levels 3 and 4
combined).
Type the number of the desired output level or
a <CR> to use the default.
MODIFY CONSTANTS (<CR>=N0)?
If you wish to run the standard version of HIWIRE
(the array sizes are set to handle a fairly large
and complex board), simply hit a <CR>.
Otherwise, you may change certain important
constants in HIWIRE for this particular run.
There are at least three possible reasons for
89
——•*--— • • •• -- - -
—. j. -»•• ni.i p. i mwi.wjiwij« ....... H ..._.,,. , ,„ ,,,, _,. ..im.«.,,..,
1
doing this:
A) You have a small board which does not re-
quire the large array limits provided in
the standard version. Decreasing the
memory requirements has the same effect as
decreasing the time limit - your priority
and turnaround time are improved.
B) You have a very large circuit and an error
message says you have overflowed some table
limit. You can increase the size of that
table and try again (you may want to increase
the size of several of the tables, since they
are fairly well matched to a given maximum
size circuit). The default memory size
should be adequate for almost any increase
in table sizes.
C) Some of the constants control how hard the
router looks for a path and how desirable
the final path will be. You may wish to
change these values, although the default
values are considered to be close to the
optimum.
90
„ ,. m i —^ vtmm—-^——•——*————*•-—?—*»~n—T !•»•--T— -^.—r—
8. The constant prompts:
You will not get the following prompts if you typed
<CR> to prompt #7. If you wish to use the default
value for a constant, type a <CR>.
A) NETTL=300?
Maximum of 300 signal nets.
B) PINTL=1500?
Maximum of 1500 pins.
C) SEGTL=4000?
Somewhat difficult to define; a net will use
one segment for each X or Y coordinate along
which any of its segments lie. Some work
space for the next connection is also required.
D) XTNTTL=6000?
Closer to the actual number of segments,
but includes 2 elements for each unconnected
pin (including those not belonging to any net)
and some workspace for figuring the next
connection.
E) BRDXSIZE=250?
BRDYSIZE=200?
Maximum X(Y) coordinate (in grid units) of
any point on the logical board.
F) EPTL=41?
Approximately the number of segments HIWIRE
91
.—
AD-A0H5 653
UNCLASSIFIED
STANFORD UNIV CALIF DIGITAL SYSTEMS LAB F/G 9/5 SPRINT - AN INTERACTIVE SYSTEM FOR PRINTED CIRCUIT BOARD DESIGN—ETC(U) JUN 77 W M VANCLEEMPUT» T C BENNETT, J A HUPP N0001U-75-C-0601 =1
DSL-TR-1U3 NL
2OF2 AD4045e53
•
DAT! FIIHED
|J | l_77 DDC
21 121 1.0 '"BS II I« 22
kl
1.25
my
IIIIIJä
1.4 11.6
MICROCOPY RESOUUttON UM CHM&1 NAtlnN.'ii HMI'IAIi 0| JAND*RDS I'"'' ft
will draw before giving up on a given
connection. Increasing this may increase
the number of connections found, but the
number of segments and vias in the added
paths may be unacceptable.
G) MAXNETPASSES=2?
Maximum number of passes HIWIRE will make
through the unconnected pins in a net,
trying to connect them to the connected
group of pins and segments (HIWIRE main-
tains a single connected group of pins; no
separately connected subgroups of pins are
allowed). HIWIRE will continue trying to
connect unconnected pins to the connected
group until this number is exceeded or no
connections are made on a given pass.
H) MAXMISSES=10?
In the path refinement process where extra-
neous backtracking is eliminated from the
original paths coming from the basic routing
algorithm, this constant governs how far
HIWIRE will look for a chance to improve
the path. An increased value will increase
run time but may improve on some paths found.
92
ll»l 1
I) VIATL=200?
The via table must be able to hold all of
the prerouted vias (from MWIRE or previous
HIWIRE run) plus the maximum number of vias
produced in any of the nets.
J) G0REGI0N=512?
Specifies the program's memory requirements
in multiples of 1024 bytes. Default value
should be able to accomodate almost any
increase in table sizes; with enough decreases
in table sizes for a small board, this can
be reduced to 320 (possibly 256 in extreme
cases). Decreasing memory requirements will
improve priority and turnaround time.
B) Unless something goes terribly wrong (bad answers to some
of the exec file prompts could be one cause), extensive
printed output about the routing should be available. This
includes:
1) Information about the input design file:
A) User name
B) Project name
C) Gridsize
D) Major component alignment (0 for horiz., 1 for
vert.)
E) Total estimated wire length in grids
93
I IMh- - •--- --*-—• • •• r»-i..—
2) Nets are listed in the order in which they were
attempted. Nets are routed in order of increasing
size of the box that would enclose all pins in the net.
Routing for one net is taken as far as possible before
going to the next net and no backup is allowed.
3) Within a net, pairs of pins are chosen for each
attempted path and printed in the form:
COMP #1 PIN #1 XLOC YLOC => COMP #2 PIN #2 XLOC YLOC
Where #1 is the source and #2 is the destination (in
many cases pin #2 ends up only giving direction to the
path since the actual connection will often be made to
some existing segment of the net instead of to the pin
itself).
4) A pin pair will either route successfully or not. If
a path is completed, the coordinates of each segment
endpoint are listed, starting with the source pin and
ending either the destination pin or the point at which a
connection was made with a previous segment. If no path
is found, a message is printed to that effect. If
HIWIRE thinks the failure may have been due to too
small a value of 'EPTL' (see exec file prompts), it will
add the message: 'path too long'. Finally, a table
is printed to indicate how HIWIRE was attempting to
complete the path. Columns in this table are:
A) Line number
94
• • • •--..-.. - . . - ..—... . .-... -.- .,,..,——.—.
—
B) X location of 'corner'
C) Y location of 'corner'
D) Minimum coordinate of test line through 'corner'
in specified orientation
E) Maximum coordinate of test line (with 'D)' indicates
where that line was looking for an intersection)
F) Orientation (l=horizontal, 2=vertical)
Entries coming down from the top of the table are from the
source pin, those coming up from the bottom are from the
destination pin (test lines are sent out from both pins to
increase the chances of connection). This list of the
automatically attempted path may aid the manual insertion
of unroutable wires. It can also indicate areas of blockage
on the board; if one or both of test line lists stop con-
siderably short of the center of the table, it probably
means a blockage exists.
5) The output for each net ends either with a statement that
all pins were connected, or with a count and list of the
unconnected pins.
6) After all possible routing is completed, a summary of the
routing is given, including:
A) Number of pins on board
B) Number of unused pins (not in any net)
C) Number of unrouted pins (in net but not connected)
D) Number of segments generated
95
• -
I ~~" ' • " ,,.,,,.-. ' ' «II I I. I II I II I I « • I-IX.I-! IMI > I »• • •
E) Number of segment elements used (LSEG) - compare
to Exec file constant 'SEGTL' (doesn't include work
area)
F) Number of extent elements used (LXTNT) - compare
to Exec file constant 'XTNTTL' (doesn't include
work area)
G) Actual number of segments put into design file
(straight lines broken into segments by vias are
output as a single segment to save space in the
design file) and their total actual length
H) Number of vias put into design file
I) Index of next available record in design file
7.3 Error Messages
The classes of errors recognized by HIWIRE are:
A) WIRING ALREADY COMPLETE IN DA FILE
Safeguard to prevent overwrite of wrong design file.
B) INPUT OUT OF RANGE
Bad input is specified; check to see that it really
is valid and change appropriate limit using exec file
if necessary.
C) INCOMPLETE PLACEMENT IN DA FILE
Flag indicating completed placement is not set; place-
ment has not been run or completed.
D) CHAINING/COUNT ERROR IN NET REALIZATION (VIA LIST) RECORDS
Number of segments(vias) specified does not equal that
96
_ i • ... .. - - • ~-
P"' '•"' • 'I "• •
I
found. Compress the design file and save it for
later analysis along with the router output.
E) TOO MANY SEGMENT GROUPS (UNIQUE SEGMENTS) (VIAS)
Out of space in one of the dynamically allocated
tables. Change the indicated limit using the exec file.
F) DESIGN FILE OVERFLOW
A fatal error. Not enough room to add
all of the segments and vias produced by HIWIRE but
some probably have been added. A good reason to keep a
compressed backup copy of whatever work has been
completed betweeen runs of any two SPRINT programs.
G) PIN TO BE ROUTED NOT FOUND AMONG OBSTACLE POINTS
All pins are considered to be obstacles, even to wires
from their own net, until it is their turn to be
routed. Here, something has gone wrong with that
convention. Save the compressed design file and router
output for later analysis.
H) PIN OFF LOGICAL BOARD
Probable program error in either PLACER or HIWIRE.
Could also result from using a design file that has
somehow become partially mangled. Please save the
compressed design file and router output for later
analysis.
I) PREROUTED WIRES BUT NO CONNECTED PINS IN NET #n
97
— -Him l liirimmnrin llllllllH i i i i i-i l I I
The segments for any net must be a connected
whole which also includes at least one pin.
MWIRE, unfortunately, does not check this condition
when multi-width segments are involved. Manual and
automatic routing must be redone.
98
L • - — -—
8. VIA ELIMINATION PROGRAM (VIAELIM)
8.1 Introduction
8.1.I Purpose
VIAELIM is a batch program designed to eliminate unnecessary
via holes from the automatic routing produced by HIWIRE. This
is a fairly important function, since HIWIRE routes all paths
with horizontal and vertical segments on opposite sides of a
board, resulting in a large number of vias. If carried through
to the final board, these vias would increase the board's cost
and decrease its reliability.
Another property of VIAELIM is that, in changing the locations
of segments from one side of the board to the other to eliminate
vias, it may clear previously blocked paths and allow further
routing to be done by another pass through HIWIRE. Segments
now on the 'wrong' side will act as new obstructions to automatic
routing, so one should not expect large numbers of previously
unroutable pins to be routed by this process. Some improvement
in the completion ratio, however, could occur.
8.1.2 Implementation
VIAELIM is based, in part, on an algorithm presented by Stevens
and Hashimoto at the 1971 Design Automation Workshop. Basically,
it models the routing as a graph in which the nodes represent
disjoint sets of mutually intersecting segments and the edges
represent vias where segments from different groups connect.
Each node is assigned one of two colors, indicating that seg-
ments in the set either stay where they are or switch sides,
attempting to minimize the number of edges between two nodes of
the same color. Edges between nodes of different colors represent
vias that can be eliminated. This procedure is equivalent to
trying to find the maximal bipartite subgraph of the modeling
graph. Routing Information is obtained from the design file
and 1s updated when via elimination 1s complete.
99
• -
I 1 I Hill II 111 UI..III.»! I.III,.W.I. I,»l. ,111 ., II.LIIIII nil ,1 .Ul.ll.lll um.|i».l^.i
8.2 Running VIAELIM
8.2.1 Exec file
An exec file is provided to help you run the via elimination
program. To use it, type:
exe fro #runvelim use pcb gro eg clr
After an introduction, the exec file will prompt you for infor-
mation needed to run the job. Typing a '?' to any of the major
prompts will print a message reminding you how to answer. The
prompts are: 1. <CR>=CLR ACT or SAV filename?
Typing a carriage return will clear the active file.
If there is something there you want to keep, type a
save command to put it into a file.
2. FILE ACCOUNT = CG.PCB
Type the account under which the design file is stored.
The format is (group.user). Type a carriage return if
under the default account.
3. DIRECT ACCESS FILE = DFILE?
Type the design file name or <CR> for default filename.
4. (FACC).(DAFNAME) ON VOLUME = SCFEV9?
Type the name of the volume on which the previously
specified design file is to be found (<CR> for default).
5. MODIFY CONSTANTS (<CR>=N0)?
If you wish to run the standard version of VIAELIM, type
a carriage return. Otherwise, you may change certain
constants (primarily array sizes) for this particular
run. Increasing allowed execution time or the size of
certain arrays may be necessary for very large or complex
circuits, perhaps in response to an error on a previous
run. If you type 'yes' to this prompt, you will be
prompted for values for each of the constants listed
below.
100
' • m i • i i. i. . i I-»I.IIHI—i ••! n i.ni i.
If the default value given is sufficient, hit <CR>; otherwise
type a new value. Responding with a '?' is not valid for these
prompts.
a. TIME=(m,ss)? Minutes (W) and seconds ('ss') of execution time allowed.
New value, if desired, should be typed using the same format
or you may type a single digit to specify minutes only. The
larger this value is, the lower your job's priority will be.
b. NETTL=value?
Should be greater than the number of signal nets in the
circuit.
c. SEGTL=value? Should be somewhat greater than the number of segments routed
in WIRE and HIWIRE.
d. VIATL-value? Should be greater than the number of vias produced in MWIRE
and HIWIRE. e. STKLN=value?
Should be greater than L0G2(2*SEGTL), i.e. if you double SEGTL,
add 2 to STKLEN.
f. GROTL=value? Maximum number of sets of mutually intersecting segments. This
varies greatly from one board to the next, and possibly between
two routings of the same circuit. The output of VIAELIM con-
tains a line 'NGR0=vaT where 'val' is actual number of groups
in that run (GROTL should be somewhat greater than this value).
g. CONNTL=value?
Two elements of the connection table (of which CONNTL is the
length) are used for each pair of groups having any segments
connecting at a common via. Also difficult to estimate; the
line ' LC0NN=vaT in VIAELIM's output gives the number of elements
actually used in that run.
101
••-••-
h. GOREGION=value?
Specifies memory requirements in multiples of 1024 bytes.
If you have substantially increased any of the table sizes,
particularly NETTL, SEGTL, or VIATL, it may be necessary
to increase this value.
6. After the exec file has set up the necessary JCL in your active
file, it will type:
TYPE 'EXE' TO RUN THE VIA ELIMINATION JOB.
+EXE PAU
If you now type 'exe', the exec file will submit your VIAELIM
job to the system to be run.
8.2.2 Output
Most of the activity in VIAELIM has to do with the design file.
A small amount of printed output, however, is generated. This
includes:
1. Information from the original design file, including the
user and project identifications and a count of the number of
segments and vias in the file.
2. Values for NGRO and LCONN mentioned above.
3. An indication of successful completion or an error message
(see below).
4. If completed successfully, a count of the number of segments
and vias in the updated design file. Note that the number of
segments may change due to the splitting of a segment into two
segments connected by a via if inserting that via eliminates
others elsewhere.
8.3 Error Messages
Classes of errors recognized by VIAELIM include:
A. Non-applicability
1. No placement in design file
2. No routing in design file.
3. No non-critical (and therefore movable) wires in design
file.
102
iinipwpK-iipmHiM i .inw^mmmmK~****!mimmmmmmmmmmi^**!< > wmm^^^^^mm*•*^*^^^
B. Input errors
1. Conflict between record chaining and stored count
for net realization (segment) records.
2. Chaining/count conflict in via records.
C. Table overflow for each of the table sizes that can be
set in the exec file.
D. Program error in the color optimization routine. If
this occurs, please save your output and the design file.
E. Design file overflow
Should never happen since fewer records should always be
needed after via elimination. Please save the output and
design file.
F. Via in design file with 0 or 1 segments attached. This is
a warning rather than a fatal error. The location of the
bad via and the net it is in are printed, the via deleted
and the program continues. This problem would generally
come from incorrect connection of multi-width wires in
MIWIRE. If you have not used any multi-width wires or
are puzzled by the message's appearance, please save the
output and design file.
103
—_—_
9. OUTPUT PLOT GENERATION
Two separate programs, PLOT and ARTWORK, are provided for
plotting a design produced with the SPRINT system.
9.1 PLOT
PLOT is a basic program for outputing a routed board on the
Versatec plotter. It produces a simplified plot consisting of
three pictures; one of each side of the board and a composite.
The drawingsare produced at 1:1 scale and the picture of the
solder side routing is a mirror image. A diagonal line is drawn
through an intersection that represents a connection, regardless of
whether or not a via exists at that point. While the plots pro-
duced by this program will probably not be acceptable as the
final output from a design, they may be useful at some inter-
mediate point.
To run this simplified plotting program, type:
exe fro #runplot use pcb gro eg clr
After an introduction you will receive the following prompts:
A) <cr>=CLR ACT or SAV filename
Type a <CR> to clear the active file for use as
a work area. Otherwise type a SAVE command to
store the active file under some filename.
B) FILE ACCOUNT • gg.uuu?
Give the account the design file is stored under.
The default, chosen by hitting <CR>, is the logged
104
on user's account. Format is gg.uuu (group.user).
C) DIRECT ACCESS FILE=DFILE?
Give the name of the file containing the design you
want to plot.
D) gg.uuu.filename ON V0LUME=SCFEV9?
The volume the specified design file is on. The
default is the scratch disk 'SCFEV9'.
E) STANDARD ORIENTATION (<CR>=yes)?
Because this program always produces a 1:1 plot
rather than scaling the picture to fit the page,
a board may be defined which would not fit on the
paper in the normal orientation (x-axis horizontal)
but would fit if rotated 90°. To get this rotated
plot, type 'no'; otherwise type a <CR>.
F) TYPE 'EXE' TO RUN THE PLOTTING JOB
The appropriate JCL nas n"w been collected in the
active file. Type 'exe' to run it.
When the program is done, its output will be in the print hold
queue. If the plot was successful, there should be a data set
labeled 'GO.UGDEVICE' containing several hundred lines. Release
this data set to obtain the plot.
The only error message produced by PLOT concerns not being
able to fit the drawing on the paper. If switching to the
opposite orientation does not eliminate the problem, PLOT cannot
be used for that board.
105
••—
9.2 ARTWORK
ARTWORK produces a more comprehensive set of drawings of a
design. The output can currently be sent to any of three devices:
A) Tektronix 4013 terminal - This option gives you a
quick look at the design on the terminal's storage
tube screen.
B) Versatec plotter - A reasonably fast way to get
hard-copy drawings of the design, generally as an
aid in making modifications during the design process.
C) Calcomp plotter (33" paper) - High-quality, 3-color
plots at 2:1 scale from which the final taping of the
board can be done.
9.2.1 Output
A set of nine pictures is produced by ARTWORK. These
Include:
A) Header and trailer pictures indicating the name and
status of the design.
B) A top view of the board showing component place-
ment.
C) A bottom view 'airline route' plot of the signal
net chaining. This point-to-point representation
of the nets can give a clear indication of how good
the placement is and show which components should be
moved closer together to improve an unsatisfactory
106
- — • ••- -
placement.
D) A bottom view composite drawing of the routing
on both sides of the board. On the Calcomp
plotter, routing from each side can be plotted
in a different color.
E) A bottom view of the component side routing
(as it would be seen looking through the board).
F) A bottom view of the foil side routing.
G) A top view of the component side routing.
H) A bottom view of the pin and via holes (pin
holes are also drawn in pictures C through G,
as square boxes, via holes are shown as X's
in pictures D through G).
All pictures are labeled and are scaled as close to 2:1
as possible in the available space. The scale used is printed
on the header and trailer sheets.
9.2.2 Running ARTWORK
To obtain ARTWORK plots on any of the devices, type:
exe fro #runart use pcb gro eg clr
After a short introduction, you will be given the
following prompts:
A) <cr>=CLR ACT or SAV filename
Type a <cr> to clear the active file. If you
want it saved under some filename, type a SAV
command.
107
-• —- - -• - -- •" "'••"- '-
-—• ••••'• • — '-—
B) DIRECT ACCESS FILE=DFILE?
Type the name of the design file you want to
produce art work for.
C) FILE filename ON V0L=SCFEV9?
Give the volume the specified design file is on.
D) GROUP.USER=gg.uuu?
Give the account the design file is stored under.
The default is the logged on user's account.
E) Output device=VERSATEC?
This is where the program becomes specialized
for a particular output device. Type a <CR>
for the default device (the Versatec plotter in
this case), 'ver' for the Versatec plotter, 'tek'
for the Tektronix 4013 terminal, or 'cal' for the
Calcomp plotter (33" paper).
F) TYPE 'EXE' TO RUN THE ARTWORK JOB
The specialized JCL has been assembled in your
active file and will be run if you type 'exe'.
The job's name will be of the form 'uuudddnn',
where uuu is the user's name, ddd is the output
device's name (e.g. 'TEK'), and nn is the last
two digits of the current job number.
9.2.3 Getting the output
The extra steps necessary to obtain the output depend
on the device used:
A) Tektronix 4013 - This job runs as an interactive
108
•"•""^•^—"—M—rt^- -- II I • • - • ...-.-...
Subsystem, much the same as PLACER and MWIRE. When
the program is ready, it will send the message to
the terminal:
FROM OPERATOR: (uuudddnn) THE PLOTTER IS READY
where 'uuudddnn' is the job name described above.
To connect the program to your terminal, type the
jobname. To "WHAT'S THE MAGIC WORD?" type, "punt".
Each picture will be drawn on the screen (there may
be some delay, particularly when the machine is heavily
loaded), then the crosshairs will appear. When you
want to generate the next picture, just hit the space
bar. After the last picture, the screen is cleared
and you are returned to Wylbur. Any printed output
from the program can be purged.
NOTE: Due to limitations on the amount of
memory available to CLASS I (interactive)
jobs, some of the routing segments may not
be output on large complex boards, parti-
cularly if VIAELIM has not been run. This
is not a problem with the Versatec or Calcomp
plots.
B) Versatec plotter - If the program completes
successfully, the output in the print hold queue
should include a data set labeled "GO.UGDEVICE"
containing several hundred lines of output.
109
nm^li^iiJMn • -• •- • " -•-- „.,.,.... i <i. i.i i i .1 i
Releasing that data set will send the output to
the plotter. The remaining printed output can
be purged when the plotting is completed.
C) Calcomp plotter - The program should produce
a plot tape which will be placed in your bin.
You must then fill out a plot request card
(available at the dispatch desk), attach it
to the tape, and place the tape in the "TO
CAMPUS' bin. A sample card, marked for the re-
commended configuration, is shown in Fig. 9.1.
Some things to note:
1) 'CAMPUS ACCT' refers to an account
valid for plotting at SCIP on campus,
not a SLAC account. See your group
secretary for an account to use or
make arrangements with SCIP accounting.
2) Fill in 'REEL NUMBER' from the tape
you receive.
3) The program scales everything for
plotting on 33" paper. This will
handle 2:1 plots of boards up to 16.5"
long by 13.75" wide. For 2:1 plots of
boards up to 5" long by 4.3125" wide or
less than 2:1 plots of larger boards on
10" paper, type:
110
• - - -' • ' • "*• ••••'• - •--""
SCIP AT SLflC 1130 D*UH PLOTTER REQUEST
NAME #.* S±&d&U BINZ3?
JpBNAMF>^50f^iDRTE &/'/77 CAMPUS REEL ^-—u* flCCT &GJWU NUMBER PLOTtf* CIRCLE THE Net Of 0 rTKRi SEI.CH • BTPPSEP ITfUS Q»E PCFBUtT
PAPER SIZE a »IQINCHCTIINCTT
PEN« 1 «PB £*BLK)
PAPER
•»BLAM STYLE
L03
COP RED
BLU
GRAPH 10 DIV/IN
LOS L08
LOT " • \
PEN« 2 PEN » 3 PB BLK PB BLK
L03 RED L03 < ̂ RED^)
BLU
LOS LOS L06 L06
-MU- LOT B5üPEVIflT10NS ur.ZJ. "B-F-KECSuRHtO ßntLPüINT
NN=LICU1C IN.<. NN 15 THt .?H"'C3C-»nrt' ?fN»
Figure 9.1
111
•
~ . M
exe fro #artcl0 use pcb gro eg clr
Everything in this exec file is identical
to #RUNART except the Calcomp plots are
scaled for 10" paper.
4) The ' L04' liquid ink pens should produce
good plots. Larger pens may be used to
produce greater line width, but 'L03' pens
should never be used as they tend to dry
out in the middle of complex pictures.
5) The color choice shown is recommended,
but may be changed to fit personal re-
quirements. Pen assignments are:
-Pen #1- used for lettering, board outline,
component outlines, component side routing.
-Pen #2- used for 'airline route' picture
and foil side routing.
-Pen #3- used for pin and via holes.
The plot should be completed within a day or sc and will
be returned, along with the tape to the 'FROM CAMPUS'
bin. If the plot is satisfactory, you may send the
tape back for another plot or return it to SLAC Dis-
patch.
9.2.4 Errors
Other than attempting to plot a non-existent or garbage
112
I —I« I I ••»••••»
^
design file, there are no expected errors in ARTWORK. If
the program should fail, please release and save the printed
output and save a compressed version of the design file for
later analysis.
The following pages contain the plots generated on the
Versatec plotter for the example of Fig. 0.1.
113
• -- -••--• - -""••• - — '
a LU h- a LU LU
N _l h- IX CL UJ X z: _l (X s CL OQ u z: XUJ s
LU CDh- CD urn CO COM OLU ^ _J LÜLIJ>-H _J i—i z< CLCLCO CL a f— (SO
C0>- X COXZLUZ) •—«CO h- \— \— Q DSh (SI h- z: M h- CJ CL CL <«-H
UJ_J _JCL < < ~ZL Z<<CD 1- h- f— CJ H-H (S)
-5 1 COiSCJCJ C/1ZÜ0 1—1 Xh~ UJ (/)ZQ_MH^ LU I— M _J h- ^EGOOO ZZÜ < -JO CL UJ CL (S) S >- O CJDLÜ Z x UJ o
CJH Z UJI LD i—i (__) i—i is o > < rs CL o CO < CL f— < o 51 X OCM COC\J UJ _J M O 1 1 a
13: LU CO CM <-H H LI) O oa_ DK < > CM
114
CL C9
Lü; X:LU ÜJZ CJLU <u _J< Ü I
CL
LU LUh- ZUJ <S)_J CLCL
uu
1
5 CM
5 i— \—1 <—
C02
C03
'
o CD
1 ' \
& 5 5 g o c
CD • 1 I
U
o
L. )
115
.. <L
G)
CD
CO UJ _J
_J
en o
a z <
CO <
a • a a a D
• a • a D a
D • DO a a
a a DO a a
D D O D a a
0 • • o a D
a a • x • a a
• • DU • D
• • a • a a
a xa a a a • a a a a a D
D a a a • a
• ax • a X X
a a
• • • X •
X X
a
X X X
a
D D x a a X
D a
D a a x n X X
x • a
• a xa XD X
ax X
a
• a a x a a cix
X X D DX
n
• a a a x X
a x X
a
a XD x nx a X
n X
n
a a x ax x a x
X a o
X X X X
X X
x a a
X X
D
• • n M n u n I] [i u [i i i u (i a a a a 11 11 r
116
,..,, ,—. .
CD
01
UJ Q
in
z LU
u
' 1
1 -
1 . 1 1— 1
1
— '— - 1
-".... 1 1 1
1
1.
1
L
117
(S
CD
CD
ID IS cr
LU CD
if)
_J M
(S
o D
a a D
a D
D
a D
a D
o
D
a • D
•
D
• B-
• D
D
a
D
G
D
a
a
o 0-
o *B-
a D n
B-i
a
C)
n XG
D
•
ax
1
• a a D
n a
a D
13-
a a
a
a •
* : l IX
"I"
a • B—1 0
a D
a
a a • a o a a
D-
S-
n n a n a
n n it n n
118
^^g^gg
IS
(3
LiJ O ^ i
CO
^1
UJ
ü ;>
U
• D
G
a D
a a
I
a ü
D
D
a •
D
a -KO
a
Q>
•
(J
a a
-o a
a D a rj
l£ Q
X
a D
• • o Ü
a
a a a a
a -a • D
• a a
a a a D
n • D
Ü
Q
D
D
D
a a
J
__= —i aaaoaaaaaaaaaoaaaaaa
119
ca
m
CO
Z) (S en
UJ 1 r—
CO IS
CJ
120
•Hi ., , ....... • •»••K» • •
GO
(D
<
U
L±J
121
1
TO. UTILITIES
This chapter describes some utility programs which, while
not a necessary part of the design process, may be of some use.
10.1 DUMP and RESTORE
DUMP and RESTORE are a pair of programs providing the
capability to compress a direct access design file into a se-
quential Wylbur edit format file and vice versa. There are
two reasons one might wish to do this. First, a direct access
file cannot be copied directly. If the designer wishes to try
several alternate designs for a given board, he can easily pro-
duce several identical copies of the design file by dumping it
once, then restoring it under several different names. The
second, and probably more prevalent use of DUMP and RESTORE in-
volves efficient use of disk space. A design file will generally
be over 100 tracks long and be stored on a scratch disk while in
use. It is a fixed size no matter what the size of the circuit.
Length of the compressed file is proportional to the size of the
circuit and compression factors between 5 and 10 can be obtained.
This makes the file small enough to be saved on a tape or perma-
nent disk, a necessary step if the design is not completed in
one day, and something which is probably desirable in any case.
Also, if there are problems with any of the SPRINT system pro-
grams, a dumped file containing the design is needed to discover
the cause of the problem.
122
Both DUMP and RESTORE make use of a temporary file called
'TEMPPY' on volume SCFEV9. The user should not have a file by
this name for any other purpose.
DUMP prints each record of the design file exactly as it
was read. This output can be released to the printer if desired.
10.2 PRINT
PRINT produces a formatted printout of the design file.
In other words, it knows the significance of the fields in the
various records and can produce an easily readable account of
the components, nets, segments, vias, etc., defined in a parti-
cular file. This kind of documentation may prove to be a use-
ful supplement to the drawings produced by ARTWORK.
10.3 Running DUMP and PRINT
Due to the common nature of their functions, the exec
files for DUMP and PRINT are almost identical. To run DUMP,
type:
exe fro #rundump use pcb gro eg clr
For PRINT, type:
exe fro #runprint use pcb gro eg clr
After an introduction, each exec file will prompt for the
following information:
A) <cr>=CLR ACT or SAV filename?
Type a SAVE command to save the active file under
some filename or hit a <cr> to clear the active
file immediately for use as a scratch area.
123
""—
B) DIRECT ACCESS FILE=DFILE?
Type the name of the file you want dumped or
printed.
C) FILE filename ON V0L=SCFEV9?
Give the volume the specified file is on.
D) GROUP.USER=gg.uuu?
Give the account the design file is saved under.
The default is the logged on user's account.
Note that even if you are dumping a file under
a different account, the compressed file will be
saved in 'TEMPPY' on SCFEV9 under the logged
on user's account.
The DUMP or PRINT job is now in the active file. Type
'exe' to run it. The output will be held in the print hold
queue when the job is completed. You can fetch it from your
terminal or release it to the printer.
10.4 Running RESTORE
To run the exec file for running RESTORE, type:
exe fro #runrest use pcb gro eg clr
Here the prompts are:
A) <cr>=CLR ACT or SAV filename?
Same as DUMP
B) Source file for restore (<cr>=ACTIVE)?
Here you have three alternatives:
124
1) Typing a <cr> will save the active
file in 'TEMPPY' to be restored.
2) Typing a Wylbur filename will cause
that file to be loaded then saved in
'TEMPPY'.
3) Typing an '?' followed by an Orvyl
filename will cause Orvyl to be set
and that file to be loaded and stored
in 'TEMPPY'.
No facilities are available for direct loading
from tapes.
C) DIRECT ACCESS FILE=DFILE?
Same as DUMP
D) FILE filename ON V0L=SCFEV9?
Same as DUMP
E) GROUP.USER=gg.uuu?
Same as DUMP
F) These files are on volume volname (gg.uuu).
The files on the given volume under the given
account are listed. This allows the user to
check for a duplicate design file name. RESTORE
will abend if a duplicate filename exists.
The JCL for RESTORE is now in the active file and is run by
typing 'exe'. The printed output from RESTORE is only useful if
the job fails due to an invalid filename or other operating system
125
r
problem (RESTORE generates no error messages), and should be
purged.
126
— -
11. Future Enhancements
The following programs are in the design/implementation phase:
1) Macro expansion of the SDL output
2) Component Assignment
3) Wire wrap output
The following programs are in the planning phase:
1) Graphic input for the SDL compiler in the form of logic
diagrams, drawn on a Tektronix 4013
2) Interactive editing of the completed board
3) Constructive initial placement of components
4) Gate and pin assignment (after the placement, before the
routing)
5) Multilayer capability (4 signal layers initially)
6) Interface to TESTAID and TEGAS logic simulators
7) Interface to SPICE and MSINC circuit analysis programs
8) Automatic logic diagram generation subsystem
127
••""
SECURITY CLASSIFICATION OF THIS PAGE (When Data Entered)
REPORT DOCUMENTATION PAGE READ INSTRUCTIONS BEFORE COMPLETING FORM
1 REPORT NUMBER
Technical Report No. 143
2 GOVT ACCESSION NO. 3 RECIPIENTS CATALOG NUMBER
4. TITLE (and Summe) 5. TYPE OF REPORT & PERIOO COVERED
SPRINT - An Interactive System for Printed
Circuit Board Design User's Guide Technical Report
6 PERFORMING ORG REPORT NUMBER
7 AUTHORd) W.M. vanCleemput T. C. Bennett J. A. Hupp K. R. Stevens
B CONTRACT OR GRANT NUMBERIsl
N00014-75-0601
9 PERFORMING ORGANIZATION NAME AND ADDRESS
Stanford Electronics Laboratories Stanford University Stanford, CA 94305
10 PROGRAM ELEMENT. PROJECT TASK AREA & WORK UNIT NUMBERS
11 CONTROLLING OFFICE NAME AND ADDRESS
Office of Naval Research Department of the Navy Washington, DC 22217
12 REPORT DATE
June 1977 / 13 NO OF PAGES
15 SECURITY CLASS, lof this report)
14 MONITORING AGENCY NAME & ADDRESS (it diff from Controlling Office)
15a. DECLASSIFICATION/DOWNGRADING SCHEDULE
16 DISTRIBUTION STATEMENT (o« this report)
Reproduction in whole or part is permitted for any purpose of the United States government.
17 DISTRIBUTION STATEMENT (of the abstract entered in Block 20. if different from report) DunibUTlOIl UlÜluilltsU
DISTRIBUTION STATEMENT Ä Appioved foi public releat«;
18 SUPPLEMENTARY NOTES
19 KEY WORDS (Continue on reverse side if necessary and identify by block number)
printed circuit board design, computer-aided design, design automation
70 ABSTRACT (Continue on rev«rs« «id« if nacaiury and identify by block number)
The SPRINT system for the design of printed circuit boards is a collection of programs that allows designers to interactively design two-sided boards using a Tektronix 4013 graphics terminal. The major parts of the system are: a compiler for SDL, the Structural Design Language, an interactive component placement program, an interactive manual conductor routing program, an auto- matic batch router, a via elimination program and a set of artwork generation programs.
DD,r,r",3.473 FORM 1 JAN 73
EDITION OF 1 NOV 65 IS OBSOLETE SECURITY CLASSIFICATION OF THIS PAGE IWhi-ri Data liilnsili
• -•
JSEP REPORTS DISTRIBUTION LIST
No. of Copies
No. of Copies
Department of Defense
Defense Documentation Center Attn: DDC-TCA (Mrs. V.Caponio) Cameron Station Alexandria, Virginia 22314
Asst. Dir., Electronics and Computer Sciences Office of Director of Defense Research and Engineering The Pentagon Washington, D.C. 20315
Office of Director of Defense Research and Engineering Information Office Lib. Branch The Pentagon Washington, D.C. 20301
ODDR&E Advisory Group on Electron Devices 201 Varick Street New York, New York 10014
Chief, R&D Division (340) Defense Donununlcations Agency Washington, D.C. 20301
Director, Nat. Security Agency Fort George G. Meade Maryland 20755 Attn: Dr. T.J.Beahn
Institute for Defense Analysis Science and Technology Division 400 Army-Navy Drive Arlington, Virginia 22202
Dr. Stickley Defense Advanced Research Projects Agency Attn: Technical Library 1400 Wilson Boulevard Arlington, Virginia 22209
Dr. R. Reynolds Defense Advanced Research
12 Projects Agency Attn: Technical Library 1400 Wilson Boulevard Arlington, Virginia 22209
1 Department of the Air Force
AF/RDPS The Pentagon Washington, D.C. 20330
1 AFSC (LJ/ Mr. Irving R. Mirman) Andrews Air Force Base Washington, D.C. 20334
Directorate of Electronics and Weapons
1 HQ AFSC/DLC Andrews AFB, Maryland 20334
Directorate of Science HQ AFSC/DLS
1 Andrews Air Force Base Washington, D.C. 20334
LTC J. W. Gregory 1 /»F Member, TAC
Air Force Office of Scientific Research Boiling Air Force Base Washington, D.C. 20332
1 Mr. Carl Sletten RADC/ETE Hanscom AFB, Maryland 01731
1 Dr. Richard Picard RADC/ETSL Hanscom AFB, Maryland 01731
Mr. Robert Barrett RADC/ETS Hanscom AFB, Maryland 01731
JSEP 3/77
I.IJl, I I IJ..I. MIIIIU I. HL.I •• -. .P •_•-•»
No. of Copies
No. of Copies
Dr. John N. Howard AFGL/CA Hanscom AFB, Maryland 01731
Dr. Richard B. Mack RADC/ETER Hanscom AFB, Maryland 01731
Documents Library (TILD) Rome Air Development Center Griffiss AFB, New York 13441
Mr. H.E.Webb, Jr. (1SCP) Rome Air Development center Griffiss AFB, New York 13441
Mr. Murray Kesselman (ISCA) Rome Air Development Center Griffiss AFB, New York 13441
Mr. W. Edwards AFAL/TE Wright-Patterson AFB Ohio 45433
Mr. R.D.Larson AFAL/DHR Wright-Patterson AFB Ohio 45433
Howard H.Steenbergen AFAL/DHE Wright-Patterson AFB Ohio 45433
Chief Scientist AFAL/CA Wright-Patterson AFB Ohio 45433
HQ ESD (DRI/Stop22) Hanscom AFB, Maryland 01731
Professor R.E. Fontana Head, Dept. of Electrical Engr. AFIT/ENE Wright-Patteraon AFB Ohio 45433
Mr. John Mott-Smith HQ ESD (AFSC) MCIT - Stop 36 Hanscom AFB, MA. 01731
LTC Richard J.Gowen Professor Dept. of Electrical Engineering USAF Academy, Colorado 80840
AUL/LSE-9663 Maxwell AFB, Alabama 36112
AFETR Technical Library P.O. Box 4608, MU 5650 Patrick AFB, Florida 32542
ADTC (DLOSL) Eglin AFB, Florida 32542
HQ AMD (RDR/Col. Godden) Brooks AFB, Texas 78235
USAF European Office of Aerospace Research Technical Information Office Box 14, FPO, New York 09510
Dr. Carl E. Baum AFWL (ES) Kirtland AFB, New Mexico 87117
ASAFSAM/RAL Brooks AFB, Texas
Department of the Army
HQDA (DAMA0ARZ-A) Washington, D.C. 20310
Commander U.S. Army Security Agency Attn: IARD-T Arlington Hall Station Arlington, Virginia 22212
JSEP 3/77
—•
No. of Copies
No. of Copies
Commander U.S. Army Materiel Dev. & Readiness Command Attn: Tech. Library Rm 7S 35 5001 Eisenhower Ave. Alexandria, Virginia 22333
Commamder Harry Diamond Laboratories ATTN: Mr. John E. Rosenberg 2800 Posder Mill Road Adelphi, Maryland 20783
Commander Research Laboratory ATTN. DRXRD-BAD U.S. Army Ballistics Aberdeen Proving Ground Aberdeen, Maryland 21005
Commander Picatinny Arsenal Dover, New Jersey 07081
ATTN: SMUPA-TS-T-S
ATTN: Dr. Herman Robl U.S. Army Research Office P.O. Box 12211 Research Triangle Park North Carolina 27709
ATTN: MR. Richard 0. Ulsh U.S. Army Research Office P.O. Box 12211 Research Triangle Park North Carolina 27709
Mr. George C.White, Jr. Deputy Director Pitman-Dunn Laboratory Frankford Arsenal Philadelphia, Penna. 19137
Commander Attn: Chief, Document Section U.S. Army Missile Command Redstone Arsenal, Alabama 35809
Commander U.S. Army Missile Command Attn: DRSMI-RR Redstone Arsenal, Alabama 35809
Commander Chief, Materials Sciences Division, Bldg. 292 Army Materials and Mechanics Research Center Watertown, Massachusetts 02172
Commandant U.S. Army Air Defense School 1 Attn: ATSAD-T-CSM Fort Bliss, Texas 79916
Commandant 1 U. S. Army Command and General Staff College Attn: Acquisition, Library Div Fort Leavenworth, Kansas 66027
Dr. Hans K.Ziegler (AMSEL-TL-D) 1 Army Member, TAC/JSEP U.S. Army Electronics Command (DRSEL-TL-D) Fort Monmouth, New Jersey 07703
Mr. J.E. Teti (AMSEL-TL-DT) 3 Executive Secretary, TAC/JSEP U.S. Army Electronics Command (DRSEL-TL-DT) Fort Monmouth, New Jersey 07703
Director 1 Night Vision Laboratory, ECOM ATTN: DRSEL-NV-D Fort Belvoir, Virginia 22060
Commander/Director 1 Atmospheric Sciences Laboratory (ECOM) Attn: DRSEL-BL/DD White Sansa Missile Range New Mexico 88002
Director Electronic Warfare Lab., ECOM Attn: DRSEL-WL-MY White Sands Missile Range New Mexico 88002
Commander US Army Armament Command Attn: DRSAR-RD Rock Island, Illinois 61201
JSEP 3/77
- MMWMM
Project Manager Ballistic Missile Defense Program Office Attn: DACS-BMP ( Mr. A. Gold) 1300 Wilson Blvd. Washington, D.C. 22209
Director, Division of Neuropsychiatry Walter Reed Army Institute 1 of Research Washington, D.C. 20012
Commander, USASATCOM 1 Kort Monmouth, New Jersey 07703
Commander, U. S. Army 1 Communications Command Attn: Director, Advanced Concepts Office Fort Huachuca, Arizona 85613
Project Manager, ARTADS 1 EAI Building West Long Branch, N. J. 07764
U.S. Army White Sands Missile Range STEWS-ID-R 1 Attn: Commander White Sands Missle Range New Mexico 88002
Mr. William T. Kawai U.S. Army R&D Group (Far East) 1 APO, San Francisco, Ca. 96343
Director, TRI-TAC 1 Attn: TT-AD (Mrs. Briller) Fort Monmouth, N. J. 07703
No. of No. of Copies Copies
1 NL-H Dr. F. Schwering TL-E Dr. S. Kronenberg TL-E Dr. J. Kohn TL-I Dr. C. Thornton NL-B Dr. S. Amorsos
Commander U.S. Army Electronics Command
1
Fort Monmouth, N.J. 07703 Attn: AMSEL-RD-O (Dr. W. S. McAfee) 1
CT-L (Dr. G. Buser) 1 NL-0 NL-T
(Dr. H.S. Bennett) (Mr. R.Kulinyi)
1 1
TL-B 1 VI.-D 1 WL-D 1 TL-MM (Mr. Li pet 7.)
(cont'd) 1
Col. Robt. W. Noce Senior Standardization Rep. U.S. Army Standardization Group, Canada Canadian Force Headquarters Ottawa, Ontario, Canada KIA 0K2
Commander CCOPS-PD Fort Huachuca, Arizona 85613 Attn: H.A. Lasitter
Department of the Navy
Dr. Sam Koslov ASN (R&D) Room 4E741 The Pentagon Washington, D.C. 20350
Office of Naval Research 800 N. Puincy Street Arlington, Virginia 22217 Attn: Codes 100
102 201 220 221 401 420 421 427 (All Hands) 432 437
Naval Research Laboratory 4555 Overlook Aven. SW Washington, D.C. 20375 Attn:
•4-
Codes 1000 - Dr. A Berman 4105 - Dr. S. Teitler 4207 - Dr. J. McCaffrey 5000 - Dr. H. North 5200 - Mr. A. Brodzinsk> 5203 - Dr. L. Young
5210 " Dr- J. Davey
JSEP 3/77
No. of Copies
Naval Research Laboratory 1 4555 Overlook Ave. SW Washington, D.C. 20375 Attn: Codes 5220 - Mr. H. Lessoff
5230 - Dr. R. Green 5250 - Cf. L. Whicker 5260 - Dr. D. Barbe 5270 - Dr. B. McCombe 5300 - Dr. M. Skolnik 5403 - Dr. J. Shore 5464/5410 - Dr. J. Davis 5500 - Dr. T. Jacobs 5509 - Dr. T. Giallorenzi 5510 - Dr. W. Faust 6400 - Dr. C. Klick
No. of Copies
7701 Mr. J. Brown
Director 1 Office of Naval Research 495 Summer Street Boston, Mass. 02210
Director 1 Office of Naval Research New York Area Office 715 Broadway 5th Floor New York, New York 10003
Director of Naval Research Branch Office 536 South Clark Street Chicago, Illinois 60605 1
R.N. Keeler 1 NAVMAT - Code 03T CP # 5 2211 Jefferson Davis Hwy. Arlington, Virginia 20360
Mel Nunn 1 NVMAT 0343 CP# 5, Room 1044 2211 Jefferson Davis Hwy. Arlington, Virginia 20360
Dr. F. I. Tanczos 1 NAVAIR-03B JP# 1, Room 412 1411 Jefferson Davis Hwy Arlington, Virginia 20360
Dr. H.J. Mueller 1 Naval Air Systems Command Code 310 JP # 1 1411 Jefferson Davis Hwy. Arlington, Virginia 20360
Mr. N. Butler 1 Naval Electronics Systems Command Code 304 NC # 1 2511 Jefferson Davis Hwy. Arlington, Virginia 20360
Director of Naval Research Branch Office 1030 East Green Street 1 Pasadena, Calif. 91101
Office of Naval Research 1 San Francisco Area Office 760 Market St. Room 447 San Francisco, Calif. 94102
Harris B. Stone 1 Office of Research, Development, Test k Evaluation N0P-987 The Pentagon. Boom 5D760 Washington, D.C. 20350
Dr. A.L.Slafkosky 1 Code RD-1 Headquarters Marine Corps Washington, D.C. 20380
Mr. L. W. Sumney 1 Naval Electronics Systems Command NC # 1 2511 Jefferson Davis Hwy. Arlington, Virginia 20360
J.H. Huth 1 NAVSEA - Code 03C NC # 3, Room 11E08 2531 Jefferson Davis Hwy. Arlington, Virginia 20362
Capt. R.B. Meeks 1 Naval Sea Systems Command NC #3 2531 Jefferson Davis Hwy. Arlington, Virginia 20362
JSFP 3 77
... i i
No. of Copies
No. of Copies
Naval Surface Weapons Center White Oak Silver Spring, Maryland 20910 Attn: Codes WR - 04 -
WR - 30 - WR - 303 WR - 34 - WR - 43 -
W. Scanlon Dr. J. Dixon
- Dr. R. Allgaier H.R. Riedl P. Wessel
Naval Surface Weapons Center Dahlgren, Virginia 22448 Attn: Codes DF - J. Mills
DF - 14 - K. Ferris DF - 36 - S. Leong
Naval Air Development Center Johnsville Warminister, Penna 18974 Attn: Codes 01 - Dr. R. Lobb
202 - T. Shoppie 20212 - S. Campagna 2022 - G. Fer
Dr. Gernot M.R. Winkler Director, Time Service U.S. Naval Observatory Mass. Ave. at 34th St., N.W. Washington, D.C. 20390
Officer in Charge Carderock Laboratory David Taylor Naval Ship Research and Development Center Bethesda, Maryland 20034
Officer in Charge Annapolis Laboratory Naval Ship Research & Development Center Annapolis, Maryland 21402
Dr. G. Gould, Technical Director Naval Coastal Systems Laboratory Panama City, Florida 32401
M. J. Wynn Code 790 Naval Coastal Systems Laboratory Panama City, Florida 32401
Dr. W. A. VonWinkle 1 Associate Technical Director for Technology Naval Underwater Systems Center New London, Connecticut 06320
Officer in Charge 1 Naval Underwater Systems Center Newport, Rhode Island 02840
Dr. H. L. Blood 1 Technical Director Naval Undersea Center San Diego, Calif. 95152
Dr. Robert R. Fossum 1 Dean of Research Naval Postgraduate School Monterey, Calif. 93940
Naval Electronics Laboratory Center 271 Catalina Blvd. 1 San Diego, Calif. 92152 Attn: Codes 0220 - H.T. Mortimer
2000 - P.C. Fletcher 2020 - V. E. Hildebrand 2100 - C.A. Nelson 2200 - J. Ritcher 2300 - C.W. Erickson 2400 - F.M. Trip*k 2500 - W. E. Richards 3000 3400 - R. Coburn 4000 - C.E. pi<;rson 4600 - I. Lagnado 5000 - A.E. Beutel 5200 - R.R. Eyres 5300 - P. H. Johnson 5600 - W. J. Dejka
Naval Weapons Center China Lake, Calif. 93555 Attn: Codes 60 - Royce
601 - F.C.Essig 6013 - V.L. Rehn 6014 - D.J.White 6018 - J.M Bennett 6019 - N. Bottka
(cont'd)
JSEP 3/77
1
No of Copies
Naval Weapons Center China Lake, Calif. 93555 Attn: Codes 605 - • w.s. McEwan 1
5515 - M.H. Ritchie 3945 - D.G. McCauley 5525 - Webster
35 - D. J. Russell 55 - B.W. Hayes
3544 - H. W. Swinford 3815 - R.S. Hughes
D.E. Kirk 1 Professor & Chairman, Electronic Engineering Sp-304 Naval Postgraduate School Monterey, Calif. 93940
Professor Sydney P. Parker 1 Electrical Engineering Sp-62 Naval Postgraduate School Monterey, Calif. 93940
Dr. Roy F. Potter 1 3868 Talbot Street San Diego, Calif. 92106
Mr. J.C. French 1 Electronics Technology Division National Bureau of Standards Washington, D.C. 20234
John L. Allen 1 Deputy Director (Research & Advanced Technology) ODDR&E The Pentagon, Room 3E114 Washington, D.C. 20301
Leonard R. Weisberg 1 Assistant Director (Electronics & Physical Sciences) ODDR&E The Pentagon Washington, D.C. 20301
George Gamota 1 Staff Specialist for Research ODDR&E
The Pentagon, Room 3D1079 Washington, D.C. 20301
No. of Copies
Robert E. Frischell 1 Johns Hopkins University Applied Physics Laboratory Laurel, Maryland 20810
Mr. G.H. Gleissmer 1 Code 18 David Taylor Naval Ship R&D Center Bethesda, Maryland 20084
Commander 1 Pacific Missile Test Center Code 4253-3 Point Mugu, Calif. 93042
Richard Holden 1 DF - 34 Naval Surface Weapons Center Dahlgren Laboratory Dahlgren, Virginia 22448
Other Government Agencies
Mr. F.C. Schwenk, RD-T 1 National Aeronautics and Space Administration Washington, D.C. 20546
Los Alamos Scientific Lab 1 Attn: Reports Library P.O. Box 1663 Los Alamos, New Mexico 87544
M. Zane Thornton 1 Deputy Director, Institute for Computer Sciences & Technology National Bureau of Standards Washington, D.C. 20550
Director, Office of Postal 1 Technology (R&D) U.S. Postal Service 11711 Parklawn Drive Rockville, Maryland 20852
NASA Lewis Research Center 1 Attn: Library 21000 Brookpark Road Cleveland, Ohio 44135
•7- JSEP 3/77
No. of Copies
Library - R51 1 Bureau of Standards Acquisit ion Boulder, Colorado 80302
MIT Lincoln Laboratory 1 Attn: Library A-082 P.O. Box 73 Lexington, Mass. 02173
Dr. Jay Harris 1 Program Director, Devices and Waves Program National Science Foundation 1800 G. Street Washington, D.C. 20550
Dr. Howard W. Etzel, Deputy Director Division of Materials Research 1 National Science Foundation 1800 G. Street Washington, D.C. 20550
Dr. Dean Mitchell, Program Director Solid-State Physics 1 Div. of Materials Research National Science
Non-Government Agencies
Director 1 Research Lab. of Electronics Massachusetts Inst. of Tech. Cambridge, Mass. 02139
Director 1 Microwave Research Institute Polytechnic Inst. of New York Long Island Graduate Center Koute 110 Farmintfdale, New York 11735
Assistant Director Microwave Research Institute Polytechnic Inat. of New York 333 Jay Street Brooklyn, New York 11201
No. of Copies
Director Columbia Radiation Laboratory Department of Physics Columbia University 538 West 120th Street New York, New York 10027
Director Electronics Research Laboratory University of California Berkeley, Calif. 94720
Director Electronics Sciences Laboratory University of Southern California Los Angeles, California 90007
Director Electronics Research Center The University of Texas at Austin Engineering-Science Bldg. 112 Austin, Texas 87812
Director of Laboratories Division of Engineering and Applied Physics - Tech. Reports Collect ion Harvard University Pierce Hall Cambridge, Massachusetts 02138
•8-
JSEP 3 77
.