statement list (stl)

Preface, Contents

Product Overview 1Structure and Components ofInstructions and Statements 2

Adressing 3Accumulator Operations andAddress Register Instructions 4

Bit Logic Instructions 5

Timer Instructions 6

Counter Instructions 7

Load and Transfer Instructions 8

Integer Math Instructions 9

Floating-Point Math Instructions 10

Comparison Instructions 11

Conversion Instructions 12

Word Logic Instructions 13

Shift and Rotate Instructions 14

Data Block Instructions 15

Jump Instructions 16

Program Control Instructions 17

Appendix

Glossary, Index

10/98

C79000-G7076-C565

Release 01

Statement List (STL) for S7-300 and S7-400Programming

Reference manual

This reference manual is part of the documentationpackage with the order number

6ES7810-4CA04-8BR0

SIMATIC S7

iiStatement List (STL) for S7-300/S7-400

C 9000 G 0 6 C 6 01

This manual contains notices which you should observe to ensure your own personal safety, as well as toprotect the product and connected equipment. These notices are highlighted in the manual by a warningtriangle and are marked as follows according to the level of danger:

!Danger

indicates that death, severe personal injury or substantial property damage will result if proper precautions arenot taken.

!Warning

indicates that death, severe personal injury or substantial property damage can result if proper precautions arenot taken.

!Caution

indicates that minor personal injury or property damage can result if proper precautions are not taken.

Note

draws your attention to particularly important information on the product, handling the product, or to a particularpart of the documentation.

Note the following:

!Warning

This device and its components may only be used for the applications described in the catalog or the technicaldescription, and only in connection with devices or components from other manufacturers which have beenapproved or recommended by Siemens.

This product can only function correctly and safely if it is transported, stored, set up, and installed correctly, andoperated and maintained as recommended.

SIMATIC�, SIMATIC HMI� and SIMATIC NET� are registered trademarks of SIEMENS AG.

Third parties using for their own purposes any other names in this document which refer to trademarks mightinfringe upon the rights of the trademark owners.

We have checked the contents of this manual for agreement with thehardware and software described. Since deviations cannot be precludedentirely, we cannot guarantee full agreement. However, the data in thismanual are reviewed regularly and any necessary corrections included insubsequent editions. Suggestions for improvement are welcomed.

� Siemens AG 1998Technical data subject to change.

Disclaimer of LiabilityCopyright � Siemens AG 1998 All rights reserved

The reproduction, transmission or use of this document or its contents isnot permitted without express written authority. Offenders will be liable fordamages. All rights, including rights created by patent grant or registrationof a utility model or design, are reserved.

Siemens AGBereich Automatisierungs- und AntriebstechnikGeschaeftsgebiet Industrie-AutomatisierungssystemePostfach 4848, D-90327 Nuernberg

Siemens Aktiengesellschaft C79000-G7076-C565

Safety Guidelines

Correct Usage

Trademarks

iiiStatement List (STL) for S7-300/S7-400C79000-G7076-C565-01

Preface

This manual is your guide to creating user programs in the Statement Listprogramming language STL.

The manual also includes a reference section that describes the syntax andfunctions of the language elements of STL.

This manual is intended for S7 programmers, operators, andmaintenance/service personnel. A working knowledge of automationprocedures is essential.

This manual is valid for release 5.0 of the STEP 7 programming softwarepackage.

STL corresponds to the “Instruction List” language defined in theInternational Electrotechnical Commission’s standard IEC 1131-3, althoughthere are substantial differences with regard to the operations. For furtherdetails, refer to the table of standards in the STEP 7 file NORM_TBL.WRI.

Purpose

Audience

Scope of theManual

Compliance withStandards

ivStatement List (STL) for S7-300/S7-400

C79000-G7076-C565-01

To use this Statement List manual effectively, you should already be familiarwith the theory behind S7 programs which is documented in the online helpfor STEP 7. The language packages also use the STEP 7 standard software,so you should be familiar with handling this software and have read theaccompanying documentation.

Documentation Purpose Order Number

STEP 7 Basic Information with

� Working with STEP 7 V5.0, Getting StartedManual

� Programming with STEP 7 V5.0

� Configuring Hardware and CommunicationConnections, STEP 7 V5.0

� From S5 to S7, Converter Manual

Basic information for technical per-sonnel describing the methods of im-plementing control tasks withSTEP 7 and the S7-300/400 pro-grammable controllers.

6ES7810-4CA04-8BA0

STEP 7 Reference with

� Ladder Logic (LAD)/Function Block Dia-gram (FBD)/Statement List (STL) forS7-300/400 manuals

� Standard and System Functions forS7-300/400

Provides reference information anddescribes the programming langua-ges LAD, FBD and STL and stan-dard and system functions extendingthe scope of the STEP 7 basic infor-mation.

6ES7810-4CA04-8BR0

Online Helps Purpose Order Number

Help on STEP 7 Basic information on programmingand configuraing hardware withSTEP 7 in the form of an onlinehelp.

Part of the STEP 7 Stan-dard software.

Reference helps on STL/LAD/FBD

Reference help on SFBs/SFCs

Reference help on Organization Blocks

Context-sensitive reference informa-tion.

Part of the STEP 7 Stan-dard software.

You can display the online help in the following ways:

� Context-sensitive help about the selected object with the menu commandHelp > Context-Sensitive Help, with the F1 function key, or by clickingthe question mark symbol in the toolbar.

� Help on STEP 7 via the menu command Help > Contents.

References to other documentation are indicated by reference numbers inslashes /.../. Using these numbers, you can check the exact title in theReferences section at the end of the manual.

Requirements

Accessing theOnline Help

References

Preface

vStatement List (STL) for S7-300/S7-400C79000-G7076-C565-01

The SIMATIC Customer Support team offers you substantial additionalinformation about SIMATIC products via its online services:

� General current information can be obtained:

– on the Internet underhttp://www.ad.siemens.de/simatic/html_00/simatic

– via the Fax-Polling number 08765-93 02 77 95 00

� Current product information leaflets and downloads which you may finduseful are available:

– on the Internet under http://www.ad.siemens.de/support/html_00/

– via the Bulletin Board System (BBS) in Nuremberg (SIMATICCustomer Support Mailbox) under the number +49 (911) 895-7100.

To dial the mailbox, use a modem with up to V.34 (28.8 Kbps) withthe following parameter settings: 8, N, 1, ANSI; or dial via ISDN(x.75, 64 Kbps).

If you have other questions, please contact the Siemens representative in yourarea. The addresses are listed, for example, in catalogs and in Compuserve(go autforum ).

Our SIMATIC Basic Hotline is also ready to help:

� in Nuremberg, Germany

– Monday to Friday 07:00 to 17:00 (local time): telephone:+49 (911) 895–7000

– or E-mail: [email protected]

� in Johnson City (TN), USA

– Monday to Friday 08:00 to 17:00 (local time): telephone:+1 423 461–2522


� in Singapore

– Monday to Friday 08:30 to 17:30 (local time): telephone:+65 740–7000


The SIMATIC Premium Hotline is available round the clock worldwidewith the SIMATIC card (telephone: +49 (911) 895-7777).

Siemens offers a number of training courses to introduce you to the SIMATICS7 automation system. Please contact your regional training center or thecentral training center in Nuremberg, Germany for details:Telephone: +49 (911) 895-3154.

SIMATIC CustomerSupport OnlineServices

AdditionalAssistance

Courses forSIMATIC Products

Preface

viStatement List (STL) for S7-300/S7-400

C79000-G7076-C565-01

To help us to provide the best possible documentation for you and futureSTEP 7 users, we need your support. If you have any comments orsuggestions relating to this manual or the online help, please complete thequestionnaire at the end of the manual and send it to the address shown.Please include your own personal rating of the documentation.

Questionnaires onthe Manual andOnline Help

Preface

viiStatement List (STL) for S7-300/S7-400C79000-G7076-C565-01

Contents

Preface iii. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1 Product Overview 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Structure and Components of Instructions and Statements 2-1. . . . . . . . . . . . . . . .

2.1 Structure of a Statement 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Meaning of the CPU Register in Statements 2-10. . . . . . . . . . . . . . . . . . . . . . . . .

3 Addressing 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 Immediate Addressing 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Direct Addressing 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 Memory Indirect Addressing 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 Address Registers 3-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5 Area-Internal Register Indirect Addressing 3-7. . . . . . . . . . . . . . . . . . . . . . . . . .

3.6 Area-Crossing Register Indirect Addressing 3-11. . . . . . . . . . . . . . . . . . . . . . . . .

4 Accumulator Operations and Address Register Instructions 4-1. . . . . . . . . . . . . . . .

4.1 Overview 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 ENT and LEAVE 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3 Incrementing and Decrementing 4-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4 +AR1 und +AR2: Adding a Constant to Address Register 1 or Address Register 2 4-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 Bit Logic Instructions 5-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1 Boolean Bit Logic 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2 Bit Logic Instructions and Relay Coil Circuit 5-6. . . . . . . . . . . . . . . . . . . . . . . . . .

5.3 Evaluating Conditions Using And, Or, and Exclusive Or 5-10. . . . . . . . . . . . . . .

5.4 Nesting Expressions and And before Or 5-14. . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.5 Instructions for Transitional Contacts: FP, FN 5-16. . . . . . . . . . . . . . . . . . . . . . . .

5.6 Output of Boolean Logic String 5-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7 Set and Reset Instructions: S and R 5-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.8 Assign Instruction (=) 5-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.9 Negating, Setting, Clearing, and Saving the RLO 5-26. . . . . . . . . . . . . . . . . . . . .

viiiStatement List (STL) for S7-300/S7-400

C79000-G7076-C565-01

6 Timer Instructions 6-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1 Overview 6-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2 Location of a Timer in Memory and Components of a Timer 6-3. . . . . . . . . . .

6.3 Loading, Starting, Resetting, and Enabling a Timer 6-5. . . . . . . . . . . . . . . . . . .

6.4 Timer Examples 6-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.5 Address Locations and Ranges for Timer Instructions 6-17. . . . . . . . . . . . . . . . .

6.6 Choosing the Right Timer 6-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7 Counter Instructions 7-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1 Overview 7-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2 Setting, Resetting, and Enabling a Counter 7-3. . . . . . . . . . . . . . . . . . . . . . . . . .

7.3 Couting Up and Counting Down 7-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.4 Loading a Count Value as Integer 7-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.5 Loading a Count Value in Binary Coded Decimal Format 7-7. . . . . . . . . . . . . .

7.6 Counter Example 7-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.7 Address Locations and Ranges for Counter Instructions 7-10. . . . . . . . . . . . . . .

8 Load and Transfer Instructions 8-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.1 Overview 8-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.2 Loading and Transferring 8-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.3 Reading the Status Word or Transferring to the Status Word 8-6. . . . . . . . . . .

8.4 Loading Times and Counts as Integers 8-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.5 Loading Times and Counts in Binary Coded Decimal Format 8-9. . . . . . . . . .

8.6 Loading and Transferring between Address Registers 8-11. . . . . . . . . . . . . . . .

8.7 Loading Data Block Information 8-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9 Integer Math Instructions 9-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.1 Four-Function Math 9-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.2 Adding an Integer to Accumulator 1 9-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10 Floating-Point Math Instructions 10-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.1 Four-Function Math 10-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.2 Forming the Absolute Value of a Floating-Point Number 10-6. . . . . . . . . . . . . . .

10.3 Extended Math Instructions 10-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.4 Forming the Square / Square Root of a Floating-Point Number 10-9. . . . . . . . .

10.5 Forming the Natural Logarithm of a Floating-Point Number 10-11. . . . . . . . . . . .

10.6 Forming the Exponential Value of a Floating-Point Number 10-12. . . . . . . . . . . .

10.7 Forming Trigonometric Functions on Angles Acting as Floating-Point Numbers 10-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents

ixStatement List (STL) for S7-300/S7-400C79000-G7076-C565-01

11 Comparison Instructions 11-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.1 Overview 11-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.2 Comparing Two Integers 11-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.3 Comparing Two Floating-Point Numbers 11-5. . . . . . . . . . . . . . . . . . . . . . . . . . . .

12 Conversion Instructions 12-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.1 Converting Binary Coded Decimal Numbers and Integers 12-2. . . . . . . . . . . . .

12.2 Converting 32-Bit Floating-Point Numbers to 32-Bit Integers 12-8. . . . . . . . . . .

12.3 Reversing the Order of Bytes within Accumulator 1 12-13. . . . . . . . . . . . . . . . . . .

12.4 Forming Complements and Negating Floating-Point Numbers 12-14. . . . . . . . .

13 Word Logic Instructions 13-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.1 Overview 13-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.2 16-Bit Word Logic Instructions 13-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.3 32-Bit Word Logic Instructions 13-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14 Shift and Rotate Instructions 14-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14.1 Shift Instructions 14-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14.2 Rotate Instructions 14-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15 Data Block Instructions 15-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15.1 Opening Data Blocks 15-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15.2 Swapping Data Block Registers 15-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15.3 Loading Data Block Lengths and Numbers 15-3. . . . . . . . . . . . . . . . . . . . . . . . . .

16 Jump Instructions 16-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16.1 Overview 16-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16.2 Unconditional Jump Instructions 16-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16.3 Conditional Jump Instructions Founded on Result of Logic Operation 16-4. . .

16.4 Conditional Jump Instructions Founded on BR, OV, or OS Bits of the Status Word 16-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16.5 Conditional Jump Instructions Based on Result in the CC 1 and CC 0 Bits of the Status Word 16-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16.6 Loop Control 16-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

17 Program Control Instructions 17-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

17.1 Parameter Assignment when Calling FCs and FBs 17-2. . . . . . . . . . . . . . . . . . .

17.2 Calling Functions and Function Blocks with CALL 17-3. . . . . . . . . . . . . . . . . . . .

17.3 Calling Functions and Function Blocks with CC and UC 17-7. . . . . . . . . . . . . . .

17.4 Working with Master Control Relay Functions 17-10. . . . . . . . . . . . . . . . . . . . . . . .

17.5 Master Control Relay Instructions 17-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

17.6 Ending Blocks 17-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents

xStatement List (STL) for S7-300/S7-400

C79000-G7076-C565-01

A Alphabetical Listing of Instructions A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A.1 Listing with (German) SIMATIC and International Mnemonics A-2. . . . . . . . . .

A.2 Alphabetical Listing with International Names A-12. . . . . . . . . . . . . . . . . . . . . . . .

B Programming Examples B-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B.1 Overview B-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B.2 Bit Logic Instructions B-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B.3 Timer Instructions B-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B.4 Counter and Comparison Instructions B-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B.5 Integer Math Instructions B-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B.6 Word Logic Instructions B-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C Source Files - Examples and Reserved Keywords C-1. . . . . . . . . . . . . . . . . . . . . . . . .

D References D-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Glossary Glossary-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Index Index-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents

1-1Statement List (STL) for S7-300/S7-400C79000-G7076-C565-01

Product Overview

Statement List (STL) is a textual programming language that can be used tocreate the code section of logic blocks. Its syntax for statements is similar toassembler language and consists of instructions followed by addresses onwhich the instructions act.

Of all the programming languages with which you can program S7controllers, STL is the closest to the machine code MC7 of the S7 CPU. Thismeans that by using it to program S7 controllers, you can optimize the runtime and the use of memory.

The programming language STL has all the necessary elements for creating acomplete user program. It contains a comprehensive range of instructions. Atotal of over 130 different basic instructions and a wide range of addressesare available. Functions and function blocks allow you to structure your STLprogram clearly.

The STL programming package is an integral part of the STEP 7 StandardSoftware. This means that following the installation of your STEP 7software, all the editor functions, compiler functions and test/debug functionsfor STL are available to you.

Using STL, you can create your own user program as follows:

� With the Incremental Editor. The input of the local data structure is madeeasier with the help of table editors.

� With a source file in the Text Editor. Text input is made easier with thehelp of block templates.

There are three programming languages in the standard software, STL, FBD,and LAD. You can switch from one language to the other almost withoutrestriction and choose the most suitable language for the particular block youare programming.

If you write programs in LAD or FBD, you can always switch over to theSTL representation. If you convert LAD programs into FBD programs andvice versa, program elements that cannot be represented in the destinationlanguage are displayed in STL.

What is StatementList?

The ProgrammingLanguage STL

The ProgrammingPackage

1

1-2Statement List (STL) for S7-300/S7-400

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Structure and Components ofInstructions and Statements

Section Description Page

2.1 Structure of a Statement 2-2

2.2 Meaning of the CPU Register in Statements 2-10

Chapter Overview

2


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2.1 Structure of a Statement

With reference to structure, an instruction statement belongs to either one ofthe following two basic groups (see also Figure 2-1):

� A statement made up of an instruction alone (for example, NOT, seeSection 5.9)

� A statement made up of an instruction and an address (see Tables 2-1through 2-5, and Table 2-9)

Statement group 1

Instruction + addressInstruction alone

Statement group 2

Figure 2-1 Basic Groups of Statements

The address of an instruction indicates a constant or the location where theinstruction finds a value (data object) on which to perform an operation. Theaddress can have a symbolic name or an absolute designation. The addresscan point to any of the following items (see also Tables 2-1 through 2-9):

� A constant, the value of a timer or counter, or an ASCII character stringto be loaded into accumulator 1 (for example, L +27, see Table 2-1)

� A bit in the status word of the programmable logic controller (forexample, A UO, see Table 2-2)

� A symbolic name (for example, A Motor.On, see Table 2-3)

� A data block and a location within the data block area (for example,L DB4.DBD10, see Table 2-4)

� A function (FC), function block (FB), integrated system function (SFC),or integrated system function block (SFB) and the number of the functionor block (see Table 2-5)

� An address identifier and a location within the memory area that isindicated by the address identifier (for example, A I 1.0, orA I [AR1,P#4.3], see Table 2-9)

Tables 2-1 through 2-9 show various statements that each include aninstruction with an address.

Components of aStatement

Address of anInstruction

Structure and Components of Instructions and Statements


Table 2-1 shows how you can use a constant value as the address of aninstruction.

Table 2-1 Addresses That Point to a Value or Character String

StatementD i iInstruction Address Description

Constant

L +27 Load the integer 27 into accumulator 1.

L ’END’ Load the ASCII characters ’END’ into accumulator 1.

The address of a statement list instruction can refer to one or more bits in thestatus word of the programmable logic controller (see Section 2.2). Theinstruction checks and reacts to the signal state of a single bit in the statusword (for example, A BR) or interprets the bit combination in two of the bits(for example, A UO).

Table 2-2 Addresses That Refer to a Bit in the Status Word

Statement

Instruction Address Description

Bit in the StatusWord

A BR The 1 or 0 in bit 8 of the status word is included in aBoolean logic combination.

A UO The instruction interprets the bit combination that itfinds in bits CC 1 and CC 0 of the status word tosee if a certain condition has been fulfilled. Forexample, a combination of 1 and 1 indicates“unordered,” that is, one of the values in afloating-point operation was not a validfloating-point number.

Constant Values

Locations in theStatus Word



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Table 2-3 shows how you use a symbolic name as the address of aninstruction. You can only use symbolic names in STL statements once youhave declared them: shared symbolic names should be entered in the symboltable and local names in a block.

Table 2-3 Addresses That Point to a Symbolic Name

StatementD i iInstruction Address Description

Symbol

A Motor.On Perform an And logic operation on the bit whosesymbolic name is “Motor.On”. In this case, thesymbolic name “Motor.On” can only represent a bitin the data block (D) area of memory or element of astructure “MOTOR” .

L SPEED Load the byte, word, or double word value, whosesymbolic name is SPEED, into accumulator 1 .

Table 2-4 shows how you use a data block and a location within the datablock as the address of an instruction.

Table 2-4 Addresses That Point to a Data Block and a Location within the DataBlock

Statement

Instruction AddressDescri ption

Data Block andLocation

Descr pt on

L DB4.DBD10 Load data double word DBD10 from data blockDB4 into accumulator 1.

A DB10.DBX4.3 Perform an And logic operation on data bit DBX4.3from data block DB10.

Symbolic Name

A Data Block and aLocation withinthe Data Block



Table 2-5 shows how you use a function (FC), function block (FB),integrated system function (SFC), or integrated system function block (SFB)and the number of the function or block as the address of an instruction.

Table 2-5 Addresses That Point to a Function, Function Block, System Function,or System Function Block

Statement

Instruction AddressD i ti

FC, FB,SFC, SFB and

Number

Description

CALL FB10, DB10 Call function block FB10 with instance data blockDB10.

CALL SFC43 Call integrated system function SFC43.

Some addresses include an address identifier and a location within thememory area indicated by the address identifier. An address identifier can beone of the following three basic types (see Tables 2-6 through 2-8):

� An address identifier that indicates the memory area and the size of a dataobject in that area as follows (see Table 2-6):

– The memory area in which an instruction finds a value (data object)on which to perform an operation (for example, “I” for the processimage input area of memory)

– The size of the value (data object) on which the instruction is toperform its operation (for example, B for “byte,” W for “word,” and Dfor “double word”)

� An address identifier that indicates a memory area but no size of a dataobject in that area (for example, an identifier that indicates the area T for“timer,” C for “counter,” or DB or DI for “data block,” plus the numberof that timer, counter, or data block, see Table 2-7)

� An address identifier that indicates the size of a data object but nomemory area. The memory area is encoded in the memory location thatfollows the address identifier (see Table 2-8).

FCs, FBs, SFCs,and SFBs

Address Identifiers



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Table 2-6 Address Identifier That Indicates Memory Area and Size of Data Object

Type of Addressing Instruction Address Identifier Memory Location

Memory Area Size of Data Object (If nosize is indicated, a bit isimplied.)

Direct A I 0.0

Direct L I B 10

Memory indirect A I [MD2]

Memory indirect L I B [DID4]

Area-internal registerindirect

A I [AR1, P#4.3]

Area-internal registerindirect

T L D [AR2, P#53.0]

Table 2-7 Address Identifier That Indicates Memory Area, but No Size of Data Object

Type of Addressing Instruction Address Identifier: MemoryArea

Number orLocation of

Number

Direct OPN DB 5

Direct SP T 7

Memory indirect OPN DB [LW2]

Memory Indirect S C [MW44]

Table 2-8 Address Identifier That Indicates Size of Data Object, but No Memory Area

Type of Addressing Instruction Size of Data Object(If no size is indicated, a bit is

implied.)

Memory Location

Area-crossing registerindirect

A [AR1, P#4.3]

Area-crossing registerindirect

L B [AR1, P#100.0]

Table 2-9 Addresses That Include Address Identifier and Location

Statement

Instruction AddressD i ti

AddressIdentifier

Location inMemory Area

or Register

Description

A I 1.0 Perform an And logic operation on input bit 1.0.

A I [MD2] Perform an And logic operation on the input bit whose exactlocation is in memory double word MD2.

L C 1 Load the count value of counter 1 into accumulator 1.



If you are working with an instruction whose address identifier indicates amemory area of your programmable logic controller and a data object that iseither a word or a double word in size (see Table 2-6), you need to be awareof the fact that the memory location is always referenced as a byte location.This byte location is the number of the most significant byte within the wordor double word. For example, the address in the statement shown inFigure 2-2 references four successive bytes in memory area M, starting atbyte 10 (MB10) and going through byte 13 (MB13).

Statement: L MD10

Address identifier Byte location

Figure 2-2 Example of Memory Location Referenced as Byte Location

Figure 2-3 illustrates data objects of the following sizes:

� Double word: memory double word MD10

� Word: memory words MW10, MW11, and MW13

� Byte: memory bytes MB10, MB11, MB12, and MB13

When you use absolute addresses that are a word or a double word in width,make sure that you do not create any byte assignments that overlap.

MB10 MB11 MB12 MB13

MW11

MD10

MW10 MW1215 0�15 0

16�15 031

MSB LSB

Figure 2-3 Referencing a Memory Location as a Byte Location

Most addresses in STL refer to memory areas. The following table lists thememory areas and describes the function of each area.

Working with Wordor Double Word asData Object

Memory Areas andtheir Functions



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Table 2-10 Memory Areas and Their Functions

Name of Area Function of AreaAccess to Area

Name of Area Funct on of Areavia Units of the Following Size: Abbrev.

Process imageinput

At the beginning of the scan cycle, the operatingsystem reads the inputs from the process andrecords the values in this area. The program canuse these values in its cyclic processing.

Input bitInput byteInput wordInput double word

IIBIWID

Process imageoutput

During the scan cycle, the program calculatesoutput values and places them in this area. At theend of the scan cycle, the operating system readsthe calculated output values from this area andsends them to the process outputs.

Output bitOutput byteOutput wordOutput double word

QQBQWQD

Bit memory This area provides storage for interim resultscalculated in the program.

Memory bitMemory byteMemory wordMemory double word

MMBMWMD

I/O:external input

This area enables your program to have directaccess to input and output modules (that is,peripheral inputs and outputs).

Peripheral input bytePeripheral input wordPeripheral input double word

PIBPIWPID

I/O:external output

Peripheral output bytePeripheral output wordPeripheral output double word

PQBPQWPQD

Timer Timers are function elements of STLprogramming. This area provides storage fortimer cells. In this area, clock timing accessestime cells to update them by decrementing thetime value and timer instructions access timecells.

Timer (T) T

Counter Counters are function elements of STLprogramming. This area provides storage forcounters. Counter instructions access them here.

Counter (C) C

Data block This area contains data that can be accessed fromany block. If you need to have two different datablocks open at the same time, you can open onewith the statement “OPN DB” and one with thestatement “OPN DI”. In this way, the CPU candistinguish which of the two data blocks yourprogram wants to access while both data blocksare open.

Data block opened with the statement“OPN DB”:

Data bitData byteData wordData double word

DBXDBBDBWDBD

are open.While you can use the “OPN DI” statement toopen any data block, the principal use of thisstatement is to open instance data blocks that areassociated with function blocks (FBs) and systemfunction blocks (SFBs). For more information onFBs, SFBs, and instance data blocks, see theSTEP 7 Online Help.

Data block opened with the statement“OPN DI”:


DIXDIBDIWDID

Local data This area contains temporary data that is usedwithin a logic block (OB, FB, or FC). These dataare also called dynamic local data. They serve asan intermediate buffer. When the logic block isfinished, these data are lost. The data arecontained in the local data stack (L stack).

Temporary local data bitTemporary local data byteTemporary local data wordTemporary local data double word

LLBLWLD



Table 2-11 lists the maximum address ranges for various memory areas. Forthe address range possible with your CPU, refer to the technical data of theCPU. For an explanation of the functions of the memory areas, seeTable 2-10.

Table 2-11 Memory Areas and Their Address Ranges

Name of AreaAccess to Area

M i Add RName of Areavia Units of the Following Size: Abbrev.

Maximum Address Range

Process image input Input bitInput byteInput wordInput double word

IIBIWID

0.0 to 65,535.70 to 65,5350 to 65,5340 to 65,532

Process imageoutput

Output bitOutput byteOutput wordOutput double word

QQBQWQD

0.0 to 65,535.70 to 65,5350 to 65,5340 to 65,532

Bit memory Memory bitMemory byteMemory wordMemory double Word

MMBMWMD

0.0 to 255.70 to 2550 to 2540 to 252

I/O:external input

Peripheral input bytePeripheral input wordPeripheral input double word

PIBPIWPID

0 to 65,5350 to 65,5340 to 65,532

I/O:external output

Peripheral output bytePeripheral output wordPeripheral output double word

PQBPQWPQD

0 to 65,5350 to 65,5340 to 65,532

Timer Timer (T) T 0 to 255

Counter Counter (C) C 0 to 255

Data block Data block opened with the statement “OPN DB”:


DBXDBBDBWDBD

0.0 to 65,535.70 to 65,5350 to 65, 5340 to 65,532

Data block opened with the statement “OPN DI”:


DIXDIBDIWDID

0.0 to 65,535.70 to 65,5350 to 65, 5340 to 65,532

Local data Temporary local data bitTemporary local data byteTemporary local data wordTemporary local data double word

LLBLWLD

0.0 to 65,535.70 to 65,5350 to 65, 5340 to 65,532



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2.2 Meaning of the CPU Register in Statements

The two 32-bit accumulators are general purpose registers that you use toprocess bytes, words, and double words. You can load constants or valuesfrom the memory as addresses into the accumulator and perform logicoperations on them. You can also transfer the result of an operation fromaccumulator 1 to a memory location. Figure 2-4 identifies the areas of anaccumulator.

The stack mechanism for accumulator administration is as follows:

� A load instruction always acts on accumulator 1 and saves the oldcontents to accumulator 2.

� A transfer instruction does not change the accumulators (with theexception of instructions TAR1 and TAR2).

� The TAK instruction swaps the contents of accumulators 1 and 2.

For information on accumulator administration for math instructions, seeSection 9.1.

0781516232431

Accumulator (1 or 2)Low wordHigh word

Low byteHigh byteLow byteHigh byte

Figure 2-4 Areas of an Accumulator

The nesting stack is a storage area that is one byte wide. This storage area isused by the nesting instructions A(, O(, X(, AN(, ON(, XN(. Theseinstructions save the current result of logic operation (RLO) to the nestingstack and start a new logic string.

The nesting stack can accommodate seven entries. A nesting stack entryconsists of the RLO, BR, and OR bits of the status word, and a function codeto indicate which of the Boolean logic operations is to be used (A, AN, O,ON, X, or XN).

The “)” instruction closes a nesting expression by performing the followingfunctions:

� Fetches an entry from the nesting stack

� Restores the OR and BR bits

� Defines the new RLO by logically combining the current RLO (that is,the RLO from the expression nested in parentheses) with the RLO of thestack entry according to the function code (see Section 5.4)

Accumulators

Nesting Stack



Figure 2-5 shows the structure of an entry in the nesting stack. BelowFigure 2-5 you can see an explanation of the bits in the nesting stack byte.

2427 26 25 2023 22 21

BR OR0 0 RLO Function code

Figure 2-5 Structure of an Entry in the Nesting Stack

The nesting stack byte contains the following bits (see Figure 2-5):

� Non-assigned bits (bits 7 and 6 with signal state “0”)

� The stored binary result (BR)

� The stored result of logic operation (RLO)

� The stored OR bit in the functions A( and AN(Zero is stored in all other functions

� The function code (in bits 2, 1 and 0)

Function code

With the help of the function code, the instruction “)” defines the functionwhich is to be used for the combination of the current RLO (that is the RLOfrom the expression nested in parentheses) with the RLO of the nesting stackentry. Table 2-12 shows the bit combinations of the function code for eachfunction type:

Table 2-12 Function Codes of Nesting Stack Byte

Instruction Function Code 2 Function Code 1 Function Code 0

A( 0 0 0

AN( 0 0 1

O( 0 1 0

ON( 0 1 1

X( 1 0 0

XN( 1 0 1



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Nesting Stack with Entries and Pointer

The nesting stack and the nesting stack pointer must be stored either in theinterrupt stack or they must be fetched from it, when the batches change. Thenumber in the nesting stack pointer indicates the number of entries availablein the nesting stack (see Figure 2-6).

15 7 0

Risingaddresses

Nesting stack pointer

Nesting stack entry 7







Figure 2-6 Structure of a Nesting Stack with Entries and Pointer

The status word contains bits that you can reference in the address of bitlogic and word logic instructions. Figure 2-7 shows the structure of the statusword. The sections that follow the figure explain the significance of bits0 through 8.

28215... ...29 2427 26 25 2023 22 21

BR OSCC 1 CC 0 OV OR STA RLO FC

Figure 2-7 Structure of the Status Word

Bit 0 of the status word is called the first-check bit (FC bit, see Figure 2-8).The signal state of 0 in the FC bit indicates that, following this point in yourprogram, the next logic instruction begins a new logic string. (The bar overthe FC indicates that it is negated.)

Each logic instruction checks the signal state of the FC bit as well as thesignal state of the location it addresses. If the FC bit is 0, the instructionstores the result of the signal state check in the result of logic operation bit ofthe status word (RLO bit, see next section) and sets the FC bit to 1. Thisprocess is called a first check (see Figure 2-8 and Section 5.6).

If the signal state of the FC bit is equal to 1, an instruction combines theresult of its signal state check on the contact it addresses with the valuestored in the previous RLO bit (see Figure 2-8).

A string of logic instructions always ends with an output instruction (S, R, or=, see Sections 5.7 and 5.8), a jump instruction related to the result of logicoperation (JC, see Section 16), or one of the nesting instructions A(, O(, X(,AN(, ON(, or XN( (see Section 5.4). Such an output, jump instruction, ornesting instruction resets the FC bit to 0 (see Figure 2-8).

Status Word

First Check



Bit 1 of the status word is called the RLO bit (RLO stands for “result of logicoperation,” see Figure 2-7). This bit stores the result of a bit logic instructionor math comparison.

For example, the second instruction in a string of bit logic instructions checksthe signal state of a contact and produces a result of 1 or 0. Then theinstruction combines this result with the value stored in the RLO bit of thestatus word according to the principles of Boolean logic (see First Checkabove and Chapter 5). The result of this logic operation is stored in the RLObit of the status word, replacing the former value in the RLO bit. Eachsubsequent instruction in the string performs a logic operation on two values:the result produced when the instruction checks the contact, and the currentRLO.

You can set the RLO to 1 unconditionally by using the SET instruction; youcan reset the RLO to 0 unconditionally by using the CLR instruction. Youcan use a Boolean bit logic instruction on a first check to assign the state ofthe contents of a Boolean bit memory location to the RLO. You can use theRLO to trigger jump instructions.

Result of check is combined withprevious RLO according to ANDtruth table. FC bit remains 1.

StatementList Program

Signal Stateof Input (I)or Output (Q)

A I 1.0

AN I 1.1

= Q 4.0

RLOBit

Result ofCheck

1 1 Result of first check is stored inRLO bit. FC bit is set to 1.

0 1

1 RLO is assigned to outputcoil. FC bit is reset to 0.

1

1

ExplanationFCBit

0

1

1

0

FC bit = 0 indicates that nextinstruction begins logic string

Figure 2-8 Effect of Signal State of FC Bit on Logic Instructions

The status bit (STA bit) stores the value of a bit that is referenced. The statusof a bit instruction that has read access to the memory (A, AN, O, ON, X,XN) is always the same as the value of the bit that this instruction checks (thebit on which it performs its logic operation). The status of a bit instructionthat has write access to the memory (S, R, =) is the same as the value of thebit to which the instruction writes or, if no writing takes place, the same asthe value of the bit that the instruction references. The status bit has nosignificance for bit instructions that do not access the memory. Suchinstructions set the status bit to 1 (STA=1). The status bit is not checked byan instruction. It is interpreted during program test (program status) only.

Result of LogicOperation

Status Bit



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The OR bit is needed if you use the O instruction to perform a logical ANDbefore OR operation. An AND function may contain the followinginstructions: A, AN A(, AN(, ), and NOT. The OR bit shows theseinstructions that a previously executed AND function has supplied thevalue 1, thus forestalling the result of the logical OR operation. Any otherbit-processing command resets the OR bit (see Section 5.4).

The overflow bit (OV bit) indicates a fault. It is set by a math instruction or afloating-point comparison instruction after a fault occurs (overflow, illegaloperation, illegal floating-point number). This bit is set according to theresult of the next math instruction or comparison instruction.

The stored overflow bit (OS bit) is set together with the OV bit when a faultoccurs. Because the OS bit remains set after the fault has been eliminated, itstores the OV bit status and indicates whether or not a fault occurred in oneof the previously executed instructions. The following commands reset theOS bit: JOS (jump after stored overflow), the block call commands, and theblock end commands.

The CC 1 and CC 0 bits (condition codes) provide information on thefollowing results or bits:

� Result of a math operation

� Result of a comparison

� Result of a digital operation

� Bits that have been shifted out by a shift or rotate command

Tables 2-13 through 2-18 list the significance of CC 1 and CC 0 after yourprogram executes certain instructions.

Table 2-13 CC 1 and CC 0 after Math Instructions, without Overflow

CC 1 CC 0 Explanation

0 0 Result = 0

0 1 Result < 0

1 0 Result > 0

Table 2-14 CC 1 and CC 0 after Integer Math Instructions, with Overflow


0 0 Negative range overflow in +I and +D

0 1 Negative range overflow in �I and �DPositive range overflow in +I, –I, +D, –D, NEGI, and NEGD

1 0 Positive range overflow in �I, �D, /I, and /DNegative range overflow in +I, –I, +D, and –D

1 1 Division by 0 in /I, /D, and MOD

OR Bit

Overflow Bit

Stored OverflowBit

Condition Code 1and ConditionCode 0



Table 2-15 CC 1 and CC 0 after Floating-Point Math Instructions, with Overflow


0 0 Gradual underflow

0 1 Negative range overflow

1 0 Positive range overflow

1 1 Invalid floating-point number

Table 2-16 CC 1 and CC 0 after Comparison Instructions


0 0 Accumulator 2 = accumulator 1

0 1 Accumulator 2 < accumulator 1

1 0 Accumulator 2 > accumulator 1

1 1 Accumulator 1 or accumulator 2 is an invalid floating-pointnumber

Table 2-17 CC 1 and CC 0 after Shift and Rotate Instructions


0 0 Last bit shifted out = 0

1 0 Last bit shifted out = 1

Table 2-18 CC 1 and CC 0 after Word Logic Instructions


0 0 Result = 0

1 0 Result <> 0



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The binary result bit (BR bit) forms a link between the processing of bits andwords. It is an efficient means of interpreting the result of a word operationas a binary result and integrates this result in a binary logic string. Viewed inthis way, the BR bit represents a machine-internal memory bit to which theRLO is saved prior to a word operation that changes the RLO, so that theRLO will be available again after the operation to continue the interrupted bitstring.

For example, the BR bit makes it possible for you to write a function block(FB) or a function (FC) in statement list (STL) and then call the FB or FCfrom ladder logic (LAD, see the Reference Manual /233/).

When writing a function block or function that you want to call from LAD,no matter whether you write the FB or FC in STL or LAD, you areresponsible for managing the BR bit. The BR bit corresponds to the enableoutput (ENO) of a LAD box. You should use the SAVE instruction (in STL,see Section 5.9) or the –––(SAVE) coil (in LAD) to store an RLO in the BRbit according to the following criteria:

� Store an RLO of 1 in the BR bit for a case where the FB or FC isexecuted without error.

� Store an RLO of 0 in the BR bit for a case where the FB or FC isexecuted with error

You should program these instructions at the end of the FB or FC so thatthese are the last instructions that are executed in the block.

When you call a system function block (SFB) or a system function (SFC) inyour program, the SFB or SFC indicates whether the CPU was able toexecute the function with or without errors by providing the followinginformation in the binary result bit:

� If an error occurred during execution, the BR bit is 0.

� If the function was executed with no error, the BR bit is 1.

Binary Result Bit



Addressing


3.1 Immediate Addressing 3-2

3.2 Direct Addressing 3-2

3.3 Memory Indirect Addressing 3-3

3.4 Address Registers 3-6

3.5 Area-Internal Register Indirect Addressing 3-7

3.6 Area-Crossing Register Indirect Addressing 3-11

Chapter Overview

3


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3.1 Immediate Addressing

With immediate addressing, the address is coded directly in the instruction;that is, it directly follows the value with which the instruction is to work (forexample, Load). An instruction can also provide its own value (for example,SET, see Table 3-1).

Table 3-1 Immediate Addressing

Example Description

SET Set the RLO to 1.

OW W#16#A320 Or Word.

L 27 Load the integer value 27 into accumulator 1.

L ’ABCD’ Load the ASCII characters ABCD into accumulator 1.

L B#(100,12) Load the two bytes 100 and 12 into accumulator 1.

L C#0100 Load the BCD value 0000 into accumulator 1.

3.2 Direct Addressing

An instruction that uses direct addressing has the following two-part addressthat indicates the location of the value that the instruction is going to process:

� An address identifier (for example, “IB” for “input byte”)

� An exact location within the memory area that is indicated by the addressidentifier

The address points directly to the location of the value.

Table 3-2 Direct Addressing

Example Description

A I 0.0 Perform an AND logic operation on input bit I 0.0.

S L 20.0 Set the local data bit L 20.0.

= M 115.4 Assign the RLO to memory bit M 115.4

L IB0 Load input byte IB0 into accumulator 1.

L MW64 Load memory word MW64 into accumulator 1.

T DBD12 Transfer the contents from accumulator 1 into datadouble word DBD12.

Description

Examples

Description

Examples

Addressing


3.3 Memory Indirect Addressing

An instruction that uses memory indirect addressing has the followingtwo-part address that indicates the location of the value that the instruction isgoing to process:

� An address identifier (for example, “IB” for “input byte”)

� One of the following pointers:

– A word that contains the number of a timer (T), counter (C), datablock (DB), function (FC), or function block (FB)

– A double word that contains the exact location of a value within thememory area that is indicated by the address identifier

The address indicates the location of the value or number indirectly via thepointer. This word or double word can be in one of the following areas:

� Bit memory (M)

� Data block (DB)

� Instance data block (DI)

� Local data (L)

The advantage of memory indirect addressing is that you can modify thestatement address dynamically during program execution.

When working with a memory indirect address that is stored in the data blockarea of memory, first you must open the data block by using the Open a DataBlock (OPN) instruction. Then you can use the data word or data doubleword as an indirect address, as shown in the following example:

OPN DB10L IB [DBD20]

Table 3-3 Memory Indirect Addressing

Example Description

A I [MD2]orA I [anna]

Perform an And logic operation on the input bit whose exact location is in memorydouble word MD2 or in the location designated by “anna” in the symbol table, as areference to MD2.

= DIX [DBD2] Assign the RLO bit to the instance data bit whose exact location is in data doubleword DBD2.

OPN DB [LW2] Open the data block whose data block number is located in local word LW2.

O Q [LD3]orO Q [boxcar]

Perform an Or logic operation on the output bit that is located in a local datadouble word LD3 or in a local TEMP variable designated as “boxcar.”

Description

Using the RightSyntax

Examples

Addressing


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There are two possible pointer formats: word and double word. Theabbreviation for a pointer in word format ends in W (for example, DBW).Figure 3-1 shows the pointer format for a word. The abbreviation for adouble word format ends in D (for example, DBD). Figure 3-2 shows thepointer format for a double word.

15.. ..8 7.. ..0n n n n n n n n

Bits 0 to 15 (nnnn nnnn nnnn nnnn): number (range 0 to 65,535) of atimer (T), counter (C), data block (DB), function (FC), or function block (FB)

n n n n n n n n

Figure 3-1 Word Pointer Format for Memory Indirect Addressing

The following two examples show how to work with the word pointerformat:

STL Explanation

L +5T MW2OPN DB[MW2]

Load the value 5 as an integer into accumulator 1.Transfer the contents of accumulator 1 to memory word MW2.Open data block 5.

STL Explanation

OPN DB10L +20T DBW10A T[DBW10]

Open data block DB10.Load the value 20 as an integer into accumulator 1.Transfer the contents of accumulator 1 to data word DBW10Check the signal state of timer T 20.

Pointer Format

Addressing


31.. ..24 23.. ..16 15.. ..8 7.. ..00 0 0 0 0 0 0 0 0 0 0 0 0 b b b b b b b b b b b b b b b b x x x

Bits 3 to 18 (bbbb bbbb bbbb bbbb): byte number (range 0 to 65,535) of theaddressed byte

Bits 0 to 2 (xxx): bit number (range 0 to 7) of the addressed bit

Figure 3-2 Double Word Pointer Format for Memory Indirect Addressing

Note

If you access a byte, word, or double word, be sure that the bit number ofyour pointer is 0.

The following two examples show you how to work with the double wordpointer format:

STL Explanation

L P#8.7

T MD2

A I [MD2]= Q [MD2]

Load 2#0000 0000 0000 0000 0000 0000 0100 0111 (binary value)into accumulator 1.Store the exact location 8.7 in memory double word MD2.

The controller checks input bit I 8.7 and assigns its signalstate to output bit Q 8.7.

STL Explanation

L P#8.0

T MD2

L IB [MD2]T MW [MD2]

Load 2#0000 0000 0000 0000 0000 0000 0100 0000 (binary value)into accumulator 1.Store the exact location 8 in memory double word MD2.

The controller loads input byte IB8 and transfers the contentsto memory word MW8. The exact location 8 comes from memorydouble word MD2.

Addressing


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3.4 Address Registers

Some types of indirect addressing in statement list programming require theuse of certain registers in the CPU. These registers are described below.

Address registers 1 and 2 (AR1 and AR2) are 32-bit registers that accept anarea-internal or area-crossing pointer for commands that use register-indirectaddressing (see Sections 3.5 and 3.6).

Pointers are used in register-indirect addressing (see Sections 3.5 and 3.6).The following two types are available:

� Area-internal: used for area-internal access to bits, bytes, words, anddouble words in memory areas P, I, Q, M, DBX, DIX, and L

� Area-crossing: used for area-crossing access to bits, bytes, words, anddouble words in memory areas P, I, Q, M, DBX, DIX, and L

Explanation

Address Registers1 and 2

Pointers

Addressing


3.5 Area-Internal Register Indirect Addressing

An instruction that uses area-internal register indirect addressing has thefollowing two-part address that indicates the memory location of the valuethat the instruction is going to process:

� An address identifier (for example, “LD” for “local data double word,”see Table 2-6)

� An address register and a pointer to specify byte and bit. The byte and bitindicate an offset, which, when added to the contents of the register,indicate the memory location of the value that the instruction is toprocess.

The address points to the memory location of the value indirectly via theaddress register plus offset.

A statement that uses area-internal register indirect addressing does notchange the value in the address register.

The address of an instruction points to the value that the instruction is goingto process. Where area-internal register indirect addressing is concerned, theaddress points to the memory location of the value indirectly via the addressregister plus offset. Figure 3-3 shows how you calculate the memory locationfor the address of the Assign (=) instruction in the following statement:

= Q [AR1, P#1.1]

Contents of address register AR1: 8.7 byte 8, bit 7

Offset P#: 1.1 byte 1, bit 1

Memory location: output byte Q 10.0 bytes: 9, bits: 8 (= 1 byte)

(9 bytes + 1 byte = 10 bytes)

+

Byte Bit

Figure 3-3 Calculating the Memory Location of Output Q [AR1, P#1.1]

You calculate the memory location of the address by adding the byte portionof the contents of the address register to the byte portion of the offset pointerand by adding the bit portion of the contents of the address register to the bitportion of the offset pointer. You calculate the byte portion of the memorylocation using decimal math and the bit portion using octal math (8 bits =1 byte). There can be a carry between the bit and byte portions.

Description

Calculating theMemory Locationof the Address

Addressing


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Table 3-4 Area-Internal Register Indirect Addressing

Example Description

A I [AR1, P#4.3] Perform an And logic operation on the input bit whosememory location is calculated by the contents ofaddress register AR1 plus 4 bytes, plus 3 bits.

= DIX [AR2, P#0.0] Assign the RLO bit to the instance data bit whosememory location is in address register AR2.

L IB [AR1, P#100.0] Load the input byte whose memory location iscalculated by the contents of address register AR1 plus100 bytes into accumulator 1.

T LD [AR2, P#56.0] Transfer the contents of accumulator 1 into local datadouble word LD whose memory location is calculatedby the contents of address register AR2 plus 56 bytes.

With reference to addressing local data, please read theWarning below.

!Warning

Possible overwriting of the data that is used by the compiler.

When you use absolute addressing to access temporary local data, there is noguarantee that there will be no conflict between the data used by thecompiler and the local data that you are attempting to access by means ofabsolute addressing. It is possible that you overwrite some of the data thatthe compiler uses. (For example, the compiler uses local data for transferringformal parameters.) Local data that the compiler needs are attached to thesymbolic data that are defined by the person doing the programming.

When accessing temporary local data, you are advised to choose symbolicaddressing over absolute addressing.

Examples

Addressing


Area-internal register indirect addressing has only one possible pointerformat: double word. This double word contains an address encoded as a bitaddress. The abbreviation for a double word format ends in D (for example,DBD). Figure 3-4 shows the pointer format for a double word.

31.. ..24 23.. ..16 15.. ..8 7.. ..00 0 0 0 0 0 0 0 0 0 0 0 0 b b b b b b b b b b b b b b b b x x x

Bit 31 = 0 to indicate area-internal register indirect addressing

Bits 3 to 18 (bbbb bbbb bbbb bbbb): byte number (range 0 to 65,535) of theaddressed bit


Figure 3-4 Double Word Pointer Format for Area-Internal Register IndirectAddressing

Note


Pointer Format

Addressing


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STL Explanation

L P#8.7

LAR1

A I [AR1, P#0.0]

= Q [AR1, P#1.1]

Load a double word pointer to bit address location 8.7 intoaccumulator 1.

Store a double word pointer to bit address location 8.7 inaddress register AR1.

The CPU adds the offset (P#0.0) to the contents of addressregister AR1 (8.7) and uses this address as the location of anAnd bit logic instruction. The contents of AR1 remainunchanged.

The CPU assigns the result of the And bit logic operation (RLO)to an address (Q 10.0). The CPU calculates this address byadding the contents of address register AR1 (8.7) and theoffset (P#1.1).

STL Explanation

L P#8.0

LAR2

L IB [AR2, P#2.0]

T MW [AR2, P#200.0]

Load a double word pointer to bit address location 8.0 intoaccumulator 1.

Store a double word pointer to bit address location 8.0 inaddress register AR2.

The CPU loads input byte IB10 into accumulator 1.

The CPU transfers the contents of accumulator 1 to memory wordMW208.

The location 208 comes from 8 (AR2) plus 200 (offset), which is208.

Addressing


3.6 Area-Crossing Register Indirect Addressing

An instruction that uses area-crossing register indirect addressing has thefollowing two-part address that indicates the memory location of the valuethat the instruction is going to process:

� An address identifier that indicates the size of a data object (for example,“B” for “byte,” see Table 2-8). The memory area is indicated in bits 24,25, and 26 of the address register.

� An address register and a pointer that indicate an offset which, whenadded to the contents of the address register, indicates the memorylocation of the value that is to be processed by the instruction. The pointeris indicated by P#byte.bit.

The address points to the memory location of the value indirectly via theaddress register plus offset.

A statement that uses area-crossing register indirect addressing does notchange the value in the address register.

The address of an instruction points to the value that the instruction is goingto process. Where area-crossing register indirect addressing is concerned, theaddress points to the memory location of the value indirectly via the addressregister plus offset. Figure 3-5 shows how you calculate the memory locationfor the address of the Assign (=) instruction in the following statement:

= [AR1, P#1.1]

Contents of address register AR1: 8.7 byte 8, bit 7

Offset P#: 1.1 byte 1, bit 1

Memory location: byte 10.0 bytes: 9, bits: 8 (= 1 byte)

(9 bytes + 1 byte = 10 bytes)

+

Byte Bit

Figure 3-5 Calculating the Address [AR1, P#1.1]

You calculate the memory location of the address by adding the byte portionof the contents of the address register to the byte portion of the offset pointerand by adding the bit portion of the contents of the address register to the bitportion of the offset pointer. You calculate the byte portion of the memorylocation using decimal math and the bit portion using octal math (8 bits =1 byte). There can be a carry between the bit and byte portions.

Description

Calculating theMemory Locationof the Address

Addressing


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Table 3-5 provides examples of area-crossing register indirect addressing.The address must contain an additional area identification in bits 24, 25, and26 of the pointer. The addressed information is in the address register.

Table 3-5 Area-Crossing Register Indirect Addressing

Example Description

A [AR1, P#4.3] Perform an And logic operation on the bit whosememory location is calculated by the contents ofaddress register AR1, plus 4 bytes plus 3 bits. Thememory area of the bit is indicated in bits 24, 25, and26 of address register AR1.

= [AR2, P#0.0] Assign the RLO bit to the bit whose memorylocation is in address register AR2. The memory areaof the bit is indicated in bits 24, 25, and 26 of addressregister AR2.

L B [AR1, P#100.0] Load into accumulator 1 the byte whose memorylocation is calculated in address register AR1 plus100 bytes. The memory area of the byte is indicatedin bits 24, 25, and 26 of address register AR1.

T D [AR2, P#56.0] Transfer the contents of accumulator 1 into thedouble word whose memory location is calculated bythe contents of address register AR2 plus 56 bytes.The memory area of the double word is indicated inbits 24, 25, and 26 of address register AR2.

Table 3-6 lists the binary code in bits 24, 25, and 26 of the pointer thatidentifies the area.

Table 3-6 Area Identification for Area-Crossing Register Indirect Addressing

Area Identification (Memory Area) Binary Contents of Bits 26, 25, and 24

P (I/O, external inputs and outputs) 000

I (process-image input) 001

Q (process-image output) 010

M (bit memory) 011

DBX (data block) 100

DIX (data block) 101

(previous local data, that is, the localdata of the previous incompletedblock)

111

Example

Addressing


Area-crossing register indirect addressing has only one possible pointerformat: double word. The abbreviation for a double word format ends in D(for example, DBD). Figure 3-6 shows the pointer format for a double word.

31.. ..24 23.. ..16 15.. ..01 0 0 0 0 r r r 0 0 0 0 0 b b b b b b b b b b b b b b b b x x x

Bit 31 = 1 to indicate area-crossing register indirect addressing

Bits 24, 25, and 26 (rrr): area identification (memory area, see Table 3-6)

Bits 3 to 18 (bbbb bbbb bbbb bbbb): byte number (range 0 to 65,535) of theaddressed bit


3....8 7..

Figure 3-6 Double Word Pointer Format for Area-Crossing Register IndirectAddressing

Note


You cannot access local data using area-crossing register indirect addressing!

Pointer Format

Addressing


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STL Explanation

L P#I 8.7

LAR1

L P#Q 8.7

LAR2

A [AR1, P#0.0]

= [AR2, P#1.1]

Load a double word pointer to bit address location I 8.7 intoaccumulator 1.

Store a double word pointer to bit address location I 8.7 inaddress register AR1.

Load a double word pointer to bit address location Q 8.7 intoaccumulator 1.

Store a double word pointer to bit address location Q 8.7 inaddress register AR2.

The CPU adds the contents of address register AR1 (P#I 8.7) andthe offset (P#0.0) and uses the address pointed to by theresult (I 8.7) as the address of an And bit logic instruction.The contents of AR1 remain unchanged.

The CPU assigns the result of the And bit logic operation (RLO)to an address (Q 10.0). The CPU calculates this address byadding the contents of address register AR2 (P#Q 8.7) and theoffset (P#1.1) and dereferencing the pointer. The contents ofAR2 remain unchanged.

STL Explanation

L P#I 8.0

LAR2

L P#M 8.0

LAR1

L B [AR2, P#2.0]

T W [AR1, P#200.0]

Load a double word pointer to bit address location I 8.0 intoaccumulator 1.

Store a double word pointer to bit address location I 8.0 inaddress register AR2.

Load a double word pointer to bit address location M 8.0 intoaccumulator 1.

Store a double word pointer to bit address location M 8.0 inaddress register AR1.

The CPU loads input byte IB10.

The CPU transfers the contents to memory word MW208.

Input byte 10 comes from 8 (AR2) plus 2 (offset).Memory word 208 comes from 8 (AR1) plus 200 (offset), which is208.

Addressing


Accumulator Operations and AddressRegister Instructions


4.1 Overview 4-2

4.2 ENT and LEAVE 4-3

4.3 Incrementing and Decrementing 4-6

4.4 +AR1 und +AR2: Adding a Constant to Address Register 1or Address Register 2

4-7

Chapter Overview

4


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4.1 Overview

The following instructions are available to you for handling the contents ofone or both accumulators:

Mnemonic Instruction Explanation

TAK Toggle Accumulator 1 withAccumulator 2

This instruction exchanges the contents of accumulator 1with the contents of accumulator 2.

PUSHwith 2 ACCUs

Accumulator 1 to Accumulator 2This instruction copies the contents of accumulator 1 toaccumulator 2.

POPwith 2 ACCUs

Accumulator 2 to Accumulator 1This instruction copies the contents of accumulator 2 toaccumulator 1.

PUSHwith 4 ACCUs

Copy ACCU 3 to ACCU 4,ACCU 2 to ACCU 3, ACCU 1to ACCU 2

This instruction copies the contents of accumulator 3 toaccumulator 4, the contents of accumulator 2 to accumula-tor 3 and the contents of accumulator 1 to accumulator 2.

POPwith 4 ACCUs

Copy ACCU 2 to ACCU 1,ACCU 3 to ACCU 2, ACCU 4to ACCU 3

This instruction copies the contents of accumulator 2 toaccumulator 1, the contents of accumulator 3 to accumula-tor 2 and the contents of accumulator 4 to accumulator 3.

ENT Enter accumulator stack This instruction copies the contents of accumulator 3 toaccumulator 4 and the contents of accumulator 2 to accu-mulator 3.

LEAVE Leave accumulator stack This instruction copies the contents of accumulator 3 toaccumulator 2 and the contents of accumulator 4 to accu-mulator 3.

INC Increment Accumulator 1 This instruction increases the contents of the low byte ofthe low word of accumulator 1 by the 8-bit constant that isindicated in the instruction statement. The constant can bein the range of 0 to 255.

DEC Decrement Accumulator 1 This instruction decreases the contents of the low byte ofthe low word of accumulator 1 by the 8-bit constant that isindicated in the instruction statement. The constant can bein the range of 0 to 255.

+AR1, +AR2 Add Accumulator 1 to AddressRegister

This instruction adds the contents of the low word of ac-cumulator 1 to address register 1 or 2.

+AR1 P#Byte.Bit,+AR2 P#Byte.Bit

Add Constant to AddressRegister

This instruction adds a constant to the contents of addressregister 1 or 2.

BLD Program Display Instruction ”This instruction does not carry out any function and doesnot influence the status bits. The instruction is only rele-vant to the programming device (PG) when a program isdisplayed. The address <number> is the ID of the instruc-tion BLD and is generated by the programming device.”

NOP 0

NOP 1

Null Instruction 0

Null Instruction 1

”These instructions do not carry out any function, nor dothey influence the contents of the status word. Theinstructions NOP 1 and NOP 0 are required for decompil-ing. The instruction code contains a bit pattern with either16 zeroes or 16 ones.”

For information on reversing the order of bytes in accumulator 1, seeSection 12.3.

Accumulator Operations


4.2 ENT and LEAVE

With the instructions ENT (Enter Accumulator Stack) and LEAVE (LeaveAccumulator Stack) you can carry out the following functions:

� The instruction ENT copies the contents of Accumulator 3 to Accumulator4 and the contents of Accumulator 2 to Accumulator 3. If you programthe ENT instruction directly before a load instruction, it SHIFTSAccumulator 2 and Accumulator 3 further in the stack.

� The instruction LEAVE copies the contents of Accumulator 3 toAccumulator 2 and the contents of Accumulator 4 to Accumulator 3. Ifyou program the LEAVE instruction directly before a shift and rotateinstruction, which combines accumulators, then the LEAVE instructionwill function like a math operation.

Figure 4-1 shows how the ENT instruction works.

031

ACCU 3 ACCU 3

ACCU 4 ACCU 4031

031 031

I II III IV

V VI VII VIII

V VI VII VIII

ENT

IX X XI XII

031

ACCU 1 ACCU 1

ACCU 2 ACCU 2031

031 031

IX X XI XII

XIII XIV XV XVI XIII XIV XV XVI

IX X XI XII

Figure 4-1 Copying the contents of Accumulator 3 to Accumulator 4 and the contents of Accumulator 2 toAccumulator 3 in the ENT instruction ENT

Description

ENT



C79000-G7076-C565-01

Figure 4-2 shows how the LEAVE instruction works.

031

ACCU 3 ACCU 3

ACCU 4 ACCU 4031

031 031

I II III IV

V VI VII VIII

031

ACCU 1 ACCU 1

ACCU 2 ACCU 2031

031 031

IX X XI XII

XIII XIV XV XVI

LEAVE

I II III IV

I II III IV

V VI VII VIII

XIII XIV XV XVI

Figure 4-2 Copying the contents of Accumulator 3 to Accumulator 2 and the contents of Accumulator 4 toAccumulator 3 in the LEAVE instruction

The following program extract shows the use of the ENT instruction.

The floating points in the data double words DBD0 and DBD4 should beadded together. The sum should then be divided by the difference of thefloating points of the data double words DBD8 and DBD12.

DBD16 =DBD0 + DBD4

DBD8 – DBD12

The quotient of the above division should be stored in DBD16.

In this example, the purpose of the ENT instruction is to take the interimresult (DBD0+DBD4), which is located in Accumulator 2 and save it inAccumulator 3. The subtraction command (-R) copies the interim result backto Accumulator 2 following the subtraction.

LEAVE

Example



STL Explanation

L DBD0

L DBD4

+R

L DBD8

ENT

L DBD12

–R

/R

T DBD16

Load the value from data double word DBD0 in ACCU1 (the valuemust be in floating-point format).Copy the value from ACCU1 to ACCU2.Load the value from datadouble word DBD4 in ACCU1 (the value must be in floating-pointformat).Add the contents of ACCU1 and ACCU2 as floating-point numbers(32 bits, IEEE-FP) and store the result in ACCU1.Copy the value from ACCU1 to ACCU2.Load the value from data double word DBD8 to ACCU1.Copy the contents of ACCU3 to ACCU4. Copy the contents of ACCU2 (interim result) to ACCU3.Copy the contents of ACCU1 to ACCU2.Load the contents from data double word DBD12 to ACCU1.Subtract the contents of ACCU1 from the contents of ACCU2.Store the result in ACCU1. Copy the contents of ACCU3 to ACCU2.Divide the contents of ACCU 2 by the contents of ACCU1. Save the quotient in ACCU1.Transfer the result (ACCU1) to the data double word DBD16.



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4.3 Incrementing and Decrementing

You can use the Increment Accumulator 1 (INC) and DecrementAccumulator 1 (DEC) instructions to perform the following functions:

� INC increases the contents of the low byte of the low word ofaccumulator 1 by the 8-bit constant that is indicated in the instructionstatement. The constant can be in the range of 0 to 255.

� DEC decreases the contents of the low byte of the low word ofaccumulator 1 by the 8-bit constant that is indicated in the instructionstatement. The constant can be in the range of 0 to 255.

The CPU always executes the INC and DEC instructions, regardless of theresult of logic operation. These instructions do not affect the RLO nor dothey change any of the bits in the status word.

Note

These instructions are not suitable for 16-bit or 32-bit math because no carryis made from the low byte of the low word of accumulator 1 to the high byteof the low word of accumulator 1. For 16-bit or 32-bit math, use the +I or+D instruction, respectively.

The following sample program provides an example of how the INCinstruction works within a loop triggered by a conditional jump.

STL Explanation

L 1T MB10

M1: L MB10INC 1T MB10..L B#16#5<= ISPB M1

Body of a loop operation

Set the loop counter to 1.

Load the contents of memory byte MB10 into accumulator 1.Increment the loop counter by 1.Transfer the contents of accumulator 1 to memory byteMB10.Instruction section which is processed five times.

If the program has not run through the loop five times,then return to LOOP.

Description

Example



4.4 +AR1 und +AR2: Adding a Constant to Address Register 1 orAddress Register 2

Using the instructions +AR1 and +AR2 you can add a constant to thecontents of address registers 1 and 2:

Table 4-1 Adding to the Contents of Address Registers

Instruction Address Function

+AR1 – Adds the contents of the low word ofaccumulator 1 to the contents of addressregister 1.

+AR2 – Adds the contents of the low word ofaccumulator 1 to the contents of addressregister 2.

+AR1 P#Byte.Bit: (range 0.0 to 4095.7)1

Adds a pointer constant to the contentsof address register 1.

+AR2 P#Byte.Bit: (range 0.0 to 4095.7)1

Adds a pointer constant to the contentsof address register 2.

1 The bits 24, 25, and 26 of the address register remain unchanged. These bits indicatethe memory area.

Note

The address register 2 is used when multiple instances are being processed.Therefore, before programming the command “+AR2”, you must “save” thecontents of AR2 and load them again later.

Below are sample statements that use the +AR1 and +AR2 instructions.Loading the pointer format into accumulator 1 and then using the +AR1 or+AR2 instruction, as shown in the first two statements below, enables you toselect from a range of 0.0 to 8191.7.

STL Explanation

L P#250.7+AR1

TAR2 #SAVE_AR2

+AR2 P#126.7..L AR2 #SAVE_AR2

Load a pointer constant (250.7) into accumulator 1.Add the contents of accumulator 1 (250.7) to the contents ofaddress register 1.Because multiple instances are using AR2 as base.

Add a pointer constant (126.7) to the contents of addressregister 2.

Restore AR2.

Description

Examples



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Bit Logic Instructions


5.1 Boolean Bit Logic 5-2

5.2 Bit Logic Instructions and Relay Coil Circuit 5-6

5.3 Evaluating Conditions Using And, Or, and Exclusive Or 5-10

5.4 Nesting Expressions and And before Or 5-14

5.5 Instructions for Transitional Contacts: FP, FN 5-16

5.6 Output of Boolean Logic String 5-20

5.7 Set and Reset Instructions: S and R 5-21

5.8 Assign Instruction (=) 5-24

5.9 Negating, Setting, Clearing, and Saving the RLO 5-26

Chapter Overview

5


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5.1 Boolean Bit Logic

Boolean bit logic applies to the following basic instructions:

� And (A) and its negated form, And Not (AN)

� Or (O) and its negated form, Or Not (ON)

� Exclusive Or (X) and its negated form, Exclusive Or Not (XN)

These instructions perform the following basic functions:

� They check the signal state of an address to establish whether an addressis activated “1”, or not activated “0”.

� They check the signal state of a timer or a counter to establish whether itis set at “0” (value = 0) or “1” (value > 0).

The FC bit determines the result of logic operation (RLO):

� If FC is 0, the result of the state check will remain unchanged and will bestored in the RLO (start of a logic string).

� If FC is 1, the result of the state check will be combined with the logicinstruction (A, O, X) according to the truth table and will be stored in theRLO.

The result of logic operation can be determined with the help of thefollowing truth table:

Mnemonic Instruction Status ofAddress

Result in RLO

A And 01

01

AN And Not 01

10

O Or 01

01

ON Or Not 01

10

X Exclusive Or 01

01

XN Exclusive Or Not 01

10

Explanation

Truth Table at theStart of a BooleanLogic String



After the second Boolean bit operation the RLO can be established with thehelp of the following table:

Mnemonic Instruction RLO BeforeInstruction

Status ofAddress

Result inRLO

A And 0011

0101

0001

AN And Not 0011

0101

0010

O Or 0011

0101

0111

ON Or Not 0011

0101

1011

X Exclusive Or 0011

0101

0110

XN Exclusive Or Not 0011

0101

1001

The address of an instruction can be a bit, a timer or a counter. Theinstruction accesses the contact with one of these addressing types:

� The address identifier and the address within the memory area defined bythe address identifier (see Tables 5-1 and 5-3).

� Bit, timer or counter transferred as parameter (see Table 5-4).

� Conditions, expressed in bits of the status word (see Table 5-8).

Truth Table withinthe Boolean LogicString

Addresses ofBasic Functions(A, AN, O, ON, X,XN)



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Table 5-1 Addresses: Direct and Indirect Addressing

Address Maximum Address Range According to Addressing Type

ID Direct Memory Indirect Register Indirect, Area-Internal

IQ

0.0 to65,535.7

[DBD][DID][LD][MD]

0 to 65,532[AR1, P#byte.bit]

[AR2, P#byte.bit]0.0 to 8,191.7

M0.0 to

65,535.7

[DBD][DID][LD][MD]


[AR2, P#byte.bit]0.0 to 8,191.7

DBXDIX

L

0.0 to65,535.7

[DBD][DID][LD][MD]


[AR2, P#byte.bit]0.0 to 8,191.7

Table 5-2 Addresses: Area-Crossing Register Indirect Addressing

Address Identifier1 Maximum Address Range

I, Q, M, DBX, DIX, or L[AR1, P#byte.bit][AR2, P#byte.bit]

0.0 to 8,191.7

1 The memory area is encoded in pointer bits 24, 25, and 26 (see Section 3.6).

Table 5-3 Addresses: Timers and Counters

Address IdentifierMaximum Address Range According to Addressing Type

Address Ident f erDirect Memory Indirect

TC

0 to 65,535

[DBW][DIW][LW][MW]

0 to 65,534

Table 5-4 Address: Bit, Timer, or Counter Transferred as Parameter

Address Address Parameter Format

Symbolic name A bit, timer, or counter transferred as parameter

Table 5-5 Addresses of Boolean Bit Logic Instructions: Bits of the Status Word

Memory Area or Reference to aLocation

Bits of the Status Word

>0, <0, <>0, >=0, <=0, ==0 7 and 6: condition codes 1 and 0 (memory area)

UO 7 and 6: condition codes 1 and 0 (memory area)

BR 8: binary result (location)

OV 5: overflow (location)

OS 4: overflow, stored (location)



Instruction OR STA RLO FC

AANA(

AN(

xx00

xx11

xx––

1100

OONO(

ON(

0000

xx11

xx––

1100

XXNX(

XN(

0000

xx11

xx––

1100

= 0 x – 0

CLR 0 0 0 0

FN 0 x x 1

FP 0 x x 1

NOT – 1 x –

R 0 x – 0

S 0 x – 0

SAVE – – – –

SET 0 1 1 0

Change of Bits inthe Status Word



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5.2 Bit Logic Instructions and Relay Coil Circuit

Bit logic instructions are also named relay logic instructions as they canexecute commands which can replace the function of a relay logic circuit.The following explains how a relay logic circuit can be reproduced with STLcommands.

Figure 5-1 shows a relay logic circuit with normally open control relaycontact between a power rail and a coil. The normal state of this contact isopen. If the contact is not activated, it remains open. The signal state of theopen contact is 0 (not activated). If the contact remains open, the power fromthe power rail cannot energize the coil at the end of the circuit. If the contactis activated (signal state of the contact is 1), power will flow to the coil.

Power Rail

Normally OpenContact

Coil

I 1.1

Q 4.0

Figure 5-1 Relay Logic Circuit with Normally Open Control Relay Contact

You can use an And (A) or an Or (O) instruction to check the signal state of anormally open control relay contact. If the normally open contact (I1.1 = 0)is open the check result is “0”, if it is closed the result is “1”.

Introduction

Normally OpenContact



Figure 5-2 shows the representation of a relay logic circuit with normallyclosed control relay contact between a power rail and a coil. The normal stateof this contact is closed. If the contact is not activated, it remains closed. Thesignal state of the closed contact is 0 (not activated). If the contact remainsclosed, power from the power rail can cross the contact to energize the coil atthe end of the circuit. Activating the contact (signal state of the contact is 1)opens the contact, interrupting the flow of power to the coil.

Power Rail

Normally ClosedContact

Coil

I 1.1

Q 4.0

Figure 5-2 Relay Logic Circuit with Normally Closed Control Relay Contact

You can use an And Not (AN) or an Or Not (ON) instruction to check thesignal state of a normally closed control relay contact. If the normally closedcontact is closed (I1.1 = 0) the check result is “1”, if it is open the result is“0”.

Figure 5-3 shows an example with a statement list that uses an ANDinstruction (A) to program two normally open contacts in series. Only whenthe signal state of both the normally open contacts is “1”, can the state ofoutput Q4.0 be set to “1” and the coil be energized.

Statement ListProgram

A I 1.0

A I 1.1

= Q 4.0

Relay Logic Diagram

I 1.0

I 1.1

Q 4.0

Figure 5-3 Using the And Instruction to Program Contacts in Series

Normally ClosedContact

Power Flow in aSeries Circuit



C79000-G7076-C565-01

Figure 5-4 shows a statement list that uses an Or instruction (O) to programeach of two normally open contacts connected in parallel to a coil.

Only when the signal state of one of the normally open contacts is “1”, canthe state of output Q4.0 be set to “1” and the coil be energized.

Relay Logic Diagram

O I 1.0

O I 1.1

= Q 4.0

PowerRail

I 1.0 I 1.1

Q 4.0

Statement ListProgram

Figure 5-4 Using the Or Instruction to Program Contacts in Parallel

The Exclusive Or (X) instruction in STL corresponds to a relay logic circuit,as in Figure 5-5, in which a normally closed contact and a normally opencontact are connected. Q4.0 is “1” when I1.0 and I1.0 have different values.

X I 1.0

X I 1.1

= Q 4.0

Statement ListProgram Relay Logic Diagram

PowerRail

ContactI 1.0

ContactI 1.1

CoilQ 4.0

Figure 5-5 Using the Exclusive Or instruction to Program Contacts in Parallel

Power Flow in aParallel Circuit

Exclusive Or



Similarly the following instructions can affect other actions:

O I 1.0

ON I 1.1

= Q 4.0

Power Rail

I 1.0NormallyOpen Contact

I 1.1NormallyClosed Contact

Q 4.0 Coil


Relay LogicDiagram


Relay LogicDiagram

A I 1.0

AN I 1.1

= Q 4.0



Q 4.0 Coil

Power Rail

X I 1.0

XN I 1.1

= Q 4.0

Power Rail



Q 4.0 Coil


Relay LogicDiagram

AN: Affects the seriesconnection of anormally closed contact..

ON: Affects the parallelconnection of anormally closedcontact.

XN: Affects theinterconnected seriesconnection of a normally closedcontact and a normally open contact.

AN, ON, XN



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5.3 Evaluating Conditions Using And, Or, and Exclusive Or

With the bit logic instructions you can check the bits of the status word CC 0,CC 1, BR, OV and OS. These can be influenced by the following instructions(Table 5-6).

Table 5-6 Instructions That Affect the CC, BR, OV, and OS Bits of the StatusWord

Type of Instruction Instruction Section inThis Manual

Integer Four-Function Math �I, �I, /I,�I, �D, �D,/D,�D, MOD

9.1

Integer Comparisons(Integer Math Instructions)

==I, <>I, <I, <=I, >I, >=I, ==D,<>D, <D, <=D,>D, >=D

11.2

Floating-Point Math �R, �R,�R , /R, SQRT, SQR,LN, EXP, SIN, COS, TAN,ASIN, ACOS, ATAN

10.1

Floating-Point Comparisons ==R, <>R, <R, <=R, >R, >=R 11.3

Conversion BTI, BTD, RND, RND�,RND�, TRUNC, NEGI, NEGD

12.1, 12.2,and 12.4

Shift and Rotate Functions SLW, SRW, SLD, SRD, SSI,SSD, RLD, RRD, RLDA, RRDA

14.1 and 14.2

Word Logic AW, OW, XOW, AD, OD, XOD 13.2

Nesting ) 5.4

Saving the RLO to BR Register SAVE 5.9

Logic Control JCB, JNB, SPS 16.1

Program Control BEB, BE, BEA, CC, UC 17.6

Transfer T STW 8.3

Description



The combination of bits CC 1 and CC 0 in the status word can easily bechecked using “replacement addresses” (for example, >0, ==0, <0, etc.).Table 5-7 shows the connection between different bit combinations andsimple checking. For example, you can check the combination CC 1 = 0 andCC 0 = 1 in an And instruction with A <0.

Table 5-7 Combination States of CC 0 and CC 1 and Relevant Check Option

If the following signal combination is in the statusword ...

... the check can becarried out using

Signal State of CC 1 Signal State of CC 0

1 0 >0

0 1 <0

0or1

1or0

<>0

1or0

0or0

>=0

0or0

1or0

<=0

0 0 ==0

1 1 UO

STL Explanation

L +10 //LOWER LIMIT

L MW30

<=I

L +100 //UPPER LIMIT

–I

U <=0

= Q 4.0

Load the integer 10 into accumulator 1 low as a lower limit.

Load the value in memory word MW30 into accumulator 1 low,transferring the integer value 10 to accumulator 2 low.

Is 10 less than or equal to the value in MW30? If yes, then setthe RLO to 1; otherwise reset the RLO to 0.

Load the integer 100 into accumulator 1 low as an upper limit,transferring the value from MW30 stored in accumulator 1 low toaccumulator 2 low.

Subtract 100 from the value in MW30. The result sets CC 1 andCC 0 with a bit combination that shows how the result comparesto 0 (see Table 5-7). The RLO is not changed.

According to the bit combination in CC 1 and CC 0, is thecondition <= 0 fulfilled? Yes produces a 1; no produces a 0(see Table 5-7). Combine this 1 or 0 with the RLO according tothe And truth table, Store the result in the RLO bit.

Write the value of the RLO to the signal state of output Q 4.0.The coil at output Q 4.0 is energized (has a signal state of 1)if the value in MW30 is greater than or equal to 10 and lessthan or equal to 100.

Relationship of aResult to 0



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The Boolean bit logic instructions can also enable your program to react ifthe result of a floating-point math operation is illegal because one of thenumbers is not a valid floating-point number (unordered, UO). Theinstruction checks the signal state of bits CC1 and CC0 of the status word(see Table 5-7).

Some of the instructions listed in Table 5-6 can set the binary result bit (BR)or the overflow bits (OV and OS) of the status word to 1. You can use the A,AN, O, ON, X, and XN bit logic instructions together with the followingmemory areas to enable your program to react to an overflow or to a binaryresult bit that is set to 1.

STL Explanation

L MW10

L MW20

+I

T MW30

A I 0.0

A OV

= Q 4.0

Load the integer in MW10 into accumulator 1 low.

Load the integer in MW20 into accumulator 1 low, transferringthe value from MW10 to accumulator 2.

Add the two integer values in the accumulators.

Transfer the result from accumulator 1 low to MW30.

Check the signal state at input I 0.0 for 1 or 0.

Check the OV bit of the status word for 1 or 0.

If the signal state of I 0.0 is 1 and there is a 1 in the OVbit of the status word (i.e., an overflow occurred during thelast math operation), set the signal state of output Q 4.0 to1; otherwise set it to 0.

STL Explanation

A BR

= Q 4.0

Check the BR bit of the status word for 1 or 0.

If there is a 1 in the BR bit of the status word, set thesignal state of output Q 4.0 to 1; otherwise set it to 0.

Overflow andBinary Result



The Boolean bit logic instructions evaluate conditions by using the addressesshown in Table 5-8.

Table 5-8 Addresses of Boolean Bit Logic Instructions: Bits of the Status Word

Memory Area or Reference to aLocation

Bit(s) of Status Word

>0, <0, <>0, >=0, <=0, ==0 7 and 6: condition codes 1 and 0 (memory area)

UO 7 and 6: condition codes 1 and 0 (memory area)

BR 8: binary result (location)

OV 5: overflow (location)

OS 4: overflow, stored (location)

Addressing theBits of the StatusWord



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5.4 Nesting Expressions and And before Or

You can use the And (A), Or (O), and Exclusive Or (X) instructions and theirnegated forms AN, ON, XN to perform Boolean logic operations on portionsof a logic string that are enclosed in parentheses (nesting expressions).Parentheses around a portion of a logic string indicate that your program willperform the operations inside the parentheses before performing the logicoperation indicated by the instruction that precedes the nesting expression.

You can also combine And and Or statements in a Boolean logic stringwithout using parentheses. By convention, the And statements are evaluatedfirst and the results are then combined according to the Or truth table.

The instruction that opens a nesting expression stores the RLO from thepreceding operation in the nesting stack. Later, the program will combine thisstored RLO with the result produced by the logic combinations performedinside the parentheses.

STL Description

A(O I 0.0

O M 10.0)

A(

O I 0.2

O M 10.3

)

A M 10.1

= Q 4.0

The statements between A( and ) make up a normal Or combina-tion. The result of the first check is stored in the RLO bit.

According to the Or truth table, the result of check is com-bined with the RLO formed by the previous statement. This com-bination forms a new result that replaces the value in the RLObit.

A( copies the value currently in the RLO bit, stores it in thenesting stack, and ends the previous logic string. Thereforethe next logic statement begins a new logic string, making a“first check.”

The statements between A( and ) make up a normal Or combina-tion. The result of the first check is stored in the RLO bit.

According to the Or truth table, the result of check is com-bined with the RLO formed by the previous statement. This com-bination forms a new result that replaces the value in the RLObit.

The ) statement combines the RLO that is stored in the nestingstack (see the A( instruction above) with the current RLO ac-cording to the And truth table. This statement uses the Andtruth table because the ) ends a nesting expression that beganwith A. This logic combination forms a new RLO.

This normal And statement combines the new RLO formed in the )instruction above with the result of its check according to theAnd truth table.

The Assign instruction (=, see Section 5.8) assigns the valueof the RLO to the output coil.

Description

Result of LogicOperation



The following statement list uses the principle of And before Or to program acircuit. By convention, the program evaluates the And statements first. Thenthe program combines the results of the And operation according to the Ortruth table. No parentheses are needed. The principle at work here is called“And before Or.”

STL Description

A I 0.0

A M 10.0

O

A I 0.2

A M 0.3

O M 10.1

= Q 4.0

The result of the first check is stored in the RLO bit.

According to the And truth table, the result of check is com-bined with the RLO formed by the previous statement. This com-bination forms a new result that replaces the value in the RLObit.

The statement O copies the value currently in the RLO bit,stores it in the Or bit and ends the previous logic string. Thestatement “O” secures the RLO as one of the two values that itwill use to carry out an Or operation, according to the princi-ple “And before Or”.

The result of the first check is stored in the RLO bit. In eachAnd operation which follows an Or operation the newly formedRLO is combined with the Or bit.

According to the And truth table, the result of check is com-bined with the RLO formed by the previous statement. This com-bination forms a new result that replaces the value in the RLObit. In each And operation the newly formed RLO is combinedwith the Or bit.

The first “O” operation fetches the stored RLO from the nestingstack and combines it with the current RLO. This operation re-sults to a new value which is stored in the RLO bit as the re-sult of an “And before Or” operation. (There is no special op-eration to end an “And before Or” operation. A special bit pro-cessor in the programmable controller finds the last A opera-tion in an “And before Or” operation. The operation that fol-lows the last A operation (e.g. =, S, R or O) ends the “Andbefore Or” operation automatically with the estimation of theRLO.)

The next “O” operation combines the result of the ”And beforeOr” operation with the check result of the second “O” opera-tion.

The Assign instruction (=, see Section 5.8) assigns the valueof the RLO to the output coil.

Output Q 4.0 is energized (its signal state is 1) if the result of either one orthe other pair of And operations is 1 or if the result of the normal Oroperation on M 10.1 is 1.

And before Or



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5.5 Instructions for Transitional Contacts: FP, FN

You can use the Edge Positive (FP) and Edge Negative (FN) instructions liketransition-sensing contacts in a relay circuit. These instructions detect andreact to transitions in the result of logic operation. A transition from 0 to 1 iscalled a “positive edge.” A transition from 1 to 0 is called a “negative edge”(see Figure 5-6).

RLO

0 Time

1Negative Edge

Positive Edge

Figure 5-6 Representation of Positive and Negative Edges

Figure 5-7 shows a statement list that enables your program to react to apositive edge transition. An explanation follows the figure.

10

10

3 75

A� I�1.0

FP M 1.0

= Q 4.0

Statement List

OB1 Scan Cycle No.:

I 1.0

Q 4.0

1 2 4 6 8 9

Signal State Diagram

10

M 1.0

Figure 5-7 Programming a Reaction to a Positive Edge Transition

If the programmable logic controller detects a positive edge at contact I 1.0,it energizes the coil at Q 4.0 for one OB1 scan cycle. The programmablelogic controller stores the result of the logic operation performed by the Ainstruction in edge memory bit M 1.0 and compares it to the RLO from theprevious scan cycle. (In the example in Figure 5-7, the RLO of the statement“A I 1.0” just happens to be the same as the signal state of input I 1.0. Thiswill not be the case for every program.) If the current RLO is 1 and the RLOfrom the previous scan cycle stored in memory bit M 1.0 is 0, then the FPstatement sets the RLO to 1. The FP statement detects a positive edge at thecontact (that is, the signal state of the RLO changed from 0 to 1). If there isno change in the RLO (current RLO and previous RLO stored in the edgememory bit are both equal to 0 or 1), then the FP statement resets the RLOto 0.

Description

Reacting to aPositive Edge



Table 5-9 Checking for Positive Edge Transition at Input I 1.0

OB1 ScanCycle No.

Signal State atInput inPrevious Cycle

Signal State atInput inCurrent Cycle

Did the signalstate changefrom 0 to 1?

Is the coil atQ 4.0energized?

1 0(default value)

0 No No

2 0 1 Yes Yes

3 1 1 No No

4 1 0 No No

5 0 0 No No

6 0 1 Yes Yes

7 1 0 No No

8 0 1 Yes Yes

9 1 1 No No

Table 5-9 applies specifically to the statement list program shown inFigure 5-7. In general, you should consider the transitions detected by FP andFN to be transitions reflected in the RLO, not in the signal states of contacts.For example, a logic string can form an RLO that is not directly related to thesignal state of a contact.

Figure 5-8 shows a statement list that enables your program to react to anegative edge transition. An explanation follows the figure.

I 1.0

2

A� I�1.0

FN M 1.0

= Q 4.0

Statement List

M 1.0

Q 4.0

3 75OB1 Scan Cycle No.: 1 4 6 8 9

Signal State Diagram

10

10

10

Figure 5-8 Programming a Reaction to a Negative Edge Transition

If the programmable logic controller detects a negative edge at contact I 1.0,it energizes the coil at Q 4.0 for one OB1 scan cycle. The programmable logic controller stores the result of the logic operationperformed by the A instruction in edge memory bit M 1.0 and compares it tothe RLO from the previous scan cycle (see Table 5-10). (In the example inFigure 5-8, the RLO of the statement “A I 1.0” just happens to be the sameas the signal state of input I 1.0. This will not be the case for every program.)If the current RLO is 0 and the RLO from the previous scan cycle stored inmemory bit M 1.0 is 1, then the FN statement sets the RLO to 1.

Reacting to aNegative Edge



C79000-G7076-C565-01

The FN statement detects a negative edge at the contact (that is, the signalstate of the RLO changed from 1 to 0). If there is no change in the RLO(current RLO and previous RLO stored in the edge memory bit are bothequal to 0 or 1), then the FN statement resets the RLO to 0.

Table 5-10 Checking for Negative Edge Transition at Input I 1.0

OB1 ScanCycle No.

Signal State atInput inPrevious Cycle

Signal State atInput inCurrent Cycle

Did the signalstate changefrom 1 to 0?

Is the coil atQ 4.0energized?

1 0(default value)

0 No No

2 0 1 No No

3 1 0 Yes Yes

4 0 0 No No

5 0 1 No No

6 1 1 No No

7 1 1 No No

8 1 0 Yes Yes

9 0 0 No No

Table 5-10 applies specifically to the statement list program shown inFigure 5-8. In general, you should consider the transitions detected by FP andFN to be transitions reflected in the RLO, not in the signal states of contacts.For example, a logic string can form an RLO that is not directly related to thesignal state of a contact.

The location that the FP or FN instruction addresses is a bit. The instructionaccesses the output through one of the following types of addresses:

� Address identifier (ID) and location within the memory area that isindicated by the address identifier (see Tables 5-11 and 5-12)

� Bit transferred as a parameter (see Table 5-13)

Addressed Bit



Table 5-11 Addresses of FP and FN: Direct and Indirect Addressing


ID1Direct Memory Indirect Area-Internal Register Indirect

I2

Q3

MDBXDIX

0.0 to65,535.7

[DBD][DID][LD][MD]


[AR2, P#byte.bit]0.0 to 8,191.7

1 See the Caution that follows this table.2 Because the operating system overwrites the process-image input table at the

beginning of every scan cycle, the RLO stored by an FP or FN instruction that usesan input bit as its address is corrupted. See the Caution that follows this table.

3 Using an output bit as the address of an FP or FN instruction is not recommended. Ifyou want to influence an output, use the S, R, or = instruction.

!Caution

Corruption of stored result of logic operation.

Can cause minor property damage.

If you use an FP or FN instruction in your program, the memory bit that isthe address of this instruction is used by FP or FN exclusively for its ownstorage purposes. Therefore you should not use any instruction that wouldchange this bit. Otherwise you will corrupt the stored RLO. This cautionapplies to all the memory areas indicated in the address identifiers listed inTable 5-11.

Table 5-12 Addresses of FP and FN: Area-Crossing Register Indirect Addressing

Address Identifier1 Address Range

I, Q, M, DBX, or DIX[AR1, P#byte.bit][AR2, P#byte.bit]

0.0 to 8,191.7

1 The memory area is encoded in AR1 or AR2, respectively (see Section 3.6).

Table 5-13 Addresses of FP and FN: Bit Transferred as Parameter


Symbolic name A bit transferred as parameter



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5.6 Output of Boolean Logic String

You can terminate a Boolean bit logic string by using one of the followingthree statement list instructions. Each of these instructions can influence a bitthat represents the end of that string.

� Set (S): if the RLO was set to 1 in the previous command, S sets thesignal state of the contact or coil that the instruction addresses to 1;

� Reset (R): if the RLO was set to 1 in the previous command, R resets thesignal state of the contact or coil that the instruction addresses to 0;

� Assign (=): independently of the state of the RLO, the value of the RLOis assigned to the location that the instruction addresses.

A logic string is terminated when the first-check bit (FC bit) is reset. Whenthe value in the FC bit is 0, this indicates that the next instruction in theprogram is the first instruction of a new logic string (see Section 2.2, FirstCheck). A Set (S), Reset (R), or Assign (=) instruction terminates a logicstring by resetting the first-check bit (FC bit) to 0. (Conditional jumpinstructions also reset the FC bit to 0, see Sections 16.3 through 16.5.)

Logic strings that are started with the instructions A(, AN(, O( etc. must beterminated with the ) instruction. Because these commands can also be usedin the middle of a logic string, they represent an interruption in the string.That means that a new logic string is started before the old one is terminated.To continue the old logic string in the correct order after closing thecommands to be carried out in brackets, the old FC bit (saved by opening thebrackets) is restored again. You can therefore imagine program sectionswithin brackets as a sort of intermediate calculation which, once completed,pick up the old thread again.

Description

Terminating aLogic String



5.7 Set and Reset Instructions: S and R

You can use the Set (S) instruction to set the signal state of an addressed bitto 1. (For information on the S instruction for setting an addressed counter toa specific value, see Section 7.2).

You can use the Reset (R) instruction to reset the signal state of an addressedbit to 0. R can also reset an addressed timer or counter to 0 (see Sections 6.3and 7.2). S and R terminate a logic string (see Section 5.6).

The S instruction sets the bit that it addresses to 1 if the result of logicoperation from the previous statement is 1 and the master control relay(MCR) is energized (that is, its signal state is 1). If the MCR is not energized(its signal state is 0), the addressed bit is not changed. The S instructionterminates a logic string.

Figure 5-9 illustrates how the S instruction holds the signal state of itsaddressed coil Q 4.0 at 1 until the R instruction changes the signal state to 0.The fact that the signal state of the addressed coil remains at 1 until anR instruction resets it to 0 indicates the static nature of the S instruction.

In the relay logic diagram, if the normally open contact at input I 1.0 isactivated (its signal state becomes 1), the contact closes. Power flows acrossthe contact at I 1.0 and across the normally closed contact beneath it,energizing the coil at output Q 4.0 (the signal state of Q 4.0 becomes 1).

When the coil is energized, the normally open contact at output Q 4.0 acrossfrom I 1.0 is closed. After that, regardless whether the contact at input I 1.0 isopened or closed, the coil at output Q�4.0 remains energized (at signalstate�1). The coil keeps itself energized.

Relay Logic Diagram

Power Rail


Q 4.0Coil

Q 4.0

Statement ListA I 1.0S Q 4.0A I 1.1R Q 4.0

I 1.0

I 1.1

Q 4.0

0

1

0

1

0

1

Signal State DiagramsNormallyClosed Contact

I 1.1

Figure 5-9 Setting and Resetting a Bit Statically

Description

Setting a Bit



C79000-G7076-C565-01

The R instruction resets the bit that it addresses to 0 if the result of logicoperation from the previous statement is 1 and the master control relay(MCR) is energized (that is, its signal state is 1). If the MCR is not energized(its signal state is 0), the addressed bit is not changed. The R instructionterminates a logic string.

Figure 5-9 illustrates how the R instruction holds the signal state of itsaddressed coil Q 4.0 at 0 regardless of a change in signal state at the contactthat triggered the reset (I 1.1). The fact that the signal state of the addressedcoil remains at 0 until an S instruction resets it to 1 indicates the static natureof the R instruction.

In the relay logic diagram, the coil at output Q 4.0 that was energized by theS instruction is de-energized (its signal state becomes 0) by closing thenormally open contact at input I 1.1. Closing contact I 1.1 allows power toflow to the coil beneath it. This coil opens the normally closed contact abovethe coil at Q 4.0, interrupting the flow of power to the coil. Closing contactI 1.1 triggers the R instruction.

The address that the S instruction references can be a bit. The address thatthe R instruction references can be a bit, a timer number, or a counternumber. The addresses can be specified as follows:

� Address identifier (ID) and location within the memory area that isindicated by the address identifier (see Tables 5-14 through 5-16)

� Bit, timer, or counter transferred as a parameter (see Table 5-17)

Table 5-14 Addresses of S and R: Direct and Indirect Addressing


ID Direct Memory Indirect Area-Internal Register Indirect

IQ

0.0 to65,535.7

[DBD][DID][LD][MD]


[AR2, P#byte.bit]0.0 to 8,191.7

M 0.0 to 255.7

[DBD][DID][LD][MD]


[AR2, P#byte.bit]0.0 to 8,191.7

DBXDIX

L

0.0 to65,535.7

[DBD][DID][LD][MD]


[AR2, P#byte.bit]0.0 to 8,191.7

Resetting a Bit

ReferencedAddress



Table 5-15 Addresses of S and R: Area-Crossing Register Indirect Addressing

Address Identifier1 Maximum Address Range

I, Q, M, D, DBX, DIX, or L[AR1, P#byte.bit][AR2, P#byte.bit]

0.0 to 8,191.7

1 The memory area is encoded in pointer bits 24, 25, and 26 (see Section 3.6).

Table 5-16 Addresses of R: Timers and Counters

Address IdentifierMaximum Address Range According to Addressing Type

Address Ident f erDirect Memory Indirect

T1

C0 to 65,535

[DW][DXW][LW][MW]

0 to 65,534

1 The S instruction that sets an addressed bit to 1 does not apply to timers or counters.An S instruction used with a counter sets that counter to a specific value. Timers arestarted with instructions for specific types of timers (see Sections 6.2, 6.3 and 7.2).

Table 5-17 Address of S and R: Bit, Timer, or Counter Transferred as Parameter


Symbolic name A bit, timer,1 or counter transferred as parameter

1 The S instruction does not apply to timers. Timers are started with instructions forspecific types of timers (see Sections 6.2 and 6.3).



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5.8 Assign Instruction (=)

Each Boolean logic operation produces a result known as the “result of logicoperation” (RLO). This RLO is either 1 or 0. In reference to contacts andcoils, a 1 indicates power flow; a 0 indicates no power flow.

You can use the Assign (=) instruction to copy the RLO from the previousstatement in a logic string and assign the RLO as the signal state of the coilthat the = instruction addresses. The = instruction terminates a logic string(see Section 5.6).

The value that the = instruction assigns to the coil that it addresses can be 1or 0, depending on the RLO of the statement that preceded the = statement.Unlike the instructions S and R, the nature of the = instruction is dynamic. Itassigns the RLO as the signal state of the coil that the = instruction addresses.Figure 5-10 shows how this value changes as the RLO of the statement“A I 1.0” changes.

In Figure 5-10, the = instruction enables the input signal at the contact I 1.0to energize or de-energize the coil represented by output Q 4.0 (that is, = setsor resets the bit represented by Q 4.0 by assigning the RLO of the previousstatement).

Relay Logic Diagram

PowerRail

Q 4.0Coil

Statement List

A I 1.0= Q 4.0

I 1.0

Q 4.0

0

1

0

1

Signal State Diagrams

I 1.1

Figure 5-10 Setting and Resetting a Bit Dynamically

DescriptionDescription

Setting orResetting a Bit



The address that the = instruction addresses can be a bit. The instructionaccesses the coil through one of the following addresses:

� Address identifier (ID) and location within the memory area that isindicated by the address identifier (see Tables 5-18 and 5-19)

� Bit transferred as a parameter (see Table 5-20)

Table 5-18 Addresses of =: Direct and Indirect Addressing



IQ

0.0 to65,535.7

[DBD][DID][LD][MD]


[AR2, P#byte.bit]0.0 to 8,191.7

M0.0 to65,535

[DBD][DID][LD][MD]


[AR2, P#byte.bit]0.0 to 8,191.7

DBXDIX

L

0.0 to65,535.7

[DBD][DID][LD][MD]


[AR2, P#byte.bit]0.0 to 8,191.7

Table 5-19 Addresses of =: Area-Crossing Register Indirect Addressing

Address Identifier1 Maximum Range of Address Parameters

I, Q, M, DBX, DIX, or L[AR1, P#byte.bit][AR2, P#byte.bit]

0.0 to 8,191.7

1 The memory area is encoded in the uppermost 8 bits of AR1 or AR2, respectively.

Table 5-20 Addresses of =: Bit Transferred as Parameter


Symbolic name A bit transferred as parameter

Addresses



C79000-G7076-C565-01

5.9 Negating, Setting, Clearing, and Saving the RLO

You can use one of the following instructions to change the result of logicoperation (RLO) stored in the RLO bit in the status word of theprogrammable logic controller (see Section 5.8):

Mnemonic Instruction Meaning

NOT Negate RLO Negating (inverting) the current RLO

SET Set RLO Setting the current RLO to 1

CLR Clear RLO Resetting the current RLO to 0

SAVE Save RLO in BR RegisterSaving the current RLO to the bit of thestatus word

Because these instructions affect the RLO directly, they have no addresses.

You can use the Negate RLO (NOT) instruction in your program to negate(invert) the current RLO. If the current RLO is 0, NOT changes it to 1; if thecurrent RLO is 1, NOT changes it to 0, provided the OR bit is not set. Thisinstruction is useful for shortening your program, for example by changingfrom positive logic to negative logic (see the timer example in Section B.3).

You can use the Set RLO (SET) instruction in your program if you need toset the RLO bit to 1 unconditionally. Figure 5-11 shows how the SETinstruction works in a program.

You can use the Clear RLO (CLR) instruction in your program if you need toreset the RLO bit to 0 unconditionally. CLR also resets the FC, OR, and STAbits to 0. As a result, the logic string is ended. Figure 5-11 shows how theCLR instruction works in a program.

You can use the Save RLO in BR Register (SAVE) instruction in yourprogram if you need to save the RLO for future use or if you want toinfluence the BR bit of the status word in the programmable logic controller,for example when you are programming function blocks (FBs) and functions(FCs) for ladder logic programming boxes.

Instruction Influence on the Bits of the Status Word

BR A1 A0 OV OS OR STA RLO FC

NOT – 1 x –

SET 0 1 1 0

CLR 0 0 0 0

SAVE x

Description

Negating the RLO

Setting the RLOto 1

Clearing the RLOto 0

Saving the RLO



The program shown in Figure 5-11 illustrates an application of the SET andCLR instructions that set and reset a bit unconditionally.

Statement List Signal State Result of Logic Operation (RLO)

SET

= M 10.0

= M 15.1

= M 16.0

CLR

= M 10.1

= M 10.2

1

0

1

1

1

0

0

Figure 5-11 Setting and Resetting a Bit Unconditionally Using SET and CLR

You could use the statements in the program shown in Figure 5-11 in astart-up organization block (OB). After you power up your programmablelogic controller, it processes the start-up OB with all the instructions that itcontains. After the programmable logic controller has executed all theinstructions, the following memory bits have a specific signal state regardlessof any conditions:

� The signal state of memory bits M 10.0, M 15.1, and M 16.0 is 1.

� The signal state of memory bits M 10.1 and M 10.2 is 0.

Applying SET andCLR



C79000-G7076-C565-01



Timer Instructions


6.1 Overview 6-2

6.2 Location of a Timer in Memory and Components of a Timer 6-3

6.3 Loading, Starting, Resetting, and Enabling a Timer 6-5

6.4 Timer Examples 6-7

6.5 Address Locations and Ranges for Timer Instructions 6-17

6.6 Choosing the Right Timer 6-18

Chapter Overview

6


C79000-G7076-C565-01

6.1 Overview

A timer is a function element of the STEP 7 programming language thatimplements and monitors timed sequences. The timer instructions enableyour program to perform the following functions:

� Provide waiting times. For example, after an injection molding procedure,the mold must remain closed for two seconds. Your program ensures thattwo seconds elapse before the part is released from the mold.

� Provide monitoring times. For example, the program monitors the speedof a motor for 30 seconds after you press the start button.

� Generate pulses. For example, the program provides pulses that cause alight to flash.

� Measure time. For example, the program can determine how long it takesfor a container to be filled.

The statement list representation of the STEP 7 programming languageprovides the following timer instructions:

� Start timer as one of the following types:

– Pulse (SP)

– Extended pulse (SE)

– On-delay (SD)

– Retentive on-delay (SS)

– Off-delay (SF)

� Reset timer (R)

� Enable a timer to start (FR)

� Load timer in one of the following formats:

– Binary (L)

– Binary coded decimal (LC)

� Check the signal state of a timer and combine the result in a Booleanlogic operation (A, AN, O, ON, X, XN) (see Chapter 11).

Figure 6-1 summarizes the instructions that use a timer word as address.

Enable timer (FR) Reset timer (R)

Load timer (L, LC)Check signal state of timer (A, O, X, AN, ON, XN)

Start timer (SP, SE, SD, SS, SF)

Timer word

Figure 6-1 Instructions That Can Use a Timer Word as an Address

Definition

AvailableInstructions

Timer Instructions


6.2 Location of a Timer in Memory and Components of a Timer

Timers have an area reserved for them in the memory of your CPU. Thismemory area reserves one 16-bit word for each timer address. The statementlist instruction set supports 256 timers. To find out how many timer words areavailable in your CPU, please refer to the CPU technical data.

The following functions have access to the timer memory area:

� Timer instructions

� Updating of timer words via clock timing. This function decrements agiven time value by one unit at the interval designated by the time baseuntil the time value is equal to zero.

Bits 0 through 9 of the timer word contain the time value in binary code. Thetime value specifies a number of units. Time updating decrements the timevalue by one unit at an interval designated by the time base. Decrementingcontinues until the time value is equal to zero. You can load a time value intothe low word of accumulator 1 in binary, hexadecimal, or binary codeddecimal (BCD) format. The time range is from 0 to 9,990 seconds.

You can pre-load a time value using either of the following syntax formats:

� L W#16#wxyz

– Where w = the time base (that is, the time interval or resolution)

– Where xyz = the time value in binary coded decimal format

� L S5T# aH_bbM_ccS_ddMS

– Where a = hours, bb = minutes, cc = seconds, and dd = milliseconds

– The time base is selected automatically and the value is rounded to thenext lower number with that time base.

The maximum time value that you can enter is 9,990 seconds, or2H_46M_30S.

Area in Memory

Time Value

Timer Instructions


C79000-G7076-C565-01

Bits 12 and 13 of the timer word contain the time base in binary code. Thetime base defines the interval at which the time value is decremented by oneunit. The smallest time base is 10 ms; the largest is 10 s.

Table 6-1 Time Base and Its Binary Code

Time Base Binary Code for the Time Base

10 ms 00

100 ms 01

1 s 10

10 s 11

Because time values are stored with only one time interval, values that arenot exact multiples of a time interval are truncated. Values that have toomuch resolution for the desired range are rounded down to achieve thedesired range but not the desired resolution. Table 6-2 shows the possibleresolutions and their corresponding ranges.

Table 6-2 Time Base Resolutions and Ranges

Resolution Range

0.01 second 10MS to 9S_990MS

0.1 second 100MS to 1M_39S_900MS

1 second 1S to 16M_39S

10 seconds 10S to 2HR_46M_30S

When a timer is started, the contents of accumulator 1 are used as the timevalue. Bits 0 through 11 of accumulator 1 low hold the time value in binarycoded decimal format (BCD format: each set of four bits contains the binarycode for one decimal value). Bits 12 and 13 hold the time base in binary code(see Table 6-1). Figure 6-2 shows the contents of accumulator 1 low loadedwith timer value 127 and a time base of 1 second. (See also Section 8.5.)

Time base1 second

Irrelevant: These bits are ignored when the timer is started.

Time value in BCD (0 to 999)

15... ...8 7... ...0

1 2 7

x x 1 0 0 0 0 1 0 0 1 0 0 1 1 1

Figure 6-2 Contents of Accumulator 1 Low: Timer Value 127, Time Base 1 Second

Time Base

Bit Configurationin Accumulator 1

Timer Instructions


6.3 Loading, Starting, Resetting, and Enabling a Timer

To start a timer in your statement list program, include three statements totrigger the following operations:

� Check a signal state for 0 or 1 (for example, A I 2.1)

� Load a time value and an accompanying time base (for example, L IW0)

� Start a timer as one of the following types:

– Pulse timer (SP, for example, SP T 1)

– Extended pulse timer (SE)

– On-delay timer (SD)

– Retentive on-delay (SS)

– Off-delay (SF)

In your statement list program, a change in the result of logic operation(RLO) prior to a Start instruction statement starts a timer. A change in theRLO from 1 to 0 starts an off–delay timer (SF); a change from 0 to 1 startsany of the other timers. The programmed time and the Start timer statementsmust follow the logic operation directly that provides the condition forstarting the timer. Section 6.4 provides examples of the five types of Startinstructions for timers.

Loading a time value as an integer or as a BCD number is described inSections 8.4 and 8.5.

Because a timer runs down to zero from a set time, you must provide thetimer with a starting time. When you start a timer in your program, the CPUlooks in accumulator 1 for the starting time. The time range is from 0 to9,990 seconds.

Figure 6-3 provides an example for starting a pulse timer. A change in signalstate from 0 to 1 at input I 2.1 starts the timer. Figure 6-3 refers to thefollowing STL program:

STL Explanation

A I 2.1L S5T#00H02M23S00MSSP T 1

Check the signal state of input I 2.1.Load the starting time into accumulator 1.Start timer T1 as a pulse timer.

I 2.1

Check I 2.1 for transitionfrom 0 to 1.

Signal state diagram:

0

0

1

1

Timer is started with the starting time given in accumulator 1.

Figure 6-3 Starting a Pulse Timer

Description

Loading

The Starting Time

Example ofStarting a Timer

Timer Instructions


C79000-G7076-C565-01

You reset a timer by using the Reset (R) instruction. The CPU resets a timerwhen the result of logic operation is 1 immediately before the R instructionin your program. As long as the RLO that comes before an R instructionstatement is 1, an A, O, or X instruction that checks the signal state of a timerproduces a result of 0 and an AN, ON, or XN instruction that checks thesignal state of a timer produces a result of 1.

Resetting a timer stops the current timing function and resets the time valueto 0.

A change in the result of logic operation from 0 to 1 in front of an Enableinstruction (FR) enables a timer. This change in signal state is alwaysnecessary to enable a timer. The CPU executes the FR instruction only on apositive signal edge.

Timer enable is not required to start a timer, nor is it required for normaltimer operation. An enable is used only to retrigger a running timer, that is, torestart the timer. This restarting is possible only when the start operationcontinues to be processed with an RLO of 1.

Resetting a Timer

Enabling a Timerfor Restart

Timer Instructions


6.4 Timer Examples

Statement list programming offers five types of timers to meet yourautomation needs. An example for each type is provided below.

Figures 6-4 and 6-5 provide examples of a pulse timer. The numbers insquares in the figures are keyed to explanations that follow Figure 6-4. Thefigures refer to the following STL program:

STL Explanation

A I 2.0FR T 1A I 2.1L S5T#0H2M23S0MSSP T 1A I 2.2R T 1A T 1= Q 4.0L T 1T MW10LC T 1T MW12

Enable timer T 1.

Start timer T 1 as a pulse timer.

Reset timer T 1.

Check the signal state of timer T 1.

Load timer T 1.

I 2.0

I 2.1

I 2.2

Q 4.0

RLO at Enable input

RLO at Start input

RLO at Reset input

Timer response

Check signal stateof timer output.

Load timer: L, LC

t

� ��

�

�

�

�

t = programmed start time

Figure 6-4 Pulse Timer Example, Part 1

Introduction

Pulse Timer: SP

Timer Instructions


C79000-G7076-C565-01

The following list describes the elements of Figures 6-4 and 6-5:

� A change in the RLO from 0 to 1 at the Start input starts the timer.The programmed time t then elapses.

� When an RLO of 0 is applied to the Start input, the timer is reset.

� Checking the signal state of output Q 4.0 of the timer results in asignal state of 1 for the entire duration of the timer operation.

� If an RLO of 1 is applied to the Reset input, the timer is reset. Aslong as a signal state of 1 remains at the Start input, a change in theRLO from 1 to 0 at the Reset input has no influence on the timer.

� A change in the RLO from 0 to 1 at the Start input with the Resetsignal applied causes the timer to start momentarily but to resetimmediately because of the Reset statement that follows directly inthe program (shown as a pulse line in the timing diagram inFigure 6-4). No checking result is obtained for this pulse, providedthat the sequence of writing the statements as they appear above isobserved.

� A change in the RLO from 0 to 1 at the Enable input while the timeris running restarts the timer. The time that is programmed is used asthe current time for the restart. A change in the RLO from 1 to 0 atthe Enable input has no effect.

� If the RLO changes from 0 to 1 at the Enable input while the timeris not running and there is still an RLO of 1 at the Start input, thetimer will also be started as a pulse with the time programmed.

� A change in the RLO from 0 to 1 at the Enable input while there isstill an RLO of 0 at the Start input has no effect on the timer.

I 2.0

I 2.1

I 2.2

Q 4.0

RLO at Enable input

RLO at Start input

RLO at Reset input

Timer response

Load timer: L, LC

t

�


t

��


Figure 6-5 Pulse Timer Example, Part 2

Timer Instructions


Figures 6-6 and 6-7 provide examples of an extended pulse timer. Thenumbers in squares in the figures are keyed to explanations that followFigure 6-6. The figures refer to the following STL program:

STL Explanation

A I 2.0FR T 1A I 2.1L S5T#0H2M23S0MSSE T 1A I 2.2R T 1A T 1= Q 4.0L T 1T MW10LC T 1T MW12

Enable timer T 1.

Start timer T 1 as an extended pulse timer.

Reset timer T 1.

Check the signal state of timer T 1.Load timer T 1 (binary coded).

Load timer T 1 (BCD coded).

I 2.0

I 2.1

I 2.2

Q 4.0

RLO atEnable input

RLO atStart input

RLO atReset input

Timerresponse

Load timer: L, LC

t

� ��

�

�

�


�

�

Check signal stateof timer output

Figure 6-6 Extended Pulse Timer Example, Part 1

Extended PulseTimer: SE

Timer Instructions


C79000-G7076-C565-01


� A change in the RLO from 0 to 1 at the Start input starts the timer.The programmed time t then elapses, regardless of a change in theRLO from 1 to 0 at the Start input.

� If the RLO changes from 0 to 1 before the time has elapsed, thetimer is retriggered with the time that was programmed originally.

� Checking the signal state of the timer output produces a result of 1for the entire duration of the timer operation.

� If an RLO of 1 is applied to the Reset input, the timer is reset. Aslong as a signal state of 1 remains at the Start input, a change in theRLO from 1 to 0 at the Reset input has no effect on the timer.



� If the RLO changes from 0 to 1 at the Enable input while the timeris not running and there is still an RLO of 1 at the Start input, thetimer will also be started as a pulse with the time programmed.

� A change in the RLO from 0 to 1 at the Enable input while there isstill an RLO of 0 at the Start input has no effect on the timer.

I 2.0

I 2.1

I 2.2

Q 4.0

RLO atEnable input

RLO atStart input

RLO atReset input

Timerresponse

Load timer: L, LC

t

�


t

��

t

�


Figure 6-7 Extended Pulse Timer Example, Part 2

Timer Instructions


Figures 6-8 and 6-9 provide examples of an on-delay timer. The numbers insquares in the figures are keyed to explanations that follow Figure 6-8. Thefigures refer to the following STL program:

STL Explanation

A I 2.0FR T 1A I 2.1L S5T#0H2M23S0MSSD T 1A I 2.2R T 1A T 1= Q 4.0L T 1T MW10LC T 1T MW12

Enable timer T 1.

Start timer T 1 as an on-delay timer.

Reset timer T 1.


Load timer T 1.

I 2.0

I 2.1

I 2.2

RLO atEnable input

RLO atStart input

RLO atReset input

Timerresponse

Load Timer: L, LC

t

�

�

�

�

�


t

�

�

�

Check signal stateof timer output Q 4.0

Figure 6-8 On-Delay Timer Example, Part 1

On-Delay Timer:SD

Timer Instructions


C79000-G7076-C565-01


� A change in the RLO from 0 to 1 at the Start input starts the timer.The programmed time t then elapses.

� When an RLO of 0 is applied to the Start input, the timer is reset.

� Checking the signal state of output Q 4.0 of the timer results in asignal state of 1 when the time has elapsed and the Start input is 1.

� If an RLO of 1 is applied to the Reset input, the timer is reset. Aslong as a signal state of 1 remains at the Start input, a change in theRLO from 1 to 0 at the Reset input has no effect on the timer.



� If the RLO changes from 0 to 1 at the Enable input followingnormal operation of the timer, the timer is not affected

� A change in the RLO from 0 to 1 at the Enable input after the timerwas reset and while there is still an RLO of 1 at the Start input startsthe timer. The time that is programmed is used as the current time.

I 2.0

I 2.1

I 2.2

Q 4.0

RLO atEnable input

RLO atStart input

RLO atReset input

Timerresponse

Load timer: L, LC

t

�

�


��


Figure 6-9 On-Delay Timer Example, Part 2

Timer Instructions


Figures 6-10 and 6-11 provide examples of a retentive on-delay timer. Thenumbers in squares in the figures are keyed to explanations that followFigure 6-10. The figures refer to the following STL program:

STL Explanation

A I 2.0FR T 1A I 2.1L S5T#0H2M23S0MSSS T 1A I 2.2R T 1A T 1= Q 4.0L T 1T MW10LC T 1T MW12

Enable timer T 1.

Start timer T 1 as a retentive on-delay timer.

Reset timer T 1.


Load timer T 1.

I 2.0

I 2.1

I 2.2

RLO atEnable input

RLO atStart input

RLO atReset input

Timerresponse

Load timer: L, LC

t


�

�

� �

�

�

�

Check signal stateof timer output Q 4.0

Figure 6-10 Retentive On-Delay Timer Example, Part 1


� A change in the RLO from 0 to 1 at the Start input starts the timer.The programmed time t then elapses regardless of a change in theRLO from 1 to 0 at the Start input.

� Checking the signal state of the timer output results in 1 if the timehas elapsed.

Retentive On-DelayTimer: SS

Timer Instructions


C79000-G7076-C565-01

� The result of checking the signal state of output Q 4.0 changes to 0only when the RLO at the Reset input is 1.

� If an RLO of 1 is applied to the Reset input, the timer is reset. Aslong as a signal state of 1 remains at the Start input, a change in theRLO from 1 to 0 at the Reset input has no influence on the timer.


� When the RLO at the Enable input changes from 0 to 1 while thetimer is running and the RLO at the Start input of the timer is 1, thetimer is restarted. The time that is programmed is used as thecurrent time for the restart. A change in the RLO from 1 to 0 at theEnable input has no effect on the timer.

� The timer is not affected when the RLO at the Enable input changesfrom 0 to 1 following normal operation of the timer.

� When the RLO at the Enable input changes from 0 to 1 while thetimer is running and the RLO at the Start input of the timer is 0, thetimer is not affected.

� If the RLO at the Enable input changes from 0 to 1 when the timeris reset and the RLO at the Start input is still 1, the timer isrestarted. The time that is programmed is used as the current timefor the restart.

I 2.0

I 2.1

I 2.2

Q 4.0

RLO atEnable input

RLO atStart input

RLO atReset input

Timerresponse

Load timer: L, LC


ttt

�

� � � �

� �


Figure 6-11 Retentive On-Delay Timer Example, Part 2

Timer Instructions


Figures 6-12 and 6-13 provide examples of an off-delay timer. The numbersin squares in the figures are keyed to explanations that follow Figure 6-12.The figures refer to the following STL program:

STL Explanation

A I 2.0FR T 1A I 2.1L S5T#0H2M23S0MSSF T 1A I 2.2R T 1A T 1= Q 4.0L T 1T MW10LC T 1T MW12

Enable timer T 1.

Start timer T 1 as an off-delay timer.

Reset timer T 1.Check the signal state of timer T 1.

Load timer T 1.

I 2.0

I 2.1

I 2.2

Q 4.0

RLO atEnable input

RLO atStart input

RLO atReset input

Timerresponse

Load timer: L, LC


t t

� � � � �

�

�

� �

� �

�


Figure 6-12 Off-Delay Timer Example, Part 1

Off-Delay Timer:SF

Timer Instructions


C79000-G7076-C565-01


� A change in the RLO from 0 to 1 at the Start input causes a changefrom 0 to 1 at output Q 4.0 of the timer. A change in the RLO from1 to 0 at the Start input starts the timer. The programmed time t thenelapses.

� If an RLO of 1 reappears at the Start input, the timer is reset.

� Checking the signal state of output Q 4.0 of the timer results in asignal state of 1 if the RLO at the Start input is 1 and if the time hasnot yet elapsed.

� If an RLO of 1 is applied to the Reset input, the timer is reset.Checking the signal state of the timer then results in 0. A change inRLO from 1 to 0 at the Reset input has no influence on the timer.

� A 1 applied to the Reset input while the timer is not running has noeffect on the timer.

� A change in the RLO from 1 to 0 at the Start input while the Resetsignal is applied causes the timer to start momentarily but to resetimmediately because of the Reset statement that follows directly inthe program (shown as a pulse line in the timing diagram inFigure 6-12). Checking the signal state of the timer then results in 0.

� The timer is not affected if the RLO at the Enable input changesfrom 0 to 1 while the timer is not running. A change in the RLOfrom 1 to 0 also has no effect on the timer.

� If the RLO at the Enable input changes from 0 to 1 while the timeris running, the timer is restarted. The time that is programmed isused as the current time for the restart.

I 2.0

I 2.1

I 2.2

Q 4.0

RLO at Enable input

RLO at Start input

RLO at Reset input

Timer response

Load timer: L, LC

t

�


��


Figure 6-13 Off-Delay Timer Example, Part 2

Timer Instructions


6.5 Address Locations and Ranges for Timer Instructions

Tables 6-3 and 6-4 show the address types, address locations, and addressranges for the timer instructions.

Table 6-3 Address Locations, Ranges, and Types for Timer Instructions

Address Range According to Addressing Type

Direct Memory Indirect

0 to 255

[DBW][DIW][LW][MW]

0 to 65,534

Table 6-4 Timer Address transferred as Parameter


Symbolicname

Time transferred as parameter

Timer Instructions


C79000-G7076-C565-01

6.6 Choosing the Right Timer

Figure 6-14 provides an overview of the five types of timers described inSection 6.4. This overview is intended to help you choose the right timer foryour timing job.

I 2.1

Q 4.0

SE:

SD:

SS:

SF:

Input signal

Output signal(Pulse timer) t

SP:

t

t

t

t

The maximum time that the output signal remains at 1 is thesame as the programmed time value t. The output signalstays at 1 for a shorter period if the input signal changes to 0.

The output signal remains at 1 for the programmed length oftime, regardless of how long the input signal stays at 1.

The output signal changes from 0 to 1 only when theprogrammed time has elapsed and the input signal is still 1.

The output signal changes from 0 to 1 only when theprogrammed time has elapsed, regardless of how long theinput signal stays at 1.

The output signal changes from 0 to 1 when the input signalchanges from 0 to 1. The output signal remains at 1 for theprogrammed length of time. The time is started when the inputsignal changes from 1 to 0.

Q 4.0Output signal(Extended pulsetimer)

Q 4.0Output signal(On-delay timer)

Q 4.0Output signal(Retentiveon-delay timer)

Q 4.0Output signal(Off-delay timer)

Figure 6-14 Choosing the Right Timer

Timer Instructions


Counter Instructions


7.1 Overview 7-2

7.2 Setting, Resetting, and Enabling a Counter 7-3

7.3 Couting Up and Counting Down 7-5

7.4 Loading a Count Value as Integer 7-6

7.5 Loading a Count Value in Binary Coded Decimal Format 7-7

7.6 Counter Example 7-8

7.7 Address Locations and Ranges for Counter Instructions 7-10

Chapter Overview

7


C79000-G7076-C565-01

7.1 Overview

A counter is a function element of the STEP 7 programming language thatcounts.

Counters have an area reserved for them in the memory of your CPU. Thismemory area reserves one 16-bit word for each counter. The statement listinstruction set supports 256 counters. To find out how many counters areavailable in your CPU, please refer to the CPU technical data.

Counter instructions are the only functions with access to the memory areareserved for the counter.

The statement list representation of the STEP 7 programming languageprovides the following counter instructions:

� Set (S)

� Reset (R)

� Count up (CU)

� Count down (CD)

� Enable counter (FR)

� Load counter in one of the following formats:

– Binary (L)

– Binary coded decimal (LC)

� Check the signal state of a counter and combine the result in a Booleanlogic operation (A, AN, O, ON, X, XN).A signal state check with an A, O or X instruction will have the result“1”, when the value of a counter is greater than “0”. A signal state check with an A, O or X instruction will have the result“0”, when the value of the counter is equal to “0”.

Figure 7-1 summarizes the instructions that use a counter word as theiraddress.

Enable a counter (FR)Count Down (CD)

Load a count value (L, LC)

Counter word

Set a counter (S)Count Up (CU) Reset a counter (R)

Check the signal state of a counter(A, AN, O, ON, X, XN)

Figure 7-1 Instructions That Can Use a Counter Word as an Address

Definition




7.2 Setting, Resetting, and Enabling a Counter

To set a counter in your statement list program, include three statements totrigger the following operations:

� Check a signal state for 0 or 1 (for example, A I 2.3)

� Load a count value (for example, L C# 3) into the low word ofaccumulator 1

� Set a counter with the count value you loaded (for example, S C 1). Thisoperation moves the count value from accumulator 1 to the counter word.

In your statement list program, a change in the result of logic operation(RLO) from 0 to 1 prior to a Set (S) instruction statement sets a counter tothe programmed count value. The programmed count value and the Setstatements must follow the logic operation directly that provides thecondition for setting the counter.

You set a counter to a specific value by loading that value into the low wordof accumulator 1 and, immediately thereafter, setting that counter. When youset a counter in your program, the CPU looks in accumulator 1 for the countvalue. Then the CPU transfers the count value from the accumulator to thecounter word that you specified in your set statement (for example, S C 1).The range of the count value is 0 to 999.

Figure 7-2 provides an example for setting a counter. A change in signal statefrom 0 to 1 at input I 2.3 sets the counter. The figure refers to the followingprogram:

STL Explanation

A I 2.3L C# 3

S C 1

Check signal state of input I 2.3.If the signal state is 1, load count value 3 intoaccumulator 1.Set counter C 1 to a count value of 3. This operationmoves the count value of 3 from the accumulator intocounter word 1.

I 2.3

Check I 2.3 for transitionfrom 0 to 1.

Counter is set to the value given in the load instruction.

Signal state diagram:

0

0

1

1

Figure 7-2 Setting a Counter

Description

The Starting Count

Example of Settinga Counter



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You reset a counter by using the Reset (R) instruction. The CPU resets acounter when the result of logic operation is 1 immediately before the Rinstruction in your program. As long as the RLO that comes before an Rinstruction statement is 1, an A, O, or X instruction that checks the signalstate of a counter produces a result of 0 and an AN, ON, or XN instructionthat checks the signal state of a counter produces a result of 1.

When your program resets a counter, it clears the counter, that is, it resets itto a value of 0.

If a counter is to be reset by a static signal at the Reset (R) and independentlyof the RLO of the other counter instructions, you need to write the Resetstatement immediately after the Set, Count Up, or Count Down statement(see Section 7.3) and before the signal check or load operation.

Programming for counters should adhere to the following sequence (see alsothe programming example in Section 7.6):

1. Count up

2. Count down

3. Set counter

4. Reset counter

5. Check signal state of counter

6. Load count value (Read count value)

A change in the result of logic operation of the Enable instruction (FR) from0 to 1 enables a counter. The CPU executes the FR instruction only on apositive signal edge.

A counter enable is not required to set a counter, nor is it required for normalcounting. An enable is only used to set a counter, or to count up or down, if apositive edge (transition from 0 to 1) in front of the corresponding countstatement is needed, and if the RLO bit in front of the correspondingstatement has a signal state of 1.

Resetting aCounter

Enabling aCounter for Restart



7.3 Couting Up and Counting Down

In your statement list program, a change in the result of logic operation from0 to 1 prior to a Count Up (CU) instruction statement increments the counter.Each time a positive edge change occurs in the RLO directly before a CountUp instruction, the count is incremented by one unit.

When the count reaches its upper limit of 999, incrementing stops and anyfurther change in the signal state at the Count Up input have no effect. Noprovisions are made for overflow (OV).

STL Explanation

A I 0.1CU C1

If there is a positive edge change at input I 0.1,counter C 1 is incremented by 1.

In your statement list program, a change in the result of logic operation from0 to 1 prior to a Count Down (CD) instruction statement decrements thecounter. Each time a positive edge change occurs in the RLO directly beforea Count Down instruction, the count is decremented by one unit.

When the count reaches its lower limit of 0, decrementing stops and anyfurther change in the signal state at the Count Down input have no effect.The counter does not count with negative values.

STL Explanation

A I 0.2CD C1

If there is a positive edge change at input I 0.2,counter C 1 is decremented by 1.

Description ofCounting Up

Description ofCounting Down



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7.4 Loading a Count Value as Integer

A count value is stored in a counter word in binary code. You can use thefollowing instruction to read the binary count value out of a counter wordand load it into the low word of accumulator 1:

L <counter word>

This type of loading is referred to as loading a counter value directly.

STL Explanation

L C 1 Load accumulator 1 low directly with the count value ofcounter C 1 in binary format.

0 0 0 0 0 0

9 0

X X X X X X

Count Value

Counter wordfor C 1

Accumulator 1low

1015

15 10 0

Figure 7-3 Loading a Count Value into Accumulator 1 Using the L Instruction

You can use the value contained in the accumulator as a result of the Loperation for further processing. You cannot transfer a value from theaccumulator to the counter word. If you want to start a counter with aspecific count value, you need to use the appropriate Set counter statement.

Description



7.5 Loading a Count Value in Binary Coded Decimal Format

A count value is stored in a counter word in binary code. You can use thefollowing instruction to read the count value in binary coded decimal (BCD)format out of a counter word and load it into the low word of accumulator 1:

LC <counter word>

This type of loading is referred to as loading a count value in BCD format.

The value contained in the low word of accumulator 1 as a result of the LCoperation has the same format as is needed to set a counter.

STL Explanation

LC C 1 Load accumulator 1 low directly with the count value ofcounter C 1 in binary coded decimal format.

Count value

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Count in BCD format

15

102 101 100

14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Binary to BCD

0 0 0 0

(Hundreds) (Tens) (Ones)

Counter word for C 1

Accumulator 1low

Figure 7-4 Loading a Count Value into Accumulator 1 Using the LC Instruction

The value contained in the accumulator as a result of the LC operation can beused for further processing, such as transferring the value to the outputs for adisplay.

Description



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7.6 Counter Example

Figure 7-5 provides an example of counting up, counting down, setting andresetting a counter, checking the signal state of a counter, and loading a countvalue. The example follows the programming sequence recommended inSection 7.2. The numbers in squares in the figure are keyed to explanationsthat follow the figure. Figure 7-5 refers to the statement list program thatfollows the explanatory list.

ÎÎÎÎÎÎ

I 2.0 Enable

I 2.1 Count Up

I 2.2 Count Down

I 2.3 Set

I 2.4 Reset

CounterResponse

�

�

Check signalstate of counteroutput Q 4.0

MW10 LoadMW12 ÎÎÎ

ÎÎÎ

ÎÎÎÎÎÎ

�

�

�

�

� �

��

�

�

�

�

Figure 7-5 Example of Counter Instructions



The following list describes the elements of Figure 7-5:

� A change in the RLO from 0 to 1 at the Set input sets the counter toa count value of 3. A transition from 1 to 0 at the Set input has noeffect on the counter.

� A change in the RLO from 0 to 1 at the Count Down input decreasesthe counter by one. A transition from 1 to 0 at the Count Downinput has no effect on the counter.

� The result of the signal state check statement A C 1 is 0 when thecount value is 0.

� A change in the RLO from 0 to 1 at the Count Up input increasesthe counter by one. A transition from 1 to 0 at the Count Up inputhas no effect on the counter.

� If an RLO of 1 is applied at the Reset input, the counter is reset.Checking the signal state produces a result of 0. A change in theRLO from 1 to 0 at the Reset input has no effect on the counter.

� A change in the RLO from 0 to 1 at the Count Up input while theReset signal is applied causes the counter to increase momentarilybut to reset immediately because of the Reset statement that followsdirectly in the program. (The momentary increase is indicated by apulse line in the timing diagram in Figure 7-5). Checking the signalstate then produces a result of 0.

� A change in the RLO from 0 to 1 at the Enable input with Count Upand Count Down applied causes the counter to increase momentarilybut then decrease immediately because of the Count Downstatement that follows directly in the program. (The momentaryincrease is indicated by a pulse line in the timing diagram inFigure 7-5). A transition from 1 to 0 at the Enable input has noeffect on the counter.

STL Explanation

A I 2.0FR C 1A I 2.1CU C 1A I 2.2CD C 1A I 2.3L C# 3S C 1A I 2.4R C 1A C 1= Q 4.0L C 1T MW10LC C 1T MW12

Enable counter C 1.

Count up (increment by 1).

Count down (decrement by 1).

Set counter C 1.

Reset counter C.

Check the signal state of counter C 1.Load counter C 1 (binary coded)

Load counter C 1 (BCD coded).



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7.7 Address Locations and Ranges for Counter Instructions

Table 7-1 shows the address types, address locations, and address ranges forthe counter instructions.

Table 7-1 Address Locations, Ranges, and Types for Counter Instructions

Address Range according to Addressing Type


0 to 65,535

[DBW][DIW][LW][MW]

0 to 65,534



Load and Transfer Instructions


8.1 Overview 8-2

8.2 Loading and Transferring 8-3

8.3 Reading the Status Word or Transferring to the Status Word 8-6

8.4 Loading Times and Counts as Integers 8-7

8.5 Loading Times and Counts in Binary Coded DecimalFormat

8-9

8.6 Loading and Transferring between Address Registers 8-11

8.7 Loading Data Block Information 8-12

Chapter Overview

8


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8.1 Overview

The Load (L) and Transfer (T) instructions enable you to program aninterchange of information between input or output modules and memoryareas, or between memory areas. The CPU executes these instructions ineach scan cycle as unconditional instructions, that is, they are not affected bythe result of logic operation of a statement.

The L and T instructions enable an interchange of information between thefollowing modules or memory areas:

� Input and output modules and the following areas of memory:

– Process-image input and output tables

– Bit memory

– Timers and counters

– Data areas

� Process-image input and output tables and the following areas ofmemory:

– Bit memory

– Timers and counters

– Data areas

� Timers and counters and the following areas of memory:

– Process-image input and output tables

– Bit memory

– Data areas

The L and T instructions provide information exchange via the accumulator.An L instruction statement writes (loads) the contents of its addressed sourcelocation into accumulator 1, shifting any information already contained thereto accumulator 2. The old contents of accumulator 2 is overwritten. AT instruction statement copies the contents of accumulator 1 and writes theminto the memory of its addressed destination. Because the T instruction onlycopies the information that is in accumulator 1, this information is stillavailable to other instructions.

The L and T instructions can handle information in bytes (8 bits), words(16 bits), and double words (32 bits).

The accumulator has a total of 32 bits. Data with fewer than 32 bits is rightjustified in the accumulator. The remaining bits of the accumulator arepadded with zeros.

16 15 0LOADSource

TRANSFERDestination

Accumulator 1

31

Definition

InformationInterchange

Method ofInterchange



8.2 Loading and Transferring

You can use the Load (L) or Transfer (T) instruction to transfer informationto or from accumulator 1 in chunks of the following sizes:

� Byte (B, 8 bits)

� Word (W, 16 bits)

� Double word (D, 32 bits)

A byte is loaded into the low byte of the low word of accumulator 1. A wordis loaded into the low word of accumulator 1. Unused bytes are reset to 0when loading into the accumulator.

The L instruction can address constants of 8, 16, and 32 bits as well as ASCIIcharacters. This type of addressing is called immediate addressing (seeSection 3.1 and Table 8-1).

Table 8-1 Addresses of L Instructions: Immediate Addressing

Address Example Explanation

�.. L +5 Loads a 16-bit integer constant into accumulator 1.

B#(..,..) L B#(1,10)

L B#(1,10,5,4)

Loads a contact as 2 bytes into accumulator 1. (In this example, the 10 goes into the low byte of the lowword of accumulator 1; the 1 goes into the high byte of thelow word of accumulator 1, see Figure 2-4.)Loads a contact as 4 bytes into accumulator 1. (In this example, the 4 and the 5 go into the low and highbyte of the low word of accumulator 1, respectively; the 10and the 1 go into the low and high byte of the high word ofaccumulator 1, respectively, see Figure 2-4.)

L#.. L L#+5 Loads a 32-bit integer constant into accumulator 1.

16#.. L B#16#EFL W#16#FAFBL DW#16#1FFE_1ABC

Loads an 8-bit hexadecimal constant into accumulator 1.Loads a 16-bit hexadecimal constant into accumulator 1.Loads a 32-bit hexadecimal constant into accumulator 1.

2#.. L 2#1111_0000_1111_0000L 2#1111_0000_1111_0000_

1111_0000_1111_0000

Loads a 16-bit binary constant into accumulator 1.Loads a 32-bit binary constant into accumulator 1.

’..’ L ’AB’L ’ABCD’

Loads 2 characters into accumulator 1.Loads 4 characters into accumulator 1.

C#.. L C#1000 Loads a 16-bit count constant into accumulator 1.

S5TIME#.. L S5TIME#2S Loads a 16-bit S5TIME constant into accumulator 1.

.. L 1.0E+5 Loads a 32-bit IEEE floating point into accumulator 1.

P#.. L P#I1.0L P##Start

L P#ANNA

Loads a 32-bit pointer into accumulator 1.Loads a 32-bit pointer to a local variable (Start) intoaccumulator 1Loads a pointer to a specified parameter in accumulator 1.(This instruction loads the relative address offset of thespecified parameter. In order to determine the absolute offsetin the instance data block of a function block with multipleinstances, the contents of the AR2 register must be added tothis value.)

Description

ImmediateAddressing



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Table 8-1 , continuedAddresses of L Instructions: Immediate Addressing, continued

Address ExplanationExample

D#.. L D#1994-3-15 Loads a 16-bit date into accumulator 1.

T#.. L T#0D_1H_1M_0S_0MS Loads a 32-bit time value into accumulator 1.

TOD#.. L TOD#1:10:3.3 Loads a 32-bit time-of-day value into accumulator 1.

The L and T instructions can address a byte (B), word (W), or double word(D) in the following memory areas using direct and indirect addressing (seealso Sections 3.2, 3.3, and 3.5):

� Process-image input and output (address identifiers IB, IW, I, QB, QW,QD)

� External inputs and outputs (address identifiers PIB, PIW, PID, PQB,PQW, PQD). External inputs can be addresses of L instructions only;external outputs can be addresses of T instructions only.

� Bit memory (address identifiers MB, MW, MD)

� Data block (address identifiers DBB, DBW, DBD, DIB, DIW, DID)

� Local data (temporary local data, address identifiers LB, LW, LD)

Table 8-2 lists the addresses for L and T instructions that use direct andindirect addressing.

Table 8-2 Addresses of L and T Instructions: Direct and Indirect Addressing

Address Maximum Address Range according to Addressing Type


IBIWID

QBQWQD

0 to 65,5350 to 65,5340 to 65,532

0 to 65,5350 to 65,5340 to 65,532

[DBD][DID][LD][MD]


[AR2, P#byte.bit]0 to 8,191

PIBPIWPID(L only)

PQBPQWPQD(T only)

0 to 65,5350 to 65,5340 to 65,532

0 to 65,5350 to 65,5340 to 65,532

[DBD][DID][LD][MD]



Direct and IndirectAddressing



Table 8-2 Addresses of L and T Instructions: Direct and Indirect AddressingAddress

ID Area-Internal Register IndirectMemory IndirectDirect

MBMWMD

0 to 2550 to 2540 to 252

[DBD][DID][LD][MD]



DBBDBWDBD

DIBDIWDID

LBLWLD

0 to 65,5350 to 65,5340 to 65,532

0 to 65,5350 to 65,5340 to 65,532

0 to 65,5350 to 65,5340 to 65,532

[DBD][DID][LD][MD]



The L and T instructions can address a byte (B), word (W), or double word(D) using area-crossing register indirect addressing (see Section 3.6).

Table 8-3 Addresses of L and T Instructions: Area-Crossing Register IndirectAddressing

Address Identifier1 Address Range

B (byte), W (word), D (double word)[AR1, P#byte.bit][AR2, P#byte.bit]

0 to 8,191

1 The memory area is encoded in bits 24 through 31 of AR1 or AR2 (see Section 3.6).

For their address, the L and T instructions can also use a byte, word, ordouble word that is transferred as parameter.

Table 8-4 Address of L and T Instructions: Byte, Word, or Double WordTransferred as Parameter


Symbolic name A byte, word, or double word transferred as parameter

Area-CrossingIndirectAddressing

Byte, Word, orDouble Word asParameter



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8.3 Reading the Status Word or Transferring to the Status Word

You can use the Load (L) instruction to load bits 0 through 8 of the statusword (see Figure 8-1) into accumulator 1. Bits 9 through 31 of accumulator1 are reset to 0. The instruction statement is shown in the example thatfollows Figure 8-1.

Note

For the S7-300 series CPUs, the statement L STW does not load the FC,STA, and OR bits of the status word. Only bits 1, 4, 5, 6, 7, and 8 are loadedinto the corresponding bit positions of the low word of accumulator 1.

28215... ...29 2427 26 25 2023 22 21

BR OSCC 1 CC 0 OV FCOR STA RLO

Figure 8-1 Structure of the Status Word

STL Explanation

L STW Loads bits 0 to 8 of the status word into the low word ofaccumulator 1.

You can use the Transfer (T) instruction to transfer the contents ofaccumulator 1 to the status word (see Figure 8-1). The instruction statementis shown in the following program excerpt.

STL Explanation

T STW Transfers the contents of accumulator 1 to the statusword.

Loading the StatusWord

Transferring to theStatus Word



8.4 Loading Times and Counts as Integers

A time value is stored in a timer word in binary code. You can use thefollowing Load (L) instruction to read the binary time value out of a timerword and load it into the low word of accumulator 1:

L <timer word>

This type of loading is referred to as loading of a time value directly.

The time value in the timer word is decremented from its starting value to 0during the processing of the user program in the CPU. When you use the Linstruction with a timer word as address, you get a value that lies between thestarting time of the timer word and 0. The time that elapses from the momenta timer starts is calculated from the difference of the start time and the timebeing read currently.

STL Explanation

L T 1 Load accumulator 1 low directly with the time of timerT 1 in binary code.

0000 00

Timer word

Accumulator 1 low

15 10 9 0

15 10 9 0Time

Figure 8-2 Loading a Time Value into Accumulator 1 Using the L Instruction

You can use the value contained in the accumulator as a result of the Loperation for further processing. You cannot transfer a value from theaccumulator to the timer word.

Note

When you use the L instruction to read out a timer word, you get a valuebetween 0 and 999. You do not get the time base that was loaded with thetime value.

Loading a Time



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A count value is stored in a counter word in binary code. You can use thefollowing Load (L) instruction to read the binary count value out of a counterword and load it into the low word of accumulator 1:

L <counter word>

This type of loading is referred to as loading a counter value directly.

STL Explanation

L C 1 Load accumulator 1 low directly with the count value ofcounter C 1 in binary format.

0 0 0 0 0 0

9 0

X X X X X X

Count Value

Counter wordfor C 1

Accumulator 1low

1015

15 10 0


You can use the value contained in the accumulator as a result of the Loperation for further processing. You cannot transfer a value from theaccumulator to the counter word. If you want to start a counter with aspecific count value, you need to use the appropriate Set counter statement(see Section 7.2).

Loading a Count



8.5 Loading Times and Counts in Binary Coded Decimal Format

A time value is stored in a timer word in binary code. You can use thefollowing Load (L) instruction to read the time value in binary coded decimal(BCD) format out of a timer word and load it into the low word ofaccumulator 1:

LC <timer word>

In addition to the time value, the time base is also loaded. The value whichappears in the low word of Accumulator 1 as the result the LC instruction,has the format which is required to start a time. This type of loading isreferred to as loading a time in BCD format.

The time value in the timer word is decremented from its start value to 0.When you use the LC instruction with a timer word as address, you get avalue that lies between the starting time of the timer word and 0. The timethat elapses from the moment a timer starts is calculated from the differenceof the start time and the time currentlybeing read.

STL Explanation

LC T 1 Load accumulator 1 low with the time and time base oftimer T 1 in BCD format.

Timer word

Accumulator 1 low

15 10 9 0Time

Binary to BCD

13 1214

15 013 1214 11

102 101 100Timebase (Hundreds) (Tens) (Ones)

11

0 0

Time base


The value contained in the accumulator as a result of the LC operation can beused for further processing, such as transferring the value to the outputs for adisplay. You cannot transfer a value from the accumulator to the timer word.

Loading a Time inBCD Format



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A count value is stored in a counter word in binary code. You can use thefollowing Load (L) instruction to read the count value in binary codeddecimal (BCD) format out of a counter word and load it into the low word ofaccumulator 1:

LC <counter word>

This type of loading is referred to as loading a count value in BCD format.The value contained in the low word of accumulator 1 as a result of the LCoperation has the same format as is needed to set a counter.

A count value is stored in a counter word in binary code. You can load thetime value into the low word of accumulator 1 in binary coded decimalformat (BCD format, see Figure 8-5). You can use the LC instruction to readout a count value in BCD format.

STL Explanation

LC C 1 Load accumulator 1 low directly with the count value ofcounter C 1 in binary coded decimal format.

Count value

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Count in BCD format

15

102 101 100

14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Binary to BCD

0 0 0 0

(Hundreds) (Tens) (Ones)

Counter word for C 1

Accumulator 1 low

X X X X X X

Figure 8-5 Loading a Count Value into Accumulator 1 Using the LC Innstruction

The value contained in the accumulator as a result of the LC operation can beused for further processing, such as transferring the value to the outputs for adisplay. You cannot transfer a value from the accumulator to the counterword.

Loading a Count inBCD Format



8.6 Loading and Transferring between Address Registers

Your program can use the following instructions to enable the CPU toexchange information between address registers or exchange the contents ofthe two registers:

Instruction Explanation

LAR1 Loads address register 1 with the contents of the area that the instruc-tion addresses. If no address is indicated, LAR1 loads address register1 with the contents of accumulator 1. LAR1 can also use AR2 as anaddress, that is LAR1 can load AR1 with the contents of AR2.

LAR2 Loads address register 2 with the contents of the area that the instruc-tion addresses. If no address is indicated, LAR2 loads address register2 with the contents of accumulator 1.

TAR1 Transfers the contents of address register 1 into the destination that theinstruction addresses. If no address is indicated, TAR1 transfers thecontents of address register 1 to accumulator 1. TAR1 can also useAR2 as an address, that is, TAR1 can transfer the contents of AR1 intoAR2.

TAR2 Transfers the contents of address register 2 into the destination that theinstruction addresses. If no address is indicated, TAR2 transfers thecontents of address register 2 to accumulator 1.

TAR Exchanges the contents of AR1 and AR2.

The LAR1 and LAR2 instructions can address constants of 32 bits. This typeof addressing is called immediate addressing (see Section 3.1). Theimmediate address is used to load a 32-bit pointer immediately into theaddress register (see Table 8-5).

LAR1 P#{area,} Byte{.Bit}

with {area} = {I, Q, M, D, DX, L} Byte = 0 to 65,535 {.Bit} = 0 to 7

Table 8-5 LAR1 and LAR2: Immediate Addressing

Example Description

LAR1 P#I0.0 Loads the area-crossing pointer P#I0.0 into addressregister 1

LAR2 P#0.0 Loads the area-internal pointer with the location 0 intoaddress register 2

LAR1 P##Start Loads an area-crossing pointer to the local variable(Start) into address register 1

Description

ImmediateAddressing



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You can use direct addressing with LAR1, LAR2, TAR1, and TAR2.

Table 8-6 LAR1, LAR2, TAR1, TAR2: Direct Addressing

Instruction Register As Address Address Identifier and Range

LAR1 {BLANK} 1) or AR2 DBDDID

0 to 65 532LAR2 {BLANK} 1 LD

0 to 65,532

MD

TAR1 {BLANK} 2) or AR2 DBDDIDDIDLD 0 to 65,532

TAR2 { BLANK} 2)LDMDTAR2 {BLANK} MD

1 {BLANK} If no address is indicated, LAR1/LAR2 loads the address register withthe contents of accumulator 1.

2 {BLANK} If no address is indicated, TAR1/TAR2 transfers the contents of theaddress register to accumulator 1.

8.7 Loading Data Block Information

You can use the Load (L) instruction to load the length or number of a datablock into accumulator 1. Table 8-7 summarizes the addresses for this type ofloading. For more information on on loading the length or number of a datablock into accumulator 1 see Section 15.3.

Table 8-7 Loading the Length or Number of a Data Block into Accumulator 1

Address Explanation

DBLG Loads the length in bytes of a shared data block into accumulator 1

DILG Loads the length in bytes of an instance data block into accumulator 1

DBNO Loads the number of a shared data block into accumulator 1

DINO Loads the number of an instance data block into accumulator 1

Direct Addressing



Integer Math Instructions


9.1 Four-Function Math 9-2

9.2 Adding an Integer to Accumulator 1 9-6

Chapter Overview

9


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9.1 Four-Function Math

Table 9-1 lists the statement list instructions that you can use to add, subtract,multiply, and divide integers (16 bits) and double integers (32 bits).

Table 9-1 Four-Function Math Instructions for Integers and Double Integers

InstructionSize in

BitsFunction

+I 16Adds the contents of the low words of accumulators 1 and 2and stores the result in the low word of accumulator 1.

–I 16Subtracts the contents of the low word of accumulator 1from the contents of the low word of accumulator 2 andstores the result in the low word of accumulator 1.

�I 16Multiplies the contents of the low words of accumulators 1and 2 and stores the result (32 bits) in accumulator 1.

/I 16

Divides the contents of the low word of accumulator 2 bythe contents of the low word of accumulator 1. The result isstored in the low word of accumulator 1. Any wholeremainder is stored in the high word of accumulator 1.

+D 32Adds the contents of accumulators 1 and 2 and stores theresult in accumulator 1.

–D 32Subtracts the contents of accumulator 1 from the contentsof accumulator 2 and stores the result in accumulator 1.

�D 32Multiplies accumulator 1 by the contents of accumulator 2and stores the result in accumulator 1.

/D 32Divides the contents of accumulator 2 by the contents ofaccumulator 1. The result is stored in accumulator 1.

MOD 32Divides the contents of accumulator 2 by the contents ofaccumulator 1 and stores the remainder as a result inaccumulator 1.

The function descriptions in Table 9-1 point out that the math operationscombine the contents of accumulators 1 and 2. The result is stored inaccumulator 1. The old contents of accumulator 1 is shifted to accumulator 2.The contents of accumulator 2 remains unchanged.

In the case of CPUs with four accumulators, the contents of accumulator 3 isthen copied into accumulator 2 and the contents of accumulator 4 intoaccumulator 3. The old contents of accumulator 4 remains unchanged.

Description

Relationship ofMath Operators toAccumulators



The Add Accumulators 1 and 2 As Integer instruction (+I) tells the CPU toadd the contents of the low word of accumulator 1 and the low word ofaccumulator 2 and store the result in the low word of accumulator 1. Thisoperation overwrites the old contents of the low word of accumulator 1. Theold contents of accumulator 2 and the high word of accumulator 1 remainunchanged (see Figure 9-1). A sample program follows the figure.

Accumulator 2

Accumulator 1

Accumulator 2

Accumulator 1

31 016 15

31 016 15

IV III

II I

IV III

+ I

II III + I

Accumulator contentsbefore math operation

Accumulator contentsafter math operation

Figure 9-1 Adding Two Integers

The Add Accumulators 1 and 2 As Integer instruction (+I) tells the CPU toadd the contents of the low word of accumulator 1 and the low word ofaccumulator 2 and store the result in the low word of accumulator 1. Thisoperation overwrites the old contents of the low word of accumulator 1. Itthen copies the contents of accumulator 3 to accumulator 2 and the contentsof accumulator 4 to accumulator 3. Accumulator 4 and the high word ofaccumulator 1 remain unchanged (see Figure 9-2).

Accumulator 2

Accumulator 1

Accumulator 2

Accumulator 1

31 016 15

31 016 15

IV III

II I

VI V

+ I

II III + I

Accumulator 3 Accumulator 331 016 15

VI V VIII VII

Accumulator 4 Accumulator 431 016 15

VIII VII VIII VII



Figure 9-2 Adding two Integers in CPUs with four Accumulators

Combining twoIntegers (16 bits)in CPUs with twoAccumulators

Combining twoIntegers (16 bits)in CPUs with fourAccumulators



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STL Explanation

L MW10

L DBW12

+I

T DBW14

Load the value of memory word MW10 into accumulator 1.Load the value of data word DBW12 into accumulator 1. Theold contents of accumulator 1 are shifted toaccumulator 2.The CPU interprets the contents of the low words ofaccumulators 1 and 2 as 16-bit integers, adds them, andstores the result in the low word of accumulator 1.Transfer the contents of the low word of accumulator 1(the result) to data word DBW14.

The math instructions affect the following bits of the status word:

� CC 1 and CC 0

� OV

� OS

A hyphen (–) entered in a bit column of the table means that the bit inquestion is not affected by the result of the integer math operation. You canuse the instructions in Table 9-5 to evaluate these bits of the status word

Table 9-2 Signal State of Bits in the Status Word for Integer Math Result in Valid Range

Valid Range for an Integer (16 Bits) and Double Bits of Status Wordg gInteger (32 Bits) Result CC 1 CC 0 OV OS

0 (zero) 0 0 0 –

I: -32,768 � Result � 0 (negative number)D: -2,147,483,648 � Result � 0 (negative number)

0 1 0 –

I: 32,767 � Result �0 (positive number)D 2,147,483,647 � Result �0 (positive number)

1 0 0 –

Table 9-3 Signal State of Bits in the Status Word for Integer Math ResultThat Is Not in Valid Range

Range Not Valid for a Double Integer Result Bits of Status Wordg g(32 Bits) CC 1 CC 0 OV OS

I: Result � 32,767 (positive number)D: Result � 2,147,483,647 (positive number)

1 0 1 1

I: � –32,768 (negative number)D: Result � -2,147,483,648 (negative number)

0 1 1 1

Evaluating the Bitsin the Status Word

Valid Result

Invalid Result



Table 9-4 Signal State of Bits in the Status Word for Double Integer MathInstructions +D, /D, and MOD

Instruct ionBits of Status Word

Instruct onCC 1 CC 0 OV OS

+D: Result = -4,294,967,296 0 0 1 1

/D or MOD: Division by 0 has occurred. 1 1 1 1

Table 9-5 Instructions That Evaluate the CC 1, CC 0, OV, and OS Bits

Instruction Reference to Bit ofthe Status Word or

Jump Label

Bits in Status WordThat Are Evaluated(indicated by an X)

Section inThis Manual

A,O,X,AN,ON,XN >0, <0, <>0, >=0, <=0,==0, UO, OV, OS

CC 1, CC 0, OV, OS 5.3

JO <jump label> OV 16.4

JOS <jump label> OS 16.4

JUO <jump label> CC 1 and CC 0 16.5

JZ <jump label> CC 1 and CC 0 16.5

JN <jump label> CC 1 and CC 0 16.5

JP <jump label> CC 1 and CC 0 16.5

JM <jump label> CC 1 and CC 0 16.5

JMZ <jump label> CC 1 and CC 0 16.5

JPZ <jump label> CC 1 and CC 0 16.5



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9.2 Adding an Integer to Accumulator 1

You can use the Add Integer Constant instruction to add an integer constantto the contents of the low word of accumulator 1. Table 9-6 lists thepossibilities. These instructions do not affect the status word bits.

Table 9-6 Adding an Integer to Accumulator 1

Instruction Address Function

+ + integer Adds a 16-bit integer constant to the contents of the low wordof accumulator 1. The result is stored in accumulator 1. Theold contents of the low word of this accumulator areoverwritten. Accumulator 2 and the high word ofaccumulator 1 remain unchanged.

+ + L#double integer Adds a 32-bit integer constant to the contents ofaccumulator 1. The result is stored in accumulator 1. The oldcontents of this accumulator are overwritten. Accumulator 2remains unchanged.

Below are two programs with Add Integer Constant instructions.

STL Explanation

L MW10L MW20+I+ –5T MW14

Load the value in MW10 into accumulator 1.Load the value in MW20 into accumulator 1.Add the 16-bit values in accumulator 1 and 2.Add a minus 5 to the result of the +I statement.Transfer the new result to MW14.

STL Explanation

L MD10L MD16+D+ L#–1T MD24

Load the value in MD10 into accumulator 1.Load the value in MD16 into accumulator 1.Add the 32-bit values in accumulator 1 and 2.Add a minus 1 to the result of the +D statement.Transfer the new result to MD24.

Add 16 and 32-BitInteger Constants

Examples



Floating-Point Math Instructions


10.1 Four-Function Math 10-2

10.2 Forming the Absolute Value of a Floating-Point Number 10-6

10.3 Extended Math Instructions 10-7

10.4 Forming the Square / Square Root of a Floating-PointNumber

10-9

10.5 Forming the Natural Logarithm of a Floating-Point Number 10-11

10.6 Forming the Exponential Value of a Floating-Point Number 10-12

10.7 Forming Trigonometric Functions on Angles Acting asFloating-Point Numbers

10-13

Chapter Overview

10


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10.1 Four-Function Math

Table 10-1 lists the statement list instructions that you can use to add,subtract, multiply, and divide 32-bit IEEE floating-point numbers. BecauseIEE 32-bit floating-point numbers belong to the data type called “REAL”,the mnemonic abbreviation for these instructions is R.

Table 10-1 Four-Function Math Instructions for IEEE 32-Bit Floating-PointNumbers

Instruction Function

+R Adds the IEEE 32-bit floating-point numbers in accumulators 1 and 2and stores the 32-bit result in accumulator 1.

-R Subtracts the IEEE 32-bit floating-point number in accumulator 1 fromthe IEEE 32-bit floating-point number in accumulator 2 and stores the32-bit result in accumulator 1.

�R Multiplies the IEEE 32-bit floating-point number in accumulator 1 bythe IEEE 32-bit floating-point number in accumulator 2 and stores the32-bit result in accumulator 1.

/R Divides the IEEE 32-bit floating-point number in accumulator 2 by theIEEE 32-bit floating-point number in accumulator 1. The 32-bit result isstored in accumulator 1.

The function descriptions in Table 10-1 point out that the math instructionscombine the contents of accumulators 1 and 2. The result is stored inaccumulator 1. The old contents of accumulator 1 is shifted to accumulator 2.The contents of accumulator 2 remains unchanged.

In the case of CPUs with four accumulators, the contents of accumulator 3 iscopied into accumulator 2 and the contents of accumulator 4 intoaccumulator 3. The old contents of accumulator 4 remains unchanged.

Description

Relationship ofMath Instructionsto Accumulators



The Add Accumulators 1 and 2 As Real instruction (+R) tells the CPU to addthe contents of accumulator 1 and accumulator 2 and store the result inaccumulator 1. This operation overwrites the old contents of accumulator 1.The old contents of accumulator 2 remain unchanged (see Figure 10-1).A sample program follows Figure 10-2.

Accumulator 2

Accumulator 1

Accumulator 2

Accumulator 1

31 016 15

31 016 15

II

I

II

+ R

II + I



Figure 10-1 Adding Two IEEE Floating-Point Numbers

The same pattern applies to the remaining floating-point math instructions.

Table 10-2 Result of Instructions with Denormalized Numbers in CPUs with TwoAccumulators

Instruction Input Value ResultAccumulator 1 Accumulator 2 Accumulator 1 Accumulator 2

+R a b a b

-R a b -a b

*R a b 0 b

+R a b FFFF b

Result ofCombining TwoIntegers in CPUswith TwoAccumulators



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The Add Accumulators 1 and 2 As Real instruction (+R) tells the CPU to addthe contents of accumulator 1 and accumulator 2 and store the result inaccumulator 1. This instruction overwrites the old contents of accumulator 1.Next the contents of accumulator 3 is copied into accumulator 2 and thecontents of accumulator 4 is copied into accumulator 3 (see Figure 10-2).

Accumulator 4

Accumulator 3

Accumulator 4

Accumulator 3

31 016 15

31 016 15

IV

III

IV

IV

Accumulator 2

Accumulator 1

Accumulator 2

Accumulator 1

31 016 15

31 016 15

II

I

II

+ R

II + I

Accumulator contentsbefore math instruction

Accumulator contentsafter math instruction

Figure 10-2 Adding Two IEEE Floating-Point Numbers in CPUs with fourAccumulators

The same pattern applies to the remaining floating-point math instructions.

STL Explanation

L MD100L DBD4

+R

T DBD16

Load the value in memory double word MD100 into accumulator 1.Load the value in data double word DBD4 into accumulator 1. The old contents of accumulator 1 are shifted toaccumulator 2. (The values in these double words must be infloating-point format.)The CPU interprets the contents of accumulators 1 and 2 as32-bit IEEE floating-point numbers, adds them, and stores theresult in accumulator 1.Transfer the contents of accumulator 1 (the result) to datadouble word DBD16. (DBD16 = MD100 + DBD4)

The math instructions do affect the following bits of the status word:

� CC 1 and CC 0

� OV

� OS

You can use the instructions in Table 10-5 to evaluate these bits of the statusword. Table 10-3 shows the signal states of the status word bits forfloating-point math results that fall within the valid range. A hyphen (–)entered in a bit column of the table means that the bit in question is notaffected by the result of the floating-point math instruction.

Result ofCombining TwoIntegers in CPUswith TwoAccumulators

Example

Bits Affected bythe MathInstructions



Table 10-3 Signal State of Bits in the Status Word for Floating-Point Math Result in Valid Range

Valid Range for a Floating Point Result (32 Bits)Bits of Status Word

Val d Range for a Float ng-Po nt Result (32 B ts)CC 1 CC 0 OV OS

+0, -0 (zero) 0 0 0 –

-3.402823E+38 � Result � -1.175494E–38(negative number)

0 1 0 –

+1.175494E–38 � Result � 3.402823E+38(positive number)

1 0 0 –

Table 10-4 Signal State of Bits in the Status Word for Floating-Point Math ResultThat Is Not in Valid Range

Range Not Valid for a Floating-Point Result Bits of Status Wordg g(32 Bits) CC 1 CC 0 OV OS

-1.175494E–38 � Result � -1.401298E–45(negative number) Underflow

0 0 1 1

+1.401298E–45 � Result � +1.175494E–38(positive number) Underflow

0 0 1 1

Result � -3.402823E+38(negative number) Overflow

0 1 1 1

Result � -3.402823E+38(positive number) Overflow

1 0 1 1

Table 10-5 Instructions That Evaluate the CC 1, CC 0, OV, and OS Bits of theStatus Word

Instruction Reference to Bit ofStatus Word or Jump

Label

Bits in Status WordThat Are Evaluated(indicate d by an X)

Section inThis Manual

A,O,X,AN,ON,XN >0, <0, <>0, >=0, <=0,==0, UO, OV, OS

CC 1, CC 0, OV, OS 5.3

JO <jump label> OV 16.4

JOS <jump label> OS 16.4

JUO <jump label> CC 1 and CC 0 16.4

JZ <jump label> CC 1 and CC 0 16.5

JN <jump label> CC 1 and CC 0 16.5

JP <jump label> CC 1 and CC 0 16.5

JM <jump label> CC 1 and CC 0 16.5

JMZ <jump label> CC 1 and CC 0 16.5

JPZ <jump label> CC 1 and CC 0 16.5



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10.2 Forming the Absolute Value of a Floating-Point Number

You can use the Absolute Value of a Real instruction (ABS) to form theabsolute value of an IEEE 32-bit floating-point number in accumulator 1. Anabsolute value is a non-negative number equal in numerical value to a givenreal number. For an absolute value, a sign (+ or -) is not relevant. Forexample, 5 is the absolute value of +5 or -5.

The following program provides an example of the ABS instruction:

STL Explanation

L DBD0

L +12.3E+00

/R

T MD20

NEGR

T MD24

ABS

T MD28

Load the value in data double word DBD0 intoaccumulator 1.Load the value +12.3E+00 into accumulator 1. The oldcontents of accumulator 1 are shifted to accumulator 2.The CPU divides the contents of accumulator 2 by thecontents of accumulator 1 and stores the result inaccumulator 1.Transfer the contents of accumulator 1 (the result) tomemory double word MD20. (MD20 = DBD0 / 12.3)Negate the IEEE floating-point number in accumulator 1(see Section 12.4).Transfer the result from accumulator 1 to memory doubleword MD24. (MD24 = [–1] � MD20)The CPU forms the absolute value of the IEEEfloating-point number in accumulator 1.Transfer the absolute value from accumulator 1 to memorydouble word MD28. (MD28 = ABS[MD20])

Description

Example



10.3 Extended Math Instructions

Table 10-6 lists the STL instructions which can be used for extended mathinstructions on floating-point numbers.

Table 10-6 Extended Math Instructions for IEEE 32-Bit Floating-Point Numbers

ÁÁÁÁÁÁÁÁÁÁ

InstructionÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

FunctionÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

SQRTÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Calculates the square root of the 32 bit IEEE floating-point number inACCU1 and stores the 32 bit result in ACCU1.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

SQR ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Calculates the square of the 32 bit IEEE floating-point number inACCU1 and stores the 32-bit result in ACCU1.


LN ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Calculates the natural logarithm of the 32 bit IEEE floating-point num-ber in ACCU1 and stores the 32-bit result in ACCU1.


EXP ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Calculates the exponential value of the 32 bit IEEE floating-point num-ber to base E and stores the 32-bit result in ACCU1.ÁÁÁÁÁ


SINÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Calculates the sine of the 32 bit IEEE floating-point number in ACCU1and stores the 32-bit result in ACCU1.


COSÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Calculates the cosine of the 32 bit IEEE floating-point number inACCU1 and stores the 32-bit result in ACCU1.


TAN ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Calculates the tangent of the 32 bit IEEE floating-point number inACCU1 and stores the 32-bit result in ACCU1.


ASIN ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Calculates the arc sine of the 32 bit IEEE floating-point number inACCU1 and stores the 32-bit result in ACCU1.ÁÁÁÁÁ


ACOSÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Calculates the arc cosine of the 32 bit IEEE floating-point number inACCU1 and stores the 32-bit result in ACCU1.


ATANÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Calculates the arc tangent of the 32 bit IEEE floating-point number inACCU1 and stores the 32-bit result in ACCU1.

The extended math instructions only work in conjunction withaccumulator 1. The value to which the operation is applied is expected inaccumulator 1. The result is stored in accumulator 1; the old contents ofaccumulator 1 is overwritten. The contents of accumulator 2, accumulator 3and accumulator 4 remain unchanged.

Description

Relationship ofExtended MathInstructions toAccumulators



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The CPU executes the four-function math instructions listed in Table 10-1,without regard to, and without affecting the result of logic operation. Theextended math instructions do affect the following bits of the status word:

� CC 1 and CC 0

� OV

� OS

To evaluate these bits, you can use the instructions in Table 10-7 (Section10.1) and see Section 5.3.

Table 10-7 Extended Math Instructions for 32-Bit IEEE Floating-PointNumbers

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

InstructionÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reference to Bit ofStatus Word or Jump

Label

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Bits in Status WordThat Are Evaluated(indicated by an X)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Section inThis

Manual

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

A, O, X, AN, ON, XNÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

>0, <0, <>0, >=0, <=0,==0, UO, OV, OS

ÁÁÁÁÁÁÁÁÁÁÁÁ

CC 1, CC 0, OV, OSÁÁÁÁÁÁÁÁÁÁ

5.3

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁJO

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ<jump label>

ÁÁÁÁÁÁÁÁÁÁÁÁOV

ÁÁÁÁÁÁÁÁÁÁ16.4ÁÁÁÁÁÁÁ


JOSÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

<jump label>ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

OSÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

16.4


JUO ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

<jump label> ÁÁÁÁÁÁÁÁÁÁÁÁ

CC 1 and CC 0ÁÁÁÁÁÁÁÁÁÁ

16.4


JZ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ



16.5


JN ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ



16.5


JP ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ



16.5


JM ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ



16.5


JMZ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ



16.5


JPZ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ



16.5

Effect of ExtendedMath Instructionson the Bits in theStatus Word



10.4 Forming the Square / Square Root of a Floating-Point Number

The instruction SQR (square) calculates the square of the 32 bit IEEEfloating-point number in accumulator 1 and stores the 32-bit result inaccumulator 1. The operation SQR overwrites the old contents ofaccumulator 1; the contents of accumulator 2, accumulator 3, andaccumulator 4 remain unchanged.

The instruction SQRT (square root) calculates the square root of the 32 bitIEEE floating-point number in accumulator 1 and stores the 32-bit result inaccumulator 1. The input value must be greater or equal to zero. Theinstruction SQRT overwrites the old contents of accumulator 1; the contentsof accumulator 2, accumulator 3, and accumulator 4 remain unchanged.This instruction gives a positive result when all the addresses are greater thanzero (“0”). The only exception: the Square Root of -0 is -0.

Table 10-8 Effects of Instruction SQR on Bits CC 1, CC 0, OV and OS

Result in Accumulator 1 CC 1 CC 0 OV OS

+ qNaN 1 1 1 1

+ Infinite (Overflow) 1 0 1 1

+ Valid 1 0 0 –

+ Not valid (Underflow) 0 0 1 1

+ Null 0 0 0 –

- qNaN 1 1 1 1

The following program extract is an example of how the instruction SQR isused.

STL Explanation

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

OPN DB17 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Open data block DB17. (It is assumed that it contains the inputvalue and will store the result).

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

L DBD0ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Load the value in data double word DBD0 into accumulator 1.(The value in this double word must be in floating-point for-mat.)ÁÁÁÁÁÁÁÁÁ


SQRÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Calculate the square of the 32 bit IEEE floating-point number.Store the result in accumulator 1.


AN OV ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Check that the status bit OV is 0.


JC OK ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

If operation SQR has no errors, jump tothe label OK


... ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

(In the event of an error an appropriate reaction takes placeat this point.)ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁOK: T DBD4ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁTransfer the result of accumulator 1 to data double word DBD4.

Description

Effects on BitsCC 1, CC 0, OVand OS of theStatus Word

Example



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Table 10-9 Effects of Instruction SQRT on Bits CC 1, CC 0, OV and OS


+ qNaN 1 1 1 1


+ Valid 1 0 0 –


+ Zero 0 0 0 –

-Zero 0 0 0 –

- qNaN 1 1 1 1

The following program extract is an example of how the instruction SQRT isused.

STL Explanation

L MD10

SQRT

AN OVJC OK

...OK: T MD20

Load the value in memory double word MD10 into accumulator 1.(The value must be in floating-point format.)Form the square root of the 32 bit IEEE floating-point numberin accumulator 1. Store the result in accumulator 1.Check that the status bit OV is 0.If operation SQR has no errors, jump to the label OK.(In the event of an error an appropriate reaction takes placeat this point.)Transfer the result (accumulator 1) in the memory double wordMD20.

Example



10.5 Forming the Natural Logarithm of a Floating-Point Number

The instruction LN (natural logarithm) calculates the natural logarithm of thefloating-point number in accumulator 1 and stores the 32-bit result inaccumulator 1. The input value must be greater than zero (0). The instructionLN overwrites the old contents of accumulator 1; the contents ofaccumulator 2, accumulator 3, and accumulator 4 remain unchanged.

Table 10-10 shows the effects that the instruction LN has on the signal stateof bits CC 1, CC 0, OV and OS of the status word. A hyphen (-) entered in abit column of the table means that the bit in question is not affected by theresult of the floating-point math instruction.

Table 10-10 Effects of Instruction LN on Bits CC 1, CC 0, OV and OS


+ qNaN 1 1 1 1


+ Valid 1 0 0 –


+ Zero 0 0 0 –

-Zero 0 0 0 –

- Not valid (Underflow) 0 0 1 1

- Valid 0 1 0 –

- Infinite (Overflow) 0 1 1 1

- qNaN 1 1 1 1

The following program extract is an example of how the instruction LN isused.

STL Explanation


L MD10 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Load the value from memory double word MD10 into accumulator 1.(The value must be in floating-point format.)


LNÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Form the natural logarithm of the 32 bit IEEE floating-pointnumber in accumulator 1. Store the result in accumulator 1.


AN OV ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ



JC OK ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

If operation SQR has no errors, jump to the label OK.


... ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

(In the event of an error an appropriate reaction takes placeat this point.)


OK: T MD20ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Transfer the result from accumulator 1 to memory double wordMD20.

Description


Example



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10.6 Forming the Exponential Value of a Floating-Point Number

The instruction EXP (exponential value to base E) calculates the exponentialvalue of the 32 bit IEEE floating-point number in accumulator 1 to base E(=2.71828) and stores the 32-bit result in accumulator 1. The input valuemust be greater than zero (0). The operation EXP overwrites the old contentsof accumulator 1; the contents of accumulator 2, accumulator 3, andaccumulator 4 remain unchanged.

Table 10-11 shows the effects that the instruction EXP has on the signal stateof bits CC 1, CC 0, OV and OS of the status word. A hyphen (-) entered in abit column means that the bit in question is not affected by the result of thefloating-point math instruction.

Table 10-11 Effects of Instruction EXP on Bits CC 1, CC 0, OV and OS of the StatusWord


+ qNaN 1 1 1 1


+ Valid 1 0 0 –

+ Not Valid (Underflow) 0 0 1 1

+ Zero 0 0 0 –

- qNaN 1 1 1 1

The following program extract is an example of how the instruction EXP isused.

STL Explanation


L MD10 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ



EXP ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Form the exponential value on basis E of the 32 bit IEEE float-ing-point number in accumulator 1. Store the result in accumu-lator 1.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

AN OV ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ



JC OK ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

If operation EXP has no errors, jump to the label OK.


... ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ



OK: T MD20ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Transfer the result from accumulator 1 to memory double wordMD20.

Description


Example



10.7 Forming Trigonometric Functions on Angles Acting asFloating-Point Numbers

Using the following instructions you can form trigonometric functions onangles acting as 32 bit IEEE floating-point numbers. The 32-bit result isstored in accumulator 1; the contents of accumulator 2, accumulator 3 andaccumulator 4 remain unchanged.

Instr. Function

SIN Form the sine of the floating-point number of an angle expressed in radians.Store the angle as a floating-point number in ACCU1.

ASIN Form the arc sine of a floating-point number in ACCU1. The result is anangle expressed in radians. The value will be in the following range: ��/ 2 � cosecant (ACCU 1) � + � / 2,when � = 3.14...

COS Form the cosine of the floating-point number of an angle expressed in radians. Store the angle as a floating-point number in ACCU1.

ACOS Form the arc cosine of a floating-point number in ACCU1. The result is anangle expressed in radians. The value will be in the following range:0 � secant (ACCU 1) � + �, when � = 3.14...

TAN Form the tangent of the floating-point number of an angle expressed in radians. Save the angle as a floating-point number in ACCU1.

ATAN Form the arc tangent of a floating-point number in ACCU1. The result is anangle expressed in radians. The value will be in the following range:��/ 2 � cotangent (ACCU 1) � + � / 2, when � = 3.14...

Table 10-12 shows the effect that the instructions SIN, ASIN, COS, ACOSand ATAN have on the signal state of bits CC 1, CC 0, OV and OS in thestatus word. Table 10-13 shows how TAN affects these bits. A hyphen (–)means that the bit in question is not affected by the instruction.

Table 10-12 Effects of Instructions SIN, ASIN, COS, ACOS and ATAN


+ qNaN 1 1 1 1

+ Valid 1 0 0 –


+ Zero 0 0 0 –

-Zero 0 0 0 –

- Not valid (Underflow) 0 0 1 1

- Valid 0 1 0 –

- qNaN 1 1 1 1

Description




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Table 10-13 Effects of Instruction TAN on Bits CC 1, CC 0, OV and OS


+ qNaN 1 1 1 1


+ Valid 1 0 0 –


+ Zero 0 0 0 –

-Zero 0 0 0 –

–-Not valid (Underflow) 0 0 1 1

-Valid 0 1 0 –

- Infinite (Overflow) 0 1 1 1

- qNaN 1 1 1 1

The following program extract is an example of how the instruction SIN isused.

STL Explanation


L MD10 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Load the value from memory double word MD10 into accumulator 1.(The value must be in floating-point format.)ÁÁÁÁÁÁÁÁ


SINÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Form the sine of the 32 bit IEEE floating-point number intoaccumulator 1. Store the result in accumulator 1.


T MD20 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Transfer the result from accumulator 1 into memory double wordMD20.

The following program extract is an example of how the instruction ASIN isused.

STL ExplanationÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

L MD10ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ



ASIN ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Form the cosecant of the 32 bit IEEE floating-point number inaccumulator 1. Store the result in accumulator 1.ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁAN OV

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Check that the status bit OV is 0.ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

JC OKÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

If operation ASIN has no errors, jump to the label OK.ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

...ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ



OK: T MD20 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Transfer the result from accumulator 1 into memory double wordMD20.

Example

Example



The extended math instructions affect the following bits in the status word:

� CC 1 and CC 0

� OV

� OS

A hyphen (–) entered in a bit column of the table means that the bit inquestion is not affected by the result of the floating-point math instruction.

Table 10-14 Inverse Functions for 32 Bit IEEE Floating-Point Numbers and ValidRanges for the Value Input

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Valid Range for a Floating-Point Result (32 Bits)ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Bits of Status Word


ÁÁÁÁ

CC 1ÁÁÁÁÁÁ

CC 0ÁÁÁÁÁÁ

OVÁÁÁÁÁÁ

OS

+0, -0 (zero) 0 0 0 –

-3.402823E+38 � Result � -1.175494E–38(negative number)

0 1 0 –

+1.175494E–38 � Result � 3.402823E+38(positive number)

1 0 0 –

Table 10-15 Signal States of the Bits in the Status Word: Calculation Result withFloating-Point Numbers outside the Valid Range



Bits of Status Word


ÁÁÁÁ

CC 1ÁÁÁÁÁÁ

CC 0ÁÁÁÁÁÁ

OVÁÁÁÁÁÁ

OS

-1.175494E–38 � Result � -1.401298E–45(negative number) Underflow

0 0 1 1

+1.401298E–45 � Result � +1.175494E–38(positive number) Underflow

0 0 1 1

Result � -3.402823E+38(negative number) Overflow

0 1 1 1

Result � -3.402823E+38(positive number) Overflow

1 0 1 1

Table 10-16 Signal States of the Bits in the Status Word: The Input Value Representsan Invalid Number or is outside the Valid Range



Bits of Status WordÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁ

CC 1ÁÁÁÁÁÁ

CC 0ÁÁÁÁÁÁ

OVÁÁÁÁÁÁ

OSÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

There is no valid 32-bit IEEE floating-point numberin ACCU 1.

ÁÁÁÁÁÁ

1ÁÁÁÁÁÁÁÁÁ

1ÁÁÁÁÁÁÁÁÁ

1ÁÁÁÁÁÁÁÁÁ

1

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Instruction not permitted: the input value in ACCU 1is outside the valid range.

ÁÁÁÁÁÁ

1ÁÁÁÁÁÁÁÁÁ

1ÁÁÁÁÁÁÁÁÁ

1ÁÁÁÁÁÁÁÁÁ

1

Evaluating the Bitsin the Status Word

Valid Result



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Comparison Instructions


11.1 Overview 11-2

11.2 Comparing Two Integers 11-3

11.3 Comparing Two Floating-Point Numbers 11-5

Chapter Overview

11


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11.1 Overview

You can use the Compare instructions to compare the following pairs ofnumeric values:

� Two integers (16 bits)

� Two double integers (32 bits)

� Two real numbers (IEEE floating-point, 32 bits)

You load the numeric values into accumulators 1 and 2. A Compareinstruction compares the value in accumulator 2 to the value inaccumulator 1 according to the criteria listed in Table 11-1.

The result of the comparison is a binary digit, that is, either a 1 or a 0. A 1indicates that the result of the comparison is true; a 0 indicates that the resultof the comparison is false (see Table 11-2). This result is stored in the resultof logic operation bit (RLO bit, see Section 3.4). You can use this result inyour program for further processing.

When the CPU executes a Compare instruction, it also sets bits in the statusword. Other statement list instructions can evaluate the bits of the statusword. The CPU executes Compare instructions without regard to the result oflogic operation.

Table 11-1 Criteria for Comparisons

Type of Numeric Value inAccumulator 2

Comparison Criterion Symbol(s) for Instruction Type of Numeric Valuein Accumulator 1

is equal to ==I==D==R

is not equal to <>I<>D<>R

Integer (16 bits)

Double integer (32 bits)

is greater than >I>D>R

Integer (16 bits)

Double integer (32 bits)g ( )

Real number (floating-point, 32 bits)

is less than <I<D<R

g ( )

Real number(floating-point, 32 bits)

is greater than or equal to >=I>=D>=R

is less than or equal to <=I<=D<=R



11.2 Comparing Two Integers

The Compare Integer instructions compare two single integers (16 bits each)and the Compare Double Integer instructions compare two double integers(32 bits each) according to the criteria listed in Table 11-2. A sampleprogram follows Table 11-3.

Table 11-2 Compare Integer and Compare Double Integer Instructions

Instruct ion ExplanationInstruct on Explanat on

==I

==D

The integer in the low word of accumulator 2 is equal to the integer in the low word of accumulator 1.The double integer in accumulator 2 is equal to the double integer in accumulator 1.

<>I

<>D

The integer in the low word of accumulator 2 is not equal to the integer in the low word ofaccumulator 1.The double integer in accumulator 2 is not equal to the double integer in accumulator 1.

>I

>D

The integer in the low word of accumulator 2 is greater than the integer in the low word ofaccumulator 1.The double integer in accumulator 2 is greater than the double integer in accumulator 1.

<I

<D

The integer in the low word of accumulator 2 is less than the integer in the low word of accumulator 1.The double integer in accumulator 2 is less than the double integer in accumulator 1.

>=I

>=D

The integer in the low word of accumulator 2 is greater than or equal to the integer in the low word of accumulator 1.The double integer in accumulator 2 is greater than or equal to the double integer in accumulator 1.

<=I

<=D

The integer in the low word of accumulator 2 is less than or equal to the integer in the low word of accumulator 1.The double integer in accumulator 2 is less than or equal to the double integer in accumulator 1.

Description



C79000-G7076-C565-01

A Compare Integer or Compare Double Integer instruction sets certaincombinations in the CC 1 and CC 0 bits to indicate what condition has beenfulfilled (see Table 11-3).

Table 11-3 Settings of Bits CC 1 and CC 0 after a Compare Instruction

Condition Signal states of CC 1 and CC 0: Possible checkwith the instructions

CC 1 CC 0 A, O, X, AN, ON, XN

ACCU 2 > ACCU 1 1 0 >0

ACCU 2 < ACCU 1 0 1 <0

ACCU 2 = ACCU 1 0 0 ==0

ACCU 2 <> ACCU 10or1

1or0

<>0

ACCU 2 >= ACCU 11or0

0or0

>=0

ACCU 2 <= ACCU 10or0

1or0

<=0

The following sample program shows how the Compare instructions forintegers (16 bits) work.

STL Explanation

L MW10

L IW0

==I

= Q 4.0

>I

= Q 4.1

<I

= Q 4.2

Load the contents of memory word MW10 into accumulator 1.

Load the contents of input word IW0 into accumulator 1. Theold contents of accumulator 1 are shifted to accumulator 2.

Compare the value in the low word of accumulator 2 to thevalue in the low word of accumulator 1 to see if they areequal.

Output Q 4.0 will be energized if MW10 and IW0 are equal.

Compare the value in the low word of accumulator 2 to seeif it is greater than the value in the low word ofaccumulator 1.

Output Q 4.1 will be energized if MW10 is greater than IW0.

Compare the value in the low word of accumulator 2 to seeif it is less than the value in the low word ofaccumulator 1.

Output Q 4.2 will be energized if MW10 is less than IW0.

Setting Bits CC 1and CC 0 of theStatus Word

Example



11.3 Comparing Two Floating-Point Numbers

The Compare Floating-Point Number instructions compare two 32-bit IEEEfloating-point numbers according to the criteria listed in Table 11-4. BecauseIEE 32-bit floating-point numbers belong to the data type called “REAL,”the mnemonic abbreviation for these instructions is R.

Table 11-4 Compare Real Instructions (IEEE 32-bit Floating-Point Numbers)

Instruct ion ExplanationInstruct on Explanat on

==R The IEEE 32-bit floating-point number in accumulator 2 is equal to theIEEE 32-bit floating-point number in accumulator 1.

<>R The IEEE 32-bit floating-point number in accumulator 2 is not equal tothe IEEE 32-bit floating-point number in accumulator 1.

>R The IEEE 32-bit floating-point number in accumulator 2 is greater thanthe IEEE 32-bit floating-point number in accumulator 1.

<R The IEEE 32-bit floating-point number in accumulator 2 is less than theIEEE 32-bit floating-point number in accumulator 1.

>=R The IEEE 32-bit floating-point number in accumulator 2 is greater thanor equal to the IEEE 32-bit floating-point number in accumulator 1.

<=R The IEEE 32-bit floating-point number in accumulator 2 is less than orequal to the IEEE 32-bit floating-point number in accumulator 1.

A Compare Real number instruction sets certain combinations in the CC 1,CC 0, OV, and OS bits of the status word to indicate what condition has beenfulfilled.

Table 11-5 Settings of Bits of the Status Word after a Compare Real Instruction(IEEE 32-bit Floating-Point Numbers)

Condition CC 1 CC 0 OV OS

== 0 0 0 not applicable

<>0or1

1or0

0 not applicable

> 1 0 0 not applicable

< 0 1 0 not applicable

>=1or0

0or0

0 not applicable

<=0or0

1or0

0 not applicable

UO 1 1 1 1

Description

Setting Bits of theStatus Word



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Other statement list instructions can evaluate the bits of the status word (seeSection 5.3 and Table 11-6).

Table 11-6 Instructions That Evaluate the CC 1, CC 0, OV, and OS Bits of the Status Word

Instruction Reference to Bits of the Status Word or JumpLabel

Section inthis Manual

A,O,X,AN,ON,XN >0, <0, <>0, >=0, <=0, ==0, UO, OV, OS 5.3

JUO <jump label> 16.4

JZ <jump label> 16.5

JN <jump label> 16.5

JP <jump label> 16.5

JM <jump label> 16.5

JMZ <jump label> 16.5

JPZ <jump label> 16.5

The following sample program shows how the Compare Real numberinstructions work.

STL Explanation

L MD24

L +1.00E+00

>R

= Q 4.1<R

= Q 4.2

Load the contents of memory double word MD24 intoaccumulator 1.Load the value 1 as a 32-bit floating-point number intoaccumulator 1.The old contents of accumulator 1 are shifted toaccumulator 2.Compare the value in accumulator 2 to see if it isgreater than the value in accumulator 1.Output Q 4.1 will be energized if MD24 is greater than 1.Compare the value in accumulator 2 to see if it is lessthan the value in accumulator 1.Output Q 4.2 will be energized if MD24 is less than 1.

Evaluating the Bitsof the Status Word

Example



Conversion Instructions


12.1 Converting Binary Coded Decimal Numbers and Integers 12-2

12.2 Converting 32-Bit Floating-Point Numbers to 32-BitIntegers

12-8

12.3 Reversing the Order of Bytes within Accumulator 1 12-13

12.4 Forming Complements and Negating Floating-PointNumbers

12-14

Chapter Overview

12


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12.1 Converting Binary Coded Decimal Numbers and Integers

You can use the following instructions to convert binary coded decimalnumbers and integers to other types of numbers:

Mne-monic


BTI BCD to Integer This instruction converts a binary coded decimal value in the low word of accumulator 1 to a 16-bit integer.

BTD BCD to DoubleInteger

This instruction converts a binary coded decimal value in accumulator 1 to a 32-bitinteger.

ITB Integer to BCD This instruction converts a 16-bit integer inthe low word of accumulator 1 to a binarycoded decimal value.

ITD Integer to DoubleInteger

This instruction converts a 16-bit integer inthe low word of accumulator 1 to a 32-bitinteger.

DTB Double Integer toBCD

This instruction converts a 32-bit integer inaccumulator 1 to a binary coded decimalvalue.

DTR Double Integer toReal

This instruction converts a 32-bit integer inaccumulator 1 to a 32-bit IEEE floating-pointnumber (real number).

Description



The BCD to Integer (BTI) instruction converts a three-place binary codeddecimal number (BCD number, see Figure 12-1) in the low word ofaccumulator 1 to a 16-bit integer. The BCD number can be in the range of-999 to +999. The result of the conversion is stored in the low word ofaccumulator 1.

Sign: 0000 stands for positive, 1111 stands for negative.

Value of the BCD number

15

102 101 100

14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

S S S S

Hundreds Tens Ones

These bits are not used during the transfer.

Figure 12-1 Structure of a Binary Coded Decimal Number to Be Converted toInteger

If a place of a BCD number is in the invalid range of 10 to 15, a BCDF erroroccurs during an attempted conversion. In this case, one of the followingoccurrences takes place:

� The CPU goes into the STOP mode. “BCD Conversion Error” is enteredin the diagnostic buffer with event ID number 2521.

� If OB121 is programmed, it is called.

The following sample program includes a BTI instruction. Figure 12-2 showshow this instruction works.

STL Explanation

L MW10BTI

T MW20

Load the BCD value in memory word MW10 into accumulator 1.Convert the BCD value to a 16-bit integer and store theresult in accumulator 1.Transfer the result to memory word MW20.

15... ...8 7... ...0

0 0 1 1

0 0 0 1 0 1 0 10 0 0 0

1 0 0 10 0 0 0

L MW10

BTI

T MW20 0 0 1 1

1 0 0 1

BCD to integer

“ + ” “ 9 ” “ 1 ” “ 5 ”

MW10

MW20

“+915” BCD

“+915” integer

Figure 12-2 Using the BTI Instruction to Convert a BCD Number to a 16-Bit Integer

BCD to Integer:BTI



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The BCD to Double Integer (BTD) instruction converts a seven-place binarycoded decimal number (BCD number, see Figure 12-3) in accumulator 1 to a32-bit integer. The BCD number can be in the range of -9,999,999 to+9,999,999. The result of the conversion is stored in accumulator 1.

If a place of a BCD number is in the invalid range of 10 to 15, a BCDF erroroccurs during an attempted conversion. In this case, either one of thefollowing occurrences takes place:

� The CPU goes into the STOP mode. “BCD Conversion Error” is enteredin the diagnostic buffer with event ID number 2521.

� If OB121 is programmed, it is called.

31... ...16 15... ...0

S S S S

106 105 104 103 102 101 100

Sign: 0000 stands for positive, 1111 stands for negative.

Value of the BCD number

These bits are not used during the transfer.

Figure 12-3 Structure of a 32-Bit BCD Number to Be Converted to Double Integer

The following sample program includes a BTD instruction. Figure 12-4shows how this instruction works.

STL Explanation

L MD10

BTD

T MD20

Load the BCD value in memory double word MD10 intoaccumulator 1.Convert the BCD value to a 32-bit integer and store theresult in accumulator 1.Transfer the result to memory double word MD20.

31... ...16 15... ...0

0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 0 0 0 1

0 1 1 10 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 1 0 0 0 1 1 0 1

L MD10

BTD

T MD20

BCD to integer

“ + ” “ 0 ” “ 1 ” “ 5 ”

MD10

MD20

“157821”

“+157821”

“ 7 ” “ 8 ” “ 2 ” “ 1 ”

Figure 12-4 Using the BTD Instruction to Convert a BCD Number to a 32-Bit Integer

BCD to DoubleInteger: BTD



The Integer to BCD (ITB) instruction converts a 16-bit integer in the lowword of accumulator 1 to a three-place binary coded decimal number. TheBCD number can be in the range of -999 to +999. The result of theconversion is stored in the low word of accumulator 1.

If the integer is too large to be represented in BCD format, no conversiontakes place and the overflow (OV) and stored overflow (OS) bits of the statusword (see Section 3.4) are set to a signal state of 1.

The following sample program includes an ITB instruction. Figure 12-5shows how this instruction works.

STL Explanation

L MW10

ITB

T MW20

Load the 16-bit integer value in memory word MW10 intoaccumulator 1.Convert the 16-bit integer to a BCD value and store theresult in accumulator 1.Transfer the result to memory word MW20.

15... ...8 7... ...0

0 1 0 0

0 1 1 0 0 0 1 11 1 1 1

0 0 0 11 1 1 1

L MW10

ITB

T MW20 0 0 1 1

1 1 1 0

Integer to BCD

“ – ” “ 4 ” “ 1 ” “ 3 ”

MW10

MW20 “-413” BCD

“-413” integer

Figure 12-5 Using the ITB Instruction to Convert a 16-Bit Integer to a BCD Number

Integer to BCD:ITB



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The Integer to Double Integer (ITD) instruction converts a 16-bit integer inthe low word of accumulator 1 to a 32-bit integer. The result of theconversion is stored in accumulator 1. The following sample programincludes an ITD instruction. Figure 12-6 shows how this instruction works.

STL Explanation

L MW10

ITD

T MD20

Load the 16-bit integer value in memory word MW10 intoaccumulator 1.Convert the 16-bit integer value to a 32-bit integer andstore the result in accumulator 1.Transfer the result to memory double word MD20.

15... ...0

1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0

1 1 1 1 0 1 1 0

L MW10

ITD

T MD20

Integer (16-bit) to integer (32-bit)

MW10

MD20

“-10”integer

“-10”integer

31... ...16 15... ...0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Figure 12-6 Using the ITD Instruction to Convert a 16-Bit Integer to a 32-Bit Integer

The Double Integer to BCD (DTB) instruction converts a 32-bit integer inaccumulator 1 to a seven-place binary coded decimal value. The BCDnumber can be in the range of -9,999,999 to +9,999,999. The result of theconversion is stored in accumulator 1.

If the double integer is too large to be represented in BCD format, noconversion takes place and the overflow (OV) and stored overflow (OS) bitsof the status word (see Section 3.4) are set to a signal state of 1.

The following sample program includes a DTB instruction. Figure 12-7shows how this instruction works.

STL Explanation

L MD10

DTB

T MD20

Load the 32-bit integer in memory double word MD10 intoaccumulator 1.Convert the 32-bit integer to a BCD value and store theresult in accumulator 1.Transfer the result to memory double word MD20.

31... ...16 15... ...0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 0 0 0 1 1

0 0 0 01 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1

L MD10

DTB

T MD20

Integer to BCD

“ – ” “ 0 ” “ 0 ” “ 0 ”

MD10

MD20

“-701”integer

“-701”BCD

“ 0 ” “ 7 ” “ 0 ” “ 1 ”

Figure 12-7 Using the DTB Instruction to Convert a 32-Bit Integer to a BCD Number

Integer to DoubleInteger: ITD

Double Integer toBCD: DTB



The Double Integer to Real (DTR) instruction converts a 32-bit integer inaccumulator 1 to a 32-bit IEEE floating-point number (real number). Ifnecessary, the instruction rounds the result. The result of the conversion isstored in accumulator 1. The following sample program includes an DTRinstruction. Figure 12-8 shows how this instruction works.

STL Explanation

L MD10

DTR

T MD20

Load the 32-bit integer in memory double word MD10 intoaccumulator 1.Convert the 32-bit integer to a 32-bit IEEEfloating-point value and store the result inaccumulator 1.Transfer the result to memory double word MD20.

31 ...0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0

0

L MD10

DTR

T MD20

Integer (32-bit) to IEEE floating-point

1 bitSign of the mantissa

8-bit exponent23-bit mantissa

MD10

MD20

“+500”integer

“+500”IEEE

30... 22...

0 0 1 1 0 0 0 00 0 0 00 0 0 00 0 0 01 0 1 01 1 111 0 0

Figure 12-8 Using the DTR Instruction to Convert a 32-Bit Integer to an IEEE 32-Bit Floating-Point Number

For a summary of the number conversions, see Figure 12-13 at the end ofSection 12.2.

Double Integer toReal: DTR



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12.2 Converting 32-Bit Floating-Point Numbers to 32-Bit Integers

You can use any of the following instructions to convert a 32-bit IEEEfloating-point number in accumulator 1 to a 32-bit integer (double integer).The individual instructions differ in their method of rounding.

Mne-monic


RND Round This instruction rounds the converted num-ber to the nearest whole number. If the frac-tional part of the converted number is mid-way between an even and an odd result, theinstruction chooses the even result.

RND+ Round to UpperDouble Integer

This instruction rounds the converted num-ber to the smallest whole number greaterthan or equal to the floating-point numberthat is converted.

RND- Round to LowerDouble Integer

This instruction rounds the converted num-ber to the largest whole number less than orequal to the floating-point number that isconverted.

TRUNC Truncate This instruction converts the whole numberpart of the floating-point number.

The result of the conversion is stored in accumulator 1. If the number to beconverted is not a floating-point number or is a floating-point number thatcannot be represented as a 32-bit integer, no conversion takes place and anoverflow is indicated.

Description



The Round (RND) instruction converts a 32-bit IEEE floating-point numberin accumulator 1 to a 32-bit integer (double integer) and rounds it to thenearest whole number. If the fractional part of the converted number ismidway between an even and an odd result, the instruction chooses the evenresult. The following sample program includes an RND instrruction.Figure 18-9 shows how this instruction works.

STL Explanation

L MD10

RND

T MD20

Load the 32-bit IEEE floating-point value in memorydouble word MD10 into accumulator 1.Convert the 32-bit floating-point number to a 32-bitinteger, round to the nearest whole number, and store theresult in accumulator 1.Transfer the result to memory double word MD20.

31 ...0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0

0

T MD20

RND

L MD10

IEEE to integer (32-bit)

MD20

MD10

“+100”integer

“+100.5”IEEE

30... 22...

31 ...0

1 1 1 1 1 0 0 1 1 1 0 0

1

T MD20

RND

L MD10


MD20

MD10

“-100”integer

“-100.5”IEEE

30... 22...

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 0 0 0 0 1 0 0 0 0 00 0 0 00 0 0 00 0 0 01 0 0 11 0 01

1 0 0 0 0 1 0 0 0 0 00 0 0 00 0 0 00 0 0 01 0 0 11 0 01

Figure 12-9 Using the RND Instruction to Convert an IEEE 32-Bit Floating-Point Number to a 32-Bit Integer

Round: RND



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The Round to Upper Double Integer (RND+) instruction converts a 32-bitIEEE floating-point number in accumulator 1 to a 32-bit integer (doubleinteger). The instruction rounds the converted number to the smallest wholenumber greater than or equal to the floating-point number that is converted.The following sample program includes an RND+ instruction. Figure 12-10shows how this instruction works.

STL Explanation

L MD10

RND+

T MD20

Load the 32-bit IEEE floating-point value in memorydouble word MD10 into accumulator 1.Convert the 32-bit floating-point number to a 32-bitinteger. Round to the smallest whole number greater thanor equal to the floating-point number that is convertedand store the result in accumulator 1.Transfer the result to memory double word MD20.

31 ...0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1

0

T MD20

RND+

L MD10


MD20

MD10

“+101”integer

“+100.5”IEEE

30... 22...

31 ...0

1 1 1 1 1 0 0 1 1 1 0 0

1

T MD20

RND+

L MD10


MD20

MD10

“-100”integer

“-100.5”IEEE

30... 22...

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 0 0 0 0 1 0 0 0 0 00 0 0 00 0 0 00 0 0 01 0 0 11 0 01

1 0 0 0 0 1 0 0 0 0 00 0 0 00 0 0 00 0 0 01 0 0 11 0 01

Figure 12-10 Using the RND+ Instruction to Convert an IEEE 32-Bit Floating-Point Number to a 32-Bit Integer

Round to UpperDouble Integer:RND+



The Round to Lower Double Integer (RND-) instruction converts a 32-bitIEEE floating-point number in accumulator 1 to a 32-bit integer (doubleinteger). The instruction rounds the converted number to the largest wholenumber less than or equal to the floating-point number that is converted. Thefollowing sample program includes an RND- instruction. Figure 12-11 showshow this instruction works.

STL Explanation

L MD10

RND–

T MD20

Load the 32-bit IEEE floating-point value in memorydouble word MD10 into accumulator 1.Convert the 32-bit floating-point number to a 32-bitinteger. Round to the largest whole number less than orequal to the floating-point number that is converted andstore the result in accumulator 1.Transfer the result to memory double word MD20.

31 ...0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0

0

T MD20

RND–

L MD10


MD20

MD10

“+100”integer

“+100.5”IEEE

30... 22...

31 ...0

1 1 1 1 1 0 0 1 1 0 1 1

1

T MD20

RND–

L MD10


MD20

MD10

“-101”integer

“-100.5”IEEE

30... 22...

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 0 0 0 0 1 0 0 0 0 00 0 0 00 0 0 00 0 0 01 0 0 11 0 01

1 0 0 0 0 1 0 0 0 0 00 0 0 00 0 0 00 0 0 01 0 0 11 0 01

Figure 12-11 Using the RND– Instruction to Convert an IEEE 32-Bit Floating-Point Number to a 32-Bit Integer

Round to LowerDouble Integer:RND-



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The Truncate (TRUNC) instruction converts a 32-bit IEEE floating-pointnumber in accumulator 1 to a 32-bit integer (double integer). The instructionconverts the whole number part of the floating-point number. The followingsample program includes a TRUNC instruction. Figure 12-12 shows how thisinstruction works.

STL Explanation

L MD10

TRUNC

T MD20

Load the 32-bit IEEE floating-point value in memory double word MD10into accumulator 1.Convert the 32-bit floating-point number to a 32-bit integer. Roundto the largest whole number less than or equal to the floating-pointnumber that is converted and store the result in accumulator 1.Transfer the result to memory double word MD20.

31 ...0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0

0

T MD20

TRUNC

L MD10


MD20

MD10

“+100”integer

“+100.5”IEEE

30... 22...

31 ...0

1 1 1 1 1 0 0 1 1 1 0 0

1

T MD20

TRUNC

L MD10


MD20

MD10

“-100”integer

“-100.5”IEEE

30... 22...

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 0 0 0 0 1 0 0 0 0 00 0 0 00 0 0 00 0 0 01 0 0 11 0 01

1 0 0 0 0 1 0 0 0 0 00 0 0 00 0 0 00 0 0 01 0 0 11 0 01

Figure 12-12 Using the TRUNC Instruction to Convert an IEEE 32-Bit Floating-Point Number to a 32-Bit Integer

Figure 12-13 summarizes number conversions and rounding (see alsoSections 12.1 and 12.2).

16-bit

32-bit

32-bitIEEE

3-place

7-place

BCD BTI Integer FloatingITB

BTDDTB

ITD

DTR

RND, RND+, RND–,TRUNC

Figure 12-13 Overview of Number Conversions and Rounding

Truncate: TRUNC

Summary ofNumberConversions



12.3 Reversing the Order of Bytes within Accumulator 1

You can use the following Change Bit Sequence in Accumulator 1instructions to reverse the order of bytes in the low word of accumulator 1 orin the entire accumulator:

� Change Byte Sequence in Accumulator 1, 16 bits (CAW)

� Change Byte Sequence in Accumulator 1, 32 bits (CAD)

CAW inverts the order of bytes in the low word of accumulator 1 (seeFigure 12-14).

31... ...16 15... ...0

0 1 0 1MD10

MD20

1 1 1 1 1 0 1 0 0 0 0 0 1 1 1 1 1 0 1 0 0 1 0 1 0 0 0 0L MD10

T MD20

CAW

0 1 0 1 1 1 1 1 1 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 1 1 1 0 1 0

Figure 12-14 Using CAW to Reverse Byte Order in the Low Word of Accumulator 1

CAD inverts the byte order in all of accumulator 1 (see Figure 12-15).

31... ...16 15... ...0

0 1 0 1MD10

MD20

1 1 1 1 1 0 1 0 0 0 0 0 1 1 1 1 1 0 1 0 0 1 0 1 0 0 0 0L MD10

T MD20

CAD

0 1 0 1 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0 0 0 1 0 1 1 1 1 11 0 1 0

Figure 12-15 Using CAD to Reverse Byte Order in Accumulator 1

Description

CAW

CAD



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12.4 Forming Complements and Negating Floating-Point Numbers

Forming the ones complement of a number in the accumulator inverts thenumber bit by bit, that is, zeros are replaced by ones and ones are replaced byzeros.

Forming the twos complement of an integer in the accumulator also invertsthe number bit by bit, that is, zeros are replaced by ones and ones arereplaced by zeros. Then a +1 is added to the contents of the accumulator.Forming the twos complement of an integer is the same as multiplying thenumber by a -1. Negating a real number inverts the sign bit.

You can use one of the following instructions to form the complement of aninteger or to invert the sign of a floating-point number:

Mne-monic


INVI Ones ComplementInteger

This instruction forms the ones complement of the16-bit value in the low word of accumulator 1. Theresult is stored in the low word of accumulator 1(see Figure 12-16).

INVD Ones ComplementDouble Integer

This instruction forms the ones complement of the32-bit value in accumulator 1. The result is stored inaccumulator 1.

NEGI Twos ComplementInteger

This instruction forms the twos complement of the16-bit value in the low word of accumulator 1, thatis, it multiplies it by -1. The result is stored in thelow word of accumulator 1 (see Figure 12-17). Inthe status word (see Section 3.4), NEGI sets theCC 1, CC 0, OV and OS bits.

NEGD Twos ComplementDouble Integer

This instruction forms the twos complement of the32-bit value in accumulator 1, that is, it multiplies itby -1. The result is stored in accumulator 1. In thestatus word (see Section 3.4), NEGI sets the CC 1,CC 0, OV and OS bits.

NEGR Negate Floating-Point Number

This instruction inverts the sign bit of the 32-bitIEEE floating-point value in accumulator 1 (see Fig-ure 12-18).

Description



Statement List Program

Bit Patterns

L DBW30 Load the value of data word DBW30 into the low word of accumulator 1.INVI Form the ones complement of the value in the low word of accumulator 1.T DBW32 Transfer the contents of the low word of accumulator 1 to data word DBW32.

0 1 0 1L DBW30

T DBW32

INVI Ones Complement Integer

1 1 0 1 0 0 1 1 1 0 0 0

1 0 1 0 0 0 1 0 1 1 0 0 0 1 1 1

Figure 12-16 Forming the Ones Complement of a 16-Bit Integer


Bit Patterns

L DBW40 Load the value of data word DBW40 into the low word of accumulator 1.NEGI Form the twos complement of the value in the low word of accumulator 1.T DBW42 Transfer the contents of the low word of accumulator 1 to data word DBW42.

0 1 0 1L DBW40

T DBW42

NEGI Twos Complement Integer

1 1 0 1 0 0 1 1 1 0 0 0

1 0 1 0 0 0 1 0 1 1 0 0 1 0 0 0

“23,864”integer

“-23,864”integer

Figure 12-17 Forming the Twos Complement of a 16-Bit Integer



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1 0 0 0 0 00 0 0 00 0 0 000 0 000 0 01 10 00 0 01 0 0

0 0 0 00 0 0 00 0 0 00 0 0 00 0 0 00100100 0000 1

0 0

037 481112Bits

Sign ofMantissa: s(1 bit)

151619202324272831

Exponent: e(8 bits)

e = 27 + 21 = 1301.f � 2e–bias = 1.25 � 23 = 10.0[1.25 � 2(130–127) = 1.25 � 23 = 10.0]

Mantissa or fraction: f(23 bits)

f = 2–2 = 0.25

1 0 0 0 1 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Hexadecimalvalue 4 1 2 0 0 0 0 0

Decimal value 10.0


L DBD62 Load the value of data double word DBD62 into accumulator 1.NEGR Invert the sign of the value in accumulator 1.T DBD66 Transfer the contents of accumulator 1 to data double word DBD66.

L DBD62

T DBD66

NEGR Negate Floating-Point Number

Sign of Mantissa (0 = positive, 1 = negative)

Figure 12-18 Inverting the Sign of a Floating-Point Number



Word Logic Instructions


13.1 Overview 13-2

13.2 16-Bit Word Logic Instructions 13-3

13.3 32-Bit Word Logic Instructions 13-6

Chapter Overview

13


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13.1 Overview

Word logic instructions combine pairs of words (16 bits) or double words(32 bits) bit by bit according to Boolean logic. Each word or double wordmust be in one of the two accumulators.

For words, the contents of the low word of accumulator 2 is combined withthe contents of the low word of accumulator 1. The result of the combinationis stored in the low word of accumulator 1, overwriting the old contents.

For double words, the contents of accumulator 2 is combined with thecontents of accumulator 1. The result of the combination is stored inaccumulator 1, overwriting the old contents.

If the result of the logic combination is 0, the CC 1 bit of the status word isreset to 0. If the result of the logic combination is not 0, CC 1 is set to 1. Inany case, the CC 0 and OV bits of the status word are reset to 0.

The following instructions are available for performing word logicoperations:

Mnemonic Instruction Function

AW And Word Combines two words bit by bitaccording to the And truth table

OW Or Word Combines two words bit by bit according to the Or truth table

XOW Exclusive Or Word Combines two words bit by bit according to the Exclusive Ortruth table

AD And Double Word Combines two double words bitby bit according to the And truthtable

OD Or Double Word Combines two double words bitby bit according to the Or truthtable

XOD Exclusive Or DoubleWord

Combines two double words bitby bit according to the ExclusiveOr truth table

An AW, OW, or XOW instruction can use a 16-bit constant as its address.The instruction combines the contents of the low word of accumulator 1 withthe 16-bit constant.

An AD, OD, or XOD instruction can use a 32-bit constant as its address.

Description

AccumulatorAdministration

Influence on Bitsof the Status Word


Constants asAddresses



13.2 16-Bit Word Logic Instructions

The And Word, Or Word, and Exclusive Or Word instructions (AW, OW,XOW) combine pairs of words (16 bits) bit by bit according to Booleanlogic.

Mnemonic Instruction RLO BeforeLogic Operation

Address Result inRLO

AW And Word 0011

0101

0001

OW Or Word 0011

0101

0111

XOW Exclusive OrWord

0011

0101

0110

For the instructions that combine 16-bit words, the contents of the low wordof accumulator 2 is combined with the contents of the low word ofaccumulator 1. The result of the logic combination is stored in the low wordof accumulator 1, overwriting the old contents. The contents of the high wordof accumulator 1 and both words of accumulator 2 remain unchanged (seeFigure 13-1).

Accumulator 2

Accumulator 1

Accumulator 2

Accumulator 1

31 016 15

31 016 15

III

II I

IV III

AW, OW, XOW

II III c. I

Accumulator contentsbefore word logic operation

Accumulator contentsafter word logic operation

CombinationIV

c = combined with

Figure 13-1 Combining the Contents of the Low Words of Accumulators 2 and 1

Description

Relationship toAccumulators



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The following sample program includes an AW instruction. Figure 13-2shows how this instruction works.

STL Explanation

L MW10

L MW20

AW

T MW24

Load the contents of memory word MW10 into accumulator 1.

Load the contents of memory word mW20 into accumulator 1.The old contents of accumulator 1 are shifted toaccumulator 2.The contents of the low word of accumulator 2 arecombined bit by bit with the contents of the low word ofaccumulator 1 according to the AND truth table. Theresult is stored in the low word of accumulator 1.Transfer the contents of accumulator 1 to memory wordMW24.

15... ...8 7... ...0

0 1 0 1 1 1 1 0 1 0 1 0

1 0 1 0 0 1 0 1 0 1 1 1

0 1 1 0

1 0 1 0

0 0 0 0 0 1 0 0 0 0 1 00 0 1 0

MW10

MW20

MW24

AND bit by bit

Figure 13-2 Combining Two Words Using the AW Instruction

An AW, OW, or XOW instruction can use a 16-bit constant as its address.The instruction combines the contents of the low word of accumulator 1 withthe 16-bit constant that is indicated in the instruction statement. The result ofthe combination is stored in the low word of accumulator 1. Accumulator 2and the high word of accumulator 1 remain unchanged (see Figure 13-3).

Accumulator 2

Accumulator 1

Accumulator 2

Accumulator 1

31 016 15

31 016 15

IV III

II I

IV III

AW2#, OW2#,XOW2#

II I c. 2#



Combination

c = combined with

Figure 13-3 Combining the Low Word of Accumulator 1 with a 16-Bit Constant

Example of an AWInstruction

CombiningAccumulator andConstant



The following sample program includes an AW instruction that makes a logiccombination with a 16-bit constant that is indicated in the instructionstatement. Figure 13-4 shows how this instruction works.

STL Explanation

L MW10

AW 2#1010_1010_0101_0101

T MW24

Load the contents of memory word MW10 intoaccumulator 1.The contents of the low word of accumulator 1 arecombined bit by bit with 1010_1010_0101_0101according to the AND truth table. The result isstored in the low word of accumulator 1.Transfer the contents of accumulator 1 to memoryword MW24.

15... ...8 7... ...0

0 0 0 0

1 1 1 0 1 0 1 0

1 0 1 0 0 1 0 1

0 1 1 0

1 0 1 0

0 1 0 01 0 1 0

0 1 0 1

0 0 0 0

0 1 0 1MW10

Value of AW statement

MW24

AND Bit by Bit

Figure 13-4 Using an AW Instruction with a 16-Bit Constant

Example of an AWInstruction withConstant



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13.3 32-Bit Word Logic Instructions

The And Double Word, Or Double Word, and Exclusive Or Double Wordinstructions (AD, OD, XOD) combine pairs of words (32 bits) bit by bitaccording to Boolean logic.

Mnemonic Instruction RLO BeforeLogic Operation

Address Resultin RLO

AD And DoubleWord

0011

0101

0001

OD Or Double Word 0011

0101

0111

XOD Exclusive OrDouble Word

0011

0101

0110

For the instructions that combine double words, the contents ofaccumulator 2 is combined with the contents of accumulator 1. The result ofthe logic combination is stored in accumulator 1, overwriting the oldcontents. The contents of accumulator 2 remains unchanged (seeFigure 13-5).

31 016 15

31 016 15

IV III

II I

IV III

IV c. II

Accumulator 2

Accumulator 1

Accumulator 2

Accumulator 1AD, OD, XOD

III c. I



Combination

c = combined with

Figure 13-5 Combining the Contents of Accumulators 2 and 1

Description

Relationship toAccumulators



The following sample program includes an AD instruction. Figure 13-6shows how this instruction works.

STL Explanation

L MD10

L MD20

AD

T MD24

Load the contents of memory double word MD10 intoaccumulator 1.Load the contents of memory double word mD20 intoaccumulator 1. The old contents of accumulator 1 areshifted to accumulator 2.The contents of accumulator 2 are combined bit by bitwith the contents of accumulator 1 according to the ANDtruth table. The result is stored in accumulator 1.Transfer the contents of accumulator 1 to memory doubleword MD24.

0 1 0 1

31... ...16 15... ...0

0 1 1 0MD10

MD20

MD24

AND bit by bit

1 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1

1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1

0 0 0 00 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

Figure 13-6 Using an AD Instruction

An AD, OD, or XOD instruction can use a 32-bit constant as its address. Theinstruction combines the contents of accumulator 1 with the 32-bit constantthat is indicated in the instruction statement. The result of the combination isstored in accumulator 1. Accumulator 2 remains unchanged (seeFigure 13-7).

31 016 15

31 016 15

IV III

II I

IV III

AD, OD, XODDW#16#

IIc.DW#16#Ic.DW#16#

Accumulator 2

Accumulator 1


Combination

c=combined with

Accumulator 2

Accumulator 1

Accumulator contents afterword logic operation

Figure 13-7 Combining Accumulator 1 with a 32-Bit Constant

Example of an ADInstruction

CombiningAccumulator andConstant



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The following sample program includes an AD instruction that makes a logiccombination with a 32-bit constant that is indicated in the instructionstatement. Figure 13-8 shows how this instruction works.

STL Explanation

L MD10

AD DW#16#AAAA_5555

T MD24

Load the contents of memory double word MD10 intoaccumulator 1.The contents of accumulator 1 are combined bit by bitwith DW#16#AAAA_5555 according to the AND truth table.The result is stored in accumulator 1.Transfer the contents of accumulator 1 to memory doubleword MD24.

0 1 0 1

31... ...16 15... ...0

0 1 1 0MD10

Value of AD statement

MD24

AND bit by bit

1 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1

1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1

0 0 0 00 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

Figure 13-8 Using an AD Instruction with a 32-Bit Constant

Example of an ADInstruction withConstant



Shift and Rotate Instructions


14.1 Shift Instructions 14-2

14.2 Rotate Instructions 14-6

Chapter Overview

14


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14.1 Shift Instructions

You can use the Shift instructions to move the contents of the low word ofaccumulator 1 or the contents of the whole accumulator bit by bit to the leftor the right. Shifting by n bits to the left multiplies the contents of theaccumulator by “2n”; shifting by n bits to the right divides the contents of theaccumulator by “2n”. For example, if you shift the binary equivalent of thedecimal value 3 to the left by 3 bits, you end up with the binary equivalent ofthe decimal value 24 in the accumulator. If you shift the binary equivalent ofthe decimal value 16 to the right by 2 bits, you end up with the binaryequivalent of the decimal value 4 in the accumulator.

The number that follows the shift instruction or a value in the low byte of thelow word of accumulator 2 indicates the number of bits by which to shift.The bit places that are vacated by the shift instruction are either filled withzeros or with the signal state of the sign bit (a 0 stands for positive and a 1stands for negative). The bit that is shifted last is loaded into the CC 1 bit ofthe status word (see Figure 2-7). The CC 0 and OV bits of the status word arereset to 0. You can use jump instructions to evaluate the CC 1 bit.

The shift operations are unconditional, that is, their execution does notdepend on any special conditions. They do not affect the result of logicoperation.

The following instruction shift the contents of the low word of accumulator 1bit by bit to the left or right:

� Shift Left Word (SLW, 16 bits)

� Shift Right Word (SRW, 16 bits)

The following instructions shift the entire contents of accumulator 1 bit bybit to the left or right:

� Shift Left Double Word (SLD, 32 bits)

� Shift Right Double Word (SRD, 32 bits)

In all cases, the free bit positions are filled with a 0,

The following sample program and Figure 14-1 provide an example of howthe SLW instruction works. Table 14-1 provides a summary of all the Shiftinstructions.

STL Explanation

L MW10

SLW 6

T MW20

Load the contents of memory word MW10 into the low word ofaccumulator 1.Shift the bits of the low word in accumulator 1 six placesto the left.Transfer the contents of the low word of accumulator 1 tomemory word MW20.

Shift Instructions

Shift Functions:UnsignedNumbers

Shift Left Word:SLW



15... ...8 7... ...0

0 1 0 1

0 1 0 1 0 1 0 10 0 0 0

0 1 0 01 1 0 1 0 0 0 0

1 1 1 1

0 0 0 0 1 1

6 places

These five bitsare lost.

The bit that is shifted out last is storedin the CC 1 bit of the status word.

The vacated placesare filled with zeros.

Figure 14-1 Shifting Bits of the Low Word of Accumulator 1 Six Bits to the Left

The following sample program and Figure 14-2 provide an example of howthe SRW instruction works. Table 14-1 provides a summary of all the Shiftinstructions.

STL Explanation

L +3L MD10

SRDT MD20

Load the value +3 into accumulator 1.Load the contents of memory double word MD10 intoaccumulator 1. The old contents of accumulator 1 (+3) ismoved to accumulator 2.Shift the bits in accumulator 1 three places to the right.Transfer the contents of accumulator 1 to memory doubleword MD20.

1 1 1

31... ...16 15... ...0

1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1

0 1 0 10 0 0 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 0 1 0 1 1 1 1 1

3 places

The vacated placesare filled with zeros. The bit that is shifted out

last is stored in the CC 1bit of the status word.

These twobits are lost.

Figure 14-2 Shifting Bits of Accumulator 1 Three Bits to the Right

Shift Right DoubleWord (32 Bits):SRD



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The Shift Sign Integer (SSI, 16 bits) instruction shifts the contents of the lowword of accumulator 1 bit by bit to the right, including sign, as described inthe overview of this chapter:

The Shift Sign Double Integer (SSD, 32 bits) instruction shifts the entirecontents of accumulator 1 bit by bit to the right, including sign.

The shift bit is copied into the free bit positions.

The following sample program and Figure 14-3 provide an example of howthe SSI instruction works. Table 14-1 provides a summary of all the Shiftinstructions.

STL Explanation

L MW10

SSI 4

T MW20

Load the contents of memory word MW10 into the low wordof accumulator 1.Shift the bits in the low word of accumulator 1,including sign, four places to the right.Transfer the contents of the low word of accumulator 1 tomemory word MW20.

15... ...8 7... ...0

1 0 1 0

0 0 0 0 1 0 1 01 0 1 0

1 1 1 11 1 1 1 0 0 0 0

1 1 1 1

4 places

The bit that is shifted out last is storedin the CC 1 bit of the status word.

The vacated places arefilled with the signalstate of the sign bit.

1 0 1 0

These threebits are lost.

Sign bit

Figure 14-3 Shifting Bits of the Low Word of Accumulator 1 Four Bits to the Right with Sign

Shift Functions:Signed Numbers

Shift Sign Integer:SSI



Table 14-1 Overview of Shift Instructions

Instruction Area Affected Direction Indication of Number ofPlaces to Shift

Filler forVacatedPlaces

ShiftRange1

SLW n Low word ofaccumulator 1

Left In the instructionstatement

0 n=0 to 15

SLW Low word ofaccumulator 1

Left In the low byte of the lowword of accumulator 2

0 0 to 2552

SLD n Accumulator 1 Left In the instructionstatement

0 n=0 to 32

SLD Accumulator 1 Left In the low byte of the lowword of accumulator 2

0 0 to 2553

SRW n Low word ofaccumulator 1

Right In the instructionstatement

0 n=0 to 15

SRW Low word ofaccumulator 1

Right In the low byte of the lowword of accumulator 2

0 0 to 2552

SRD n Accumulator 1 Right In the instructionstatement

0 n=0 to 32

SRD Accumulator 1 Right In the low byte of the lowword of accumulator 2

0 0 to 2553

SSI n Low word ofaccumulator 1

Right In the instructionstatement

Sign bit n=0 to 15

SSI Low word ofaccumulator 1

Right In the low byte of the lowword of accumulator 2

Sign bit 0 to 2554

SSD n Accumulator 1 Right In the instructionstatement

Sign bit n=0 to 32

SSD Accumulator 1 Right In the low byte of the lowword of accumulator 2

Sign bit 0 to 2555

1 If the number of bits by which to shift or rotate is 0, the instruction is executed like a NOP.2 For shift numbers greater than 16, the result of the shift function is W#16#0000 and CC 1 = 0.3 For shift numbers greater than 32, the result of the shift function is DW#16#0000_0000 and CC 1 = 0.4 For shift numbers greater than 15, the result of the shift function is W#16#0000 and CC 1 = 0 or W#16#FFFF and

CC 1 = 1 depending on the sign (0 or 1).5 For shift numbers greater than 31, the result of the shift function is DW#16#0000_0000 (CC 1 = 0) or

DW#16#FFFF_FFFF (CC 1 = 1) depending on the sign of the number of bits to be shifted.



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14.2 Rotate Instructions

You can use the Rotate instructions to rotate the entire contents ofaccumulator 1 bit by bit to the left or to the right. The Rotate instructionstrigger functions that are similar to the shift functions described inSection 14.1. However, the vacated bit places are filled with the signal statesof the bits that are shifted out of the accumulator.

The number that follows the rotate instruction or a value in the low byte ofthe low word of accumulator 2 indicates the number of bits by which torotate.

Depending on the instruction, rotation takes place via the CC 1 bit of thestatus word (see Section 2.2). The CC 0 bit of the status word is reset to 0.

The following Rotate instructions are available:

� Rotate Left Double Word (RLD)

� Rotate Right Double Word (RRD)

� Rotate Accumulator 1 Left via CC 1 (RLDA)

� Rotate Accumulator 1 Right via CC 1 (RRDA)

If the number of bits that are rotated is 0, then the instruction is carried out asa Null Operation (NOP).

Table 14-2 Overview of the Rotate Instructions

Instruction Rotate via CC 1? Direction Indication of Number of Places to Shift Shift Range

RLD n No Left In the instruction statement n=0 to 32

RLD No Left In the low byte of the low word ofaccumulator 2

0 to 255

RRD No Right In the instruction statement 0 to 32

RRD No Right In the low byte of the low word ofaccumulator 2

0 to 255

RLDA Yes Left 1 (fixed)

RRDA Yes Right 1 (fixed)

Description



Table 14-2 provides a summary of all the Rotate instructions. The followingsample program and Figure 14-4 provide an example of how the RLDinstruction works.

STL Explanation

L MD10

RLD 3T MD20

Load the contents of memory double word MD10 intoaccumulator 1.Rotate the bits in accumulator 1 three places to the left.Transfer the contents of accumulator 1 to memory doubleword MD20.

1 1 1

31... ...16 15... ...0

1 1 1 1 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 1 1 11 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1

3 places

The three bits that are shiftedout are inserted in the vacatedplaces.

The last bit shifted isalso stored in CC 1.

Figure 14-4 Rotating Bits of Accumulator 1 Three Bits to the Left

The following sample program and Figure 14-5 provide an example of howthe RRD instruction works.

STL Explanation

L +3L MD10

RRDT MD20

Load the value +3 into accumulator 1.Load the contents of memory double word MD10 intoaccumulator 1. The old contents of accumulator 1 (+3) ismoved to accumulator 2.Rotate the bits in accumulator 1 three places to the right.Transfer the contents of accumulator 1 to memory doubleword MD20.

Rotate Left DoubleWord: RLD

Rotate RightDouble Word: RRD



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1 0 1

31... ...16 15... ...0

1 0 1 0 1 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 1

1 1 1 01 0 1 1 0 1 0 1 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 1 0

3 places


The three bits that areshifted out are insertedin the vacated places.

Figure 14-5 Rotating Bits of Accumulator 1 Three Bits to the Right

Figure 14-6 shows an example of how the RLDA instruction works.

X

1

31... ...16 15... ...0

1 0 1 0 1 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 1

1 0 1 01 0 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 0 1 X

1 place


CC1

The signal state of theCC 1 bit is loaded intothe vacated bit place.

Figure 14-6 Rotating Accumulator 1 One Bit to the Left via the CC 1 Bit of the Status Word

The RRDA instruction works in a manner similar to the RLDA instruction.The only difference is in the direction of the rotation.

RotateAccumulator 1 Leftvia CC 1: RLDA

RotateAccumulator 1Right via CC 1:RRDA



Data Block Instructions


15.1 Opening Data Blocks 15-2

15.2 Swapping Data Block Registers 15-2

15.3 Loading Data Block Lengths and Numbers 15-3

Chapter Overview

15


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15.1 Opening Data Blocks

You can use the Open a Data Block (OPN) instruction to open a data block asa shared data block or as an instance data block. The program itself canaccomodate one open shared data block and one open instance data block atthe same time.

Tables 15-1 and 15-2 lists the addresses and their ranges for the OPNinstruction.

Table 15-1 Addresses of the Open a Data Block Instruction OPN

Data BlockA

Maximum Address Range according to Addressing TypeArea


DBDI

1 to 65,535

[DBW][DIW][LW][MW]

1 to 65,534

Table 15-2 Addresses of the Open a Data Block Instruction OPN Transferred asParameter

Type of DB Opened Address Parameter Format

DBpara BLOCK_DB

DIpara

15.2 Swapping Data Block Registers

You can use the Exchange Shared DB and Instance DB (CDB) instruction toexchange data block registers. A shared data block becomes an instance datablock and vice versa.

Description

AddressingFormat

Description



15.3 Loading Data Block Lengths and Numbers

You can use the following instructions to load the length (in bytes) or thenumber of a shared data block or an instance data block into accumulator 1:

� Load Length of Shared DB in Accumulator 1 (L DBLG)

� Load Number of Shared DB in Accumulator 1 (L DBNO)

� Load Length of Instance DB in Accumulator 1 (L DILG)

� Load Number of Instance DB in Accumulator 1 (L DINO)

The following sample program illustrates how you can use the L DBLGinstruction to jump to the label ERR if the length of a data block is 50 bytesor more. The statement at the label ERR calls FC10, which you haveprogrammed as an appropriate reaction if the length of the data block inquestion is 50 bytes or more.

STL Explanation

OPN DB40

L DBLG

L +50

>=I

JC ERR

A I 0.0= M 1.0

BEU

ERR: CALL FC10

Open shared data block DB40.

Load the length of the open data block into accumulator 1.

Load the integer +50 into accumulator 1. The old contents ofaccumulator 1 (the length of the open data block) are movedto accumulator 2.

Compare the contents of accumulator 2 (the length of theopen data block) to the contents of accumulator 1 (+50).

If the length of the data block is greater than or equal to+50, jump to the label ERR. If the length of the data blockis less than +50, continue to the next instructionstatement.

The program continues with an And instruction.

End the current block, regardless of the result of logicoperation.

FC10 contains an appropriate reaction in the event that thelength of DB40 is 50 bytes or more.

Description

Examples



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The following sample program illustrates how you can use the L DBNOinstruction to check the data block that is presently open in your program tosee if it falls into a particular range of data blocks, for example, data blockDB190 to data block DB250.

STL Explanation

L DBNO

L +190

<I

JC ERR

L DBNO

L +250

>I

JC ERR

SET= M 1.0

BEU

ERR: CALL FC10

Load into accumulator 1 the number of the data block that ispresently open.

Load the integer +190 as lower limit into accumulator 1. Theold contents of accumulator 1 (the number of the open datablock) are moved to accumulator 2.

Compare the contents of accumulator 2 (the number of theopen data block) to the contents of accumulator 1 (+190).

If the number of the data block is less than +190, jump tothe label ERR. If the number of the data block is not lessthan +190, continue to the next instruction statement.

Load into accumulator 1 the number of the data block that ispresently open.

Load the integer +250 as upper limit into accumulator 1. Theold contents of accumulator 1 (the number of the open datablock) are moved to accumulator 2.

Compare the contents of accumulator 2 (the number of theopen data block) to the contents of accumulator 1 (+250).

If the number of the data block is greater than +250, jumpto the label ERR. If the number of the data block is notgreater than +250, continue to the next instructionstatement.

Set the RLO to 1.Assign the RLO to memory bit M 1.0.

End the current block, regardless of the result of logicoperation.

FC10 contains an appropriate reaction in the event that thenumber of the data block that is currently open does notfall into the range of DB190 to DB250.



Jump Instructions


16.1 Overview 16-2

16.2 Unconditional Jump Instructions 16-3

16.3 Conditional Jump Instructions Based on Result of LogicOperation

16-4

16.4 Conditional Jump Instructions Based on BR, OV, or OS Bitsof the Status Word

16-5

16.5 Conditional Jump Instructions Based on Result in the CC 1and CC 0 Bits of the Status Word

16-6

16.6 Loop Control 16-8

Chapter Overview

16


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16.1 Overview

You can use the following Jump and Loop instructions to control the flow oflogic, enabling your program to interrupt its linear flow to resume scanningat a different point. The address of a Jump or Loop instruction is a label.

Instruction Explanation

Unconditional jump instructions

JU Jump Unconditional

JL Jump to List

Conditional jump instructions, condition based on RLO

JC Jump if RLO = 1

JCN Jump if RLO = 0

JCB Jump if RLO = 1 WITH BR

JNB Jump if RLO = 0 WITH BR

Conditional jump instructions, condition based on result in CC 1 and CC 0

JBI Jump If BR = 1

JNBI Jump If BR = 0

JO Jump If OV = 1

JOS Jump If OS = 1

Conditional jump instructions, condition based on result in CC 1 and CC 0

JZ Jump If Zero

JN Jump If Not Zero

JP Jump If Plus

JM Jump If Minus

JMZ Jump If Minus or Zero

JPZ Jump If Plus or Zero

JUO Jump If Unordered

Loop control

LOOP Jump if the contents of Accumulator 1 > 0

Although the Master Control Relay instructions also control the flow of logicin a program, they are not included in this chapter. For information on MCRinstructions, see Sections 17.4 and 17.5.

A jump label can be the address of a jump instruction or serve as a markerfor the destination of a jump instruction. It consists of a maximum of fourcharacters. The first character must be a letter of the alphabet; the othercharacters can be letters or numbers (for example, SEG3:). When used as adestination marker, the jump label must be closed with a colon. In this case, astatement must follow the jump label (for example, SEG3: NOP 0).

Instructions

Jump Label

Logic Control Instructions


16.2 Unconditional Jump Instructions

You can use the following jump instructions to interrupt the normal flow ofyour program unconditionally:

� Jump Unconditional (JU)

� Jump to List (JL)

A Jump Unconditional (JU) instruction in your program interrupts the normalflow of logic control and causes the program to jump to a label (the addressof the JU instruction). The label marks the point at which the program shouldcontinue. The jump is made regardless of any condition.

The Jump to List (JL) instruction is a jump distributor. It is followed by aseries of unconditional jumps to labels (see Figure 16-1). Access to the list isin accumulator 1.

Start

L MB100

JL LIST

JU SEG0

JU SEG1

JU COMM

JU SEG3

LIST: JU COMM

SEG0:

JU COMM

SEG1:

JU COMM

SEG3:

COMM:

ProgramSegment 0

CommonProgram

Selection according toSegment Number(jump distributor)

CommonProgram

End

Jump distributorwith length offour

=0 =1 =2 =3 >3

Seg. 0 Seg. 1 Seg. 3

ProgramSegment 1

ProgramSegment 3

Load destination:0 = Jump to SEG01 = Jump to SEG12 = Jump to GEM3 = Jump to SEG3

>3 = Jump to LIST

Figure 16-1 Controlling the Flow of Logic Control Using the Jump to List Instruction JL

Description

JumpUnconditional: JU

Jump to List: JL



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16.3 Conditional Jump Instructions Founded on Result of LogicOperation

The following jump instructions interrupt the flow of logic in your programbased on the result of logic operation (RLO) produced by the previousinstruction statement:

� Jump If RLO = 1 (JC)

� Jump If RLO = 0 (JCN)

� Jump If RLO = 1 with BR (JCB): The RLO is saved in the BR bit of thestatus word.

� Jump If RLO = 0 with BR (JNB): The RLO is saved in the BR bit of thestatus word.

Irrespectively of the jump, the following status word bits are described:

OR :=0STA :=1RLO :=1FC :=0

I 1.0 = 1and I 1.1 = 1?

Start

Program Section B

Erase MB10

CommonProgram

No RLO=1

Yes RLO=0

End

A I1.0

A I1.1

JCN COMM

L 0

T MB10

COMM:

Section B

CommonProgram

IFRLO=0

Figure 16-2 Controlling the Flow of Logic Control Using the Jump If RLO = 0 Instruction JCN

Description



16.4 Conditional Jump Instructions Founded on BR, OV, or OS Bits ofthe Status Word

The following jump instructions interrupt the flow of logic in your programbased on the signal state of a bit in the status word (see Section 2.2).

� Jump If BR = 1 with BR (JBI) or Jump If BR = 0 (JNBI)

� Jump If OV = 1 ( JO) or Jump If OS = 1 (JOS)

The JBI and JNBI instructions reset the OR and FC bits of the status word to0 and set the STA bit to 1. The JOS instruction resets the OS bit to 0.

Overflowstored?

Start

Section C

Erase<MB10>

Yes

No

JOS ODEL

ODEL: L MW12

L MW14

+ I

L MW16

– I

T MW10

JOS SECC*

JPZ SECB

L +10

T MW20

JU COMM

SECB: L +17

T MW30

JU COMM

SECC: L 0

T MW10

COMM:

Section A

Section B

CommonProgram

ResetOS Bit

Calculate<MW10>=<MW12>+<MW14>–<MW16>

Section A

<MW20> = 10

CommonProgram

End

Result<MW10> � 0

Yes

No

Section B

<MW30> = 17

Calculate

Reset OS Bit

Section C

* In this case, do not use the JO instruction.The JO instruction would check only theprevious – I instruction if an overflowoccurred.

Figure 16-3 Controlling the Flow of Logic Control Using the Jump If OS = 1 Instruction JOS, JP

Description



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16.5 Conditional Jump Instructions Based on Result in the CC 1 andCC 0 Bits of the Status Word

The following jump instructions interrupt the flow of logic in your programbased on the result of a calculation:

� Jump If Zero (JZ)

� Jump If Not Zero (JN)

� Jump If Plus (JP, that is, greater than zero)

� Jump If Minus (JM, that is, less than zero)

� Jump If Minus or Zero (JMZ, that is, less than or equal to zero)

� Jump If Plus or Zero (JPZ, that is, greater than or equal to zero, seeFigure 16-4)

� Jump If Unordered (JUO, that is, if one of the numbers in a floating-pointmath operation is not a valid floating-point number)

The status word bits CC 1 and CC 0 are described, irrespectively of the resultof the previous operation. The signal states of the CC 1 and CC 0 bits of thestatus word indicate the conditions shown in Table 16-1.

Table 16-1 Relationship of CC 1 and CC 0 to Conditional Jump Instructions

Signal StateResult of Calculation Jump Instruct ion Tr iggered

CC 1 CC 0Result of Calculat on Jump Instruct on Tr ggered

0 0 =0 JZ

1or0

0or1

<>0 JN

1 0 >0 JP

0 1 <0 JM

0or1

0or0

>=0 JPZ

0or0

0or1

<=0 JMZ

1 1 UO (unordered) JUO

Description

CC 1 and CC 0 inthe Status Word



Overflowstored?

Start

Section C

Erase <MB10>

Yes

No

JOS ODEL

ODEL: L MW12

L MW14

+ I

L MW16

– I

T MW10

JOS SECC*

JPZ SECB

L +10

T MW20

JU COMM

SECB: L +17

T MW30

JU COMM

SECC: L 0

T MW10

COMM:

Section A

Section B

CommonProgram

ResetOS–Bit

Calculate<MW10>=<MW12>+<MW14>–<MW16>

Section A

<MW20> = 10

CommonProgram

End

Result<MW10> >=0?

Yes

No

Section B

<MW30> = 17

Calculate

Reset OS–Bit

Section C

* In this case, do not use the JO instruction.The JO instruction would check only theprevious – I instruction if an overflowhappened.

Figure 16-4 Controlling the Flow of Logic Control Using the Jump If Plus or Zero Instruction JPZ



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16.6 Loop Control

You can use the Loop (LOOP) instruction to call a program segment multipletimes (see Figure 16-5). The Loop instruction decrements the low word ofaccumulator 1 by 1. Then the value in the low word of accumulator 1 istested. If it is not 0, a jump is executed to the label indicated in the address ofthe Loop instruction; otherwise the next instruction is executed.

You provide the Loop instruction with a label so it knows the point to whichit should return in the program. For example, the Loop instruction in theprogram shown in Figure 22-5 has the label NEXT as its address. This labeltells the instruction to return to the statement T MB10 in th program. At thispoint, the program processes Section A. The Loop instruction returns to thelabel as many times as you tell it to. You provide this information in the lowword of accumulator 1. One way to do this is to set up a loop counter andload it into the accumulator.

Loop Counter<> 0?

Start

Program Section A

Yes

No

End

L +5

NEXT: T MB10

L MB10

LOOP NEXT

Section A

Initialize LoopCounter

Decrement LoopCounter by 1

InitializeLoopCounter

Figure 16-5 Using the Loop Instruction to Call a Program Segment Multiple Times

Description

Providing a Labelas Address



You provide the Loop instruction with a value that indicates how many timesyou want LOOP to call a particular program segment.

The Loop instruction interprets the loop counter as a WORD data type.

Table 16-2 provides information about the two possible formats for a loopcounter.

Table 16-2 Possible Format for a Loop Counter

Value Type Value Range Data Type Memory Area

Integer1 to 65,535

(positive value only)WORD I, Q, M, D, L

WordW#16#0001 toW#16#FFFF

WORD I, Q, M, D, L

In order to avoid running a loop more times than is necessary, you need to beaware of the following characteristics of the Loop instruction:

� If you initialize the loop counter with a 0, the loop is executed 65,535times.

� You should avoid initializing the loop counter with a negative number.

Setting Up a LoopCounter

Using the LoopInstructionEfficiently



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Program Control Instructions


17.1 Parameter Assignment when Calling FCs and FBs 17-2

17.2 Calling Functions and Function Blocks with CALL 17-3

17.3 Calling Functions and Function Blocks with CC and UC 17-7

17.4 Working with Master Control Relay Functions 17-10

17.5 Master Control Relay Instructions 17-11

17.6 Ending Blocks 17-16

Chapter Overview

17


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17.1 Parameter Assignment when Calling FCs and FBs

When calling blocks that require parameters the terms formal parametersand actual parameters play an important role.

A formal parameter is a parameter whose name and data type are assignedand declared (for example, as INPUT, OUTPUT parameters) when the block iscreated. When a block is called in the Incremental Editor (for example CALLSFC31), STEP 7 automatically displays a list of all the formal parameters.

The next step is to assign actual parameters to the formal parameters. Anactual parameter is a parameter which functions and function blocks useduring the actual run time of the user program.

The following diagram shows the call of SFC31 “QRY_TINT” (QueryTime-of-Day Interrupt) in STL.

STL Representation

CALL SFC 31 OB_NO := 10 RET_VAL:= MW 22 STATUS := MW 100

Formal parameters

Actual parameters

Terms



17.2 Calling Functions and Function Blocks with CALL

You can use the Call (CALL) instruction to call functions (FCs) and functionblocks (FBs) that you have created for your program or that you havereceived as standard functions and standard function blocks from Siemens.The Call instruction calls the FC or FB that you indicate as an addressregardless of the result of logic operation or any other condition.

When you use the Call instruction to call a function block, you must supplythe function block with an instance data block (instance DB) or declare it as alocal instance. The instance data block stores all the static variables andactual parameters of the function block.

If you need information on how to program a function or a function block, orhow to work with their parameters, see the STEP 7 Online Help.

When calling a function (FC) or a function block (FB), you must assigncorresponding actual parameters to the declared formal parameters.

The actual parameter that is specified when a function block is called musthave the same data type as the formal parameter.

The actual parameters used when a function (FC) or function block (FB) iscalled are generally specified symbolically. Absolute addressing of actualparameters is possible only for an address whose maximum size is a doubleword (for example, I 1.0, MB2, QW4, ID0).

When you call a function, all formal parameters must be supplied with actualparameters. You only need to declare the actual parameters when these aredifferent to the parameters of the previous call (actual parameters remainstored in the instance data block after the processing of the function blockhas been completed).

When you call a function block, the Call instruction copies one of thefollowing items into the instance data block of the function block, dependingon the data type of the actual parameter and on the declaration of the formalparameter (IN, OUT, IN_OUT):

� The value of the actual parameter

� A pointer to the address of the actual parameter

� A pointer to the L stack of the calling block where the value of the actualparameter has been buffered

Description

Formal Parametersand ActualParameters

Specifying theActual Parameters



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The call can take place once the following details are entered:

� The name of the function block

� The name of the instance data block and

� The parameters (if the actual parameter is a data block, the completeabsolute address must always be specified, for example DB1.DBW2).

The call uses either with an absolute or a symbolic address.

Absolute Call:

CALL FBx,DBy ( pass parameters );

x = block numbery = data block number

Symbolic Call:

CALL fbname,datablockname (pass parameters);

fbname = symbolic block namedatablockname = symbolic data block name

The following example shows the call of function block FB40 with instancedata block DB41. In this example, the formal parameters have the followingdata types:

IN1: BOOLIN2: WORDOUT1: DWORD

STL Explanation

CALL FB40,DB41IN1:= I1.0

IN2:= MW2

OUT1:= MD20

L MD20

Call of FB40 with instance data block DB41.IN1 (formal parameter) is supplied with I 1.0 (actualparameter).IN2 (formal parameter) is supplied with MW2 (actualparameter).OUT1 (formal parameter) is supplied with MD20 (actualparameter).With this instruction, the program accesses the formalparameter OUT1.

The following example shows the call of function block FB50 with instancedata block DB51. In this example, the formal parameters have the followingdata types:

IN10: BOOLOUT11: STRUCT

V1: BOOLV2: INT

END_STRUCT

Calling an FB withInstance DB andBlock Parameters

Examples



STL Explanation

CALL FB50,DB51IN10:= I1.0

OUT11:= ACTPA11

Call of FB50 with instance data block DB51.IN10 (formal parameter) is supplied with I 1.0 (actualparameter).Here it is not possible to specify an absolute actual parameter (for example, MW10) because the formalparameter OUT11 was defined as a structure. Instead, thesymbolic actual parameter ACTPA11 is specified. Pleasenote that ACTPA11 has the same structure as the formalparameter OUT11.

Access to the values of the structure OUT11 in FB50 would be made asfollows:

STL Explanation

A OUT11.V1L OUT11.V2

Perform an AND logic operation on the bit OUT11.V1.Load word OUT11.V2 into accumulator 1.


� The instance name (= name of a static variable of the type FB z) and

� The Parameters

The call always has a symbolic designation.

CALL Instance Name (pass parameters);

STL Explanation

FUNCTION_BLOCK FB 11VARloc_inst : FB 10;END_VARBEGIN NETWORKCALL #loc_inst (in_bool := M0.0);

Source file

Declaration of a multiple instance with data type FB10

Call of the multiple instance with syntaxParameter pass(in_bool in this case is a variable declared in FB10)

Calling MultipleInstances



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� The name of the fucntion block and

� The parameters

The call is addressed either with an absolute or a symbolic name.

Absolute Call:

CALL FCx ( pass parameters );

x = block number

Symbolic Call:

CALL fcname (pass parameters);

fcname = symbolic block name

The following example shows the call of function FC80 with blockparameters. In this example, the formal parameters have the following datatypes:

INC1: BOOLINC2: INTOUT: WORD

STL Explanation

CALL FC80INC1:= M 1.0

INC2:= IW2

OUT:= QW4

Call FC80.INC1 (formal parameter) is supplied with M 1.0 (actualparameter).INC2 (formal parameter) is supplied with IW2 (actualparameter).OUT (formal parameter) is supplied with QW4 (actualparameter).

You can create a function (FC) that delivers a return value (RET_VAL). Forexample, if you want to create a floating-point math function, you can usethis return value as an output for the result of your function. When you callthis function in your program, you provide the output “RET_VAL” with adouble word location to accommodate the 32-bit result of your floating-pointmath function.

Calling an FC withBlock Parameters

Example

Calling an FC ThatDelivers a ReturnValue



17.3 Calling Functions and Function Blocks with CC and UC

You can use the following instructions to call functions (FCs) and functionblocks (FBs) that you have created for your program in the same way asusing the Call instruction. Using these instructions, you cannot transferparameters.

� Conditional Call (CC): Calls the function or function block that youindicate as an address if the result of logic operation is 1.

� Unconditional Call (UC): Calls the function or function block that youindicate as an address regardless of the result of logic operation or anyother condition.

It is not possible for function blocks which are called with either a CC or aUC instruction to have associated data blocks.

A CC or UC instruction can call a function (FC) or a function block (FB)using direct or memory indirect addressing or via an FC or FB transferred asa parameter (see Tables 17-1 and 17-2). The address is FC plus the number ofthe FC.

Table 17-1 Addresses of CC and UC Instructions: Direct and Indirect Addressing

FC or FBPart of

Maximum Range of Address Number according to Addressing TypePart ofAddress Direct Memory Indirect

FCFB

0 to 65,535

[DBW][DIW][LW][MW]

0 to 65,534

Table 17-2 Addresses of CC and UC Instructions: FC Transferred as Parameter

Address Parameter Data Types

Name of the formal parameter or asymbolic name

BLOCK_FC 1

BLOCK_FB 1

1 Parameters of type BLOCK_FC or BLOCK_FB cannot be used with the CC command in FCs and FBs.

To call an FC that you had created and given the number 12, you would useone of the following instructions, depending on whether you want the call tobe conditional or not:

CC FC12 (Call FC12 if the RLO is 1.)UC FC12 (Call FC12 no matter what the RLO is.)

Description

AddressingFormat

Example



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Depending on the data type there are various ways to assign actualparameters to the formal parameters when you call a function or a functionblock. The following table is compiled according to the length of the datatype.

Table 17-3 Assigning Actual Parameters

Data Type ofF l P t

Example of Assigning an Actual ParameterFormal Parameter Direct Input (Value) Input of a Shared

Data ElementSymbolic Input1

BOOL (Bit) TRUE M 100.0

I 0.0

Q 0.0

DBX 3.0

#OK_BIT

BYTE (Byte) B#16#1F MB 100

IB 0

QB 0

#TYP_BYTE

CHAR ’K’ DBB 1 #TYP_CHAR

WORD (Word) W#16#1F12

2#0001_1111_0001_0010

C#32

B#(5,25)

MW 100

IW 0

QW 0

DBW 2

#TYP_WORD

INT (Integer) 27

–25

#TYP_INT

S5TIME (S5 Time) S5T#10MS #TYP_S5_TIME

DATE (IEC Date) D#1995–12–24 #TYP_DATE

DWORD (DoubleWord)

DW#16#FFFF_0F02

2#0001_1111_0001_0010_0001_1111_0001_0010

B#(5,4,59,8)

MD 100

ID 0

QD 0

DBD 4

#TYP_DWORD

DINT (DoubleInteger)

L#170

L#-350

#TYP_DINT

REAL (Floating-Point Number)

1.23 #TYP_REAL

TIME (IEC Time) T#20MS #TYP_TIME

TIME_OF_DAY(IEC Time-of-Day)

TOD#23:59:12.3 #TYP_TOD

Assigning ActualParameters



Table 17-3 Assigning Actual Parameters, continued

Data Type ofFormal Parameter

Example of Assigning an Actual ParameterData Type ofFormal Parameter Symbolic Input1Input of a Shared

Data ElementDirect Input (Value)

DATE_AND_TIME(IEC Date and Time)

Not possible

(Variable must be declared, for example, temporaryvariable)

#TYP_8_BYTE

ANY (Data type ofany type and size)

P#M0.0 BYTE20

20 bytes 2 ...... from bit memory 0.0 3

Prefix for ANY pointer

P#DB58.DBX16.0 BYTE14

14 bytes 2 ...... in DB58 from data bit 16.0 3

Prefix for ANY pointer

E 0.0

MB 5

AW 2

(Use of any STEP 7shared addressespossible)

#TYP_ANYTYP

(Declaration ofarrays and struc-tures)

1 Prerequisite: In the case of shared data, the name (= symbol) must be declared in the symbol table before it can be usedas an actual parameter. In the case of local data, the name (= symbol) must be declared in the declaration table of theblock before it can be used as an actual parameter. Local data symbols must be preceded by a hash #.

2 Length specification can include elementary data types, for example BOOL, BYTE, WORD or DWORD or complextypes, for example DATE_AND_TIME.

3 Always enter a bit address; in length specifications enter 0 as the bit address (exception: BOOL).

In order to call an SFC conditionally, you can follow a sequence similar tothe following:

STL Explanation

A #OK_BIT_MEMORYJCNB m001CALL SFC 28 OB_NO := 10 SDT := #OUT_TIME_DATE PERIOD := W#16#1201 RET_VAL := MW 200

m001: A BR= M 202.3

Condition for the callIf the condition is not fulfilled(RLO=0), the call of the SFC isjumped and the RLO in the status bitis saved.

Check status bit BR

Conditional Call inSTL



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17.4 Working with Master Control Relay Functions

The Master Control Relay (MCR) is an American relay ladder logic masterswitch for energizing and de-energizing power flow (current path). Ade-energized current path corresponds to an instruction sequence that writes azero value instead of the calculated value, or, to an instruction sequence thatleaves the existing memory value unchanged. Operations triggered by thefollowing bit logic and transfer instructions are dependent on the MCR:

� =

� S

� R

� T (used with byte, word, or double word)

The T instruction used with byte, word, or double word, and the = instructionwrite a 0 to the memory if the MCR is 0. The S and R instructions leave theexisting value unchanged.

Table 17-4 Operations Dependent on MCR and How They React to Its Signal State

Signal Stateof MCR

= S or R T

0 Writes 0

(Imitates a relay thatfalls to its quiet statewhen voltage isremoved)

Does not write

(Imitates a latchingrelay that remains inits current state whenvoltage is removed)

Writes 0

(Imitates a componentthat, on loss ofvoltage, produces avalue of 0)

1 Normal execution Normal execution Normal execution

Description



17.5 Master Control Relay Instructions

You can use the following statements to implement a master control relay:

� MCRA Activate MCR Area

� MCRD Deactivate MCR Area

� MCR( Save RLO in MCR Stack, Begin MCR Area

� )MCR End MCR Area

The following instructions activate or deactivate an MCR area, that is, theyspecify which instructions in your program depend on the MCR (see alsoFigure 17-1):

� Activate MCR Area: MCRA

� Deactivate MCR Area: MCRD

The instructions that are programmed between the MCRA and the MCRDstatements depend on the signal state of the MCR bit. The instructions thatare programmed outside an MCRA-MCRD sequence do not depend on thesignal state of the MCR bit. If an MCRD instruction is missing, theinstructions programmed between an MCRA instruction and a BEUinstruction depend on the MCR bit (see Figure 17-1).

You must program the MCR dependency of functions (FCs) and functionblocks (FBs) in the blocks themselves, that is, if such a function or functionblock is called from an MCRA-MCRD sequence, all the commands withinthat sequence are not automatically dependent on the MCR bit. To make theinstructions in a called block dependent on the MCR bit, you must use theMCRA instruction in the block that is called.

!Danger

Never use the MCR instruction as an emergency off or personnel safetydevice.

Overview

Description:MCRA, MCRD



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ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ

ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ

ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ

ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ

ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ

OB1

MCRA

MCRD

MCRA

MCRA

MCRA

MCRD

BEU

BEU

Instructions depend on the MCR bit

Instructions do not depend on the MCR bit

CALL FBx

FBx FCy

CALL FCy

Figure 17-1 Activating and Deactivating a Master Control Relay Area



The following instructions turn the Master Control Relay function on and off:

� Save RLO in MCR Stack, Begin MCR: MCR(

� End MCR: )MCR

You can nest MCR( and )MCR instructions. The maximum nesting depth iseight, that is, you can have a maximum of eight MCR( instructions insequence before you insert an )MCR instruction. You must program an equalnumber of MCR( and )MCR instructions (see Figure 17-3).

When MCR( instructions are nested, the MCR bit of the deeper nesting levelsis formed. To form this MCR bit, the MCR( instruction combines the currentRLO with the current MCR bit according to the And truth table.

The )MCR instruction terminates a nesting level by restoring the MCR bitfrom the higher level. The )MCR instruction of the highest level sets theMCR bit to 1.

If you use MCR( and )MCR in your program, you must always use them inpairs.

Figure 17-2 shows how to implement a Master Control Relay.

If the MCR bit is 1, then the MCR contact is closed. The signal states ofoutputs Q 4.0 and Q 4.1 are calculated according to the signal state of inputsI 1.0 to I 1.3 and their logic combinations.

If the MCR bit is 0, then the MCR contact is opened. The outputs Q 4.0 andQ 4.1 are reset to 0, regardless of the signal states of inputs I 1.0 to I 1.3.

Power rail

I 2.0

MCRcontact

MCR coil

Master Control Relayimplemented with the MCR(and )MCR instructions

I 1.0 I 1.1

Q 4.0 Q 4.1

I 1.2

I 1.3

MCRAA I 2.0MCR(O I 1.0O I 1.1= Q 4.0A I 1.2A I 1.3= Q 4.1)MCRMCRD

Area which is controlled by the MCR(Master Control Relay), implemented withMCRA and MCRD instructions

Relay Logic DiagramSTL

Figure 17-2 Implementation of a Master Control Relay

Description: MCR(,)MCR

Example



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Figure 17-3 shows the nesting application of the instructions.

MCRAA I 1.1MCR (A I 1.2MCR (A I 1.3MCR (

S M 1.0)MCR

S M 1.1)MCR

)MCRMCRD

1

Result ofCheck

SignalState

RLO MCR Bit of Level

This bit (M 1.0) remains unchangedregardless of any previous logicstring because the MCR bit = 0.

STL

00000

This bit (M 1.1) is changed due tothe previous logic string and thefunction of the S instruction becausethe MCR = 1.

**

1 2 3

1 1

0 0 0*

1 1 111

* The MCR bit of the deeper nesting level is formed. To form this MCR bit, the MCR(instruction combines the current RLO with the MCR bit of the currentnesting level according to the And truth table.

** When the )MCR instruction ends a nesting level, the instruction restores the MCR bit of thenext higher level.

11

1111

1111

Figure 17-3 Nesting Application of MCR Instructions



Important Notes on Using MCR Functions

Take care with blocks in which the Master Control Relay was activated withMCRA:

� If the MCR is deactivated, the value 0 is written by all assignments inprogram segments between (MCR<) and (MCR>).

� The MCR is deactivated if the RLO was =0 before an (MCR<) instruc-tion.

!Danger

PLC in STOP or undefined runtime characteristics!

The compiler also uses write access to local data behind the temporary varia-bles defined in VAR_TEMP for calculating addresses.

Formal parameter access

� Access to components of complex FC parameters of the type STRUCT,UDT, ARRAY, STRING

� Access to components of complex FB parameters of the type STRUCT,UDT, ARRAY, STRING from the IN_OUT area in a version 2 block.

� Access to parameters of a version 2 function block if its address isgreater than 8180.0.

� Access in a version 2 function block to a parameter of the typeBLOCK_DB opens DB0. Any subsequent data access sets the CPU toSTOP. T 0, C 0, FC0 or FB0 are always used for TIMER, COUNTER,BLOCK_FC, and BLOCK_FB.

Parameter passing

� Calls in which parameters are transferred.

KOP/FUP

� T branches and midline outputs in Ladder or FBD starting with RLO=0.

Remedy:

Free the above commands from their dependence on the MCR:

1. Deactivate the Master Control Relay using the Master Control Relay De-activate instruction before the statement or network in question.

2. Activate the Master Control Relay again mit Master Control Relay Acti-vate instruction after the statement or network in question.



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17.6 Ending Blocks

A Block End instruction is by itself a programming statement that terminatesthe scanning of a block. You can use either of the following types ofBlock End instructions to end a block:

� Block End Unconditional (BEU): This instruction ends scanning in thecurrent block and returns control to the block that called the one that hasbeen terminated. When the program encounters a BEU instruction, itterminates the current block, regardless of the result of logic operation.

� Block End Conditional (BEC): This instruction ends scanning in thecurrent block and returns control to the block that called the one that hasbeen terminated. When the program encounters a BEC instruction, itterminates the current block only if the result of logic operation is 1(RLO = 1). If the RLO is 0, the program does not execute the Block EndConditional (BEC) statement. The RLO is set to 1 and program scanningcontinues within the current block.

Description


Alphabetical Listing ofInstructions A

Programming Examples B

Source Files – Examples andReserved Key Words C

References D

Appendix

Q-2Statement List (STL) for S7-300/S7-400

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A-1Statement List (STL) for S7-300/S7-400C79000-G7076-C565-01

Alphabetical Listing of Instructions


A.1 Listing with (German) SIMATIC and InternationalMnemonics

A-2

A.2 Alphabetical Listing with International Names A-12

Chapter Overview

A

A-2Statement List (STL) for S7-300/S7-400

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A.1 Listing with (German) SIMATIC and International Mnemonics

Table A-1 provides an alphabetical listing of the mnemonic abbreviations ofthe statement list instructions. Next to each German abbreviation are theequivalent international abbreviation, the full international name and thepage on which the instruction is explained.

Table A-1 Alphabetical Listing with the SIMATIC and the International Mnemonic Abbreviations

SIMATICAbbreviation

InternationalAbbreviation

Name PageNo.

+ + Add Integer Constant (8, 16, 32-Bit) 9-6

= = Assign 5-24

) ) Nesting Closed 5-14

+AR1 +AR1 Add Accumulator 1 to Address Register 1 4-7


+D +D Add Accumulator 1 and Accumulator 2 as Double Integer (32-Bit) 9-2

-D -D Subtract Accumulator 1 and Accumulator 2 as Double Integer (32-Bit)9-2

*D *D Multiply Accumulator 1 by Accumulator 2 as Double Integer (32-Bit) 9-2

/D /D Divide Accumulator 2 by Accumulator 1 as Doubel Integer (32-Bit) 9-2

==D ==D Compare Double Integer (32-Bit) >, <, >=, <=, ==, <> 17-3

+I +I Add Accumulator 1 and Accumulator 2 as Integer (16-Bit) 9-2

-I -I Subtract Accumulator 1 from Accumulator 2 as Integer (16-Bit) 9-2

*I *I Multiply Accumulator 1 by Accumulator 2 as Integer (16-Bit) 9-2

/I /I Divide Accumulator 2 by Accumulator 1 as Integer (16-Bit) 9-2

==I ==I Compare Integer (16-Bit) >, <, >=, <=, ==, <> 17-3

+R +R Add Accumulator 1 and Accumulator 2 as Real (32-Bit IEEE FP) 10-2

-R -R Subtract Accumulator 1 from Accumulator 2 as Real (32-Bit IEEE FP)10-2

*R *R Multiply Accumulator 1 by Accumulator 2 as Real (32 Bit IEEE FP) 10-2

/R /R Divide Accumulator 2 by Accumulator 1 as Real (32-Bit IEEE FP) 10-2

==R ==R Compare Real >, <, >=, <=, ==, <> 17-5

ABS ABS Absolute Value of a Real (32-Bit IEEE FP) 10-6

ACOS ACOS Arc Cosine of a Floating-Point Number (32-Bit IEEE FP) 10-7

ASIN ASIN Arc Sine of a Floating-Point Number (32-Bit IEEE FP) 10-7

ATAN ATAN Arc Tangent of a Floating-Point Number (32-Bit IEEE FP) 10-7

AUF OPN Call a Data Block 21-2

BEA BEU Block End Unconditional 17-16

BEB BEC Block End Conditional 17-16

BLD BLD Program Display Instruction 4-2

BTD BTD BCD to Double Integer (32-Bit) 18-4

BTI BTI BCD to Integer (16-Bit) 18-2

CALL CALL Call 17-3



Table A-1 Alphabetical Listing with the SIMATIC and the International Mnemonic Abbreviations, cont.

SIMATICAbbreviation

PageNo.

NameInternationalAbbreviation

CC CC Conditional Call 17-7

CLR CLR Clear RLO (= 0) 5-26

COS COS Cosine of a Floating-Point Number (32-Bit IEEE FP) 10-7

DEC DEC Decrement Accumulator 1 4-6

DTB DTB Double Integer (32-Bit) to BCD 12-6

DTR DTR Double Integer (32-Bit) to Real (32-Bit IEEE FP) 12-7

ENT ENT Accumulator 3 ---> Accumulator 4, Accumulator 2 ---> Accumulator 34-3

EXP EXP Exponential Value of a Floating-Point Number (32-Bit IEEE FP) toBase E

10-12

FN FN Edge Negative 5-17

FP FP Edge Positive 5-16

FR FR Enable Counter (Free, FR C 0 to C 255) 6-5

FR FR Enable Timer (Free, FR T 0 to T 255) 7-3

INC INC Increment Accumulator 1 4-6

INVD INVD Ones Complement Double Integer (32-Bit) 12-14

INVI INVI Ones Complement Integer (16-Bit) 12-14

ITB ITB Integer (16-Bit) to BCD 12-5

ITD ITD Integer (16-Bit) to Double Integer (32-Bit) 12-6

L L Load 8-3

L L Load Length of Shared Data Block into Accumulator 1 (L DBLG) 8-1215-2

L L Load Number of Shared Data Block into Accumulator 1 (L DBNO) 8-12

L L Load Length of Instance Data Block into Accumulator 1 (L DILG) 8-1215-2

L L Load Number of Instance Data Block into Accumulator 1 (L DINO) 8-1215-2

L L Load Status Word into Accumulator 1 (L STW) 8-6

L L Load Current Timer Value into Accumulator 1 as Integer (where thenumber of the current timer can be in the range of 0 to 255, for example:L T 32)

8-7

L L Load Current Counter Value into Accumulator 1 as Integer (where thenumber of the current counter can be in the range of 0 to 255, for exam-ple: L C 15)

7-68-8

LAR1 LAR1 Load Address Register 1 from Accumulator 1 (if no address is indicated)

8-11

LAR1 LAR1 Load Address Register 1 from ... (from address indicated) 8-11

LAR1 LAR1 Load Address Register 1 from Address Register 2 (LAR1 AR2) 8-11

LAR1 LAR1 Load Address Register 1 with Double Integer (32-Bit, LAR1 P#areabyte.bit)

8-11

LAR2 LAR2 Load Address Register 2 from Accumulator 1 (if no address is indi-cated)

8-11



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SIMATICAbbreviation

PageNo.




8-11

LC LC Load Current Counter Value into Accumulator 1 as BCD (where thenumber of the current counter can be in the range of 0 to 255, forexample: LC C 15)

8-9

LC LC Load Current Timer Value into Accumulator 1 as BCD (where thenumber of the current timer can be in the range of 0 to 255, for example:LC T 32)

7-78-9

LEAVE LEAVE Accumulator 3 ---> Accumulator 2, Accumulator 4 ---> Accumulator 34-3

LN LN Natural Logarithm of a Floating-Point Number (32-Bit IEEE FP) 10-11

LOOP LOOP Loop 16-8

MCR( MCR( Save RLO in MCR Stack, Begin MCR 17-11

)MCR MCR) Restore RLO, End MCR 17-11

MCRA MCRA Activate MCR Area 17-11

MCRD MCRD Deactivate MCR Area 17-11

MOD MOD Division Remainder Double Integer (32-Bit) 9-5

NEGD NEGD Twos Complement Double Integer (32-Bit) 12-14

NEGI NEGI Twos Complement Integer (16-Bit) 12-14

NEGR NEGR Negate Real Number 12-14

NOP 0 NOP 0 Null Operation 0 4-2


NOT NOT Negate RLO 5-26

O O Or 5-10

O( O( Or with Nesting Open 5-14

OD OD Or Double Word (32-Bit) 13-6

ON ON Or Not 5-8

ON( ON( Or Not with Nesting Open 5-14

OW OW Or Word (16-Bit) 13-3

POP POP Accumulator 1 <--- Accumulator 2, Accumulator 2 <--- Accumulator 3,Accumulator 3 <--- Accumulator 4

4-2

PUSH PUSH Accumulator 3 ---> Accumulator 4, Accumulator 2 ---> Accumulator 3,Accumulator 1 ---> Accumulator 2

4-2

R R Reset 5-22

R R Reset Counter (where the current counter can have a number in therange of 0 to 255, for example: R C 15)

6-5

R R Reset Timer (where the current timer can have a number in the range of0 to 255, for example: R T 32)

7-4

RLD RLD Rotate Left Double Word (32-Bit) 14-8

RLDA RLDA Rotate Accumulator 1 Left via CC 1 (32-Bit) 14-6




SIMATICAbbreviation

PageNo.


RND RND Round 12-9

RND+ RND+ Round to Upper Double Integer 12-10

RND- RND- Round to Lower Double Integer 12-11

RRD RRD Rotate Right Double Word (32-Bit) 14-8

RRDA RRDA Rotate Accumulator 1 Right via CC 1 (32-Bit) 14-6

S S Set 5-21

S S Set Counter Preset Value (where the current counter can have a numberin the range of 0 to 255, for example: S C 15)

7-3

SA SF Off-Delay Timer 6-15

SAVE SAVE Save RLO in BR Register 5-26

SE SD On-Delay Timer 6-11

SET SET Set RLO (= 1) 5-26

SI SP Pulse Timer 6-7

SIN SIN Sine of a Floating-Point Number (32-Bit IEEE FP) 10-7

SLD SLD Shift Left Double Word (32-Bit) 14-2

SLW SLW Shift Left Word (16-Bit) 14-2

SPA JU Jump Unconditional 16-3

SPB JC Jump if RLO = 1 16-4

SPBB JCB Jump if RLO = 1 with BR 16-4

SPBI JBI Jump if BR = 1 16-4

SPBIN JNBI Jump if BR = 0 16-4

SPBN JCN Jump if RLO = 0 16-4

SPBNB JNB Jump if RLO = 0 with BR 16-4

SPL JL Jump to Labels 16-3

SPM JM Jump if Minus 16-6

SPMZ JMZ Jump if Minus or 0 16-6

SPN JN Jump if Not 0 16-6

SPO JO Jump if OV = 1 16-5

SPP JP Jump if Plus 16-6

SPPZ JPZ Jump if Plus or 0 16-6

SPS JOS Jump if OS = 1 16-5

SPU JUO Jump if Unordered 16-6

SPZ JZ Jump if 0 16-6

SQR SQR Square of a Floating-Point Number (32-Bit IEEE PF) 10-9

SQRT SQRT Square Root of a Floating-Point Number (32-Bit IEEE PF) 10-9

SRD SRD Shift Right Double Word (32-Bit) 14-3

SRW SRW Shift Right Word (16-Bit) 14-2



C79000-G7076-C565-01


SIMATICAbbreviation

PageNo.


SS SS Retentive On-Delay Timer 6-13

SSD SSD Shift Sign Double Integer (32-Bit) 14-4

SSI SSI Shift Sign Integer (16-Bit) 14-4

SV SE Extended Pulse Timer 6-9

T T Transfer 8-3

T T Transfer Accumulator 1 to Status Word (T STW) 8-6

TAD CAD Change Byte Sequence in Accumulator 1 (32-Bit) 12-13

TAK TAK Toggle Accumulator 1 with Accumulator 2 4-2

TAN TAN Tangent of a Floating-Point Number (32-Bit IEEE FP) 10-7

TAR CAR Exchange Address Register 1 with Address Register 2 8-11

TAR1 TAR1 Transfer Address Register 1 to Accumulator 1 (if no address isindicated)

8-11

TAR1 TAR1 Transfer Address Register 1 to ... (to address indicated) 8-11

TAR1 TAR1 Transfer Address Register 1 to Address Register 2 (T AR1 AR2) 8-11

TAR2 TAR2 Transfer Address Register 2 to Accumulator 1 (if no address isindicated)

8-11


TAW CAW Change Byte Sequence in Accumulator 1 (16-Bit) 12-13

TDB CDB Exchange Shared Data Block and Instance Data Block 15-2

TRUNC TRUNC Truncate 12-12

U A And 5-10

U( A( And with Nesting Open 5-14

UC UC Unconditional Call 17-7

UD AD And Double Word (32-Bit) 13-6

UN AN And Not 5-8

UN( AN( And Not with Nesting Open 5-14

UW AW And Word (16-Bit) 13-3

X X Exclusive Or 5-10

X( X( Exclusive Or with Nesting Open 5-14

XN XN Exclusive Or Not 5-8

XN( XN( Exclusive Or Not with Nesting Open 5-14

XOD XOD Exclusive Or Double Word (32-Bit) 13-6

XOW XOW Exclusive Or Word (16-Bit) 13-3

ZR CD Counter Down 7-5

ZV CU Counter Up 7-5



Table A-2 provides an alphabetical listing of the mnemonic abbreviations ofthe statement list instructions. Next to each international abbreviation are theequivalent (German) SIMATIC abbreviation, the full international name andthe page on which the instruction is explained.

Table A-2 Alphabetical Listing with the International and the SIMATIC Mnemonic Abbreviations


SIMATICAbbreviation

Name PageNo.

+ + Add Integer Constant (8, 16, 32-Bit) 15-6

= = Assign 11-24

) ) Nesting Closed 11-14



+D +D Add Accumulator 1 and Accumulator 2 as Double Integer (32-Bit) 15-2

-D -D Subtract Accumulator 1 from Accumulator 2 as Double Integer(32-Bit)

15-2

*D *D Multiply Accumulator 1 by Accumulator 2 as Double Integer (32-Bit)15-2

/D /D Divide Accumulator 2 by Accumulator 1 as Double Integer (32-Bit) 15-2

==D ==D Compare Double Integer (32-Bit) >, <, >=, <=, ==, <> 17-3

+I +I Add Accumulator 1 and Accumulator 2 as Integer (16-Bit) 15-2

-I -I Subtract Accumulator 1 from Accumulator 2 as Integer (16-Bit) 15-2

*I *I Multiply Accumulator 1 by Accumulator 2 as Integer (16-Bit) 15-2

/I /I Divide Accumulator 2 by Accumulator 1 as Integer (16-Bit) 15-2

==I ==I Compare Integer (16-Bit) >, <, >=, <=, ==, <> 17-3

+R +R Add Accumulator 1 and Accumulator 2 as Real (32-Bit IEEE FP) 16-2

-R -R Subtract Accumulator 1 from Accumulator 2 as Real (32-Bit IEEE FP)16-2

*R *R Multiply Accumulator 1 by Accumulator 2 as Real (32-Bit IEEE FP) 16-2

/R /R Divide Accumulator 2 by Accumulator 1 as Real (32-Bit IEEE FP) 16-2

==R ==R Compare Real >, <, >=, <=, ==, <> 17-5

A U And 11-10

A( U( And with Nesting Open 11-14

ABS ABS Absolute Value of a Real (32-Bit IEEE FP) 16-6

ACOS ACOS Arc Cosine of a Floating-Point Number (32-Bit IEEE FP) 16-7

AD UD And Double Word (32-Bit) 19-6

AN UN And Not 11-9

AN( UN( And Not with Nesting Open 11-14

ASIN ASIN Arc Sine of a Floating-Point Number (32-Bit IEEE FP) 16-7

ATAN ATAN Arc Tangent of a Floating-Point Number (32-Bit IEEE FP) 16-7

AW UW And Word (16-Bit) 19-3

BEC BEB Block End Conditional 23-15

BEU BEA Block End Unconditional 23-15



C79000-G7076-C565-01

Table A-2 Alphabetical Listing with the International and the SIMATIC Mnemonic Abbreviations, cont.


PageNo.

NameSIMATICAbbreviation

BLD BLD Program Display Instruction 10-2

BTD BTD BCD to Double Integer (32-Bit) 18-4

BTI BTI BCD to Integer (16-Bit) 18-2

CAD TAD Change Byte Sequence in Accumulator 1 (32-Bit) 18-13

CALL CALL Call 23-3

CAR TAR Exchange Address Register 1 with Address Register 2 14-11

CAW TAW Change Byte Sequence in Accumulator 1 (16-Bit) 18-13

CC CC Conditional Call 23-7

CD ZR Counter Down 13-5

CDB TDB Exchange Shared Data Block and Instance Data Block 21-2

CLR CLR Clear RLO (= 0) 11-26

COS COS Cosine of a Floating-Point Number (32-Bit IEEE FP) 16-7

CU ZV Counter Up 13-5

DEC DEC Decrement Accumulator 1 10-6

DTB DTB Double Integer (32-Bit) to BCD 18-6

DTR DTR Double Integer (32-Bit) to Real (32-Bit IEEE FP) 18-7

ENT ENT Accumulator 3 ---> Accumulator 4, Accumulator 2 ---> Accumulator 310-3

EXP EXP Exponential Value of a Floating-Point Number (32-Bit IEEE FP) tobase E

16-12

FN FN Edge Negative 11-17

FP FP Edge Positive 11-16

FR FR Enable Counter (Free, FR C 0 to C 255) 12-5

FR FR Enable Timer (Free, FR T 0 to T 255) 13-3

INC INC Increment Accumulator 1 10-6

INVD INVD Ones Complement Double Integer (32-Bit) 18-14

INVI INVI Ones Complement Integer (16-Bit) 18-14

ITB ITB Integer (16-Bit) to BCD 18-5

ITD ITD Integer (16-Bit) to Double Integer 18-6

JBI SPBI Jump if BR = 1 22-4

JC SPB Jump if RLO = 1 22-4

JCB SPBB Jump if RLO = 1 with BR 22-4

JCN SPBN Jump if RLO = 0 22-4

JL SPL Jump to Labels 22-3

JM SPM Jump if Minus 22-6

JMZ SPMZ Jump if Minus or 0 22-6

JN SPN Jump if Not 0 22-6

JNB SPBNB Jump if RLO = 0 with BR 22-4





PageNo.


JNBI SPBIN Jump if BR = 0 22-4

JO SPO Jump if OV = 1 22-5

JOS SPS Jump if OS = 1 22-5

JP SPP Jump if Plus 22-5

JPZ SPPZ Jump if Plus or 0 22-6

JU SPA Jump Unconditional 22-3

JUO SPU Jump if Unordered 22-6

JZ SPZ Jump if 0 22-6

L L Load 14-3

L L Load Length of Shared Data Block into Accumulator 1 (L DBLG) 14-1221-2

L L Load Number of Shared Data Block into Accumulator 1 (L DBNO) 14-12

L L Load Length of Instance Data Block into Accumulator 1 (L DILG) 14-1221-2

L L Load Number of Instance Data Block into Accumulator 1 (L DINO) 14-1221-2

L L Load Status Word into Accumulator 1 (L STW) 14-6

L L Load Current Timer Value into Accumulator 1 as Integer (where thenumber of the current timer can be in the range of 0 to 255, forexample: L T 32)

14-7

L L Load Current Counter Value into Accumulator 1 as Integer (where thenumber of the current counter can be in the range of 0 to 255, forexample: L C 15)

13-614-8

LAR1 LAR1 Load Address Register 1 from Accumulator 1 (if no address isindicated)

14-11


LAR1 LAR1 Load Address Register 1 from Address Register 2 (LAR1 AR2) 14-11

LAR1 LAR1 Load Address Register 1 with Double Integer (32-Bit, LAR1 P#area byte.bit)

14-11

LAR2 LAR2 Load Address Register 2 from Accumulator 1 (if no address isindicated)

14-11



14-11

LC LC Load Current Counter Value into Accumulator 1 as BCD (where thenumber of the current counter can be in the range of 0 to 255, forexample: LC C 15)

14-9

LC LC Load Current Timer Value into Accumulator 1 as BCD (where thenumber of the current timer can be in the range of 0 to 255, forexample: LC T 32)

13-714-10

LEAVE LEAVE Accumulator 3 ---> Accumulator 2, Accumulator 4 ---> Accumulator 310-3

LN LN Natural Logarithm of a Floating-Point Number (32-Bit IEEE FP) 16-11



C79000-G7076-C565-01



PageNo.


LOOP LOOP Loop 22-8

MCR( MCR( Save RLO in MCR Stack, Begin MCR 23-11

MCR) )MCR Restore RLO, End MCR 23-11

MCRA MCRA Activate MCR Area 23-11

MCRD MCRD Deactivate MCR Area 23-11

MOD MOD Division Remainder Double Integer (32-Bit) 15-5

NEGD NEGD Twos Complement Double Integer (32-Bit) 18-14

NEGI NEGI Twos Complement Integer (16-Bit) 18-14

NEGR NEGR Negate Real Number (32-Bit IEEE FP) 18-14



NOT NOT Negate RLO 11-26

O O Or 11-10

O( O( Or with Nesting Open 11-14

OD OD Or Double Word (32-Bit) 19-6

ON ON Or Not 11-9

ON( ON( Or Not with Nesting Open 11-14

OPN AUF Open a Data Block 21-2

OW OW Or Word (16-Bit) 19-3

POP POP Accumulator 1 <--- Accumulator 2, Accumulator 2 <--- Accumulator 3,Accumulator 3 <--- Accumulator 4

10-2

PUSH PUSH Accumulator 3 ---> Accumulator 4, Accumulator 2 ---> Accumulator 3,Accumulator 1 ---> Accumulator 2

10-2

R R Reset 11-22

R R Reset Counter (where the current counter can have a number in therange of 0 to 255, for example: R C 15)

12-5

R R Reset Timer (where the current timer can have a number in the range of0 to 255, for example: R T 32)

13-4

RLD RLD Rotate Left Double Word (32-Bit) 20-6

RLDA RLDA Rotate Accumulator 1 Left via CC 1 (32-Bit) 20-6

RND RND Round 18-9

RND+ RND+ Round to Upper Double Integer 18-10

RND- RND- Round to Lower Double Integer 18-11

RRD RRD Rotate Right Double Word (32-Bit) 20-8

RRDA RRDA Rotate Accumulator 1 Right via CC 1 (32-Bit) 20-6

S S Set 11-21

S S Set Counter Preset Value (where the current counter can have a numberin the range of 0 to 255, for example: S C 15)

13-3

SAVE SAVE Save RLO in BR Register 11-26





PageNo.


SD SE On-Delay Timer 12-11

SE SV Extended Pulse Timer 12-9

SET SET Set RLO (= 1) 11-26

SF SA Off-Delay Timer 12-15

SIN SIN Sine of a Floating-Point Number (32-Bit IEEE FP) 16-7

SLD SLD Shift Left Double Word (32-Bit) 20-2

SLW SLW Shift Left Word (16-Bit) 20-2

SP SI Pulse Timer 12-7

SQR SQR Square of a Floating-Point Number (32-Bit IEEE PF) 16-9

SQRT SQRT Square Root of a Floating-Point Number (32-Bit IEEE PF) 16-9

SRD SRD Shift Right Double Word (32-Bit) 20-3

SRW SRW Shift Right Word (16-Bit) 20-2

SS SS Retentive On-Delay Timer 12-13

SSD SSD Shift Sign Double Integer (32-Bit) 20-4

SSI SSI Shift Sign Integer (16-Bit) 20-4

T T Transfer 14-3

T T Transfer Accumulator 1 to Status Word (T STW) 14-6

TAK TAK Toggle Accumulator 1 with Accumulator 2 10-2

TAN TAN Tangent of a Floating-Point Number (32-Bit IEEE FP) 16-7

TAR1 TAR1 Transfer Address Register 1 to Accumulator 1 (if no address is indicated)

14-11


TAR1 TAR1 Transfer Address Register 1 to Address Register 2 (T AR1 AR2) 14-11

TAR2 TAR2 Transfer Address Register 2 to Accumulator 1 (if no address is indicated)

14-11


TRUNC TRUNC Truncate 18-12

UC UC Unconditional Call 23-7

X X Exclusive Or 11-10

X( X( Exclusive Or with Nesting Open 11-14

XN XN Exclusive Or Not 11-9

XN( XN( Exclusive Or Not with Nesting Open 11-14

XOD XOD Exclusive Or Double Word (32-Bit) 19-6

XOW XOW Exclusive Or Word (16-Bit) 19-3



C79000-G7076-C565-01

A.2 Alphabetical Listing with International Names

Table A-3 provides an alphabetical listing of the full international names ofthe statement list instructions. Next to each name is its internationalmnemonic abbreviation and the page on which the instruction is explained.

Table A-3 Statement List Instructions Arranged Alphabetically by International Full Name

Name MnemonicAbbreviation

Page No.

Absolute Value of a Real (32-Bit IEEE FP) ABS 16-6

Accumulator 1 ---> Accumulator 2 PUSH 10-2

Accumulator 1 <--- Accumulator 2 POP 10-2

Accumulator 1 <--- Accumulator 2, Accumulator 2 <--- Accumulator 3, Accumulator 3 <--- Accumulator 4

POP 10-2

Accumulator 3 ---> Accumulator 2, Accumulator 4 ---> Accumulator 3 LEAVE 10-3

Accumulator 3 ---> Accumulator 4, Accumulator 2 ---> Accumulator 3 ENT 10-3

Accumulator 3 ---> Accumulator 4, Accumulator 2 ---> Accumulator 3, Accumulator 1 ---> Accumulator 2

PUSH 10-2

Activate MCR Area MCRA 23-11

Add Accumulator 1 and Accumulator 2 as Double Integer (32-Bit) +D 15-2

Add Accumulator 1 and Accumulator 2 as Integer (16-Bit) +I 15-2

Add Accumulator 1 and Accumulator 2 as Real (32-Bit IEEE FP) +R 16-2

Add Accumulator 1 to Address Register 1 +AR1 10-7

Add Accumulator 1 to Address Register 2 +AR2 10-7

Add Integer Constant (8, 16, 32-Bit) + 15-6

And A 11-10

And Double Word (32-Bit) AD 19-6

And Not AN 11-9

And Not with Nesting Open AN( 11-14

And with Nesting Open A( 11-14

And Word (16-Bit) AW 19-3

Arc Cosine of a Floating-Point Number (32-Bit IEEE FP) ACOS 16-7

Arc Sine of a Floating-Point Number (32-Bit IEEE FP) ASIN 16-7

Arc Tangent of a Floating-Point Number (32-Bit IEEE FP) ATAN 16-7

Assign = 11-24

BCD to Double Integer (32-Bit) BTD 18-4

BCD to Integer (16-Bit) BTI 18-2

Block End Conditional BEC 23-15

Block End Unconditional BEU 23-15

Call CALL 23-3

Change Byte Sequence in Accumulator 1 (16-Bit) CAW 18-13

Change Byte Sequence in Accumulator 1 (32-Bit) CAD 18-13



Table A-3 Statement List Instructions Arranged Alphabetically by International Full Name, continued

Name Page No.MnemonicAbbreviation

Clear RLO (= 0) CLR 11-26

Compare Double Integer (32-Bit) >, <, >=, <=, ==, <> ==D 17-3

Compare Integer (16-Bit) >, <, >=, <=, ==, <> ==I 17-3

Compare Real >, <, >=, <=, ==, <> ==R 17-3

Conditional Call CC 23-7

Cosine of a Floating-Point Number (32-Bit IEEE FP) COS 16-7

Counter Down CD 13-5

Counter Up CU 13-5

Deactivate MCR Area MCRD 23-11

Decrement Accumulator 1 DEC 10-6

Divide Accumulator 2 by Accumulator 1 as Double Integer (32-Bit) /D 15-2

Divide Accumulator 2 by Accumulator 1 as Integer (16-Bit) /I 15-2

Divide Accumulator 2 by Accumulator 1 as Real (32-Bit IEEE FP) /R 16-2

Division Remainder Double Integer (32-Bit) MOD 15-5

Double Integer (32-Bit) to BCD DTB 18-6

Double Integer (32-Bit) to Real (32-Bit IEEE FP) DTR 18-7

Edge Negative FN 11-17

Edge Positive FP 11-16

Enable Counter (Free, FR C 0 to C 255) FR 12-5

Enable Timer (Free, FR T 0 to T 255) FR 13-3

Exchange Address Register 1 with Address Register 2 CAR 14-11

Exchange Shared Data Block and Instance Data Block CDB 21-2

Exclusive Or X 11-10

Exclusive Or Double Word (32-Bit) XOD 19-6

Exclusive Or Not XN 11-9

Exclusive Or Not with Nesting Open XN( 11-14

Exclusive Or with Nesting Open X( 11-14

Exclusive Or Word (16-Bit) XOW 19-3

Exponential Value of a Floating-Point Number (32-Bit IEEE FP) to base E EXP 16-12

Extended Pulse Timer SE 12-9

Increment Accumulator 1 INC 10-6

Integer (16-Bit) to BCD ITB 18-5

Integer (16-Bit) to Double Integer ITD 18-6

Jump if 0 JZ 22-6

Jump if BR = 0 JNBI 22-4

Jump if BR = 1 JBI 22-4

Jump if Minus JM 22-6



C79000-G7076-C565-01



Jump if Minus or 0 JMZ 22-6

Jump if Not 0 JN 22-6

Jump if OS = 1 JOS 22-5

Jump if OV = 1 JO 22-5

Jump if Plus JP 22-6

Jump if Plus or 0 JPZ 22-6

Jump if RLO = 0 JCN 22-4

Jump if RLO = 0 with BR JNB 22-4

Jump if RLO = 1 JC 22-4

Jump if RLO = 1 with BR JCB 22-4

Jump if Unordered JUO 22-6

Jump to Labels JL 22-3

Jump Unconditional JU 22-3

Load L 14-3

Load Address Register 1 from ... (from address indicated) LAR1 14-11

Load Address Register 1 from Accumulator 1 (if no address is indicated) LAR1 14-11

Load Address Register 1 from Address Register 2 (LAR1 AR2) LAR1 14-11

Load Address Register 1 with Double Integer (32-Bit, LAR1 P#area byte.bit) LAR1 14-11

Load Address Register 2 from ... (from address indicated) LAR2 14-11

Load Address Register 2 from Accumulator 1 (if no address is indicated) LAR2 14-11

Load Address Register 2 with Double Integer (32-Bit, LAR2 P#area byte.bit) LAR2 14-11

Load Current Counter Value into Accumulator 1 as Integer (where the number of thecurrent counter can be in the range of 0 to 255, for example: L C 15)

L 13-614-8

Load Current Counter Value into Accumulator 1 as BCD (where the number of thecurrent counter can be in the range of 0 to 255, for example: LC C 15)

LC 14-9

Load Current Timer Value into Accumulator 1 as BCD (where the number of thecurrent timer can be in the range of 0 to 255, for example: LC T 32)

LC 13-714-10

Load Current Timer Value into Accumulator 1 as Integer (where the number of thecurrent timer can be in the range of 0 to 255, for example: L T 32)

L 14-7

Load Length of Instance Data Block into Accumulator 1 (L DILG) L 14-1221-2

Load Length of Shared Data Block into Accumulator 1 (L DBLG) L 14-1221-2

Load Number of Instance Data Block into Accumulator 1 (L DINO) L 14-1221-2

Load Number of Shared Data Block into Accumulator 1 (L DBNO) L 14-1221-2

Load Status Word into Accumulator 1 (L STW) L 14-6

Loop LOOP 22-8

Multiply Accumulator 1 by Accumulator 2 as Double Integer (32-Bit) *D 15-2





Multiply Accumulator 1 by Accumulator 2 as Integer (16-Bit) *I 15-2

Multiply Accumulator 1 by Accumulator 2 as Real (32-Bit IEEE FP) *R 16-2

Natural Logarithm of a Floating-Point Number (32-Bit IEEE FP) LN 16-11

Negate Real Number (32-Bit IEEE FP) NEGR 18-14

Negate RLO NOT 11-26

Nesting Closed ) 11-14

Null Operation 0 NOP 0 10-2

Null Operation 1 NOP 1 10-2

Off-Delay Timer SF 12-15

On-Delay Timer SD 12-11

Ones Complement Double Integer (32-Bit) INVD 18-14

Ones Complement Integer (16-Bit) INVI 18-14

Open a Data Block OPN 21-2

Or O 11-10

Or Double Word (32-Bit) OD 19-6

Or Not ON 11-9

Or Not with Nesting Open ON( 11-14

Or with Nesting Open O( 11-14

OR Word (16-Bit) OW 19-3

Program Display Instruction BLD 10-2

Pulse Timer SP 12-7

Reset R 11-22

Reset Counter (where the current counter can have a number in the range of 0 to 255,for example: R C 15)

R 12-5

Reset Timer (where the current timer can have a number in the range of 0 to 255, forexample: R T 32)

R 13-4

Restore RLO, End MCR )MCR 23-11

Retentive On-Delay Timer SS 12-13

Rotate Accumulator 1 Left via CC 1 (32-Bit) RLDA 20-8

Rotate Accumulator 1 Right via CC 1 (32-Bit) RRDA 20-6

Rotate Left Double Word (32-Bit) RLD 20-6

Rotate Right Double Word (32-Bit) RRD 20-8

Round RND 18-9

Round to Lower Double Integer RND- 18-11

Round to Upper Double Integer RND+ 18-10

Save RLO in BR Register SAVE 11-26

Save RLO in MCR Stack, Begin MCR MCR( 23-11

Set S 11-21



C79000-G7076-C565-01



Set Counter Preset Value (where the current counter can have a number in the range of0 to 255, for example: S C 15)

S 13-3

Set RLO (= 1) SET 11-26

Shift Left Double Word (32-Bit) SLD 20-2

Shift Left Word (16-Bit) SLW 20-2

Shift Right Double Word (32-Bit) SRD 20-3

Shift Right Word (16-Bit) SRW 20-2

Shift Sign Double Integer (32-Bit) SSD 20-4

Shift Sign Integer (16-Bit) SSI 20-4

Sine of a Floating-Point Number (32-Bit IEEE FP) SIN 16-7

Square of a Floating-Point Number (32-Bit IEEE PF) SQR 16-9

Square Root of a Floating-Point Number (32-Bit IEEE PF) SQRT 16-9

Subtract Accumulator 1 from Accumulator 2 as Double Integer (32-Bit) -D 15-2

Subtract Accumulator 1 from Accumulator 2 as Integer (16-Bit) -I 15-2

Subtract Accumulator 1 from Accumulator 2 as Real (32-Bit IEEE FP) -R 16-2

Tangent of a Floating-Point Number (32-Bit IEEE FP) TAN 16-7

Toggle Accumulator 1 with Accumulator 2 TAK 10-2

Transfer T 14-3

Transfer Accumulator 1 to Status Word (T STW) T 14-6

Transfer Address Register 1 to ... (to address indicated) TAR1 14-11

Transfer Address Register 1 to Accumulator 1 (if no address is indicated) TAR1 14-11

Transfer Address Register 1 to Address Register 2 (T AR1 AR2) TAR1 14-11

Transfer Address Register 2 to ... (to address indicated) TAR2 14-11

Transfer Address Register 2 to Accumulator 1 (if no address is indicated) TAR2 14-11

Truncate TRUNC 18-12

Twos Complement Double Integer (32-Bit) NEGD 18-14

Twos Complement Integer (16-Bit) NEGI 18-14

Unconditional Call UC 23-7


B-1Statement List (STL) for S7-300/S7-400C79000-G7076-C565-01

Programming Examples


B.1 Overview B-2

B.2 Bit Logic Instructions B-3

B.3 Timer Instructions B-7

B.4 Counter and Comparison Instructions B-10

B.5 Integer Math Instructions B-12

B.6 Word Logic Instructions B-14

Chapter Overview

B

B-2Statement List (STL) for S7-300/S7-400

C79000-G7076-C565-01

B.1 Overview

Each statement list instruction described in this manual triggers a specificoperation. When you combine these instructions into a program, you canaccomplish a wide variety of automation tasks. This chapter provides thefollowing examples of practical applications of the statement list instructions:

� Controlling a conveyor belt using bit logic instructions

� Detecting direction of movement on a conveyor belt using bit logicinstructions

� Generating a clock pulse using timer instructions

� Keeping track of storage space using counter and comparison instructions

� Solving a problem using integer math instructions

� Setting the length of time for heating an oven

When you create an ASCII file that will be imported into the STL editor, youmust follow the conventions outlined in Appendix C.

The examples in this chapter use the following instructions:

� And (A) and And Not (AN)

� Assign (=)

� Block End (BE) and Block End Conditional (BEC)

� Compare Integer (16-bit, <=, >=)

� Counter Down (CD) and Counter Up (CU)

� Edge Positive (FP)

� Extended Pulse Timer (SE)

� Increment Accumulator 1 (INC)

� Integer Four-function Math (16 BITS)

– Add Accumulators 1 and 2 As Integer (+I)

– Divide Accumulator 2 by Accumulator 1 As Integer (/I)

– Multiply Accumulators 1 and 2 As Integers (�I)

� Load (L) and Transfer (T)

� Negate RLO (NOT)

� Or (O) and Or Not (ON)

� Set (S) and Reset (R)

� Word Logic (And Word, Or Word)

PracticalApplications

Instructions Used



B.2 Bit Logic Instructions

Figure B-1 shows a conveyor belt that can be activated electrically. There aretwo push button switches at the beginning of the belt: S1 for START and S2for STOP. There are also two push button switches at the end of the belt: S3for START and S4 for STOP. It it possible to start or stop the belt from eitherend. Also, sensor S5 stops the belt when an item on the belt reaches the end.

You can write a program to control the conveyor belt shown in Figure B-1using symbols that represent the various components of the conveyor system.If you choose this method, you need to make a symbol table to correlate thesymbols you choose with absolute values (see Table B-1). Table B-3compares a statement list program that uses symbols as addresses to aprogram that uses absolute values as addresses. You define the symbols in thesymbol table (see STEP 7 Online Help).

Table B-1 Elements of Symbolic Programming for Conveyor Belt System

System ComponentAbsoluteAddress

Symbol Symbol Table

Push Button Start Switch I 1.1 S1 I 1.1 S1

Push Button Stop Switch I 1.2 S2 I 1.2 S2

Push Button Start Switch I 1.3 S3 I 1.3 S3

Push Button Stop Switch I 1.4 S4 I 1.4 S4

Sensor I 1.5 S5 I 1.5 S5

Motor Q 4.0 MOTOR_ON Q 4.0 MOTOR_ON

MOTOR_ON

S1S2

� Start� Stop

S3S4

� Start� Stop

Sensor S5

Figure B-1 Conveyor Belt System

Controlling aConveyor Belt

SymbolicProgramming



C79000-G7076-C565-01

You can write a program to control the conveyor belt shown in Figure B-1using absolute values that represent the different components of the conveyorsystem (see Table B-2). Table B-3 compares a statement list program thatuses absolute values as addresses to a program that uses symbols asaddresses. An explanation of the program follows the tables.

Table B-2 Elements of Absolute Programming for Conveyor Belt System

System Component Absolute Address

Push Button Start Switch I 1.1

Push Button Stop Switch I 1.2

Push Button Start Switch I 1.3

Push Button Stop Switch I 1.4

Sensor I 1.5

Motor Q 4.0

Table B-3 Symbolic and Absolute Programs to Control a Conveyor Belt

Symbolic Program Absolute Program

O S1O S3S MOTOR_ONO S2O S4ON S5R MOTOR_ON

O I 1.1O I 1.3S Q 4.0O I 1.2O I 1.4ON I 1.5R Q 4.0

STL Explanation

O I 1.1O I 1.3S Q 4.0O I 1.2O I 1.4ON I 1.5R Q 4.0

Pressing either start switch turns the motor on.

Pressing either stop switch or opening the normally closedcontact at the end of the belt turns the motor off.

AbsoluteProgramming



Figure B-2 shows a conveyor belt that is equipped with two photoelectricbarriers (PEB1 and PEB2) that are designed to detect the direction in which apackage is moving on the belt. Each photoelectric light barrier functions likea normally open contact (see Section 5.1).

You can write a program to activate a direction display for the conveyor beltsystem shown in Figure B-2 using symbols that represent the variouscomponents of the conveyor system, including the photoelectric barriers thatdetect direction. If you choose this method, you need to make a symbol tableto correlate the symbols you choose with absolute values (see Table B-4).Table B-6 compares a statement list program that uses symbols as addressesto a program that uses absolute values as addresses. You define the symbolsin the symbol table (see the STEP 7 Online Help).

Table B-4 Elements of Symbolic Programming for Detecting Direction

System ComponentAbsoluteAddress

Symbol Symbol Table

Photo electric barrier 1 I 0.0 PEB1 I 0.0 PEB1

Photo electric barrier 2 I 0.1 PEB2 I 0.1 PEB2

Display for movement to right Q 4.0 RIGHT Q 4.0 RIGHT

Display for movement to left Q 4.1 LEFT Q 4.1 LEFT

Pulse memory bit 1 M 0.0 PMB1 M 0.0 PMB1

Pulse memory bit 2 M 0.1 PMB2 M 0.1 PMB2

PEB1PEB2 Q 4.1Q 4.0

Figure B-2 Conveyor Belt System with Photoelectric Light Barriers for Detecting Direction

Detecting theDirection of aConveyor Belt

SymbolicProgramming



C79000-G7076-C565-01

You can write a program to control the direction display for the conveyor beltshown in Figure B-2 using absolute values that represent the photoelectricbarriers that detect direction (see Table B-5). Table B-6 compares a statementlist program that uses absolute values as addresses to a program that usessymbols as addresses. An explanation of the program follows the figure.

Table B-5 Elements of Absolute Programming for Detecting Direction

System Component Absolute Address

Photo electric barrier 1 I 0.0

Photo electric barrier 2 I 0.1

Display for movement to right Q 4.0

Display for movement to left Q 4.1

Pulse memory bit 1 M 0.0

Pulse memory bit 2 M 0.1

Table B-6 Symbolic and Absolute Programs to Detect Direction

Symbolic Program Absolute Program

A I PEB1FP PMB1AN PEB2S LEFTA PEB2FP PMB2AN PEB1S RIGHTAN PEB1AN PEB2R RIGHTR LEFT

A I 0.0FP M 0.0AN I 0.1S Q 4.1A I 0.1FP M 0.1AN I 0.0S Q 4.0AN I 0.0AN I 0.1R Q 4.0R Q 4.1

STL Explanation

A I 0.0FP M 0.0AN I 0.1S Q 4.1

A I 0.1FP M 0.1AN I 0.0S Q 4.0

AN I 0.0AN I 0.1R Q 4.0R Q 4.1

If there is a transition in signal state from 0 to 1(positive edge) at input I 0.0 and, at the same time, thesignal state at input I 0.1 is 0, then the package on the belt is moving to the left.

If there is a transition in signal state from 0 to 1(positive edge) at input I 0.1 and, at the same time, thesignal state at input I 0.0 is 0, then the package on the belt is moving to the right. If one of thephotoelectric light barriers is broken, this means that there is a package between the barriers.

If neither photoelectric barrier is broken, then there is no package between the barriers. The direction pointershuts off.

AbsoluteProgramming



B.3 Timer Instructions

You can use a clock pulse generator or flasher relay when you need toproduce a signal that repeats periodically. A clock pulse generator is commonin a signalling system that controls the flashing of indicator lamps.

When you use the S7-300, you can implement the clock pulse generatorfunction by using time-driven processing in special organization blocks. Theexample shown in the following statement list program, however, illustratesthe use of timer functions to generate a clock pulse.

The following example shows how to implement a freewheeling clock pulsegenerator by using a timer (pulse duty factor 1:1). The frequency is dividedinto the values listed in Table B-7.

STL Explanation

AN T 1L S5T#250msSE T 1NOTBECL MB100INC 1T MB100

If timer T 1 has expired, load the time value 250 ms intoT 1 and start T 1 as an extended-pulse timer.Negate (invert) the result of logic operation.If the timer is running, end the current block. If thetimer has expired, load the contents of memory byte MB100,increment the contents by 1, and transfer the result tomemory byte MB100.

A signal check of timer T 1 produces the result of logic operation.

0

1

250 ms

Figure B-3 RLO for AN T 1 Statement in the Clock Pulse Timer Example

As soon as the time runs out, the timer is restarted. Therefore, the signalcheck made by the statement AN T 1 produces a signal state of 1 onlybriefly.

0

1

250 ms

Figure B-4 Negated RLO Bit of Timer T 1 in the Clock Pulse Timer Example

Every 250 ms the RLO bit is 0. Figure B-4 shows what the negated (inverted)RLO bit looks like. Then the BEC statement does not end the processing ofthe block. Instead, the contents of memory byte MB100 is incremented by 1.

The contents of memory byte MB100 changes every 250 ms as follows:0 �1�2�3��... �254�255�0�1 ...

Clock PulseGenerator



C79000-G7076-C565-01

Table B-7 lists the frequencies that you can achieve from the individual bitsof memory byte MB100. The statement list program that follows the tableshows how you can use the frequencies that are generated.

Table B-7 Frequencies for Clock Pulse Timer Example

Bits ofMB100

Frequency in Hertz Duration

M 100.0 2.0 0.5 s (250 ms on/250 ms off)

M 100.1 1.0 1 s (0.5 s on/0.5 s off)

M 100.2 0.5 2 s (1 s on/1 s off

M 100.3 0.25 4 s (2 s on/2 s off)

M 100.4 0.125 8 s (4 s on/4 s off)

M 100.5 0.0625 16 s (8 s on/8 s off)

M 100.6 0.03125 32 s (16 s on/16 s off)

M 100.7 0.015625 64 s (32 s on/32 s off)

STL Explanation

A M 10.0A M 100.1= Q 4.0

M 10.0 = 1 when a fault occurs.

The fault lamp blinks at a frequency of 1 Hz when a fault occurs.

Achieving aSpecificFrequency



Table B-8 lists the signal states of the bits of memory byte MB100.Figure B-5 shows the RLO of memory bit M100.1.

Table B-8 Signal States of the Bits of Memory Byte MB100

Scan Signal State of Bits of Memory Byte MB100 TimeValueCycle 7 6 5 4 3 2 1 0Valuein ms

0 0 0 0 0 0 0 0 0 250

1 0 0 0 0 0 0 0 1 250

2 0 0 0 0 0 0 1 0 250

3 0 0 0 0 0 0 1 1 250

4 0 0 0 0 0 1 0 0 250

5 0 0 0 0 0 1 0 1 250

6 0 0 0 0 0 1 1 0 250

7 0 0 0 0 0 1 1 1 250

8 0 0 0 0 1 0 0 0 250

9 0 0 0 0 1 0 0 1 250

10 0 0 0 0 1 0 1 0 250

11 0 0 0 0 1 0 1 1 250

12 0 0 0 0 1 1 0 0 250

M 100.1

250 ms 0.5 s 0.75 s 1 s 1.25 s 1.5 s

T

Time01

Frequency� 1T�

11 s

� 1Hz

0

Figure B-5 Signal State of Bit 1 MB100 (M 100.1)



C79000-G7076-C565-01

B.4 Counter and Comparison Instructions

Figure B-6 shows a system with two conveyor belts and a temporary storagearea in between them. Conveyor belt 1 delivers packages to the storage area.A photoelectric barrier at the end of conveyor belt 1 near the storage areadetermines how many packages are delivered to the storage area. Conveyorbelt 2 transports packages from the temporary storage area to a loading dockwhere trucks take the packages away for delivery to customers. Aphotoelectric barrier at the end of conveyor belt 2 near the storage areadetermines how many packages leave the storage area to go to the loadingdock.

A display panel with five lamps indicates the fill level of the temporarystorage area. The sample program that follows Figure B-6 is the program thatactivates the indicator lamps on the display panel.

Storage areaempty

Display Panel

Storage areafilled to capacity

Storage area90% full

Storage area50% full

Storage areanot empty

Packages in Packages outI 0.0 I 0.1

Conveyor belt 2Conveyor belt 1

Photoelectric barrier 1 Photoelectric barrier 2

Temporarystorage for 100packages

(Q 4.0) (Q 4.1) (Q 4.2) (Q 4.3) (Q 4.4)

Figure B-6 Storage Area with Counter and Comparator

Storage Area withCounter andComparator



STL Explanation

A I 0.0CU C 1

A I 0.1CD C 1

AN C 1= Q 4.0A C 1= Q 4.1L +50L C 1<=I= Q 4.2L +90>=I= Q 4.3L C 1L 100>=I= Q 4.4

Each pulse generated by photoelectric barrier 1 increasesthe count value of counter C 1 by one, thereby countingthe number of packages going into the storage area.Each pulse generated by photoelectric barrier 2 decreasesthe count value of counter C 1 by one, thereby countingthe packages that leave the storage area.If the count value is 0, the indicator lamp for “Storagearea empty” comes on.If the count value is not 0, the indicator lamp for“Storage area not empty” comes on.If 50 is less than or equal to the count value, theindicator lamp for “Storage area 50% full” comes on.

If the count value is greater than or equal to 90, theindicator lamp for “Storage area 90% full” comes on.

If the count value is greater than or equal to 100, theindicator lamp for “Storage area filled to capacity”comes on. (You could also use output Q 4.4 to lockconveyor belt 1.)



C79000-G7076-C565-01

B.5 Integer Math Instructions

The following sample program (applicable for the S7-300 only) shows youhow to use three integer math instructions, along with Load and Transfer, toproduce the same result as the following equation:

MD4�(IW0�DBW3)� 15

MW2

STL Explanation

L IW0L DB5.DBW3

+I

L +15

�I

L MW2

/I

T MD4

Load the value from input word IW0 into accumulator 1.Load the value from shared data word DBW3 of DB5 intoaccumulator 1. The old contents of accumulator 1 areshifted to accumulator 2.Add the contents of the low words of accumulators 1 and2. The result is stored in the low word of accumulator 1. The contents of accumulator 2 and the high word ofaccumulator 1 remain unchanged.Load the constant value +15 into accumulator 1. The oldcontents of accumulator 1 are shifted to accumulator 2.Multiply the contents of the low word of accumulator 2 by the contents of the low word of accumulator 1. Theresult is stored in accumulator 1. The contents ofaccumulator 2 remain unchanged.Load the value from memory word MW2 into accumulator 1.The old contents of accumulator 1 are shifted toaccumulator 2.Divide the contents of the low word of accumulator 2 bythe contents of the low word of accumulator 1. The result is stored in accumulator 1. The contents ofaccumulator 2 remain unchanged.Transfer the final result to memory double word MD4. Thecontents of both accumulators remain unchanged.

Solving a MathProblem



Figure B-7 shows the relationship of the program to the equation.

+

L IW0

L DBW3

+I

L +15

�I

L MW2

/I

T MD4

Accumulator 1 Accumulator 2

(IW0) � (Old contents)

(DBW3) � (IW0)

(IW0) + (DBW3) (IW0)

15 � (IW0) + (DBW3)

[(IW0) + (DBW3)] �15 (IW0) + (DBW3)

MW2 � [(IW0) + (DBW3)] �15

(IW0�DBW3)� 15MW2

(IW0�DBW3)� 15

(IW0�DBW3)� 15MW2

�

��

/�

MD4�(IW0�DBW5)� 15

MW2

(IW0�DBW3)� 15

Figure B-7 Relationship of Integer Math Statements to an Equation (S7-300)



C79000-G7076-C565-01

B.6 Word Logic Instructions

The operator of the oven shown in Figure B-8 starts the oven heating bypushing the start push button. The operator can set the length of time forheating by using the thumbwheel switches shown in the figure. The valuethat the operator sets indicates seconds in binary coded decimal (BCD)format. Table B-9 lists the components of the heating system and theircorresponding absolute addresses used in the sample program that followsFigure B-8.

Table B-9 Heating System Components and Corresponding Absolute Addresses

System Component Absolute Address in STL Program

Start push button I 0.7

Thumbwheel for ones I 1.0 to I 1.3

Thumbwheel for tens I 1.4 to I 1.7

Thumbwheel for hundreds I 0.0 to I 0.3

Heating starts Q 4.0

7....

OvenÎÎÎÎÎÎÎÎÎÎ

1 0 0 1 0 0 0 1X X X X 0 0 0 1

HeatQ 4.0

Thumbwheels for setting BCD digits

IW0

4 4 4

Start push button I 0.7

IB1IB0 Bytes

Bits7......0 ...0

Figure B-8 Using the Inputs and Outputs for the Time-Limited Heating Process

STL Explanation

A T 1= Q 4.0BEC

L IW0AW W#16#0FFF

OW W#16#2000

A I 0.7SE T 1BE

If the timer is running, then turn on the heat.

If the timer is running, then end processing here. This preventstimer T 1 from being restarted if the push button is pressed.Mask input bits I 0.4 through I 0.7 (that is, reset them to 0).The time value in seconds is in the low word of accumulator 1 inbinary coded decimal format.Assign the time base as seconds in bits 12 and 13 of the low wordof accumulator 1.Start timer T 1 as an extended pulse timer if the push button ispressed.End the program network.

Heating an Oven


C-1Statement List (STL) for S7-300/S7-400C79000-G7076-C565-01

Source Files - Examples andReserved Keywords

A keyword is a reserved identifier which cannot be used as a generalidentifier.

To use a keyword as a global symbol it must be marked as scan cyclecheckpoint (SCC).

To use a keyword as a local symbol it must be marked with #.

Table C-1 lists all keywords reserved for STEP 7.

Table C-1 Keywords

Keywords

A B

AB BEGIN

AD BIE

ANY BLOCK_DB

AO BLOCK_FB

AR1 BLOCK_FC

AR2 BLOCK_SDB

ARRAY BOOL

AUTHOR BYTE

AW

C DATA_BLOCK

CALL DATE

CHAR DATE_AND_TIME

COUNTER DB

DBB

DBD

DBLG

DBNO

DBW

DBX

Definition

Overview

C

C-2Statement List (STL) for S7-300/S7-400

C79000-G7076-C565-01

Table C-1 Keywords, continued

Keywords

DI

DIB

DID

DILG

DINO

DINT

DIW

DIX

DT

DWORD

E FALSE

EB FAMILY

ED FB

END_Data_Block FC

END_Function FUNCTION

END_Function_Block FUNCTION_BLOCK

END_Organization_Block

END_Struct I

END_System_Function IB

END_System_Function_Block ID

END_Type INT

END_VAR IW

EW

KA L

KNOW_HOW_PROTECT LB

KP LD

LW

M NAME

MB NETWORK

MD NI

MW NO

OB PA

OF PAB

ORGANIZATION_BLOCK PAD

Source Files – Examples and Reserved Keywords

C-3Statement List (STL) for S7-300/S7-400C79000-G7076-C565-01


Keywords

OS PAW

OV PE

PEB

PED

PEW

PI

PIB

PID

PIW

PQ

PQB

PQD

PQW

POINTER

Q READ_ONLY

QB REAL

QD RET_VAL

QW

S5T T

S5TIME TIME

SDB TIME_OF_DAY

SFB TIMER

SFC TITLE

STANDARD TOD

STRING TRUE

STRUCT TYPE

STW

SYSTEM_FUNCTION

SYSTEM_FUNCTION_BLOCK

UDT VAR

UNLINKED VAR_IN_OUT

UO VAR_INPUT

VAR_OUTPUT

VAR_TEMP

VERSION


C-4Statement List (STL) for S7-300/S7-400

C79000-G7076-C565-01


Keywords

VOID

WORD Z


D-1Statement List (STL) for S7-300/S7-400C79000-G7076-C565-01

References

/30/ Getting Started: Working with STEP 7 V5.0

/70/ Manual: S7-300 Programmable Controller, Hardware and Installation

/71/ Reference Manual: S7-300, M7-300 Programmable ControllersModule Specifications

/72/ Instruction List: S7-300 Programmable Controller

/100/ Manual: S7-400/M7-400 Programmable Controllers,Hardware and Installation

/101/ Reference Manual: S7-400/M7-400 Programmable ControllersModule Specifications

/102/ Instruction List: S7-400 Programmable Controller

/231/ Manual:Configuring Hardware and Communication Connections, STEP 7 V5.0

/233/ Reference Manual: Ladder Logic (LAD) for S7-300 and S7-400Programming

/234/ Manual: Programming with STEP 7 V5.0

/235/ Reference Manual: System Software for S7-300 and S7-400System and Standard Functions

/236/ Reference Manual: Function Block Diagram (FBD) for S7-300 and 400,Programming

/250/ Manual: Structured Control Language (SCL) for S7-300/S7-400, Programming

/251/ Manual: S7-GRAPH for S7-300 and S7-400, Programming Sequential Control Systems

/252/ Manual: S7-HiGraph for S7-300 and S7-400, Programming State Graphs

/253/ Manual: C Programming for S7-300 and S7-400, Writing C Programs

/254/ Manual: Continuous Function Charts (CFC) for S7 and M7, Programming Continuous Function Charts

/270/ Manual: S7-PDIAG for S7-300 and S7-400“Configuring Process Diagnostics for LAD, STL, and FBD”

/271/ Manual: NETPRO, “Configuring Networks”

D

D-2Statement List (STL) for S7-300/S7-400

C79000-G7076-C565-01

/800/ DOCPROCreating Wiring Diagrams (CD only)

/801/ TeleService for S7, C7 and M7Remote Maintenance for Automation Systems (CD only)

/802/ PLC Simulation for S7-300 and S7-400 (CD only)

/803/ Reference Manual: Standard Software for S7-300 and S7-400,STEP 7 Standard Functions, Part 2

References

Glossary-1Statement List (STL) for S7-300/S7-400C79000-G7076-C565-01

Glossary

A

In absolute addressing, the memory location of the address to be processed isgiven.

Accumulators are registers in the CPU which act as intermediate buffers forload, transfer, comparison, math, and conversion operations.

Actual parameters replace the formal parameters when function blocks (FBs)and functions (FCs) are called.

Example: The formal parameter “Start” is replaced by the actual parameter“I3.6”.

An address is part of a STEP 7 statement and specifies what the processorshould execute the instruction on. Addresses can be absolute or symbolic.

An address identifier is the part of the address which contains various data.The data can include elements such as a value itself (data object) or the sizeof a value with which the instruction can, for example, perform a logicoperation. In the instruction statement “L IB10” IB is the address identifier(“I” indicates the memory input area and “B” indicates a byte in that area).

The address register is part of the registers in the communication part of theCPU. They act as pointers for register indirect addressing (possible in STL).

An array is a complex data type which consists of data elements of the sametype. These data elements can be elementary or complex.

AbsoluteAddressing

Accumulator

Actual Parameter

Address

Address Identifier

Address Register

Array

Glossary-2Statement List (STL) for S7-300/S7-400

C79000-G7076-C565-01

B

The bit result is the link between bit and word-oriented processing. This is anefficient method to allow the binary interpretation of the result of a wordinstruction and to include it in a series of logic operations.

C

All blocks must be called first before they can be processed. The sequenceand nesting of these calls within an organized block is called the callhierarchy.

The CC 1 and CC 0 bits (condition codes) provide information on thefollowing results or bits:

� Result of a math operation

� Result of a comparison

� Result of a digital operation

� Bits that have been shifted out by a shift or rotate command

A CPU (central processing unit) is the central module in a programmablecontroller in which the user program is stored and processed. It consists of anoperating system, processing unit, and communication interfaces.

Characteristic of the Ladder Logic programming language. Current pathscontain contacts and coils. Complex elements (for example, math functions)can also be inserted into current paths in the form of “boxes.” Current pathsare connected to power rails.

D

Data blocks (DBs) are areas in a user program which store user data. Thereare shared data blocks which can be accessed by all logic blocks and thereare instance data blocks which are associated with a certain function block(FB) call. In contrast to all other blocks, data blocks do not containinstructions.

Bit Result (BR)

Call Hierarchy

Condition CodesCC 1 and CC 0

CPU

Current Path

Data Block (DB)

Glossary


Static data are local data of a function block which are stored in the instancedata block and, therefore, remain intact until the function block is processedagain.

A data type defines how the value of a variable or a constant should be usedin the user program.

In SIMATIC STEP 7 two data types are available to the user (IEC 1131–3):

� Elementary data types

� Complex data types

Complex data types are created by the user with the data type declaration.They do not have their own name and cannot, therefore, be used again. Theycan either be arrays or structures. The data types STRING and DATE ANDTIME are classed as complex data types.

Elementary data types are preset data types according to IEC 1131–3.

Examples:

� Data type “BOOL” defines a binary variable (“Bit”)

� Data type “INT” defines a 16-bit fixed-point variable.

The declaration section is used for the declaration of the local data of a logicblock when programming in the Text Editor.

In direct addressing, the address contains the memory location of a valuewhich is to be used by the instruction.

Example:

The location Q4.0 defines bit 0 in byte 4 of the process-image output table.

F

First check of the result of logic operation.

Directory of the user interface of the SIMATIC Manager which can beopened and can hold other directories or objects.

Data, Static

Data Type

Data Type,Complex

Data Type,Elementary

Declaration

Direct Addressing

First Check Bit

Folder

Glossary


C79000-G7076-C565-01

A formal parameter is a placeholder for the actual parameter in logic blocks.In function blocks (FBs) and functions (FCs) the formal parameters aredeclared by the user, in system function blocks (SFBs) and system functions(SFCs) they are already available. When a block is called, formal parametersare assigned actual parameters, so the called block works with the currentvalues.The formal parameters are classed as local data. They can be input, output, orin/out parameters.

According to the International Electrotechnical Commission’s IEC 1131–3standard, functions are logic blocks without a ‘memory’ (meaning they donot have static data). A function allows you to transfer parameters in the userprogram, which means they are suitable for programming frequentlyrecurring, complex functions, such as calculations. Important: As a functionhas no memory, you must continue processing the calculated values directlyafter the function has been called.

According to the International Electrotechnical Commission’s IEC 1131–3standard, function blocks are logic blocks with a ‘memory’ (meaning theyhave static data). A function block allows you to transfer parameters in theuser program, which means they are suitable for programming frequentlyrecurring, complex functions, such as closed-loop control and operatingmode selection. As a function block has a memory (instance data block), youcan access its parameters (for example, outputs) at any time and at any pointin the user program.

Function Block Diagram (FBD) is one of the programming languages inSTEP 5 and STEP 7. FBD represents logic in the boxes familiar fromBoolean algebra. In addition, complex functions (for example, mathfunctions) can be represented in direct connection with the logic box.Programs created with FBD can also be translated into other programminglanguages (for example, Ladder Logic).

I

In immediate addressing, the address contains the value with which theinstruction works.

Example: L.27 means load constant 27 into accumulator.

When a block is input incrementally, each line or element is checkedimmediately for errors (for example, syntax errors). If an error is detected, itis marked and must be corrected before programming is completed.Incremental input is possible in STL (Statement List), LAD (Ladder Logic),and FBD (Function Block Diagram).

Formal Parameter

Function (FC)

Function Block(FB)

Function BlockDiagram (FBD)

ImmediateAddressing

Input, Incremental

Glossary


An “instance” is the call of a function block. An instance data block isassigned to each call.

An instance data block stores the formal parameters and the static data offunction blocks. An instance data block can be assigned to one functionblock call or a call hierarchy of function blocks.

An instruction is part of a STEP 7 statement; it specifies what the processorshould do.

K

Keywords are used when programming with source files to identify the startand end of a block and to select sections in the declaration section of blocks,the start of block comments and the start of titles.

L

Ladder Logic is a graphic programming language in STEP 5 and STEP 7. Itsrepresentation is standardized in compliance with DIN 19239 (internationalstandard IEC 1131-1). Ladder Logic representation corresponds to therepresentation of relay ladder logic diagrams. In contrast to Statement List(STL), LAD has a restricted set of instructions.

Logic blocks are blocks within SIMATIC S7 that contain a part of theSTEP 7 user program. In contrast, data blocks (DBs) only contain data. Thereare the following types of logic blocks: organization blocks (OBs), functionblocks (FBs), functions (FCs), system function blocks (SFBs), and systemfunctions (SFCs). Blocks are stored in the “Blocks” folder under the “S7Program” folder.

A logic string is that portion of a user program which begins with an FC bitthat has a signal state of 0 and which ends when an instruction or event resetsthe FC bit to 0. When the CPU executes the first instruction in a logic string,the FC bit is set to 1. Certain instructions such as output instructions (forexample, Set, Reset, or Assign) reset the FC bit to 0. See First Check Bitabove.

Instance

Instance DataBlock (DB)

Instruction

Keyword

Ladder Logic(LAD)

Logic Block

Logic String

Glossary


C79000-G7076-C565-01

M

The Master Control Relay (MCR) is an American relay ladder logic masterswitch for energizing and de-energizing power flow (current path). Ade-energized current path corresponds to an instruction sequence that writes azero value instead of the calculated value, or, to an instruction sequence thatleaves the existing memory value unchanged.

In SIMATIC S7 a CPU has three memory areas:

� Load memory

� Work memory

� System memory

A type of addressing in which the address of an instruction indicates thelocation of the value with which the instruction is to work.

Mnemonic representation is an abbreviated form for displaying the names ofaddresses and programming instructions in the program (for example, “I”stands for “input”). STEP 7 supports the international representation (basedon the English language), and the SIMATIC representation (based on theGerman abbreviations of the instruction set and the SIMATIC addressingconventions).

N

The nesting stack is a storage byte used by the nesting instructions A(, O(,X(, AN(, ON(, XN(. A total of eight bit logic instructions can be stacked.

Networks subdivide LAD and FBD blocks into complete current paths andStatement List (STL) blocks into clear units.

O

The OR bit is needed if you perform a logical AND before OR operation.The OR bit shows these instructions that a previously executed AND functionhas supplied the value 1, thus forestalling the result of the logical ORoperation. Any other bit-processing command resets the OR bit (seeSection 5.4).

Master ControlRelay

Memory Area

Memory IndirectAddressing

MnemonicRepresentation

Nesting Stack

Network

OR Bit

Glossary


The status bit OV stands for overflow. An overflow can occur, for example,after a math operation.

P

You can use a pointer to identify the address of a variable. A pointer containsan identifier instead of a value. If you allocate an actual parameter type, youprovide the memory address. With STEP 7 you can either enter the pointer inpointer format or simply as an identifier (for example, M 50.0). In thefollowing example, the pointer format is shown with which data from M 50.0is accessed:

P#M50.0

A project is a folder for all objects in an automation task, irrespective of thenumber of stations, modules, and how they are connected in networks.

R

Reference data are used to check your S7 program and include thecross-reference list, the assignment lists, the program structure, the list ofunused addresses, and the list of addresses without symbols.

A type of addressing in which the address of an instruction indicatesindirectly via an address register and an offset the memory location of thevalue with which the instruction is to work.

The result of logic operation (RLO) is the result of the logic string which isused to process other binary signals. The execution of certain instructionsdepends entirely on their preceding RLO.

S

A folder for blocks, source files, and charts for S7 programmable controllers.The S7 program also includes the symbol table.

A shared data block is a DB whose address is loaded in the DB addressregister when it is opened. It provides storage and data for all logic blocks(FCs, FBs, or OBs) that are being executed.

Overflow Bit

Pointer

Project

Reference Data

Register IndirectAddressing

Result of LogicOperation (RLO)

S7 Program

Shared Data Block(DB)

Glossary


C79000-G7076-C565-01

In contrast, an instance DB is designed to be used as specific storage and datafor the FB with which it has been associated.

The SIMATIC Manager is the graphical user interface for SIMATIC usersunder Windows 95.

A source file (text file) is part of a program created either with a graphic or atext-oriented editor and is compiled into an executable S7 user program orthe machine code for M7.

An S7 source file is stored in the “Sources” folder under the “S7 program”folder.

A statement is the smallest independent part of a user program created in atextual language. The statement represents a command for the processor.

Statement List (STL) is a textual representation of the STEP 7 programminglanguage, similar to machine code. STL is the assembler language of STEP 5and STEP 7. If you program in STL, the individual statements represent theactual steps in which the CPU executes the program.

A station is a device which can be connected to one or more subnets; forexample, the programmable controller, programming device, and operatorstation.

The status bit stores the value of a bit that is referenced. The status of a bitinstruction that has read access to the memory (A, AN, O, ON, X, XN) isalways the same as the value of the bit that this instruction checks (the bit onwhich it performs its logic operation). The status of a bit instruction that haswrite access to the memory (S, R, =) is the same as the value of the bit towhich the instruction writes or, if no writing takes place, the same as thevalue of the bit that the instruction references. The status bit has nosignificance for bit instructions that do not access the memory. Suchinstructions set the status bit to 1 (STA=1). The status bit is not checked byan instruction. It is interpreted during program test (program status) only.

The status word is part of the register of the CPU. It contains statusinformation and error information which is displayed when specific STEP 7commands are executed. The status bits can be read and written on by theuser, the error bits can only be read.

A source file programmed in Statement List; corresponds to a source or textfile.

SIMATIC Manager

Source File

Statement

Statement List(STL)

Station

Status Bit

Status Word

STL Source File

Glossary


The status bit OS stands for “stored overflow bit of the status word”. Anoverflow can take place, for example, after a math operation.

A symbol is a name which can be defined by the user subject to syntaxguidelines. After it has been declared (for example, as a variable, data type,jump label, block etc) the symbol can be used for programming and foroperator interface functions. Example: Address: I 5.0, data type: BOOL,Symbol: momentary contact switch / emergency stop.

A table in which the symbols of addresses for shared data and blocks areallocated. Examples: Emergency Stop (symbol) -I 1.7 (address) orclosed-loop control (symbol) - SFB24 (block).

In symbolic addressing, the address being processed is designated with asymbol (as opposed to an absolute address).

A system function is a function (without a memory) that is integrated in theS7 operating system and can, if necessary, be called from the STEP 7 userprogram like a function (FC).

A system function block (SFB) is a function (with a memory) that isintegrated in the S7 operating system and can, if necessary, be called fromthe STEP 7 user program like a function block (FB).

U

User data types are special data structures which you can create yourself anduse in the entire user program after they have been defined. They can be usedlike elementary or complex data types in the variable declaration of logicblocks (FCs, FBs, OBs) or as a template for creating data blocks with thesame data structure.

The user program contains all the statements and declarations and all the datafor signal processing which can be used to control a device or a process. It ispart of a programmable module (CPU, FM) and can be structured withsmaller units (blocks).

The user program structure describes the call hierarchy of the blocks withinan S7 program and provides an overview of the blocks used and theirdependency.

Stored OverflowBit

Symbol

Symbol Table

SymbolicAddressing

System Function(SFC)

System FunctionBlock (SFB)

User Data Types(UDTs)

User Program

User ProgramStructure

Glossary


C79000-G7076-C565-01

V

The variable declaration includes a symbolic name, a data type and,optionally, an initial value, an address and a comment.

The variable declaration table is used for declaring the local data of a logicblock, when programming takes place in the Incremental Editor.

The variable table is used to collect together the variables that you want tomonitor and modify and set their relevant formats.

VariableDeclaration

VariableDeclaration Table

Variable Table(VAT)

Glossary

Index-1Statement List (STL) for S7-300/S7-400C79000-G7076-C565-01

Index

Symbols)MCR. See Restore RLO, End MCR instruction+. See Instructions, integer math, adding an in-

teger to accumulator 1+I. See Four-function math, Adding two 16-bit

integers; Instructions, integer math, addingtwo 16-bit integers

+R. See Floating-point math, Adding two float-ing-point numbers

=. See Assign (=) instruction

AABS. See Absolute value, forming the absolute

value of a real (floating–point ) numberAbsolute addressing, practical application, B-4Absolute value

definition of, 10-6forming the absolute value of a real (float-

ing-point) number, 10-6Accumulator 1 to Accumulator 2 (PUSH), 4-2Accumulator 2 to Accumulator 1 (POP), 4-2Accumulator operations and address register

instructions, 4-2–4-6Accumulator 1 to Accumulator 2 (PUSH),

4-2Accumulator 2 to Accumulator 1 (POP), 4-2Decrement Accumulator 1 (DEC), 4-6Decrement Accumulator 1 (DEC), 4-6Increment Accumulator 1 (INC), 4-6Increment Accumulator 1 (INC), 4-6Toggle ACCU 1 with ACCU 2, 4-2

Accumulatorsadding a constant to an address register, 4-7adding an integer to accumulator 1, 9-6description of, 2-10functions

Accumulator 2 to Accumulator 1 (POP),4-2

Decrement Accumulator 1 (DEC), 4-6Increment Accumulator 1 (INC), 4-6

handling the contents of, 4-2–4-6information interchange using Load and

Transfer instructions, 8-2loading the status word into, 8-6operation of, 2-10

with comparison instructions, 11-2with floating-point math instructions,

10-2–10-3with integer math instructions, 9-2–9-3with Load and Transfer instructions, 8-2with word logic instructions, 13-2, 13-3,

13-6operations

Accumulator 1 to Accumulator 2(PUSH), 4-2

Decrement Accumulator 1 (DEC), 4-6Increment Accumulator 1 (INC), 4-6

reversing the order of bytes within accumu-lator 1Change Byte Sequence in Accumulator

1, 16 bits (CAW) instruction, 12-13Change Byte Sequence in Accumulator

1, 32 bits (CAD) instruction, 12-13time value in, 6-4Toggle ACCU 1 with ACCU 2, 4-2Toggle the contents of, 4-2transferring the contents of to the status

word, 8-6

Index-2Statement List (STL) for S7-300/S7-400

C79000-G7076-C565-01

ACOS. See SecantActivate MCR Area (MCRA) instruction,

17-11–17-12Actual parameter, 17-2, 17-3Actual parameters, assignment, 17-8AD. See And Double Word instructionAddress

assigning addresses to a Call (CALL) in-struction, 17-3

bits of the status word as, 5-13constants as, 13-2description of, 2-2label for a jump instruction, 16-2label for a loop instruction, 16-2of instructions

Assign (=), 5-25Conditional Call (CC), 17-7counter, 7-10Edge Negative (FN), 5-19Edge Positive (FP), 5-19Load (L) and Transfer (T), 8-3–8-5Open a Data Block (OPN), 15-2Reset (R), 5-23Set (S), 5-23Timer, 6-17Unconditional Call (UC), 17-7

symbolic, 17-3types

address identifier and location, 2-5–2-6constants, 2-3, 13-2data block, 2-4function (FC), 2-5function block (FB), 2-5location in status word, 2-3symbolic, 2-4system function (SFC), 2-5system function block (SFB), 2-5

Address register, adding a real number to an ad-dress register, 4-7

Address registers, 3-6loading and transferring between, 8-11–8-12

Addressingabsolute, 17-3, B-4area-crossing register indirect, 3-11–3-14area-internal register indirect, 3-7–3-9constants, 2-3direct, 3-2immediate, 3-2memory indirect, 3-3–3-5pointer format

area-crossing register indirect, 3-13–3-14area-internal register indirect, 3-8area–internal register indirect, 3-9–3-10memory indirect, 3-4–3-5

ranges, 2-9symbolic, 2-4, 17-3, B-3

And (A), using counters as bit operands, 7-2And (A) instruction, 5-3And before Or, 5-15–5-16And Double Word (AD) instruction, 13-7–13-8And Not (AN), using counters as bit operands,

7-2And Not (AN) instruction, 5-3And Word (AW) instruction, 13-4–13-5

combining accumulator and constant,13-4–13-5

ANY, 17-9Arc cosine (ACOS), 10-13–10-15Arc sine (ASIN), 10-13–10-14Arc tangent (ATAN), 10-13Area-crossing register indirect addressing,

3-11–3-15Area-internal register indirect addressing,

3-7–3-9Areas of memory

address ranges, 2-9bit memory, 2-8counter, 2-8data block, 2-8I/O (external I/O), 2-8local data, 2-8peripheral I/O. See Areas of memory, I/O

(external I/O)process image input, 2-8process image output, 2-8timer, 2-8

ASIN. See CosecantAssign (=) instruction, 5-20, 5-24–5-25Assigning addresses to a Call (CALL) instruc-

tion, 17-3ATAN. See CotangentAW. See And Word instruction

Index


BBCD to Double Integer (BTD) conversion in-

struction, 12-4BCD to Integer (BTI) conversion instruction,

12-3–12-4BCDF. See Errors, binary coded decimal con-

versionBEC. See Blocks, ending: Block End Condi-

tional instructionBeginning a logic string, 2-12–2-13BEU. See Blocks, ending: Block End Uncondi-

tional instructionBinary coded decimal (BCD) format

loading a count in, 8-10loading a time in, 8-9

Binary coded decimal (BCD) numbersconverting, 12-2–12-9structure of a BCD number converted from a

32-bit integer, 12-6structure of a BCD number to be converted

from integer, 12-5structure of a BCD number to be converted

to integer, 12-3structure of a32-bit BCD number to be con-

verted to double integer, 12-4Binary result (BR), bit of status word, 2-16Bit logic instructions, And (A), using counters

as Boolean operands, 7-2Bit logic

Boolean, 5-2–5-12practical applications, B-3–B-6

Bit logic instructions, 5-2–5-5And Not (AN), using counters as Boolean

operands, 7-2Assign (=), 5-20, 5-24–5-25Clear RLO (CLR), 5-26–5-27Edge Negative (FN), 5-16–5-19Edge Positive (FP), 5-16–5-19Exclusive Or (X), using counters as Boolean

operands, 7-2Exclusive Or Not (XN), using counters as

Boolean operands, 7-2Negate RLO (NOT), 5-26Or (O), using counters as Boolean operands,

7-2Or Not (ON), using counters as Boolean op-

erands, 7-2practical applications, B-3–B-6Reset (R), 5-20, 5-21–5-23, 7-8–7-9

counter, 7-4timer, 6-6

Save RLO in BR Register (SAVE), 5-26Set (S), 5-20, 5-21–5-23

counter, 7-3, 7-8–7-9Set RLO (SET), 5-26, 5-27using counters as bit operands, 7-2

Bit memory area of memory, 2-8address ranges, 2-9

Blocks, endingBlock End Conditional (BEC) instruction,

17-16Block End Unconditional (BEU) instruction,

17-16Boolean bit logic, 5-2–5-12

And (A) instruction, 5-3And Not (AN) instruction, 5-3checking condition codes (CC 1 and CC 0),

2-14–2-15checking for overflow, 5-12–5-13nesting expressions, 5-14–5-15output of logic string, 5-20

BR. See Binary resultBTD. See BCD to Double Integer conversion

instructionBTI. See BCD to Integer conversion instruction

Index


C79000-G7076-C565-01

CCAD. See Change Byte Sequence in Accumula-

tor 1 conversion instruction, 32 bitsCALL. See Call instructionCall instruction, 17-3–17-5Calling a function that delivers a return value,

17-6Calling a program segment multiple times, 16-8CAW. See Change Byte Sequence in Accumula-

tor 1 conversion instruction, 16 bitsCC. See Conditional Call instructionCC 1 and CC 0. See Condition codesCD. See Count Down instructionCDB. See Exchange Shared DB and Instance

DB instructionChange Byte Sequence in Accumulator 1 con-

version instruction16 bits (CAW), 12-1332 bits (CAD), 12-13

Checking condition codes (CC 1 and CC 0),2-14–2-15

ClearingRLO (CRL) instruction, 5-26–5-27the result of logic operation, 5-26–5-27

CLR. See Clear RLO instructionComparing

two integers, 11-3–11-5two real numbers, 11-5–11-6

Comparison instructions, 11-2–11-3Compare Double Integer, 11-3–11-5Compare Integer, 11-3–11-5Compare Real Number, 11-5criteria for comparisons, 11-2operation of accumulators, 11-2practical applications, B-10–B-11

Complements, forming, 12-14

Condition codes (CC 1 and CC 0)as affected by Compare instructions, 11-4,

11-5as affected by floating-point math instruc-

tions, 10-4as affected by integer math instructions, 9-4as affected by the shift and rotate instruc-

tions, 14-2as affected by word logic instructions, 13-2bits of status word, 2-14–2-15instructions that evaluate CC 1 and CC 0,

11-6relationship to conditional jump instructions,

16-6Conditional Call (CC) instruction, 17-7Conditional jump instructions

Jump If BR = 0 (JNBI), 16-5Jump If BR = 1 (JBI), 16-5Jump If Minus (JM), 16-6Jump If Minus or Zero (JMZ), 16-6Jump If Not Zero (JN), 16-6Jump If OS = 1 (JOS), 16-5Jump If OV = 1 (JO), 16-5Jump If Plus (JP), 16-6Jump If Plus or Zero (JPZ), 16-6, 16-7Jump If RLO = 0 (JCN), 16-4Jump If RLO = 0 with BR (JNB), 16-4Jump If RLO = 1 (JC), 16-4Jump If RLO = 1 with BR (JCB), 16-4Jump If Unordered (JUO), 16-6Jump If Zero (JZ), 16-6relationship of condition codes CC 1 and CC

0, 16-6

Index


Constantsadding an integer constant to accumulator 1,

9-6as addresses of word logic instructions, 13-2,

13-4–13-7Decrement Accumulator 1 by an 8-bit

constant, 4-6Decrementing Accumulator 1 by an 8-bit

constant, 4-6Incrementing Accumulator 1 by an 8-bit

constant, 4-6used as address, 2-3

Conversion instructionsBCD to Double Integer (BTD), 12-4BCD to Integer (BTI), 12-3–12-4Change Byte Sequence in Accumulator 1

16 bits (CAW), 12-1332 bits (CAD), 12-13

Double Integer to BCD (DTB), 12-6Double Integer to Real (DTR), 12-7Integer to BCD (ITB), 12-5Integer to Double Integer (ITD), 12-6Negate Real Number (NEGR), 12-14–12-15Ones Complement Double Integer (INVD),

12-14Ones Complement Integer (INVI), 12-14overview of number conversion and round-

ing, 12-12Round (RND), 12-9Round to Lower Double Integer (RND–),

12-11Round to Upper Double Integer (RND+),

12-10Truncate (TRUNC), 12-12Twos Complement Double Integer (NEGD),

12-14Twos Complement Integer (NEGI),

12-14–12-15Converting

32-bit floating-point numbers to 32-bit inte-gers, 12-8–12-12

binary coded decimal numbers and integers,12-2–12-9

numbers, 12-12COS. See CosineCosine (COS), 10-13Count Down (CD) instruction, 7-5Count Up (CU) instruction, 7-5Count value, format, 7-6–7-7

Countersarea of memory, 2-8

address ranges, 2-9components, 7-2count instructions, bit logic instructions, 7-2count value, format, 7-6–7-7definition of, 7-2enabling, 7-4, 7-8–7-9instructions used with counters, 7-2–7-9

bit logic, 5-22–5-23, 7-2Count Down (CD), 7-2, 7-5Count Up (CU), 7-2, 7-5Enable (FR), 7-2, 7-4Load Current Counter Value into Accu-

mulator 1 as Binary Coded Decimal(LC), 7-2, 8-10

Load Current Counter Value into Accu-mulator 1 as Integer, 7-2

practical applications, B-10–B-11Reset (R), 7-2, 7-4, 7-8–7-9Set (S), 7-2, 7-3, 7-8–7-9

resetting, 7-2, 7-4, 7-8–7-9setting, 7-2, 7-3, 7-8–7-9types

Count Down (CD), 7-2, 7-8–7-9Count Up (CU), 7-2, 7-8–7-9

CPU, registers, 3-6–3-11nesting stack, 2-10operation of accumulators, 2-10pointers, 3-6status word, 2-12–2-16time value in accumulator 1, 6-4

CU. See Count Up instruction

Index


C79000-G7076-C565-01

DData block (DB)

area of memory, 2-8address ranges, 2-9

instance, 17-3lengths and numbers, loading, 15-3–15-4loading the length of a shared data block

into accumulator 1 (L DBLG), 8-12, 15-3loading the length of an instance data block

into accumulator 1 (L DILG), 8-12, 15-3loading the number of a shared data block

into accumulator 1 (L DBNO), 8-12,15-3–15-4

loading the number of an instance data blockinto accumulator 1 (L DINO), 8-12, 15-3

registers, exchanging, 15-2Data block (DB) instructions

Exchange Shared DB and Instance DB(CDB), 15-2

Load Length of Instance Data Block in Ac-cumulator 1 (DILG), 15-3

Load Length of Shared Data Block in Accu-mulator 1 (DBLG), 15-3

Load Number of Instance Data Block in Ac-cumulator 1 (DINO), 15-3

Load Number of Shared Data Block in Ac-cumulator 1 (DBNO), 15-3–15-4

Open a Data Block (OPN), 15-2Data types

ANY, 17-9for actual and formal parameters, 17-3

DBLG. See Load Length of Shared DB in Accu-mulator 1 instruction

DBNO. See Load Number of Shared DB in Ac-cumulator 1 instruction

Deactivate MCR Area (MCRD) instruction,17-11–17-12

DEC. See Decrement Accumulator 1Decrement Accumulator 1 (DEC), 4-6DILG. See Load Length of Instance DB in Ac-

cumulator 1 instructionDINO. See Load Number of Instance DB in Ac-

cumulator 1 instructionDirect addressing, 3-2Double Integer to BCD (DTB) conversion in-

struction, 12-6Double Integer to Real (DTR) conversion in-

struction, 12-7Double integers, comparing two, 11-3–11-5DTB. See Double Integer to BCD conversion

instruction

DTR. See Double Integer to Real conversioninstruction

EEdge Negative (FN) instruction, 5-16–5-19Edge Positive (FP) instruction, 5-16–5-19Enable (FR) instruction

counters, 7-4, 7-8–7-9timers, 6-6

Enable output (ENO). See Binary resultEnding blocks

Block End Conditional (BEC) instruction,17-16

Block End Unconditional (BEU) instruction,17-16

Errors, binary coded decimal conversion(BCDF), 12-3, 12-4

Examples, practical applications of instructions,B-2–B-14

Exchange Shared DB and Instance DB (CDB)instruction, 15-2

Exchange the contents of accumulators, 4-2Exclusive Or (X), using counters as Boolean

operands, 7-2Exclusive Or Not (XN), using counters as Bool-

ean operands, 7-2Exclusive Or Word (XOW) instruction, 13-3,

13-4–13-5combining accumulator and constant,

13-4–13-5EXP. See Exponential value to base EExponential value to base E, EXP, 10-12Extended Pulse Timer (SE), 6-5, 6-9–6-10

FFBs. See Function blocksFCs. See FunctionsFirst check (FC)

bit of status word, 2-12–2-13result of, 2-12

Index


Floating-point mathAdding two floating-point numbers (+R),

10-3, 10-4instructions

forming the absolute value of a real num-ber (ABS), 10-6

overview of four-function math, 10-2relationship to accumulators, 10-2–10-3valid ranges of result, 10-4

Floating-point math, extended operationsarc cosine (ACOS), 10-13–10-15arc tangent (ATAN), 10-13

Floating-point math, extended math operations,arc sine (ASIN), 10-13–10-14

FN. See Edge Negative instructionFormal parameter, 17-2Formal parameters, 17-3Format

count value, 7-6–7-7time value, 6-4

Forming complements, 12-14Four-function math, Adding two 16-bit integers

(+I), 9-3FP. See Edge Positive instructionFR. See Enable instructionFunction (FC)

as address of an instruction, 2-5calling FCs with the Call (CALL) instruc-

tion, 17-3–17-5calling FCs with the Conditional Call (CC)

instruction, 17-7calling FCs with the Unconditional Call

(UC) instruction, 17-7dependency on Master Control Relay

(MCR), 17-11Function block (FB)

as address of an instruction, 2-5calling FBs with the Call (CALL) instruc-

tion, 17-3–17-5calling FBs with the Conditional Call (CC)

instruction, 17-7calling FBs with the Unconditional Call

(UC) instruction, 17-7dependency on Master Control Relay

(MCR), 17-11

II/O (external I/O) area of memory, 2-8

address ranges, 2-9Image registers. See Process-imageImmediate addessing, 3-2INC. See Increment Accumulator 1Increment Accumulator 1 (INC), 4-6Instruction statement

addressingconstants, 2-3symbolic, 2-4

structure of, 2-2–2-7Instructions

accumulator operation and address register,4-2–4-6

alphabetical listing, international names,A-12–A-16

bit logic, practical applications, B-3–B-6comparison, 11-2–11-8

criteria for comparison, 11-2operation of accumulators, 11-2practical applications, B-10–B-11

conversion, overview of number conversionand rounding, 12-12

counter, 7-2–7-13practical applications, B-10–B-11

dependent on the Master Control Relay(MCR), 17-11

dependent on the Master control Relay(MCR), 17-10

floating-point mathoverview of four-function math, 10-2relationship to accumulators, 10-2–10-3valid ranges of results, 10-4

integer mathoverview of four-function math instruc-

tions, 9-2practical applications, B-12–B-13relationship to accumulators, 9-2–9-3valid ranges of results, 9-4

jump, unconditional, 16-3–16-4Load (L) and Transfer (T), 8-2–8-12

area-crossing indirect addressing, 8-5

Index


C79000-G7076-C565-01

byte, word, or double word as address,8-5

definition of, 8-2direct addressing, 8-4immediate addressing, 8-3indirect addressing, 8-4information interchange, 8-2loading and transferring between address

registers (LAR and TAR), 8-11–8-12loading bits of the status word into accu-

mulator 1, 8-6loading the status word into accumulator

1, 8-6transferring the contents of accumulator

1 to the status word, 8-6loading and transferring between address

registers (LAR and TAR), 8-11–8-12logic control, 16-2–16-11

See also Jump instructionsLoop (LOOP), 16-8

providing a label as address, 16-8using efficiently, 16-9

practical applications, B-2–B-14program control, assigning addresses to a

call, 17-3rotate, 14-6–14-8shift, 14-2–14-6

signed numbers, 14-4unsigned numbers, 14-2–14-3

shift and rotate, 14-2–14-6that evaluate the condition codes (CC 1 and

CC 0), 9-4, 10-4that evaluate the overflow bit (OV) of the

status word, 9-4, 10-4that evaluate the stored overflow bit (OS) of

the status word, 9-4, 10-4timer, 6-2–6-17

practical applications, B-7–B-10Transfer (T). See Load (L) and Transfer (T)

instructionsword logic, 13-2–13-8

16-bit, 13-3–13-832-bit, 13-6–13-8accumulator administration, 13-2, 13-3,

13-6constants as addresses, 13-2influence on status word bits, 13-2practical applications, B-14

Instructions that affect the status word, 5-10Integer math, adding a real to an address regis-

ter, 4-7

Integer math instructionsadding an integer constant to accumulator 1,

9-6adding two 16-bit integers (+I), 9-3overview of four-function math instructions,

9-2practical applications, B-12–B-13relationship to accumulators, 9-2–9-3valid ranges of results, 9-4

Integer to BCD (ITB) conversion instruction,12-5

Integer to Double Integer (ITD) conversion in-struction, 12-6

Integersadding to accumulator 1, 9-6comparing two, 11-3–11-5converting, 12-2–12-9

International names for instructions, alphabeti-cal listing, A-12–A-16

International names of the statement list (STL)instructions, A-12

INVD. See Ones Complement Double Integerconversion instruction

Inverting numbers bit by bit, 12-14INVI. See Ones Complement Integer conversion

instructionITB. See Integer to BCD conversion instructionITD. See Integer to Double Integer conversion

instruction

JJBI. See Jump If BR = 1 instructionJC. See Jump If RLO = 1 instructionJCB. See Jump If RLO = 1 with BR instructionJCN. See Jump If RLO = 0 instructionJL. See Jump to List instructionJM. See Jump If Minus instructionJMZ. See Jump If Minus or Zero instructionJN. See Jump If Not Zero instructionJNB. See Jump If RLO = 0 with BR instructionJNBI. See Jump If BR = 0 instructionJO. See Jump If OV = 1 instructionJOS. See Jump If OS = 1 instructionJP. See Jump If Plus instructionJPZ. See Jump If Plus or Zero instructionJU. See Jump Unconditional instructionJump If BR = 0 (JNBI) instruction, 16-5Jump If BR = 1 (JBI) instruction, 16-5Jump If Minus (JM) instruction, 16-6

Index


Jump If Minus or Zero (JMZ) instruction, 16-6Jump If Not Zero (JN) instruction, 16-6Jump If OS = 1 (JOS) instruction, 16-5Jump If OV = 1 (JO) instruction, 16-5Jump If Plus (JP) instruction, 16-6Jump If Plus or Zero (JPZ) instruction, 16-6,

16-7Jump If RLO = 0 (JCN) instruction, 16-4Jump If RLO = 0 with BR (JNB) instruction,

16-4Jump If RLO = 1 (JC) instruction, 16-4Jump If RLO = 1 with BR (JCB) instruction,

16-4Jump If Unordered (JUO) instruction, 16-6Jump If Zero (JZ) instruction, 16-6Jump instructions, 16-3–16-10

condition based on BR, OV, or OS bit of sta-tus word, 16-5

condition based on result in condition codebits (CC 1 and CC 0) of status word,16-6–16-7

condition based on result of logic operation(RLO), 16-4–16-5

conditionalJump If BR = 0 (JNBI), 16-5Jump If BR = 1 (JBI), 16-5Jump If Minus (JM), 16-6Jump If Minus or Zero (JMZ), 16-6Jump If Not Zero (JN), 16-6Jump If OS = 1 (JOS), 16-5Jump If OV = 1 (JO), 16-5Jump If Plus (JP), 16-6Jump If Plus or Zero (JPZ), 16-6, 16-7Jump If RLO = 0 (JCN), 16-4Jump If RLO = 0 with BR (JNB), 16-4Jump If RLO = 1 (JC), 16-4Jump If RLO = 1 with BR (JCB), 16-4Jump If Unordered (JUO), 16-6Jump If Zero (JZ), 16-6

label as address, 16-2overview of, 16-2unconditional, 16-3–16-4

Jump to List (JL), 16-3Jump Unconditional (JU), 16-3

Jump to List (JL) instruction, 16-3Jump Unconditional (JU) instruction, 16-3JUO. See Jump If Unordered instructionJZ. See Jump If Zero instruction

KKeywords, definition, C-1

LL. See Load and Transfer instructionsLabel, as address of a jump or loop instruction,

16-2LAR. See Loading and transferring between ad-

dress registersLC. See Load Current Value into Accumulator 1

as Binary Coded DecimalLN. See Natural LogarithmLoad (L) and Transfer (T) instructions, 8-2–8-12

See also Instructions, Load (L) and Transfer(T)

area-crossing indirect addressing, 8-5byte, word, or double word as address, 8-5definition of, 8-2direct addressing, 8-4immediate addressing, 8-3indirect addressing, 8-4information interchange, 8-2

between modules and memory areas, 8-2by way of the accumulator, 8-2

Load Current Counter Value into Accumula-tor 1 as Binary Coded Decimal (LC),8-10

loading and transferring between addressregisters (LAR and TAR), 8-11–8-12

loading bits of the status word into accumu-lator 1, 8-6

loading the length of a shared data blockinto accumulator 1 (L DBLG), 8-12

loading the length of an instance data blockinto accumulator 1 (L DILG), 8-12

loading the number of a shared data blockinto accumulator 1 (L DBNO), 8-12

loading the number of an instance data blockinto accumulator 1 (L DINO), 8-12

loading the status into accumulator 1, 8-6transferring the contents of accumulator 1 to

the status word, 8-6Load Current Value into Accumulator 1 as

Binary Coded Decimalcounter, 7-2timer, 6-2

Index


C79000-G7076-C565-01

Load Length of Instance DB in Accumulator 1(DILG) instruction, 15-3

Load Length of Shared DB in Accumulator 1(DBLG) instruction, 15-3

Load Number of Instance DB in Accumulator 1(DINO) instruction, 15-3

Load Number of Shared DB in Accumulator 1(DBNO) instruction, 15-3–15-4

Loading a count valueformat, 7-6in binary coded decimal (BCD) format (LC

counter word), 8-10in binary form (L counter word), 8-8

Loading a time valueformat, 6-3in binary coded decimal (BCD) format (LC

timer word), 8-9in binary form (L timer word), 8-7range, 6-5

Loading and transferring between address regis-ters, 8-11–8-12

Loading data block lengths and numbers,15-3–15-4

Loading the length of a data block into accumu-lator 1instance data block (L DILG), 8-12shared data block (L DBLG), 8-12

Loading the number of a data block into accu-mulator 1instance data block (L DINO), 8-12shared data block (L DBNO), 8-12

Local data, area of memory, 2-8address ranges, 2-9

Logic control instructions, 16-2–16-11See also Jump and Loop instructions

Logic stringbeginning of, 2-12–2-13definition of, 2-12–2-13output of, 5-20terminating, 5-20

Loop (LOOP) instruction, 16-8label as address, 16-2, 16-8using efficiently, 16-9

MMaster Control Relay (MCR)

dependency on, 17-10, 17-11effect on Set (S) and Reset (R) instructions,

5-21–5-22, 17-10implementation of, 17-13Important notes, 17-15

Master Control Relay (MCR) instructions,17-10–17-15See also Program control instructionsnesting, 17-13–17-15

MCR functions, Important notes, 17-15MCR(. See Save RLO in MCR Stack, Begin

MCR instructionMCRA. See Activate MCR Area instructionMCRD. See Deactivate MCR Area instructionMemory areas

address ranges, 2-9bit memory, 2-8counter, 2-8data block, 2-8I/O (external I/O), 2-8local data, 2-8process image input, 2-8process image output, 2-8timer, 2-8

Memory indirect addressing, 3-3–3-5Multiplying a number by –1, 12-14

NNatural Logarithm (LN), 10-11Negate Real Number (NEGR) conversion in-

struction, 12-14–12-15Negate RLO (NOT) instruction, 5-26Negating numbers, 12-14Negating the result of logic operation, 5-26Negative edge transitions, 5-16–5-19NEGD. See Twos Complement Double Integer

conversion instructionNEGI. See Twos Complement Integer conver-

sion instructionNEGR. See Negate Real Number conversion

instructionNesting expressions, 5-14–5-17

And before Or, 5-15–5-16Nesting stack, 2-10, 5-14Normally closed contact, 5-7Normally open contact, 5-6NOT. See Negate RLO instruction

Index


OOff-Delay Timer (SF), 6-5, 6-15–6-16On-Delay Timer (SD), 6-5, 6-11–6-12Ones Complement Double Integer (INVD) con-

version instruction, 12-14Ones Complement Integer (INVI) conversion

instruction, 12-14Open a Data Block (OPN) instruction, 15-2Operand. See AddressOPN. See Open a Data Block instructionOR, bit of status word, 2-14Or (O), using counters as bit operands, 7-2Or branch, nesting expressions, 5-14–5-17Or Not (ON), using counters as bit operands,

7-2Or Word (OW) instruction, 13-3, 13-4–13-5

combining accumulator and constant,13-4–13-5

Order of processing And with Or instructions,5-15–5-16

OS. See Stored overflowOutput of a logic string, 5-20OV. See OverflowOverflow (OV)

as affected by comparing two real numbers,11-5

as affected by floating-point math instruc-tions, 10-4

as affected by integer math instructions, 9-4as affected by the shift and rotate instruc-

tions, 14-2as affected by word logic instructions, 13-2bit of status word, 2-14

PParallel branch, nesting expressions, 5-14–5-17Parameters

actual, 17-3formal, 17-3

Pointer formatarea-crossing register indirect addressing,

3-13–3-14area–internal register indirect addressing,

3-9memory indirect addressing, 3-4–3-5

POP. See Accumulator 2 to Accumulator 1Positive edge transitions, 5-16–5-19

Process image input area of memory, 2-8Process image output area of memory, 2-8Process-image input area of memory, address

ranges, 2-9Process-image output area of memory, address

ranges, 2-9Processing order for And with Or instructions,

5-15–5-16Program control instructions

Activate MCR Area, 17-11–17-12assigning addresses to a Call (CALL) in-

struction, 17-3Block End Conditional (BEC), 17-16Block End Unconditional (BEU), 17-16Call (CALL), 17-3–17-5Conditional Call (CC), 17-7Deactivate MCR Area, 17-11–17-12Master Control Relay (MCR) functions,

17-10–17-15Restore RLO, End MCR: )MCR,

17-11–17-12, 17-13–17-14Save RLO in MCR Stack, Begin MCR:

MCR(, 17-11–17-12, 17-13–17-14Unconditional Call (UC), 17-7

Programming, practical applications, B-2–B-14Pulse Timer (SP), 6-5–6-6, 6-7–6-8PUSH. See Accumulator 1 to Accumulator 2

RR. See Reset instructionReal number

comparing two real numbers, 11-5forming the absolute value, 10-6

Registersaddress, 3-6CPU, 3-6–3-11Exchange Shared DB and Instance DB

(CDB) instruction, 15-2exchanging data block registers, 15-2image. See Process-image

Reset (R) instruction, 5-20, 5-21–5-23counters, 7-4, 7-8–7-9timers, 6-6

Resettinga counter, 7-4a timer, 6-6

Index


C79000-G7076-C565-01

Restore RLO, End MCR instruction: )MCR,17-11–17-12, 17-13–17-14

Result of logic operation (RLO)bit of status word, 2-13clearing, 5-26–5-27instructions that do not affect the RLO, 4-6negating, 5-26relationship to Block End instructions, 17-16saving, 5-26setting, 5-26, 5-27stored in nesting stack, 5-14transitions of, 5-16–5-19with Assign (=) instruction, 5-24–5-25

Retentive On-Delay Timer (SS), 6-5, 6-13–6-14Return value, calling a function that delivers a

return value, 17-6Reversing the order of bytes within accumulator

1, 12-13RLD. See Rotate instructions, Rotate Left

Double WordRLDA. See Rotate instructions, Rotate Accumu-

lator 1 Left via CC 1RLO. See Result of Logic OperationRND. See Round conversion instructionRND+. See Round to Upper Double Integer

conversion instructionRND–. See Round to Lower Double Integer

conversion instructionRotate instructions, 14-6–14-8

Rotate Accumulator 1 Left via CC 1(RLDA), 14-8

Rotate Accumulator 1 Right via CC 1(RRDA), 14-8

Rotate Left Double Word (RLD), 14-7–14-8Rotate Right Double Word (RRD), 14-7

Round (RND) conversion instruction, 12-9Round to Lower Double Integer (RND–) con-

version instruction, 12-11Round to Upper Double Integer (RND+) con-

version instruction, 12-10Rounding

32-bit floating-point numbers to double inte-gers, 12-8–12-11

numbers, overview, 12-12real numbers to double integers, 12-8–12-11

RRD. See Rotate instructions, Rotate RightDouble Word

RRDA. See Rotate instructions, Rotate Accu-mulator 1 Right via CC 1

SS. See Set instructionS5 TIME

time base, 6-4–6-5time value, 6-3

SAVE. See Save RLO in BR Register instruc-tion

Save RLO in BR Register (SAVE) instruction,5-26

Save RLO in MCR Stack, Begin MCR instruc-tion: MCR(, 17-11–17-12, 17-13–17-14

Saving, the result of logic operation, 5-26SD. See On–Delay TimerSE. See Extended Pulse TimerSET. See Set RLO instructionSet (S) instruction, 5-20, 5-21–5-23

counters, 7-3Set RLO (SET) instruction, 5-26, 5-27Setting

a counter, 7-3, 7-8–7-9the result of logic operation, 5-26, 5-27

SF. See Off–Delay TimerSFBs. See System function blocksSFCs. See System functionsShift and rotate instructions, 14-2–14-8Shift instructions, 14-2–14-6

effect on condition codes CC 1 and CC 0and on the Overflow bit(OV) of the sta-tus word, 14-2

method of operation, 14-2Shift Left Double Word (SLD, 32 bits), 14-2Shift Left Word (SLW, 16 bits), 14-2Shift Right Double Word (SRD, 32 bits),

14-2, 14-3Shift Right Word (SRW, 16 bits), 14-2Shift Sign Double Integer (SSD, 32 bits),

14-4Shift Sign Integer (SSI, 16 bits), 14-4signed numbers, 14-4unsigned numbers, 14-2–14-3

SIMATIC and International mnemonic abbrevi-ations of the statement list (STL) instruc-tions, A-2, A-7

SIN. See SineSine (SIN), 10-13SLD. See Shift instructions, Shift Left Double

WordSLW. See Shift instructions, Shift Left Word

Index


SP. See Pulse TimerSQR. See SquareSQRT. See Square rootSquare (SQR), 10-9Square root (SQRT), 10-9SRD. See Shift instructions, Shift Right Double

WordSRW. See Shift instructions, Shift Right WordSS. See Retentive On–Delay TimerSSD. See Shift instructions, Shift Sign Double

IntegerSSI. See Shift instructions, Shift Sign IntegerSTA. See Status, bit of status wordStarting a logic string, 2-12–2-13Starting a timer, 6-5Statement. See Instruction statementStatement list (STL), 1-1

definition of, 1-1Status (STA), bit of status word, 2-13Status word

binary result (BR) bit, 2-16bits affected by floating-point math instruc-

tions, 10-4bits affected by integer math instructions,

9-4bits affected by the shift and rotate instruc-

tions, 14-2condition code bits (CC 1 and CC 0), over-

flow bit (OV) as affected by word logicinstructions, 13-2

condition code bits CC 1 and CC 0, relation-ship to conditional jump instructions,16-6

condition codes (CC 1 and CC 0), 2-14–2-15condition codes CC 1 and CC 0 after a

Compare instruction, 11-4, 11-5description of, 2-12–2-16evaluation of 32-bit integer math result, 9-4first check (FC) bit, 2-12–2-13indication of valid range for integer math

result, 9-4instructions that affect the status word, 5-10instructions that evaluate the bits of the sta-

tus word, 11-6OR bit, 2-14overflow (OV) bit, 2-14overflow bit (OV) after a Compare Real

number instruction, 11-5reading using the Load (L) instruction, 8-6

result of logic operation (RLO) bit, 2-13status (STA) bit, 2-13stored overflow (OS) bit, 2-14stored overflow bit (OS) after a Compare

Real number instruction, 11-5transferring the contents of accumulator 1 to

it, 8-6STL instructions, alphabetical listing

arranged by International full name,A-12–A-16

arranged by the International mnemonic ab-breviations, A-7–A-11

arranged by the SIMATIC mnemonic abbre-viations, A-2–A-11

Stored overflow (OS)as affected by floating-point math instruc-

tions, 10-4as affected by integer math instructions, 9-4bit of status word, 2-14

Stored overflow (OV), as affected by comparingtwo real numbers, 11-5

Structure of an instruction statement, 2-2–2-7STW. See Status wordSwapping, data block registers, 15-2Symbolic addresses, 17-3Symbolic addressing, 2-4, 17-3

practical example, B-3System function blocks (SFBs), as address of an

instruction, 2-5System functions (SFCs), as address of an in-

struction, 2-5

TT. See Load and Transfer instructionsTAK. See Toggle Accumulator 1 with Accumu-

lator 2TAN. See TangentTangent (TAN), 10-13TAR. See Loading and transferring between ad-

dress registersTerminating a logic string, 5-20Terminating the scanning of a block, 17-16Time base for S5 TIME, 6-4–6-5Time resolution. See Time base for S5 TIME

Index


C79000-G7076-C565-01

Time valueformat in accumulator 1, 6-4range, 6-3–6-4syntax, 6-3

Timersarea of memory, 2-8

address ranges, 2-9components, 6-3–6-4definition of, 6-2enabling, 6-6instructions used with, 6-2–6-17instructions used with timers

bit logic, 5-22–5-23Enable (FR), 6-6Extended Pulse Timer (SE), 6-5,

6-9–6-10Off-Delay Timer (SF), 6-5, 6-15–6-16On-Delay Timer (SD), 6-5, 6-11–6-12practical applications, B-7–B-10Pulse Timer (SP), 6-5–6-6, 6-7–6-8Reset (R), 6-6Retentive On-Delay Timer (SS), 6-5,

6-13–6-14location in memory, 6-3number supported, 6-3resetting, 6-6resolution. See Time base for S5 TIMEstarting, 6-5time base for S5 TIME, 6-4–6-5time value, 6-3

range, 6-3–6-4syntax, 6-3

types, 6-2Extended Pulse (SE), 6-2, 6-5, 6-9–6-10Off-Delay (SF), 6-2, 6-5, 6-15–6-16On-Delay (SD), 6-2, 6-5, 6-11–6-12overview, 6-18Pulse (SP), 6-2, 6-5–6-6, 6-7–6-8Retentive On-Delay (SS), 6-2, 6-5,

6-13–6-14Toggle Accumulator 1 with Accumulator 2. See

TAK

Toggle the contents of Accumulator 1 with Ac-cumulator 2, 4-2

Transfer (T) instruction. See Load (L) andTransfer (T) instructions

Transferring the contents of accumulator 1 tothe status word, 8-6

Transitional contacts, 5-16–5-19TRUNC. See Truncate conversion instructionTruncate (TRUNC) conversion instruction,

12-12Twos Complement Double Integer (NEGD)

conversion instruction, 12-14Twos Complement Integer (NEGI) conversion

instruction, 12-14–12-15

UUC. See Unconditional Call instructionUnconditional Call (UC) instruction, 17-7Unconditional jump instructions

Jump to List (JL), 16-3Jump Unconditional (JU), 16-3

WWord logic instructions, 13-2–13-8

16-bit, 13-3–13-832-bit, 13-6–13-8accumulator administration, 13-2, 13-3, 13-6And Double Word (AD), 13-7–13-8And Word (AW), 13-4, 13-5Exclusive Or Word (XOW), 13-3Or Word (OW), 13-3, 13-4practical applications, B-14

XX. See Exclusive Or instructionXN. See Exclusive Or Not instruction

Index

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