static timing analysis basics by selva kumar

Static Timing Analysis

Selva Kumar R.

[email protected]

Selvakumar @ [email protected] 2

Overview

� Even though a digital circuit may be logically correct, one needs to know how it will perform on physical implementation

� Timing analysis is required • To meet a performance specification

• To evaluate how the design operates

� Timing Analysis : Point-point analysis of design without stimulus vectors


Session Topics

� Timing Paths

� Clock Skew

� Timing Constraints

� Slack


Timing Analysis� A ‘N’ bit input design to be verified completely requires

a 2N test patterns

� The approach of generating 2N patterns and applying them at different time & sequence is impractical

� The complexity of analysis of netlist is reduced by breaking the process into two steps

• One of functional verification

• Other of timing Verification

� The process of verifying the netlist through test benches and test patterns after P&R is known as Dynamic Timing Analysis

• Requires input from user / verification engineer


Dynamic Timing Analysis

� Dynamic timing analysis / simulation guarantees 100% coverage

� Though this guarantee comes at a cost of time

• Time of generation of patterns

• Time of application of patterns etc

� It is design specific

� One method cannot be used to all designs

� Hence for each design a unique test bench needs to be created

� A generalized approach is required so that verification process is speeded up


•Static Timing Analysis is a method of calculating the

expected timing of a digital circuit without requiring

simulation.

•STA is method of analyzing and validating the timing

performance of a design.

STA – What is Static Timing Analysis?

�Advantages:

�Much faster than gate-level simulation.

�Exhaustive

�Proper circuit functionality is not checked.

�Vector generation NOT required.


What is Timing Analysis?

Setup Requirement

Hold Requirement

�What are our circuit timing requirements?

Clk

100 200 300 400 5000

Data

Data Cannot

Change Within

These Windows

Data

Clk

D Q

QBOutput

OutputBar


Timing Terminologies

� Setup Time : Time for which data should be stable at the input of the ff before the arrival of clock (active edge) at the ff’s clock pin

� Hold Time : Time for which data should be stable at the input of the ff after the arrival of clock (active edge) at the ff’s clock pin

TSETUP

THOLD


Metastability

� For any flop to work its setup time and hold time requirements should be met


STA Process

� STA happens in three steps

� Circuit is broken down to sets of timing paths

� Delay of each path is calculated

� Path delays are checked to see if timing constraints have been met


Timing Paths

� ‘Timing’ refers to the time taken by data to travel from one point to the other

� The point at which data is expected to originate is considered a ‘start point’• Input Port

• Clock Pin of sequential elements

� The location at which data terminates is considered as the stop point• Output Port

• Data Pin of sequential elements


Three Steps in Timing Analysis

• Circuit is broken down into sets of timing paths.

• Delay of each path is calculated.

• Path delays are checked to see if timing constraints

have been met.


What is a Timing Path?

•A Timing Path is a point-to-point path in a design which

can propagate data from one flip-flop to another.

•Each path has a startpoint and an endpoint

•Startpoints:

•Input ports, Clock pins of flip-flops

•Endpoints:

•Output ports, Data input pins of flip-flops



� Critical Path : Theoretically path which has maximum delay

� Arrival Time : Time taken by data to reach a end point from a specific start point. Depends on complexity of logic through which data traverses

� Required Time : Time at which data is required at a particular end point. Depends on the requirements / specifications

� Slack : Difference in required time and arrival time. For a design to work the slack value should always be positive


Timing Paths

� Depending on the logic through which data propogates a design can be considered to comprise of 4 paths

• input –> reg : Data from Input port to the first flip-flop

• reg –> reg : Data from one flip-flop to another ff

• reg –> out : Data from last flip-flop to output port

• input –> output : Data from Input – Output with no

sequential components in between


Timing paths

� Input -> Reg

� Reg -> Reg

� Reg -> Output

� Input -> Output

• Input / Output also called as ‘Pad’ / ‘Pin’

• ‘Reg’ can be any of - flop, latch, RAM etc

• ‘Reg’ also called as clock / setup


Input –> Reg

� Path which starts at any input port and ends at the data pin of any sequential element that is first encountered

� Is controlled by the capture clock

� Data may start independently but must reach the sequential element before clock reaches the element


Reg –> Reg

� Path which starts at the clock pin of a ff or enable pin of latch and ends at the data pin of any sequential element that is next encountered


Reg –> Reg

� Path which starts at the clock pin of a ff or enable pin of latch and ends at the data pin of any sequential element that is next encountered

� Is controlled by both the launch as well as capture clock

� Data leaves the first sequential element on the clock and then races forward to reach the next sequential element before clock / enable reaches the element


Reg –> Out

� Path which starts at the clock pin of a ff or enable pin of latch and ends at the output port of the design

� Clock launches the data after which data runs uncontrolled


Input –> Output

� Path which starts at any input port and ends at any output port without traversing through any sequential element

� Clock has no role to play in this path

� Is seen mainly in purely combinational circuits practically rare in designs


Timing Paths Example

� How many start points are there in the circuit

� How many end points are there in the circuit

� How many paths are there in the circuit


Anatomy Of A Sequential Path

Combinational

Logic

Tclock-to-Q Tlogic Tsetup

Flip

Flop

φ

Flip

Flop

φ

One clock cycle

setupcomboQtoclockcycle TTTT ++= −−


Propagation Delay

� Delay of a cell depends on many factors such as

• Operating Conditions

• Functionality of the cell

• Type of Inputs

� Based on the factors above a cell can propagate data either quickly or slowly

� Depending on the kind of analysis being done at any point of time one needs to consider either minimum delays or maximum delays


Real world effects

� All parameters vary based on PVT which stands for Process, Voltage, Temperature.

• Higher voltage usually speeds things up.

• Higher temperature usually slows things down.

• Process variation is more difficult to quantify.

� Most datasheets specify maximum delays.


Delay Types

� Assume the ‘and’ gate shown below has a maximum delay of 3 ns at max operating conditions and for a 0-1 transition

� Let the ‘and’ gate have a delay of 0.6 ns at minimum operating conditions and for a 1-0 transition

� Which is the delay to be considered for analysis?


Clock Skew

� Clock feeds multimillion flip-flops

� Theoretically clock should arrive at same instance at all flip-flops – Practically impossible


Clock Skew

• Clock Skew: The maximum difference in arrival time of the

clock signal to each register in the design

clock

Clock arrivaltime at 1.1ns

Clock arrival time at 1.3ns

Skew = 1.3ns - 1.1ns = .2ns

•It is also defined as the difference in time that a single clock signal

takes to reach two different registers.


Clock Skew

� Variation in arrival of clock at clock pin of subsequent / consecutive flip-flops is known as skew


Clock Jitter

� The difference in arrival of clock at different flip-flops could be due to

• Jitter – cycle to cycle variation in clock period due to aging of oscillator, anomalies in the plletc


Clock Skew

� Skew can be considered to be of two types

• When clock arrives earlier than expected –generally known as negative skew

• When clock arrives later than expected –generally known as positive skew

� +ve skew can occur when data & clock travel in same direction

� -ve skew can occur when data & clock travel in opposite directions


Positive & Negative Skew

R1In

(a) Positive skew

CombinationalLogic

D Q

tCLK1CLK

delay

tCLK2

R2

D QCombinational

Logic

tCLK3

R3

• • •D Q

delay

R1In

(b) Negative skew

CombinationalLogic

D Q

tCLK1

delay

tCLK2

R2

D QCombinational

Logic

tCLK3

R3

• • •D Q

delay CLK


Positive Skew

Launching edge arrives before the receiving edge

+ve skewTclk + δ >= tcq1 + tcombo + t su2

(th2 + δ) < tcq1 + tcombo

CLK1

CLK2

T CLK

δ

T CLK + δ

+ t h δ

2

1

4

3


Negative Skew

Receiving edge arrives before the launching edge

-ve skewTclk - δ >= tcq1 + tcombo + t su2

(th2 - δ) < tcq1 + tcombo

CLK1

CLK2

T CLK

δ

T CLK - δ

2

1

4

3



� Critical Path : Theoretically path which has maximum delay

� Arrival Time : Time taken by data to reach a particular end point from a specific start point. Depends on complexity of logic through which data traverses

� Required Time : Time at which data is required at a particular end point. Depends on the requirements / specifications

� Slack : Difference in required time and arrival time. For a design to work the slack value should always be positive


Maximum Frequency

� For a circuit to meet its specifications the minimum time period or maximum frequency at which it works should be identified

� The frequency of operation of a circuit depends on the logic of the paths

� Each of the four kinds of paths have different required times


Frequency Calculations

� Arrival Time = TCOMBO, Max

� Required Time = TCP + TClock_Delay - TSETUP



� Arrival Time : TClk-Q + TCombo, MAX

� Required Time = TCP + TClock_Skew - TSETUP



� Arrival Time : TCombo, MAX

� Required Time : Explicit Timing Constraint

(If Specified)



� Arrival Time = TClk-Q + TCombo, MAX

� Required Time = Explicit Timing Constraint

(If Specified)


Problem 1

� Find The maximum Frequency for the circuit shown in figure below


Solution Methodology

� Step One : Find the total number of paths in the design

� Step Two : Identify the paths that are constrained by clock

� Step Three : Identify the arrival times of all the paths identified in step 2 above

� Step Four : Identify the required time equations of all paths identified in step 2

� Step Five : Equate the arrival times and required times of all relevant paths to obtain the time periods

� Step Six : Select the maximum applicable clock frequency from the clocks identified in step 5


Solution

� Three paths in the design• Input – Reg

• Reg – Reg

• Reg – Out

� Reg – Out path not constrained hence can be discarded for timing calculation

� Relevant Paths are Input – Reg and Reg – Reg

� Input – Reg Path• Arrival Time = 3

• Required Time = CP + 0.5 + 0.6 -Tsetup= CP + 1.1 -0.65

• Equating the 2, CP = 3 – 1.1 + 0.65 = 2.55


Solution

� Reg – Reg Path• Arrival Time = 0.5 + 0.6 + 1.4 + 4 = 6.5

• Required Time = 0.5 + 0.7 + 0.8 + CP – 0.75 = CP + 1.25

• Equating the two, CP = 6.5 – 1.25 = 5.25

� Two time periods available from the calculations 5.25, 2.55. Though first path can work if clock time period is 5.25 the second path can not work if clock time period is 2.55

� Hence the maximum clock frequency at which the circuit can work is 1/5.25


Problem 2

Paths from Q1 to Q1:




None

TW ≥ max tPDFF +tJKsu = 20 +10 = 30 ns

TW ≥ max tPDFF + max tAND + tJKsu = 20 + 12 + 10 = 42 ns

TW ≥ max tPJKFF + tOR + TDsu = 25 + 10 + 5 = 40 ns

TW ≥ max tPJKFF + max tAND + tJKsu = 25 + 12 + 10 = 47 ns

TW ≥ 47 ns


Problem 3

� Find the maximum applicable clock frequency for the circuit shown in figure below


Problem 4

� For the circuit shown in figure below find the maximum applicable clock frequency


Problem 5

� For the circuit shown in figure below find the maximum applicable clock frequency


Failure / Data loss Due To Large Skew

Combinational

LogicFlip

Flop

Flip

Flop

δ delayclk

“B”

AoutAin

“A”

Bin

� If new data (Ain) gets to point “B” before clock does, system will fail by simply skipping over old data…

� For this illustration - ignore tsetup


Combinational

LogicFlip

Flop

Flip

Flop

δ delayclk

“B”

AoutAin

“A”

Bin

Clock arrives at point “A”

T = 0ns


Data arrives at comb logic input

Combinational

LogicFlip

Flop

Flip

Flop

δ delayclk

“B”

Ain

“A”

BinAout

T = tclk-to-Q


Data Exits Comb Logic

Combinational

LogicFlip

Flop

Flip

Flop

δ delayclk

“B”

Ain

“A”

Aoutnew

Bin

Bin

T = tclk-to-Q + tlogic


Clock Reaches “B”

Combinational

LogicFlip

Flop

Flip

Flop

clk

“B”

Ain

“A”

Aoutnew

Bin

Bin

δ delay

T = tclk-to-Q + tlogic T = tδ


Failure!!!

Combinational

LogicFlip

Flop

Flip

Flop

clk

“B”

Ain

“A”

Aoutnew

Bin

Bin

δ delay

New

Bin

What happened to old Bin???

If tclk-to-Q+tlogic < tδ it fails…


Example 1D Q

QCK

Q

TW ≥ max tPFF + tsu

� For the 7474, max tPLH = 25ns, max tPHL = 40ns, tsu = 20ns

TW ≥ max (max tPLH + tsu, max tPHL + tsu)

TW ≥ max (25+20, 40+20) = 60


D Q

C K

Q

TW ≥ max tPFF + max tPINV + tsu

Example 2


Example 3

D Q

Q

D Q

Q

MUX

0

1

Q0 Q1

CK

TW ≥ max tPFF + max tPMUX + tsu


False paths• Paths that physically exist in a design but are not

logic/functional paths

• These paths never get sensitized under any input conditions

Mux 1

C C1 C2A

B

Mux 2

S

B1 B2

OUT

Total 4 timing paths

PATH 1 – A-C-C1-C2-OUT

PATH 2 – A-C-OUT

PATH 3 – B-B1-B2-C-C1-C2-OUT

PATH 4 – B-B1-B2-C-OUT

Only path1 and 4 above are valid logic paths as select line for the 2 muxes are the same


Multicycle Path

�Multicycle paths are paths which intentionally require more than one clock cycle to propagate.

�This information cannot possibly be inferred by the timing tool, so it must be specified by the designer so the analyzer can mark the path and correctly compute the timing.

�A start point, end point and/or "through" point is specified, along with the number of allowed clock

cycles.

static timing analysis basics by selva kumar

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