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Page 1: Static Timing Analysis Interview Questions · Static Timing Analysis is a technique of analysing timing paths in a digital logic by adding up delays along a timing path (both gate
Page 2: Static Timing Analysis Interview Questions · Static Timing Analysis is a technique of analysing timing paths in a digital logic by adding up delays along a timing path (both gate

Contents1)WhatisSTA?2)SetupandHoldTimeViolations.3)SignalIntegrity.4)Variation.5)Clocks.6)Metastability.7)Misc.

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Page 3: Static Timing Analysis Interview Questions · Static Timing Analysis is a technique of analysing timing paths in a digital logic by adding up delays along a timing path (both gate

WhatisSTA?QuestionW1):WhatisSTA(StaticTimingAnalysis)?AnswerW1):StaticTimingAnalysisisatechniqueofanalysingtimingpathsinadigitallogicbyaddingupdelaysalongatimingpath(bothgateandinterconnect)andcomparingitwithconstraints(clockperiod)tocheckwhetherthepathmeetstheconstraint.Incontrasttothedynamicspicesimulationofwholedesign,statictiminganalysisperformsaworstcaseanalysisusingverysimplemodelsofdeviceandwiredelays.Alookuptablemodelorasimpleconstantcurrentorvoltagesourcebasedmodelofdeviceisused.Elmoredelayorequivalentmodelisusedtoquicklyfigureoutwiredelays.StaticTimingAnalysisispopularbecauseitissimpletouseandonlyneedscommonlyavailableinputsliketechnologylibrary,netlist,constraints,andparasitics(RandC).StaticTimingAnalysisiscomprehensiveandprovidesaveryhighleveloftimingcoverage.Italsohonourstimingexceptiontoexcludethepathsthatareeithernottruepatharenotexercisedinanactualdesign.Agoodstatictimingtoolcorrelateswellwithactualsilicon.QuestionW2):Whatarealltheitemsthatarecheckedbystatictiminganalysis?AnswerW2):StaticTimingAnalysisisusedtocheckmainlythesetupandholdtimechecks.Butitalsochecksfortheassumptionsmadeduringtiminganalysistobeholdingtrue.Mainlyitchecksforcellstobewithinthelibrarycharacterizationrangeforinputslope,outputloadcapacitance.Italsochecksforintegrityofclocksignalandclockwaveformtoguaranteetheassumptionsmaderegardingtheclockwaveforms.Apartiallistofthingsitchecksishere:SetupTimingHoldtimingRemovalandRecoveryTimingonresetsClockgatingchecksMinmaxtransitiontimesMin/maxfanoutMaxcapacitanceMax/mintimingbetweentwopointsonasegmentoftimingpath.LatchTimeBorrowingClockpulsewidthrequirements

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Page 4: Static Timing Analysis Interview Questions · Static Timing Analysis is a technique of analysing timing paths in a digital logic by adding up delays along a timing path (both gate

SetupandHoldTimeViolations.QuestionS1):Describeatimingpath.AnswerS1):Forstandardcellbaseddesigns,followingfigureillustratesbasictimingpath.Timingpathtypicallystartsatoneofthesequential(storageelement)whichcouldbeeitheraflip-floporalatch.Thetimingpathstartsattheclockpinoftheflip-flop/latch.Activeclockedgeonthiselementtriggersthedataattheoutputofsuchelementtochange.Thisisthefirststagedelaywhichisalsocalledclock->dataout(Q)delay.Thendatagoesthroughstagesofcombinationaldelayandinterconnectwires.Eachofsuchstagehasitsowntimingdelaythataccumulatesalongthepath.Eventuallythedataarrivesatthesamplingstorageelement,whichisagainaflip-floporalatch.That’swheredatahastomeetsetupandholdchecksagainsttheclockofthereceivingflip-flop/latch.Alsonoticeforthetimingpathsinthesameclockdomain,generatingflip-flopclockandsamplingflip-flopclocksarederivedfromasinglesource,whichiscalledthepointofdivergence.Inreality,actualstartpointforasynchronousclockbasedcircuitsisthefirstinstancewhereclocksbranchofftogeneratingpathandsamplingpathasshownhereinthepicture,whichisalsocalledpointofdivergence.Tosimplifyanalysisweagreethatclockwillarriveatverymuchafixedtimeattheclockpinofallsequentialsinthedesign.Thissimplifiedtheanalysisofthetimingpath.fromonesequentialtoanothersequential.

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Page 5: Static Timing Analysis Interview Questions · Static Timing Analysis is a technique of analysing timing paths in a digital logic by adding up delays along a timing path (both gate

FigureS1.TimingpathfromoneFlipfloptoanotherFlipflop.QuestionS2):Whataredifferenttypesoftimingpaths?AnswerS2):Adigitallogiccanbebrokendownintoanumberoftimingpaths.Atimingpathcanbeanyofthefollowing:

FigureS2.Varioustypesoftimingpaths.

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Page 6: Static Timing Analysis Interview Questions · Static Timing Analysis is a technique of analysing timing paths in a digital logic by adding up delays along a timing path (both gate

i.Apathbetweentheclockpinofregister/latchtothed-pinof

anotherregister/latch.ii.Apathbetweenprimaryinputtothed-pinofaregisterorlatch.iii.Apathbetweenclock-pinofaregistertoaprimaryoutput.iv.Atimingpathfromprimaryinputtomacroinputpin.v.Atimingpathfrommacrooutputpintoprimaryoutputpin.vi.Atimingpathfromamacrooutputpintoanothermacroinput

pin(notshowninthefigure)vii.Apathpassingthroughinputpinandoutputpinofablock

throughcombinationallogicinsidetheblock.QuestionS3):Whatisalaunchedge?AnswerS3):Insynchronousdesign,certainactivityorcertainamountofcomputationisdonewithinaclockcycle.Memoryelementslikeflip-flopandlatchesareusedinsynchronousdesignstoholdtheinputvaluesstableduringtheclockcyclewhilethecomputationsarebeingperformed.Beginningoftheclockcycleinitiatetheactivityandbytheendoftheclockcycleactivityhastobecompletedandresultshavetobeready.Memoryelementsinadesigntransferdatafrominputtooutputoneitherrisingorthefallingedgeoftheclock.Thisedgeiscalledtheactiveedgeoftheclock.Duringtheclockcycle,datapropagatesfromoutputofonememoryelement,throughthecombinationallogictotheinputofsecondmemoryelement.Thedatahastomeetacertainarrivaltimerequirementattheinputofthesecondmemoryelement.

FigureS3.Launchedgeandcaptureedge.

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Page 7: Static Timing Analysis Interview Questions · Static Timing Analysis is a technique of analysing timing paths in a digital logic by adding up delays along a timing path (both gate

Asshownintheabovefigure,theactiveedgeoftheclock(showninred)atthefirstmemoryelementmakesnewdataavailableattheoutputofthememoryelementandstartsdatatopropagatethroughthelogic.Input‘in’hasrisentoonebeforethefirstactive(rising)edgeoftheclock,butthisvalueof‘in’istransferredtoQ1pinonlywhenclockrises.Thisactiveedgeoftheclockiscalledthelaunchedge,becauseitlaunchesthedataattheoutputoffirstmemoryelement,whicheventuallyhastobecapturedbynextmemoryelementalongthedatapropagationpath.QuestionS4):Whatiscaptureedge?AnswerS4):Aswediscussedinpreviousquestion,thewaysynchronouscircuitswork,certainamountofcomputationhastobedonewithinaclockcycle.Atthelaunchedgeoftheclock,memoryelementstransferfreshsetofdataattheoutputpinofthelaunchingmemoryelements.Thisnewdata,ripplesthroughthecombinationallogicthatcarriesoutthestipulatedcomputation.Bytheendoftheclockcycle,newcomputeddatahastobeavailableatthenextsetofmemoryelements.Becausenextactiveclockedge,whichsignifiestheendofoneclockcycle,capturesthecomputedresultsattheD2pinofthememoryelementandtransferstheresultstotheQ2pinforthesubsequentclockcycle.Thisnextactiveedgeoftheclock,showinblueatfigure1,iscalledthecaptureedge,asitreallyiscapturingtheresultsattheendoftheclockcycle.Therearesomecaveatstobeawareof.ThedataD2hastoarrivecertaintimebeforethecaptureedgeofclock,inordertobecapturedproperly.Thisiscalledsetuptimerequirement,whichwewilldiscusslater.Althoughitissaidthatcomputationhastobedonewithinoneclockcycle,itisnotalwaysthecase.Ingeneralitistruethatcomputationhastobedonewithinoneclockcycle,butmanytimes,computationcantakemorethanonecycle.Whenthishappenswecallitamulticyclepath.QuestionS5):Whatissetuptime?AnswerS5):Foranysequentialelemente.g.latchorflip-flop,inputdataneedstobestablewhenclock-captureedgeisactive.Actuallydataneedstobestableforacertaintimebeforeclock-captureedgeactivates,becauseifdataischangingneartheclock-captureedge,sequentialelement(latchorflip-flop)cangetintoametastablestateanditcouldtakeunpredictableamountoftimetoresolvethemetastabilityandcouldsettleatatstatewhichisdifferentfromtheinputvalue,thuscancaptureunintendedvalueattheoutput.Thetimerequirementforinputdatatobestablebeforetheclockcaptureedgeactivatesiscalledthesetuptimeofthatsequentialelement.QuestionS6)Whatisholdtime?

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AnswerS6)Aswesawinpreviousquestionaboutsetuptime,foranysequentialelemente.g.latchorflip-flop,dataneedstobeheldstablewhenclock-captureedgeisactive.Actuallydataneedstobeheldstableforacertaintimeafterclock-captureedgedeactivates,becauseifdataischangingneartheclock-captureedge,sequentialelementcangetintoametastablestateandcancapturewrongvalueattheoutput.Thistimerequirementthatdataneedstobeheldstableforaftertheclockcapture-edgedeactivatesiscalledholdtimerequirementforthatsequential.QuestionS7):Whatdoesthesetuptimeofaflopdependupon?AnswerS7):Setuptimeofaflip-flopdependsupontheInputdataslope,ClockslopeandOutputload.QuestionS8):Whatdoestheholdtimeofaflip-flopdependupon?AnswerS8):Holdtimeofaflip-flopdependsupontheInputdataslope,ClockslopeandOutputload.QuestionS9)Explainsignaltimingpropagationfromoneflip-floptoanotherflip-flopthroughcombinationaldelay.AnswerS9)Followingisasimplestructurewhereoutputofaflopgoesthroughsomestagesofcombinationallogic,representedbypinkbubbleandiseventuallysamplesbyreceivingflop.Receivingflop,whichsamplestheFF2_indata,posestimingrequirementsontheinputdatasignal.ThelogicbetweenFF1_outtoFF2_inshouldbesuchthatsignaltransitionscouldpropagatethroughthislogicfastenoughtobecapturedbythereceivingflop.Forafloptocorrectlycaptureinputdata,theinputdatatoflophastoarriveandbecomestableforsomeperiodoftimebeforethecaptureclockedgeattheflop.Thisrequirementiscalledthesetuptimeoftheflop.Usuallyyou'llrunintosetuptimeissueswhenthereistoomuchlogicinbetweentwofloporthecombinationaldelayistoosmall.Hencethisissometimescalledmaxdelayorslowdelaytimingissueandtheconstraintsiscalledmaxdelayconstraint.InfigurethereismaxdelayconstraintonFF2_ininputatreceivingflop.Nowyoucanrealizethatmaxdelayorslowdelayconstraintisfrequencydependent.Ifyouarefailingsetuptoaflopandifyouslowdowntheclockfrequency,yourclockcycletimeincreases,henceyou'velargertimeforyourslowsignaltransitionstopropagatethroughandyou'llnowmeetsetuprequirements.Typicallyyourdigitalcircuitisrunatcertainfrequencywhichsetsyourmaxdelay

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constraints.Amountoftimethesignalfallsshorttomeetthesetuptimeiscalledsetupormax,slackormargin.

FigureS9.Signaltimingpropagationfromflip-floptoflip-flopQuestionS10)Explainsetupfailuretoaflip-flop.AnswerS10)Followingfiguredescribesvisuallyasetupfailure.Asyoucanseethatfirstflopreleasesthedataattheactiveedgeofclock,whichhappenstobetherisingedgeoftheclock.FF1_outfallssometimeaftertheclk1rises.Thedelayfromtheclockrisingtothedatachangingatoutputpiniscommonlyreferredtoasclocktooutdelay.ThereisfinitedelayfromFF1_outtoFF2_inthroughsomecombinationallogicforthesignaltotravel.AfterthisdelaysignalarrivesatsecondflopandFF2_infalls.BecauseoflargedelayfromFF1_outtoFF2_in,FF2_infallsafterthesetuprequirementofsecondflop,indicatedbytheorange/redverticaldottedline.ThismeansinputsignaltosecondflopFF2_in,isnotheldstableforsetuptimerequirementoftheflopandhencethisflopgoesmetastableanddoesn'tcorrectlycapturethisdataatit'soutput.

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Asyoucanseeonewould'veexpected'Out'nodetogolow,butitdoesn'tbecauseofsetuptimeormaxdelayfailureattheinputofthesecondflop.Setuptimerequirementdictatesthatinputsignalbesteadyduringthesetupwindow(whichisacertaintimebeforetheclockcaptureedge).Asmentionedearlierifwereducefrequency,ourcycletimeincreasesandeventuallyFF2_inwillbeabletomakeitintimeandtherewillnotbeasetupfailure.Alsonoticethataclockskewisobservedatthesecondflop.Theclocktosecondflopclk2isnotalignedwithclk1anymoreanditarrivesearlier,whichexacerbatesthesetupfailure.Thisisarealworldsituationwhereclocktoallreceiverswillnotarrivalatsametimeanddesignerwillhavetoaccountfortheclockskew.We'lltalkseparatelyaboutclockskewindetails

FigureS10.Setup/Maxdelayfailuretoaflip-flop.QuestionS11)Explainholdfailuretoaflip-flop.AnswerS11)Likesetup,thereisa'Hold'requirementforeachsequentialelement(floporalatch).Thatrequirementdictatesthataftertheassertionoftheactive/capturingedgeofthesequentialelementinputdataneedstobestableforacertaintime/window.Ifinputdatachangeswithinthisholdrequirementtime/window,outputofthe

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sequentialelementcouldgometastableoroutputcouldcaptureunintentionalinputdata.Thereforeitisverycrucialthatinputdatabeheldtillholdrequirementtimeismetforthesequentialinquestion.Inourfigurebelow,dataatinputpin'In'ofthefirstflopismeetingsetupandiscorrectlycapturedbyfirstflop.Outputoffirstflop'FF1_out'happenstobeinvertedversionofinput'In'.Asyoucanseeoncetheactiveedgeoftheclockforthefirstflophappens,whichisrisingedgehere,afteracertainclocktooutdelayoutputFF1_outfalls.NowforsakeofourunderstandingassumethatcombinationaldelayfromFF1_outtoFF2_inisveryverysmallandsignalgoesblazingfastfromFF1_outtoFF2_inasshowninthefigurebelow.Inreallifethiscouldhappenbecauseofseveralreasons,itcouldhappenbydesign(imaginenodevicebetweenfirstandsecondflopandjustsmallwire,evenbetterthinkofbothflopsabuttingeach-other),itcouldbebecauseofdevicevariationandyoucouldendupwithveryveryfastdevice/devicesalongthesignalpath,therecouldbecapacitancecouplinghappeningwithadjacentwires,favoringthetransitionsalongtheFF1_outtoFF2_in,nodeadjacenttoFF2_inmightbetransitioninghightolow(fall)withasharpslewrateorslopewhichcouplesfavorablywithFF2_ingoingdownandspeedsupFF2_infalldelay.Inshortinrealitythereareseveralreasonsfordevicedelaytospeedupalongthesignalpropagationpath.NowwhatendsuphappeningbecauseoffastdataisthatFF2_intransitionswithintheholdtimerequirementwindowofflopclockedbyclk2andessentiallyviolatestheholdrequirementforclk2flop.ThiscausesthethefallingtransitionofFF2_intobecapturedinfirstclk2cyclewhereasdesignintentionwastocapturefallingtransitionofFF2_ininsecondcycleofclk2.Inanormalsynchronousdesignwhereyouhaveseriesofflip-flopsclockedbyagridclock(clockshowninfigurebelow)intentionisthatinfirstclockcycleforclk1&clk2,FF1_outtransitionsandtherewouldbeenoughdelayfromFF1_outtoFF2_insuchthatonewouldideallyhavemetholdrequirementforthefirstclockcycleofclk2atsecondflopandFF2_inwouldmeetsetupbeforethesecondclockcycleofclk2andwhensecondclockcyclestarts,attheactiveedgeofclk2originaltransitionofFF1_outispropagatedtoOut.Nowifyounoticethereisskewbetweenclk1andclk2,theskewismakingclk2edgecomelaterthantheclk1edge(ideallyweexpectclk1&clk2tobealignedperfectly,that'sideally!!).Inourexamplethisisexacerbatingtheholdissue,ifbothclockswereperfectlyaligned,FF2_infallcouldhavehappenedlaterandwouldhavemetholdrequirementfortheclk2flopandwewouldn'thavecapturedwrongdata!!

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FigureS11.Hold/Mindelayrequirementforaflop.QuestionS12):Ifholdviolationexistsindesign,isitOKtosignoffdesign?Ifnot,why?AnswerS12):Noyoucannotsignoffthedesignifyouhaveholdviolations.Becauseholdviolationsarefunctionalfailures.Setupviolationsarefrequencydependent.Youcanreducefrequencyandpreventsetupfailures.Holdviolationsstemmingfromthesameclockedgerace,arefrequencyindependentandarefunctionalfailuresbecauseyoucanendupcapturingunintendeddata,thusputtingyourstatemachineinanunknownstate.QuestionS13)Whataresetupandholdchecksforclockgatingandwhyaretheyneeded?AnswerS13):Thepurposeofclockgatingistoblocktheclockpulsesandpreventclocktoggling.AnenablesignaleithermasksorunmaskstheclockpulseswiththehelpofanANDgate.Asitisclocksignalwhichisinconsiderationhere,carehastobetakensuchthatwedonotchangetheshapeoftheclockpulsethatwearepassingthroughandwedon’tintroduceanyglitchesintheclockpulsethatwearepassingthrough.

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Page 13: Static Timing Analysis Interview Questions · Static Timing Analysis is a technique of analysing timing paths in a digital logic by adding up delays along a timing path (both gate

FigureS13.Clockgatingsetupandholdcheck

Asyoucanseeinthefiguretheenablesignalhastosetupinadvanceoftherisingedgeoftheclockinsuchawaythatitdoesn’tchoptherisingedgeoftheclock.Thisiscalledtheclockgatingsetuporclockgatingdefaultmaxcheck.Similarlythetuningofforgoingawayedgeoftheenable(EN)signalhastohappenwellpasttheturningofforgoingawayedgeoftheclock,againtomakesureitdoesn’tgetchoppedoff.Thisiscalledtheclockgatingholdorclockgatingdefaultmincheck.QuestionS14):Whatdeterminesthemaxfrequencyadigitaldesignwillworkon.Whyholdtimeisnotincludedinthecalculationfortheabove?AnswerS14):Worstmaxmarginwilldecidethemaxfrequencyadesignwillworkon.Assetupfailureisfrequencydependent.Holdfailureisnotfrequencydependenthenceitisnotfactoredintothefrequencycalculation.QuestionS15).Onechipwhichcamebackafterbeingmanufacturedfailssetuptestandanotheronefailsaholdtest.Whichonemaystillbeusedhowandwhy?AnswerS15):Setupfailureisfrequencydependent.Ifcertainpathfailssetuprequirement,youcanreducefrequencyandeventuallysetupwillpass.Thisisbecausewhenyoureducefrequencyyouprovidemoretimefortheflop/latchinputdatatomeetsetup.Hencewecallsetupfailureafrequencydependentfailure.Whileholdfailureisnotfrequencydependent.Holdfailureisfunctionalfailure.Followingfigureshowsfrequencydependenceofsetupfailure.

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FigureS15a.Frequencydependenceofsetupfailure.

Youcanseeintheabovefigurethatwithfasterclock,Dinputtothecaptureedgefailssetup.Theredverticallineshowsthesetupwindowofthecaptureflop.TheDinputshouldhavearrivedbeforethesetupwindowshownbythereddottedverticallines.AsDfailssetuptheoutputnodeOUTgoesmetastableandtakessometimebeforeitsettlesdown.Thismetastabilitycouldcauseproblemsdownstreaminthecircuit.Nowiftheclockissloweddown,youcanseethatDwillmeetthesetupforthecaptureflop.Althoughitisnotshowninthefigurebutforsimplicityreasons,butthelaunchclockisalsoslownow,althoughthelaunchclockcanbeassumedtothesameasfastclock.Youcanseethatsetupwindowdoesn’tchangewithclockasitisthepropertyofthecaptureflopanddoesn’tdependuponclock.Thatiswhywecanmeetsetupwithslowclock.Followingfigureillustrateswhyslowingdownfrequencydoesn’tresolveholdfailures.

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FigureS15b.Frequencyindependentholdfailure.

Asyoucanseeinthefigure,theholdfailureisadatarace.Because‘IN’goeslow,theQoutputoflaunchflop(LF)goeslowandthisissupposedtobecapturedbycaptureflop(CF)andoutputofcaptureissupposedtogolowafteraclockcycle.Butbecausethereisno(verysmall)delayfromQtoD,Dgoeslowwithintheholdwindowofthecaptureflop.InotherwordsDgoeslowandviolatestheholdtimeforthecaptureflop.InsuchcaseseithercaptureflopoutputcangometastableorthenewvalueofDcouldbecapturedrightawayattheoutput‘OUT’ofthecaptureflop.Inthefigureaboveitisshownthat‘OUT’alsogoeslowrightaway.Thedesignintentionwasfor‘OUT’togolowafteraclockcyclebutbecauseoffastdata,dataatinput‘D’snuckintothecurrentclockcycleandappearedatthe‘OUT’,causing‘OUT’tohavewrongvalueforthisclockcycle.Thismeansunknownstateforthedownstreamlogic,becauseofthewrong‘OUT’value.Asyoucanseeinthebottomportionofthewaveforms,eveniftheslowerclockisused,theproblempersists.BecausethisisreallyadataraceissuebecauseoffastdatadelayfromQtoD,whichisstillthereevenifwechangetheclockfrequencyasitisindependentoftheclockfrequency.Hencewecanseethatholdfailurescouldbefrequencyindependent.

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Page 16: Static Timing Analysis Interview Questions · Static Timing Analysis is a technique of analysing timing paths in a digital logic by adding up delays along a timing path (both gate

QuestionS16):WhatisMaxTimingEquation?AnswerS16):Bestwaytounderstandmaxtimingequationistolookatthewaveforms.Pleasegothroughfollowingfigurecarefully.

FigureS16Maxtimingequation.

Abovementionedfigurevisuallydescribeswhatconstitutesamaxorsetuptimingpathalongwithallthecomponentsthatareinvolvedincomingupwiththemaxtimingslack.SourceclockintheabovefigureistheoriginalsourceoftheclockwhichcouldbePLLoutputorwhereverthestartingpointofthesourceclockisdefined.ForclockswhicharenotthedirectoutputofPLLs,orcomingfromprimarychipinput,theyarereferredtoasderivedclock,virtualclockorgeneratedclock.Thisisourmasterreferenceclockandmostofthetimethisisthestartpointorthe0pspoint.

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Page 17: Static Timing Analysis Interview Questions · Static Timing Analysis is a technique of analysing timing paths in a digital logic by adding up delays along a timing path (both gate

Westartwiththesourceclockat0psintime.Fromsourceclockthereisclocknetworkdelayfromthesourceclocktothelaunchflopthatweaddup.Onethelaunchclockactiveedgearrivesatthelaunchflop,itreleasesdataafterclocktoQdelay,weaddthisup.FromQpinoftheflopdatatravelsthroughcellsandwirestoarrivesattheDinputpinofthecaptureflop.Thisiscalledthepathdelayasthisisthepathfromlaunchfloptocaptureflop,weaddthisup.Thesumsofarrepresentsthedataarrivalatthecaptureflopinputpin.Thiseventhastohappenbeforethesetuprequirement,orinotherwords,thissumhastobelessthanorequaltothesetuporcapturerequirements,showninfigurewithverticaldashedredline.RememberthatinSTAweworstcasetheanalysis,hencewewilltaketheslowestdelayuptothecaptureflopinput.Letslookatthecapturerequirement.Weknowthatcapturehappensonecyclelaterwithrespecttothelaunchclock,hencewestartwithsourceclockcaptureedgewhichisonecyclelaterwithrespecttolaunchedgeattimeequivalenttooneclockcycle.Similartolaunchthereisclocknetworkdelayfromsourceclocktothecaptureflop,weaddthisupasthisinrealityispushingoutthecaptureclock.Toworstcase,weusethefastestcaptureclockdelay,becausefasterthecaptureclocklesstimewewillhavetomeetsetup.Nowoncethecaptureclockarrivesatthecaptureflop,theinputdataattheflophastomeetthesetuprequirement.Thisisarequirementwherebytheinputdatatothecaptureflophastoarrivethatmuchearlier,hencewesubtractsetuptimefromourcapturerequirementcalculation.Ontopofthisweneedtoaccountforclockuncertaintyasbecauseofvariation,IRdropandotherreasons,actualclockarrivaltimescouldvaryandweneedtobuildadditionalmarginforthisuncertainty.Thisisapenaltyorrequirementandassuchforcesdatatoarriveevenearlier,whichmeanswesubtractthisvaluefromthecapturerequirement.Sourcelaunchclockedge(0ps)+Launchclocknetworkslowestdelay+ClocktoQslowestdelay+SlowestPathdelay(cell+interconnect)=<Sourcecaptureclockedge(Oneclockcycle)+Captureclocknetworkfastestdelay-Setuptime-Maxclockuncertainty.Also.Maxmargin/slack=[Sourcecaptureclockedge(Oneclockcycle)+Captureclocknetworkfastestdelay-Setuptime-Maxclockuncertainty]-[Sourcelaunchclockedge(0ps)+Launchclocknetworkslowestdelay+ClocktoQslowestdelay+Slowestpathdelay(cell+interconnect)]QuestionS17):Whatismintimingequation?AnswerS17):Letsgothroughthefollowingwaveformstobetterunderstandthemintimingequation.

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FigureS17.Mintimingequation.

Asweknowthatmintimingcheckorholdtimecheckisessentiallyensuringthatthedatalaunchedonthelaunchedgeatthelaunchflopisnotinadvertentlycapturedbythecaptureflopatthelaunchedge,becauselauncheddataissupposedtobecapturedonecyclelaterandnotinthecurrentclockitself.Justlikemaxtimingsourceclockisthemasterreferenceandsourceclockstart(rising)edgeisthestartpoint.Fromtherejustclocktravelstothelaunchflopthroughlaunchclocknetwork,soweadduplaunchclocknetworkdelay.Oncelaunchclockedgearrivesatthelaunchflop,itreleasesthedataattheoutputoflaunchflopafterclocktoQdelay,weaddupthisdelay.Nextweadduppathdelay.Nowthedatahasarrivedatcaptureflop.Thisdatahastohavearrivedaftertheholdormintimerequirement.Nextwecalculateholdtimerequirements.Forholdrequirementoncapturesidewestartwiththesameclockedgethatwestartedonatthelaunchside.Oneofthealternativewaytolookatthisistolookatsetupcaptureclockedgeforthesamelaunchandcapturefloptimingpathandpickclockedgewhichisoneclockcycleearlier.Actuallythatishowmanyofthetimingtools

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likePrimeTimefigureoutwhichedgetocheckholdtimerequirementagainst.Thetoolfirstfindoutthesetuprequirementcaptureclockedge,whichisoneclockcycleafterthelaunchedge,thenittracesbackoneclockcycle,whichisthesameclockedgeasthelaunchedge.Fromthisclockedgeweaddtheholdtimerequirement,asinputdataarrivingatthecaptureflopinputpin,hastoholdpasttheholdtimerequirementforthatflop.Weaddclockuncertaintyasclockedgeatthecaptureflopcouldarrivethatmuchlater.Thelauncheddatahastohavearrivedlaterthanthisholdtimerequirementatcaptureflop.Againtomaketheanalysisworstcase,weusethefastestdelayuptocaptureflopinputandweuseslowestdelayforthecaptureclocknetwork.Sourceclocklaunchclockedge(0ps)+Launchclocknetworkfastestdelay+ClocktoQfastestdelay+Fastestpathdelay(cell+interconnectdelays)>=Sourceclocklaunchedge(Sourceclockcaptureedgecorrespondingtothesetuppath-1clockperiod,sameas0ps)+Captureclocknetworkslowestdelay+Capturefloplibraryholdtime+HoldtimeclockuncertaintyAndMinmargin=[Sourceclocklaunchclockedge(0ps)+Launchclocknetworkfastestdelay+ClocktoQfastestdelay+Fastestpathdelay(cell+interconnectdelays)]-[Sourceclocklaunchedge(Sourceclockcaptureedgecorrespondingtothesetuppath-1clockperiod,sameas0ps)+Captureclocknetworkslowestdelay+Capturefloplibraryholdtime+Holdtimeclockuncertainty]QuestionS18):Istheclockperiodenoughforthegivencircuit?AnswerS18):

FigureS18:Clockfrequencyquestion.

Weknowthemaxtimingequation.

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Maxmargin=[Clockcycle+captureclocknetworkfastestdelay-setuptime-maxclockuncertainty]-[0ps+launchclocknetworkslowestdelay+clktoqslowestdelay+slowestpathdelay]Maxmargin=[0.5ns(2Ghz)+1.1ns-0.05ns-0.1ns]-[1ns+0.05ns+0.5ns]Maxmargin=[1.45ns]-[1.55ns]=-0.1nsMaxmarginisnegativemeansclockperiodisnotenoughandcaptureflopsetuptimecheckisviolated.QuestionS19):Whatisresetrecoverytime?AnswerS19):Foraflipflopwithasynchronousresetpin,onlytheassertingedge(activeedge)ofresetisasynchronous.Whichmeansifresetpinisactivelow(resetbar),onlyresetsignalgoingdown(falling)canhappenasynchronouslywithouttheknowledgeoftheclock.Butoncetheresethasgoneactive,ithastode-assertatsomepointintimeandhastogettheflipflopoutoftheresetstate.Thisresetde-assertioncannothappenindependentlyoftheclocks.Thewaysuchflipflopsaredesigned,theresetdeassertionhastohappencertaintimebeforetheactiveedgeoftheclockfortheflipflop.Thisisverysimilartosetupcheckfordata,andthisrequirementofresetde-assertionbeforetheactiveedgeoftheclockiscalledtherecoverytime.

FigureS19.Resetrecoverytime

QuestionS20):Whatisrestremovaltime.AnswerS20):Removaltimeisthecounterpartofrecoverytime.Itisexactlyholdtimeequivalentofrecoverytime.Justlikeinrecoverytime,resetdeassertionhastohappencertaintimebeforetheactiveedgeoftheclock,removaltimerequirementiswheretheresetdeassertionhastoholdpasttheactiveedgeoftheclock.Resetdeassertioncannothappenrightaroundtheclockedge,ithastohappencertaintimeaftertheactiveedgeoftheclock.

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FigureS20.ResetremovaltimeQuestionS21):Givenasetupcheckfromanlaunchelementtocaptureelement,howdoestiminganalysistooldecidetoperformtheholdcheck?AnswerS21):Thisquestionmightseemvagueatfirst,butthekeyistounderstandfollowingbehaviorofthetiminganalysistoo.ThisismainlyapplicabletoPrimeTimetool,otherSTAtoolsmaynotfollowthesamemethod.Onekeythingtorememberisthat,holdcheckisperformedalwayswithreferencetosetupcheck.WHichmeanstimingtoolsfirstfindsoutwhichclockedgestoperformsetupcheck,andthenitinfersholdchecksbasedonthesetupcheck.Forfollowinganalysisweassumebothlaunchandcaptureflopsarerisingedgetriggered.Normallyforasetupcheck,thecaptureclockedgeischosentobetheactiveclockedgewhichcomesoneclockcycleafterthelaunchedge.

FigureS21.Hold&Setupclockedges.

Weknowthatonceanactiveedgeofclockispickedaslaunchclockedge,thesetupcheckisdonetothecaptureedgeisoneclockcyclelater.Oncesetupcheckedgeshavebeenidentified,thetimingtoolslooksattwoscenariostofindtheclockedgestobepickedupfortheactualholdcheck.Itfirstchecks

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whetherthedatalaunchedbythelaunchclockedgecorrespondingtothesetupcheck,isheldenoughtonotinadvertentlygetcapturedbythesameedgeatthecaptureflop.Thisisshowninfigurebygreendottedarrownumber1.Thenitlooksforsecondscenario.Thistimeitstartsatthecaptureclockedgecorrespondingtothesetupcheckanditensuresthatthedatareleasedattheoutputoflaunchflopbythisclockedgeisnotinadvertentlycapturedbythecaptureflopatthesameclockedge.Thisisshowninfigurewithgreendottedarrownumber2.Havinglookedatbothscenarios,timingtoolpicksthemorestringentholdcheckanditperformsthatholdtimecheck.Intheabovefigurecase,wecanseethatbothscenarios,number1andnumber2areidentical,sotimingtoolwouldjustpickeither.Oneclarificationaboutholdchecks.Theholdcheckissupposedtobemorestringentwhencaptureedgeisveryclosetothelaunchedge,becausethatiswhenitismorelikelythatdatalaunchedbylaunchclockcouldbeinadvertentlygetcapturedbynearbycaptureedge,whichisinrealitymeantforthesubsequentcaptureedge.Asyousee,morethelaunchedgehappenslaterintimecomparedtocaptureedge,lesstheriskofholdtimeviolation.Basicallymorethelaunchedgelaunchespastthecaptureedge,morereadilyweknowthedatalaunchedbylaunchedgewillbeheldpastthecaptureedge.QuestionS22):Whattypeofsetupandholdcheckswillbeperformedwhenlaunchandcaptureclockarenotofthesamefrequency?AnswerS22):Let’sconsiderthreecasescenarioshere.Scenario1)Launchclockisamultipleofcaptureclockandistwiceasfastascaptureclock.Scenario2)Captureclockisamultipleoflaunchclockandistwiceasfastaslaunchclock.Scenario3)Launchandcaptureclocksarenotmultipleofeachother.Onehastohammerthisdeepintotheirmind.Statictiminganalysisisaworstcaseanalysis.Wheneveracertaincheckisperformed,toolwillfindtheworstpossiblecasetodotheanalysisorperformthecheck.Takesetupcheck.STAtoolwillalwaysperformworstcasesetupcheck.Whichmeans,onceanactiveclockedgelaunchesdataatthelaunchflop,toolwillfindtheearliestpossiblenextactiveedgewhenthedatacanbecapturedatthecaptureflop.Inotherwords,itwilltakelaunchclockandcaptureclockandfindoutthesmallestdistancebetweenactivelaunchedgeandactivecaptureedge,whichisgreaterthanzero(itwon’tpickthesameedge,asitisobviousthatitisnotthecorrectedge)anditwillusethatforsetupcheck.Andweknowfrompreviousquestionthatitderivesholdcheckwithreferencetosetupcheck.Againinholdcheck,itlooksattwoscenariosandpickstheworstone.

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FigureS22SetupandHoldclockedges.

Wewillassumerisingedgelaunchandcaptureflopshere.Letslookatscenario1),herethelaunchclockisfasterthanthecaptureclock.Asstatedearlier,toolwillpicktheshortestdistancebetweentwoactiveedgesinlaunchandcaptureclockforthesetuptimingcheck.Theclockedgesandactualsetupcheckisshownwithdottedredline.Setupcheckisrelativelystraightforward.Oncehavingfoundsetupcheck,itwilllookatthetwotypicalpossibilitiesforfindingholdcheck.Twoholdcheckpossibilitiesareshownwithgreendottedline.Firstoneisfromthelaunchofthesetupchecktotheoneclockcycleearlierthanthesetupcaptureedgeofthecaptureclock.Thisisholdchecknumber1.Secondpossibilityisthecheckfromactiveedgeofthelaunchclockwhichisonecyclelaterthanthesetupchecklaunchedgetothesetupcaptureedgeofthecaptureclockagainshowningreendottedlineasholdchecknumber2.Asyoucanseeinthefigureholdcheck2ismorestringent,hencetoolwillpickscenario2forholdcheck.Inscenario2)wherelaunchclockisslowerthanthecaptureclock.Analysisissimilartoearlierscenarioandwecanseethatholdcheck1ismorestringent,hencetoolpicksholdcheck1.Inscenario3)hold2seemstobemorestringentandwillbepickedastheholdcheck.Unlessspecificoverridesorexceptionstoinstructionsaregiventotimingtool,it

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doesn’tcareaboutthenatureandfrequencyofthelaunchandcaptureclocks,itwillsticktotheworst-casebehaviortoperformthetimingchecks.Manytimes,thetoolmightperformwrongchecks,asitmightviolationdesignintentwhileperformingtheworstcasecheck.Wewilllookatsuchcaseinsubsequentquestions.QuestionS23):AreclockdomaincrossingissuesdetectedbySTAtool?AnswerS23):NoclockDomaincrossingissuesarenotdetectedbyStaticTimingAnalysistool.Asmentionedearlier,toolsimplytriestofindouttheworstcasesetupandholdchecksbetweenlaunchandcaptureedge.Designerhastodesignforclockdomaincrossings.QuestionS24):Howdoeslockuplatchhelpwithavoidingholdviolations.AnswerS24):Ifyouunderstandholdtimecheckverywell,orifyouhavebeenanalyzingthewaveformsforholdtimecheck,youwillrealizethatholdtimeissuesstarthappeningassoonaslaunchandcaptureclockedgealignwitheachotherorareveryclosetoeachother.Weknowthatmorespreadapartlaunchandcaptureedgeareinsuchawaythatlaunchedgeislaterthanthecaptureedge,lessofaholdtimeconcernthereis.Weknowthatwhenlaunchandcaptureclockarefromthesamesourceandhavesamewaveform,thegreatestdistancebetweenanedgeinlaunchclockandanedgeincaptureclockcannotbegreaterthanclockphase.Becauseiftrytodothatyouwillapproachoneoftheedgecloserontheotherside.Ifthefallingedgeofclockisthelaunchedgeandrisingedgeofclockiscaptureedge,weknowthatlaunchandcaptureedgewouldbeaphaseapartandaslongaslaunchedgehappensaftercaptureedge,wewouldhaveaphaseworthofmarginforholdcheck.Thisistrueforthecasewherefallingclockedgeiscaptureedgeandrisingedgeislaunchedge.Thekeyisthattheyareaclockphaseapartandlaunchhappenslaterthancapture.Thisiswhatexactlyalockuplatchachieves.Itchangesthelaunchedgefromrisingtofallingedgeandcaptureedgeremainsrising.Sowegetlaunchandcaptureedgestobefarthestapart(clockphase)givingusbestpossibleholdtimeprotection.Alsolaunchhappenslaterthancapture,whichiswhatwewant.Letstakealookatthefigurebelowtobetterunderstandthis.

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FigureS24a.Lockuplatch.Hereweareassuminglaunchandcaptureflopstoberisingedgetriggered.Asshowninfigurebeforelockuplatch,it’sasimplesetupandholdcheck.Theissueisthistypeofholdcheck(alsocalledraceaslaunchandcaptureedgesarethesame,itislikeadatarace),itcouldbeverydifficultandexpensivetofixthistypeofholdviolations,iflaunchandcapturedclockcommonpointsarefarapart,therecouldbequitealargeclockuncertainty.Thisisverytypicalforscanortestclockswherelastflopinonescanchainisinaspecificclockdomainandfirstcellofnextscanchainisinadifferentclockdomain.Therecouldbelargeholdviolationsforsuchpaths.Lowphaselatch,launchesdataatthefallingedgeoftheclockandremainstransparentduringlowphase.Essentiallybyintroducingthelockuplatch,wemovedlaunchedgefromrisingtofalling,andnowourlaunchandcaptureedgesareaclockphaseapart,wehaveaclockphaseworthofmargin(slack)tomeettheholdtimerequirement.

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FigureS24bTestclockholdviolation.

Asshowninfiguretherecanbealargeuncertaintybetweentestclock_aandtestclock_b.Ifyourecallfromtheholdmarginequation,largertheclockuncertaintylargerthenegativeslackthatwillhavetobefixed.Insuchsituationsthelockuplatchisintroducedbetweenthetwochainstoaddresstheholdviolation.

FigureS24c.Interscanchainlockuplatch

Onehastorealizethatlockuplatchdoesn’tcomecompletelyfree.Becauseitchangesthelaunchedgefromrisingtofalling,wearemodifyingoursetupormaxtimingpathfromtheoriginallaunchfloptocaptureflopfromafullclockcycletohalfclockcycle(clockphase).Normallyyouwouldthinkofaddinglockuplatchonlyifyouhadholdissuestobeginwithwhichmeans,therewasnotasetupproblemtobeginwith.Becauseifyouhadholdproblemsthatmeanstherewasn’tmuchpathdelayfromthelaunchfloptocaptureflop.QuestionS25):Doeslocationoflockuplatchmatter?Whatifinpreviousexampleyoumovedlockuplatchfromnearlaunchfloptocaptureflop?AnswerS25):Thelocationoflockuplatchverymuchmatters.Whenyouintroducelockuplatchin

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betweentwoflops,youareessentiallybreakingtimingpathintotwosegments.Onepathfromtheoriginallaunchfloptothelockuplatchandothertimingpathfromthelockuplatchtotheoriginalcaptureflop.Thereisareasonwhywedidn’tbotheraboutthetimingpathfromthelaunchfloptothelockuplatch.Originallaunchfloplaunchesdataatrisingedgeoftheclockandlowphaselockuplatchcapturesdataattherisingedgeoftheclockaswell.Thiscouldbeaholdtimeissues,butitreallyisnotbecauseweclockedthelockuplatchwiththesameclockthatwasclockingthelaunchflop.InFactitisessentialwedothisandplacelowphaselockuplatchrightnexttothelaunchflop.Doingsowillensurethatthereisnoholdtimeissuefromthelaunchfloptothelockuplatch,asessentiallyitisthesameclocknetthatisdrivingboth,hencetherecannotbeadataracefromthelaunchfloptothelockuplatch.

FigureS25a.Timingpathsplitafterlockuplatch

Asshowninthisfigure,thereisaholdcheckthatissupposedtohappenfromthelaunchfloptothelockuplatch,butitreallyisnotanissuebecauseofthesameclockedgefirstlaunchingdataandthencapturingthedata.Manytimingtoolsunderstandthisconfigurationandmightnotreportthisholdcheck,andeveniftimingtoolreportsthisholdcheck,itshouldpass.

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FigureS25b.Wronglockuplatchlocation.Youcanseethatoncethelockuplatchismovedclosetocaptureflop,theholdviolationfromthelaunchfloptothelockuplatchbecomestherealissueasbothclocksarenowdifferentandcouldcomefromdifferentdomainaswesawintestclockexampleandlockuplatchisreallynotservinganypurposetofixtheholdviolation.Henceitisvitaltoplacethelockuplatchatcorrectlocationwithcorrectclock.QuestionS26):Whatareyouroptionstofixatimingpath?AnswerS26):Thereareseveraldifferentpossibilitiesforfixingatimingpath.-Obviouslogicoptimization.Doyouhaveredundantchainofbuffersorinverters?Canyoudrivewithfewerbufferorinverters?IfthereisaNANDfollowedbylatch,doyouhavealibraryNAND-latchavailabletreplace?-Betterplacement.Canyoumovelogicaroundtofixthepath?Issubgroupoflogicalongthepath,justtoofarawayfromlaunchandcaptureflop?Inthatcasecanyoujustmovethatlogicclosertothelaunchandcaptureflop?Canyoumovelaunchflopclosetothecaptureflopalongwiththelogicinbetween?Orviceversa?-Morepipelining.

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Canyouintroducenewfloponthefailingpath?Doesarchitecturalperformanceallowforthat?Basicallybyintroducingextraflop,youareintroducingoneextraclockcyclealongthetimingpathandhurtingoverallthroughputofthelogic.-Movelogictopreviouspipestage?Canyoumovesomelogicfromcurrentfailingpathtobeforethelaunchflop?Youhavetomakesureyoudon’tbreakfunctionalityandyourformalequivalencewithRTLhastostillpass.ForexampleifthereisaNANDgaterightafterlaunchflop,onecaninvestigateiftheotherinputofNANDgatewhichisnotcomingfromlaunchflopinquestion,doesthatotherinputhaveapreviousclockcycleversionavailable?IfthatisavailabletheNANDgatecanbemovedbeforeflop.-Replicatedrivers.Ifaspecificstageistooslowandthereasonforthestageistoomuchloadwithmultiplereceivers,replicatedriverandsplitnumberofreceivinggatesamongthereplicateddrivers.Ifasinglebufferwasdriving8receivers,replicatebufferandhaveeachofthemdrive4receivers.-ParallelisminRTLSearchforopportunitiesinRTLwherebyyoucanchangeserialoperationsintoparallel.Serialoperationstakemoretimeastherearemorestageswithinaclockcycle.Ifwecansplitalargeserialoperationintomultiplesmallerlengthparalleloperationswecaneasilymeettimingoneachoftheindividualoperation.-UseofMacro.Istheresynthesizedlogic,whichisactuallyamemory?IfthatisthecaseRAMsaremuchfasterthanthesynthesizedflops.MapthelogictoSRAMorregisterfile.-Synthesizedif...elseif...elseifseries.Ifrandomlogichasbeensynthesizedforsuchif...elseifseries,thelogiccanbemappedtopassgate4:1mux,giventhatsuchlibrarycellisavailable.Mostofthetimesuchmuxisgoingtobefasterthanthestaticgates.-OneHotinsteadofBinarycodedStateRegistersIfpossibleconvertbinarycodedstateregisterstoonehotregisters.Inonehotconfigurationonlyoneofthemisgoingtoswitchatagiventimeandoveralloperationwillbefaster,-Physicaldesigntechniques.Canyoupromotemetalwirestohighermetal?Orcanthewirebewidened?Inbothcasesthedriverwillseemorecapacitance,sodriverstrengthwillneedtobeincreased.Canthespacingbetweenwirebeincreased?Thiswillreducecapacitanceandspeedupwiredelays.-Powertradeofftechniques.Switchtolowthresholdvoltagelibrarycells.Thesecellshavelowerthresholdvoltage,

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highergateleakageandfasterspeed.Youwillincreasespeedattheexpenseofleakagepower,youwillhavetobewithinanoverallbudgetforthechipforusageofsuchdevices.Youcanusetimeborrowingcaptureflipflops.Suchflopshaveclockdelayedbycertainstages.Whatthisdoesisthepushedoutthecaptureclockwhichhelpsmeetsetuptimeascaptureedgehappenslater.Butmoreclockbuffersalongtheclockpathmeansmoreclocktogglingandmoreactivepower,moredevicesmeansmoreleakageandmorevariation.QuestionS26):Bydefaultdesigncompiler(DC)triestooptimisethepathwithworstviolation.Isthereanythingcanbedonetomakeitworkonmorepathsthanjustworse?AnswerS26):Youcanusegroup_pathcommandtoachievethis.Onecanspecify'critical_range'onthatgrouptohaveDCfocusonaslackrange.

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TimingExceptions(Overrides).QuestionTE1)Whataremulticyclepaths?AnswerTE1):Bydefaulttimingpathsaresinglecyclelong.Hereiswhatitreallymeans.Indigitalcircuits,memoryelementslikeflipflopsorlatches,launchnewdataatthebeginningoftheclockcycle.Duringtheclockcycle,theactualcomputationisperformedthroughthecombinationallogicandattheendoftheclockcycledataisreadyandiscapturedbythenextmemoryelementattherisingedgeofthenextclockcycle,whichisthesameasendingofthecurrentclockcycle.Followingfigureillustratesthis.

FigureTE1a.Singlecycle(default)timingpath

Asshowninthefigure,thelaunchingflopkeepsgeneratingnewsetofdataattheoutputpinQofthelaunchflopwitheveryrisingedgeoftheclockcycle.Similarlycaptureflopkeepssamplinginputdataeveryrisingedgeoftheclockcycle.Asyoucanseeinthefigurethedatalaunchedonrisingedge‘1’(inred)issupposedtobecapturedbycaptureedge‘1’(inblue).Similarlycaptureedge‘2’correspondstolaunchedge‘2’andsoon.Thisiscalledasinglecycletimingpath.Thereisoneclockcyclefromthelaunchofthedatatothecaptureofthedata.Bydefault,timingtoolsassumethistobethecircuitbehavior.Timingtoolswillperformasetupcheckwithrespecttoacaptureclockedge,whichisoneclockcycleafterthelaunchclockedge.Butthismaynotbethecaseeverytime.Manytimeswhathappensisthatthecombinationaldelayfromthelaunchfloptothecaptureflopismorethanoneclockcycle.Insuchcases,onecannotkeeplaunchingdataatthebeginningoftheevery

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clockcycleandhopetocapturecorrectdataattheendofeveryclockcycle.Insuchcasesdatalaunchedatthebeginningofaclockcyclewilljustnotreachthecaptureedgeattheendofclockcycle.Whenthisisthecase,thecircuitdesignerhastoaccountforthisfactanddesignofthecircuit.Ifthecombinationaldelayfromlaunchfloptothecaptureflopismorethanoneclockcycle,butlessthantwoclockcycles,thecircuitdesignerhastodesignthecircuitinsuchawaythatdataisnotlaunchedfromthelaunchflopateveryclockcycle,butislaunchedateveryotherclockcycle.Andthedatalaunchedatthebeginningofaclockcycleiscapturednotafteroneclockcycle,buttwoclockcycles.Followingfiguredepictsthis.

FigureTE1b.Multi(2)cycletimingpath.

Asshowninthefigure,let'ssaythatwehaveacircuitwhereweknowthatcombinationaldelayfromlaunchfloptothecaptureflopismorethanoneclockcyclebutquiteabitlessthantwoclockcycles,suchthatitcanmeetsetuptimerequirementscomfortablyintwoclockcycles,butitdoesn’tmeetsetupinoneclockcycle.Youcanseeinthefigurethedatalaunchedatthelaunchclock‘1’,approximatelyarrivesatthecaptureflop(Datatobecaptured(D))afteraboutoneandhalfclockcycles.Asitwasmentionedearlier,bydefaulttimingtoolsthinkthatalltimingpathsareoneclockcyclelong.Inotherwords,ifthedatawaslaunchedatlaunchclock‘1’,thetimingtoolwillthinkthatitneedstobecapturedatthecaptureedgewhichisoneclockcycleafterthelaunchedge,whichisthecaptureedgeshowninthefigurewithblackrisingarrow.

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Timingtoolbydefaultwillchecksetupwithrespectthecaptureedgeshowninfigurewithblackrisingarrowandwillreportthatinputdatatothecaptureflop(Datatobecaptured(D)),failsthesetuptothecaptureflopasitarriveslaterthanthecaptureedge.Thischeckisshowninfigurewithdottedline.Inrealityweknowthatthisisfalsesetupcheck.Thecaptureflopinputsetupcheckshouldbeagainstthecaptureedgeshownbythebluecolor.Asstatedearlier,ourdesignhereissuchthatweexpectdatatobetaketwoclockcyclestotravelfromlaunchfloptocaptureflopandwehavedesignedourcircuitsuchthatlaunchflopdoesn’tlaunchnewdataeveryclockcycle,butitlauncheseveryotherclockcycleasshownbytheredcolorlaunchedges.Insuchscenario,weneedtoprovidethetimingtoolwithanexceptionoranoverrideandweneedtotellthetimingtoolthat,itneedstopostponeitsdefaultsetupcheckbyoneclockcycle.Inotherwords,weneedtoasktimingtooltogivetheoneadditionalclockcycletimeforthesetupcheck.Usuallythisisachievedbysomethinglikefollowing.set_multi_cycle2-from<start_point>-to<end_point>Where‘2’istheclockcyclecount.Itinstructstimingtooltouse2clockcyclesandnotjustdefault‘1’forthecaseswherewewanttimingtooltouse2clockcycles.QuestionTE2).WhatarefalsepathsAnswerTE2):Statictiminganalysisisexhaustivebynature.Timingtoolwillexhaustivelylookatallpossibletimingpathsandwillperformtimingchecks.Becauseofthis,itwillalsoperformtimingchecksontimingpathswhichcannotreallyhappen.Bestwaytounderstandthisisbyexamples.Considerthecircuitdescribedintheimagebelow.

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FigureTE2a.Falsetimingpath.

Thistypeofcircuitconfigurationisverycommonindigitalcircuits.Functionalclockisactiveonlyinfunctionalmodeandtestclockisactiveonlytestmode.Thismeanswhenatimingpathstartswithfunctionalclocklaunchingdataatfunctionalflop(FF)outputQF,itshouldbecapturedbyreceivingflop(RF)andcaptureclockshouldonlybefunctionalclock.Becauseoftheexhaustivenatureoftimingtools,itwillalsotimeapathwherefunctionalclocklaunchesdataatQFoutputoffunctionflop(FF)andiscapturedatDinputofthereceivingflop(RF)throughtest_clk.Giventhatfunctionalclockandtestclockarenotactiveatthesametime,thistimingpathisfalseandcanneverhappen.WhenfunctionalclocklaunchesdataatQFoutputoffunctionalflop(FF)anditcapturedatDinputofreceivingflop(RF),itcanonlybesampledthroughfunctionalclockandnottestclock,asonlyfunctionalclockwillbeactiveatthattime.Todrivethispointfurther,takealookatthefollowingcircuit.

FigureTE2b.Onemorefalsepath.

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Intheabovefigureamuxisusedtoselectbetweenfunctionalclockandtestclock.Infunctionalmodeonlyfunctionalclockisactiveandtestclockininactive.Intestmodeonlytestclockactiveandfunctionalclockisturnedoff.Fortheabovecircuitthereareonlytwovalidtimingpaths.FirsttimingpathiswherefunctionalclocklaunchesthedataatQoutputoflaunchflop(LF)andthisdataiscapturedagainbyfunctionalclockatcaptureflop(CF)inputD.Secondtimingpathissimilarbutwithtestclock,i.e.wheretestclocklaunchesthedataatQoutputoflaunchflop(LF)andthisdataiscapturedbytestclockatcaptureflop(CF)inputD.Butbecauseoftheexhaustivenatureofthestatictiminganalysis,timingtoolbydefaultcomeupwithfourtimingpaths.1)Functionalclocklaunch=>Functionalclockcapture.2)Functionalclocklaunch=>Testclockcapture.3)Testclocklaunch=>Testclockcapture.4)Testclocklaunch=>Functionalclockcapture.Asyoucanseeonlypaths1)and3)arevalidandpaths2)and4)arefalse.Anexplicitexceptionoroverrideneedstobeprovidedtothetimingtooltoaddressthisfalsepaths.QuestionTE3):WhathappensifamulticycleexceptionisprovidedonlyforsetupormaxtimeinPrimeTime?AnswerTE3):MostofthetimeitisnotenoughtojustprovidemulticycleexceptionformaxonlyinPrimeTime.Becauseasdiscussedearlier,holdtimingcheckiswithrespecttosetupcheckandwhenyouprovidemulticycleexceptionforsetuponlyitchangesthedefaultbehaviorofthesetupcheckandbecauseholdcheckisdependentuponsetupcheck,defaultholdcheckbehaviorisalsochanged.Sowealsohavetoprovidemulticycleexceptionforholdtime,butitismoreofacorrectingbehaviorthananythingelse.Followingdiagramshouldclarifythis.

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FigureTE3.Multicyclesetuponlyexceptionproblem.Asyoucanseeinfigure,firstwaveformiswithoutanyexceptions,whichwehaveanalyzedbefore.Secondwaveformiswithsetuponlymulticycleexception.Whenamulticycleexceptionwith-setupoptionisprovidedinPrimeTimeliketools,whathappensisthatthecaptureedgeforthesetupcheckispushedoutbytheamountofextracyclesspecifiedintheexception.Intheabovefigure,oneextracycleisspecifiedsocaptureedgeispushedoutbyonecycle.Actualmulticycleexceptionwouldhavelookedlikefollowing:set_multicycle_exception1-setupHere‘1’isthenumberofextracycleswewanttoallow,inourcaseitisoneadditionalcycle.Rememberthisnumberisinadditionaltodefault‘1’cycle.Settingmulticycleexceptionby‘1’additionalcyclegivestotaltwoclockcyclesforsetupcheck.Nowweknowthatholdchecksareperformedwithrespecttothesetupcheck.Basedonthenewexceptionbasedsetupcheck,newholdcheckoptionsarederivedasyoucanseebygreendottedlines.Youcanseethatbothholdchecksareviolatingbyaboutacycle.Isthisviolationreal?Nottypically.Inourdesignwestillhavebacktobackrisingedgetriggeredflopsandmostlikelythecellandinterconnectdelaybetweenthemislargeenoughtowarrantamulticycleexception.Butwestillwanttheholdchecktoreflectthenormaltimingcheckwherewewanttoensurethatlauncheddatadoesnotrushthroughtothesamecyclecaptureedge,aslauncheddataismeanttobecapturedattheendofclockcycle.Thismeans,evenwiththesetupmulticycleexceptionwewantholdchecktolooklikejustregularholdcheckwithoutany

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exception,justlikefirstsetofwaveforms.Obviouslywhattoolinferredtobetheholdcheckwithmulticyclesetupexceptioniswrong.Ifyoulookatthewrongholdchecks,youcanseethatwereallyneedthelaunchedgesfortheholdchecktobepushedoutbyonecycle.Whichiswhatamulticycleexceptionwith-holdoptiondoes.Henceweconcludethatwheneverweusemulticycleexceptionwith-setupoption,weneedtoaddmulticycleexceptionwith-holdoptionwithequalnumberofextracycles.Lastsetofwaveformsconfirmthis,wecanseethatonceboth-setupand-holdexceptionsareinplacewegetcorrectsetupandholdtimingchecks.

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SignalIntegrity.QuestionSI1):Whatissignalintegrity?AnswerSI1):Inintegratedcircuits,oneofthephenomenonthatdesignershavetobeawareofis,cross-couplingeffectorcross-talkonwires.Becauseofthiseffect,yoursignalcanloseitsintegrityandyoumightendupcapturingbadsignaldata.Onintegratedcircuits,wiresareroutednexttoeachotherwithinsulatingmaterialinbetweenthem.Thisformsthecapacitorsandswitchingbehaviorofonewireaffectsotherwires.Ifsignalisrising,orgoingfromlowvaluetohighvalueononewire,itcoupleintherisingdirectionwithneighboringwiresandpushesneighboringwiresignalvaluestobumphigh,similarlyonewirescancouplehightolowwithotherwires.Becauseofthiscouplingeffect,signalcanloseitsintegrityandmayloseitsvalue.

FigureSI1.Wiretowirecoupling.

Asshowninthefigureabovewire‘a’andwire‘b’areroutednexttoeachotherandtheycarrysignal‘a’and‘b’respectively.Letssaysignalbissupposedtoremainlowthroughoutthetimeperiodthatweareobserving.Asshowninfigure,ifsignal‘a’switchesandgoeslowtohigh,itisgoingtocouplewithwire‘b’.Becauseofthiscouplingeffect,signal‘b’,whichisnormallyatlowlevel,isgoingtostartrising.Althoughsignal‘b’isnotgoingcontinuerisingforalongtime.Therearetworeasonsforthat.Signal‘a’couplingwithsignal‘b’isatransientevent,signal‘a’isonlygoingtocouplewithsignal‘b’whileitisrising,oncesignal‘a’isdonerising,theeffectis

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goneandtherewillnotbefurthereffecttopushsignal‘b’toriseanymore.Secondreasonisthatwhensignal‘b’islow,itmeantheatthedriverofsignal‘b’,thenmosdeviceisonandassoonasnewchargeonwire‘b’appearsbecauseofthecouplingfromneighbor,nmosdevicewilldischargewire‘b’andpullitdowntolowlevel.Asyoucanseethatif,thecaptureedgeoftheclockforthesignal‘b’,happenstoarriveveryclosetothecouplingglitchonsignal‘b’,thecaptureflip-flopwillcaptureawrongvalueforsignal‘b’.Captureflopshouldhavereallycaptured,lowvalueforsignal‘b’,butasyoucanseeitcaptureshighvalue(showninred)forsignal‘b’andsignal‘b’haslostitsintegritynow.Theheightanddurationofthecouplingglitchobservedonsignal‘b’willdependuponseveralfactors,includingfollowingones.-Capacitancebetweentwowires.-Strengthofthedriverforsignal‘a’andtheslopeorslewrateforsignal‘a’.-Strengthofthedriverforsignal‘b’.Mindwell,thatthisisonlyoneoftheeventthatcausesthesignalintegritytobelost.Thereareseveralotherfactorsthatalsocancausethesignalintegritytobelost,especiallypowerdroopandpropagatedglitch.QuestionSI2):Howtofixcrosstalkglitch?AnswerSI2):Layouttoolswilltakecrosstalkanalysisintoaccountwhenyoustartrouting.Youcantellyourphysicallayouttooltoleaveadjacentroutesofhighfrequencynets,likeclocktrees,tobeempty.Onceyouhavearouteddatabase,youcangetsomesortofcrosstalkreportsandthenfixitinthelayouttool.TwoofthecommonmethodsIcanthinkoffwouldbetoaddstrongerbufferstothevictimnets(ofcoursethatcanaffectyourtiming)oryoucouldroutethenetsinajoggedformationsothattheadjacentareabetweenthevictimandtheaggressoriscomparativelyless.QuestionSI3):Howissignalintegrity(SI)inrelatedtoTiming?HowdoyouimprovetimingfromSIeffects?AnswerSI3)Withshrinkingtechnologies,crosscoupledcapacitancebetweenmetallayersincreases.Asaresult,whenasignalisactivelyswitching,itcancause"crosstalkglitch"ora"crosstalkdelay"onaneighboringsignal(victimnet).Assumeyouhaveanetthatisbeingdrivenbyastrongdriveranditisnexttoanothernet(victim)whichisbeingdrivenbyarelativelyweakerdriver.Whenthevictimisgoingfromhightolowandatthesametime,ifaggressorgoesfromlowtohigh,theaggressorwillcausethevictimswitchfromhightolowalittlelater.Thinkofitasiftheaggressorpreventeditfromgoingfromhightolowrightawaybypullingitinthesamedirectionasitsown.Becauseofthisdelayonthevictimnetgoingfromhightolowincreases,andfurtherdownthelogiccone,thiscancausefailures.Thisiscalled“crosstalkdeltadelay”.

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Inanothercase,ifthevictimislowandifstrongaggressorswitchesfromlowtohigh.Thiswillpullthevictimnetstatefromlowtohighforashorttime,enoughtocauseaglitchonthevictimnet,whichisreferredas“crosstalkglitch”.Thisglitchcouldbecapturedbyaflopdownstreamandcancausestatemachinecorruption.Inbothcasesofcrosstalkdelayandglitchtheamountofdelayortheheightoftheglitchdependsupontheamountofcrosscouplingcapacitance,strengthoftheaggressorandthestrengthofthevictim.Closertheaggressorandvictimaremorecrosscouplingcapacitancewillbe.Strongertheaggressor,morecouplingeffectwillbe.Strongthevictimdriver,lessofthecouplingeffectitwillobserveasitwillbeabletorestoretheoriginallogiclevelonthevictimnetsoonerandwillbeabletorecoverfromglitchfaster.Onecanincreasespacingtoreducecrosscoupling.Onecanreducetheaggressordriverstrengthoronecanincreasevictimdrivestrengthtominimizethecrosscouplingtimingslowdownorthecrosstalkglitch.

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Variation.QuestionV1):Whatisonchipvariation?AnswerV1):Fortimingsign-off,digitaldesignerstypicallysimulatecircuitsatextremeprocesscorners.Thatanalysistypicallyassumesthatgateandinterconnectperformanceatanygivencornermatchacrossthechipordie.Itisassumedthatallcellsorallinterconnectacrosswholechiptobeatthegiven,worst-caseorbest-casecorner.Unfortunately,thatassumptionisnolongervalid.Becauseinrealitythatisnotthecase.Giventhecomplexitiesandintricatenatureofdeep-submicronprocesses,thevariationbetweendevicesandinterconnectcharacteristicsonthesamedie,cannolongerbeignored.Adevicewithspecificsizeisexpectedtorunatcertainspecificspeedatacertainprocesscorneronthechip.Wewantalldeviceswithsamesizeacrossthechiptorunatthesamespeed.Inrealitythatisnotthecase.Becauseinreality,differentpartofchipgetsmanufacturedwithsomevariation.Actualdevicesshapescomeouttobedifferentindifferentpartsofthechip.Manufacturers'librariestypicallycharacterizetheselayersattheabsoluteworst-,typical-,andbest-casecorners.Thefinaldiemostlikelyisnotgoingtohavehavebothworst-case-speedandbest-case-speedtransistorsonit,butitwillhavesignificantvariationinbotheffectivechannellengthandwidthoftransistors.Differentdevicesintendedtobesamewidth(size)endsuphavingslightlydifferentwidthcomparedtooriginalintention,purelybecauseofsomeofthelimitationsinmanufacturingofsuchdevices.Followingaresomeofthevariationacrosschip/diethatcandirectlyaffecttiming.-Thresholdvoltagevariation(Vth)-Channellengthvariation(Le)-Transistorwidthvariation.-Interconnectvariation.-IRdropvariation.-Temperaturevariation.Someofthemajorsourcesofthisvariationare.-TheCMP(chemical-mechanical-planarization)process.-Theproximityeffectsinthephotolithography.-Theproximityeffectsinetchprocesses.TheCMP(chemical-mechanical-planarization)processThereisadifferenceinhardnessbetweentheinterconnectmaterialandthedielectric.afterthedesignerhasetchedtrenchesintothedielectricbelowaninterconnectlayerandcopperonthewafer,theCMPprocessremovestheunwantedcopper,leavingonlywirelinesandvias.Thecopperlineissofterthanthedielectricmaterial,resultingin

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‘dishing’anderosion,whichcauseunevenremovalofthecopperanddielectric.Dishingisafunctionoflinewidthanddensity,anderosionisafunctionoflinespaceanddensity

FigureV1a.DishingandErosion.CMPalsocausesamorerandomvariationininterconnectthickness,resultinginagradientacrossthewafer.Thisgradientisvisibleindie-to-dievariationsandevenacross-dievariationsforlargedie.TheproximityeffectsinthephotolithographyElectronbeamlithographyprovidesneededhighresolutionpatterningforsub-microntechnologies.However,theeffectofelectronscatteringinresistandsubstrateleadstoanundesiredinfluenceintheregionsadjacenttothoseexposedbytheelectronbeam.Thiseffectiscalledtheproximityeffect.Resultisunintendedeffectonneighboringcircuits.Theeffectsarepatternanddensitydependentandvaryacrossdie,resultinginvariationindeviceandinterconnectcharacteristicsacrossthechip.Theproximityeffectsinetchprocesses.Theetchrateofsilicon,duringreactiveionetching(RIE),dependsonthetotalexposedarea.Thisiscalledtheloadingeffect.However,localvariationsinthepatterndensitywill,inasimilarway,causelocalvariationsintheetchrate.Thiseffectiscausedbyalocaldepletionofreactivespeciesandiscalledthemicroloadingeffect.Basicallyetchrateisdependentuponpatterndensityandaspatterndensityvariesacrosschip/die,theetchratevariestooandgivesrisetovariation.Isolatedwiresare

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overetched.Over-etchedtrenchesarewiderandresultsinwiderwiresforisolatedwires.

FigureV1b.Isolatedwiresturnoutwider.Componentsofvariation:Onecandescribeon-chipvariationhavingarandomandasystematiccomponent.Therandomcomponentofcriticalparametervariationoccursfromlottolot,wafertowafer,anddietodie.Examplesarevariationsingate-oxidethickness,implantdoses,andmetalordielectricthickness.Thesystematiccomponentcomprisesvariationsthatyoucanpredictfromtheirlocationonthewaferorthenatureofsurroundingpatterns.Thesevariationsrelatetoproximityeffects,densityeffects,andtherelativedistanceofdevices.ExamplesarevariationsingatechannellengthorwidthandinterconnectheightandwidthDelayvariationandtimingimpact:Variationscausechangesinboththewidthofatransistor'sactiveareaandthedevice'seffectivechannellengthOneoftheissuethatcomplicatestiminganalysisisRC-interconnectvariation.Variationsincriticaldimensionsofminimum-widthlinescanoccurduringmaskgenerationandintheprocessstagesforactiveandpolysiliconlayers.VariationsinthewidthorheightofinterconnectingmetallinescancauselargeRCvariationalonglongernets.Variationininterconnectheightandwidth,resultsinvariationinbothresistanceandcapacitanceofwires.Interconnectdelayindeep-submicronprocessescanoftendominatetotaldelayasgeometriesshrink.Becauseofthis,oneshouldmodelinterconnectvariationasaccuratelyaspossible.MetallineresistivevariationwillcauseIRdrop,whichdirectlyaffectsthestandardcelldelays.Differentpartsofchipendsuphavingdifferentvoltages,eveniftheoriginalintentwastohavesamevoltageacrossthechip.ThisisbecausedifferentpartsofchipwillexperiencedifferentIRdropbecausedifferentresistivevariationsalongdifferentpathsalongwithpotentiallydifferenttemperature.Temperaturevariationscanalsocausedifferencesinelectricalbehaviorand,henceaffecttiming.Fortunately,itisnotcommontofindextremetemperaturecornersonthesamedieduringoperation.Butnonuniformon-chippowerdistribution,interconnect

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heating,andthermalcharacteristicsofthedieandpackagematerialscaninfluenceactualoperatingtemperatures.SomeofthewaystominimizevariationOnecanminimizevariationbychoosingcellsthatarewiderthanminimum.Byrestrictingtheclock-treecellstohigh-drivecells,youensuresmallestvariationandthussmallestmismatchacrossthevarioussubtrees.

Clocks.QuestionC1):Whatarethemainclockdistributionstylesused?AnswerC1):Indigitaldesignstherearetwomainclockdistributionstylesthatareused.1)ClockmeshorClockgriddistributionsystem.2)CTS(Clocktreesynthesis),orClocktreedistributionsystem.QuestionC2):WhatisClockmeshorclockgriddistributionsystem?AnswerC2):Theobjectiveoftheclockmeshorclockgriddistributionsystemistoprovideafixedamountofdelayfromthesourceoftheclock(PLL)totheallendreceiversoftheclock,whichareflops,latches,macrosandclock-gaters.Inotherwords,itaimstominimizeclockskewacrossallthefinalreceiversoftheclock.Theclockdistributionscheme,triestoachievesameoveralldelay,bybalancingnumberofstagesfromthesourcetoalldistributionandbyhavingsamestagedelayforallstagesinsuchdistribution.Thisdistributionalsoaimstolimitthenumberofstagestosmallestpossiblenumber.Thisnumberwouldvarydependingmainlyonthesizeofthedie,typeofprocesstechnologyetc.Suchadistributioncanusuallybethoughtofasatwostepdistribution.Thereasonisthatmostofthetimeachipisdividedintoblocks.ThePLLlieswithinoneoftheblocksandtherearetwolevelsofdistribution.OnefromthePLLtoallblocksboundarieswithinchip,anotherdistributionfromtheblockboundarytoinsideoftheblock.Followingfigureshowsthefirstlevelofdistribution.

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FigureC2a.ClockdistributionfromPLLtoblocks.Thesecondlevelofdistributionhappensinsideblock.Hereiswhere,theclockdistributionthroughfixednumberofstagesisachievedthroughagridorameshofclockbuffers.Ifclockistobedistributedwithinaregion,asymmetricmeshorgridoffinalclockbuffersisformedwithinthatregion.Ideaisthatnomatterwherethefloporfinalreceiverisresidingwithinthatregion,thereshouldbelocalclockbufferinthevicinityofthatreceiver.Thisfinalclockbufferisdrivenbyanotherbufferwhichisagainpartofasymmetricmeshorgrid,whichwouldbelessdenseasitwouldneedtodrivejustthesymmetricallyplacedgridoflaststagedrivers.Belowfigureillustratestheideaoftheclockmesh.Letsassumethatfigurerepresents

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FigureC2b.Clockmeshdistribution.

theareaortheblockwherefinalclockreceivers(flops)arescatteredthroughouttheregion,shownherewith‘F’.Asyoucanseetheplacementof‘F’couldverylikelyberandom.Inthisfiguregreenbufferrepresentsthestartingpointforthedistributionwithinthisregion.UsuallytherearefewstagesofclockbuffersdrivingfromPLLtothegreenbufferstage,whichisthefirststageGreeninverterdrivesallredinverters,whicharesymmetricallyplacedwithrespecttogreendriverstobalancedelays.Reddriversinturndrivebluedrivers,whichagainaresymmetricallyplacedwithrespecttoreddriversforbalancingpurpose.Finallybluedriversdrivethenearbyflops.Thepurposeofthisschemeistobalanceclockdelayfromgreendrivertoallflopreceivers.Asyoucanseethatdelaytoallflopreceiverswillbeveryclose,butitcannotbeidentical,becauseofseveralfactors,likedevicevariationetc.Usuallyclockroutesareshieldedtominimizethecouplingeffectsandvariationstemmingfromcouplingeffects.QuestionC3):Whatisclocktreedistributionsystem?AnswerC3):Clocktreedistributionsystemvariesfromclockmeshdistributionatblocklevel,astohowclockisdistributedtoallfinalclockreceivers.Thekeydifferenceisthat,aclockbuffertreeisbuildfromthesource(main)clockdriverattheblockinputtoallreceivers.Suchclocktreeaimstohaveanoptimalnumberofbranchstagestotheclockreceiver.

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FigureC3.Clocktreedistribution.Asyoucansee,therecouldbedifferentnumberofclockinverter/bufferstagestodifferentreceivers.Theideaistonothaveasamenumberofstagestoallreceivers,buthaveanoptimalnumberofstagesalongeachbranch.Thereasonforchoosingthisoptionisthat,thoughclockmeshgivesmuchbetterskew,itisattheexpenseofmorepowerdissipation,becauseitneedsmorenumberofdevicestoachievebalancingandmanytimes,theoutputofcertainstagesareshortedtominimizeskew.Usuallyclocktreedistributionisusedforrelativelyslowerclocksinyourdesign.Itshouldbenotedthatclocktreedistributiondoesnotcompletelyignoreclockskew,butitdoesnottryhardtobalanceclockdelaystothereceivers.QuestionC4):ExplainCTS(ClockTreeSynthesis)flow.AnswerC4):Manytimes,peoplegetconfusedwithclocktreedistributionandclocktreesynthesis.Theyaretwodifferentthings.Clocktreesynthesisisthedesignsteptoformtheclocktreedistribution.ThegoaloftheCTSflowistominimizetheclockskewandtheclockinsertiondelay.Thisistheflowwhereactualclockdistributiontreeissynthesized.BeforeCTStimingtoolsuseidealclockarrivaltimes.AfterCTSrealclockdistributiontreeisavailablesorealclockarrivaltimesareused.QuestionC5)Whatisclockskew?AnswerC5):Insynchronouscircuitdesign,wewantclocktoarriveatthesametimeforallsequentialreceiversfortheclock,asthatwouldmakeiteasiertodostatictiminganalysis.Weattempttoachievethisbydesignedabalancedclockdistributionscheme.Inrealitywecannotachieveexactsameclockarrivaltimeatallreceivers,butclockarrivesatdifferenttimesatdifferentclockreceiversinthedesign.Thisphenomenonofclockarrivingatdifferenttimesatdifferentplacesiscalled‘clockskew’.Mostlyclockskewisunintentional,butitcouldbeintentionalaswell.

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Oneofthemainreasonfortheclockskewisdesignlimitations.Wewantclocktoarriveatthesameatallreceivers,buttheydonot,becauseofseveralreasonslike,devicedelayvariationbecauseofthresholdvoltageandchannellengthvariation,onchipdevicevariation,differinginterconnect/wiredelays,interconnectdelayvariation,temperaturevariation,capacitivecoupling,varyingreceiverload,badclockdistributiontreedesign.Inindustryclockskewiscommonlyreferredasclockuncertainty.Sometimestheclockskewisintroducedintentionallyinthedesign.Clockskewcanhelpfixsetupviolationsbydelayingthecapturingedgeoftheclockattheexpenseofmorepowerdissipation.Moredetailsareavailableinthequestionsregardinghowtofixsetupviolations.Skewcouldhelporhurtinyourdesign.Ifinrealityclockarriveslaterthanexpectedatasamplingelement,andifthereisminimaldatadelayfromprevioussamplingelement,newdatacanracethroughfromtheprevioussamplingelementandcangetinadvertentlycapturedatthesamplingelementwhereclockarriveslate.Orifthereisenoughofdatadelayfromprevioussamplingelementtothecurrentelement,thelatearrivingclockcomparedtodatacanhelpmeetsetuprequirementatthesamplingelement.Followingfiguredescribesthefalsedatacapturebecauseofclockbeinglateanddatabeingfast.

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FigureC5.Falsedatacapturebecauseoflateclock(clockskew)

Asyoucanseetheinputtotheseriesofbacktobackflopis‘din’.Input‘din’isinitiallylowandrightbeforethesecondrisingclockedgearrives,itgoeshigh.Thefirstflopneedstocapturethehighvalueof‘din’,whichitdoescorrectlyas‘din’meetsthesetuptime.Soonafterclk1rises(secondedge),‘din1’goeshighasitfollows‘din’.Thereiscertaindelayfromdin1todin2,whichmeans‘din2’goesafterafterthatdelay,asitfollows‘din1’.Thishighgoingedgeof‘din2’issupposedtobecapturedbysecondflop,thethirdrisingedgeofclk2.Thatishownormaldigitalsynchronousdesignwithbacktobackflopissupposedtowork.Butwhathappensissecondflopcapturestherisingvalueof‘din2’atthesecondrisingedgeoftheclk2,whichiswrongdatatobecapturedbysecondflop.Nowthestateattheoutputofsecondflopiswrongandsubsequentcalculationsandthestatemachineentersintoanunknownstate.Thisisthetypeofdamageclockskewcando.Asmentionedpreviouslywewilltalkaboutintentionalclockskewtohelpwithsetup

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failuresinaseparatequestion.QuestionC6)Whatisclock-gating?AnswerC6)Clockgatingisapowersavingtechnique.Insynchronouscircuitsalogicgate(AND)isaddedtotheclocknet,whereotherinputoftheANDgatecanbeusedtoturnoffclocktocertainreceivingsequentialswhicharenotactive,thussavingpowerbecauseoftogglingclock.

FigureC6GatedClock.

QuestionC7).Whyisclockgatingdone?AnswerC7)Asyoucanseeinthefigurebyclockgatingwecanmaskcertainclockpulses,orinotherwordswecancontroltheclocktogglingactivity.Clockisusuallyaveryhighfanoutsignalwhichisdistributedthroughoutthechip.Becauseitusuallydriveslargenumberofelementsandnormallycontinuouslytoggles,itaccountformajorportionofdynamicpowerdissipationofthechip.Abilitytoturnoffclocktogglingwhennotneededisthemosteffectivedynamicpowersavingmechanism.Fromtimingperspective,onehastoensurethatclockgatingdoesn’tintroduceglitchesorchangestheshapeoftheclockpulse.Therearesetupandholdcheckstoensurethis.QuestionC8):WhatdoesCRPRstandforandwhatdoesitmean?AnswerC8):CRPRstandsforClockReconvergencePessimismRemoval.Statictiminganalysisisaworstcaseanalysis.Forsetupanalysis,itusestheslowestpossiblelaunchclocknetworkdelay,theslowestpossibleclocktoQforthelaunchflop,theslowestpossiblepathdelayfromthelaunchfloptoQpintothecaptureflopDpin.Alsoitusesfastestpossibleclocknetworkdelayforcaptureclock.Thiswayittriestoworstcasewholeanalysis.Ifthelaunchandcaptureclocknetworksshareacommonpath,thenabovementioned

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worsecasingispessimisticasoneacommonpath,youcannothaveslowestdelayandfastestdelayhappensimultaneously.

FigureC8.CRPRFormaxanalysisSTAtoolwilldofollowing.UseslowestclocknetworkdelayfromAthroughBtoLUsefastestclocknetworkdelayfromAthroughBtoC.WeknowthatforcommonsegmentAthroughB,usingslowestforlaunchandfastestforcaptureispessimisticasitwillhaveonlyonetypeofdelay.STAtoolwillgivecreditwhichisequivalenttothedifferencebetweenslowestdelayfromAthroughBandfastestdelayfromAtoB.Thiscreditwillbeappliedduringthetiminganalysis.Thisistrueformintiminganalysisaswell.

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Metastability.QuestionM1):Whatismetastabilityandwhatareitseffects?AnswerM1):Wheneverthereissetuporholdtimeviolationsinaflip-flop,itentersastatewhereitsoutputisunpredictable.Thisstateofunpredictableoutputisknownasmetastablestate.Tounderstandthecausemetastability,onehastounderstandhowalatchoraflopworks.Asshowninfollowingfigurealatch(oraflop)hasaninverterfeedbackloopwhichactsasamemoryelement.

FigureM1a.DlatchIfyourecallinvertervoltagetransfercurve,itlooksomethinglikethis.

FigureM1b.Invertervoltagetransfercurve.

Fortheinverterloopinthelatchabove,thevoltagetransfercurvegetssuperimposedanditcanbeseeninthefigurebelow.

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FigureM1c.Inverterloopvoltagetransfercurve.

Wherevertwocurvesareintersecting,thosearethestablepointsfortheinverterloop.YoucanseeithasstabilitypointsalongtheXandYaxis.Thosearethecases,inputoftheinverterloopiseitherat‘0’orVmaxvoltage.Youcannoticethatthereisonemorepoint,wheretransfercurvesintersect.ThisiswhentheinputtotheinverterloopisatVmax/2voltage.Thisisthemetastablepointalongthecurve.Theloopcangetstuckhereforaverylongperiodoftime.Butthispointisnotthemoststablepointfortheinvertersloop.Themoststablepointsalongthecurvearethepointsalongaxis,wheninputiseither‘0’orVmax.Dependingonthesizesoftheinvetersintheloop,eventuallyloopwillconvergetothemoststablepoints.Whenavalueistobewrittenintothelatch,theinputvalueisdriventhroughtheinputpin‘D’ofthelatch,whilepassgateisopen.Thiscausesthelatchnode‘I’tobewritten‘0’or‘1’asinputisstronglydriventhroughpin‘D’.Nowifthepassgateisturnedoffearlier,whilelatchnode‘I’hasnotcompletelyreachedto‘0’levelorVmaxlevel,thenode‘I’cangetstucknearVmax/2value,whichisametastablepoint.Toavoidfromthishappening,theinputhastobestableacertaintimebeforethethepassgatecloses.Passgatecloseswhentheclockarrives.Aswe’lllearninotherquestion,thisiscalledthesetuptimeforthelatch.Metastablestateisalsocalledquasistablestate.Attheendofmetastablestate,theflip-flopsettlesdowntoeither'1'or'0'.Thewholeprocessisknownasmetastability.QuestionM2)Howtoavoidmetastability?AnswerM2)

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Ifweensurethatinputdatameetssetupandholdrequirements,wecanguaranteethatweavoidmetastability.Sometimesit’snotpossibletoguaranteetomeetsetup/holdrequirements,especiallygeneratingsignaliscomingfromadifferentclockdomaincomparedtosamplingclock.Insuchcases,whatwedoisplacebacktobackflip-flopsandallocateextratimingcyclesofclockstosamplethedata.Suchaseriesofbacktobackflopsiscalledametastabilityhardenedflop.

FigureM2.Metastabilityhardenedflops

Asyoucanseeinfigure,inputqtothefirstflopclockedbyclkbchangesrightwhenclockisrising,byviolatingthesetuptimeofthisflop.Thiscausestheflip-floptogometastable,duringfirstsamplingclockcycleandwegivefirstflopafullsamplingclockcycletorecoverfrommetastability.Withinfirstcyclefirstfloprecoverstocorrectvalue,wecapturecorrectvalueatoutputsecondflip-flopatbeginningofsecondclockcycleandqsisthecorrectlysynchronizedvalueavailableatthebeginningofsecondclockcycleofclkb.Iffirstfloprecoverstowrongstagewe’vetowaitforonemorecyclei.e.beginningof3rdcycleofsamplingclocktocapturethecorrectvalue.Sometimesit’spossiblethatfirstfloptakeslongerthanonesamplingclockcycletorecovertostablevalue,inwhichcase3flip-flopsinseriescanbeused.Moreflopsinseriesreducesthefailureincapturingthecorrectvalueatoutputatexpenseofmorenumberofcycles.QuestionM3):Howdoyousynchronizebetween2clockdomains?

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AnswerM3):Therearetwowaystodothis.1)AsynchronousFIFO,2)Synchronizer.QuestionM4):ExplaintheworkingofaFIFO.AnswerM4):FIFOisusedforhighthroughputasynchronousdatatransfer.Whenyou’resendingdatafromonedomaintoanotherdomainandifhighperformanceisrequired,youcannotjustgetawaywithsimplesynchronizer(Metaflop).Asyoucan’taffordtolooseclockcycles(Insynchronizeryoumerelywaitforadditionalclockcyclesuntilyouguaranteemetastabilityfreeoperation),youcomeupwithstorageelementandreasonablycomplexhandshakingschemeforcontrolsignalstofacilitatethetransfer.AnAsynchronousFIFOhastwointerfaces,oneforwritingthedataintotheFIFOandtheotherforreadingthedataoutofFIFO.Ithastwoclocks,oneforwritingandtheotherforreading.BlockAwritesthedataintheFIFOandBlockBreadsoutthedatafromit.Tofacilitateerrorfreeoperations,wehaveFIFOfullandFIFOemptysignals.Thesesignalsaregeneratedwithrespecttothecorrespondingclock.Keepinmindthat,becausecontrolsignalsaregeneratedintheircorrespondingdomainsandsuchdomainsareasynchronoustoeachother,thesecontrolsignalshavetobesynchronizedthroughthesynchronizer!FIFOfullsignalisusedbyblockA(whenFIFOisfull,wedon'twantblockAtowritedataintoFIFO,thisdatawillbelost),soitwillbedrivenbythewriteclock.Similarly,FIFOemptywillbedrivenbythereadclock.HerereadclockmeansblockBclockandwriteclockmeansblockAclockAsynchronousFIFOisusedatplaceswhentheperformancemattersmore,whenonedoesnotwanttowasteclockcyclesinhandshakeandmoreresourcesareavailable.

FigureM4.AsynchronousFIFO.

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QuestionD27):HowisFIFOdepth/sizedetermined?AnswerD27):SizeoftheFIFOdependsonbothreadandwriteclockdomainfrequencies,theirrespectiveclockskewandwriteandreaddatarates.Dataratecanvarydependingonthetwoclockdomainoperationandrequirementandfrequency.FIFOhastobeabletohandlethecasewhendatarateofwritingoperationismaximumandforreadoperationisminimum.

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Miscellaneous.QuestionMI1):Designaflipflopusingamux.AnswerMI1):Thereisatwostepanswertothisproblem.Aflip-flopisdesignedusingtwolatchesinamasterslaveconfiguration.Meaningaflip-flopisdesignedusingconnectingtwolatchesbacktoback,firstlatchbeingthemasterandsecondlatchbeingtheslave.Alsowecanmakealatchusingamux.Hence,wefirstmakealatchusingamuxandthenconnecttwosuchlatchesbacktobackinamasterslaveconfigurationtocomeupwiththeflip-flop.

FigureMI1a.Latchusing2:1MUX.

Asshowninthefigure,ifwetieoutputofa2:1MUXbacktoD0pinofmux,wheneverselectisat‘0’,weholdtheoutputstateasitisfedbacktoitselfthroughtheD0inputoftheMUX.Wetieinput‘D’toD1pinoftheMUXandtieselectlinetoCLK(Clock).Wheneverselectline,whichisclock,ishighwepassvalueoninputpinDtotheoutputO.Nowlet’sexplorehowaflip-flopismadeusingtwolatches.

FigureMI1b.Master-Slaveflip-flop

Asshowninthefigure,whenyouconnectalowphaselatchfollowedbyahighphase

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latchwithoutanydelayinbetweenthem,yougetaflip-flop.Firstlatchiscalledmasterandsecondlatchiscalledslave,becausesecondlatchalwaysfollowsthedatathatfirstlatchcaptures.Inasensefirstlatchactsasamasterdeviceandsecondlatchalwaysfollowsmaster.Masterlatchisactivelowphase,henceitisopenduringthelowphaseoftheclockandinputdataat‘D’pinofthislatchhastosetuptotherisingedgeoftheclock,asthatistheedgewhenmasterlatchcloses,orcapturesthedata.Itisimportanttorealizethatthedataatinputpin‘D’ofthemasterlatchthatarrivesatduringthetransparentwindowofthemasterlatch,cannotpushtransparentlythroughslave,aswhilemasterlatchisopenduringthelowphaseofclock,slavelatchisclosedduringthistime.Whenclockrises,masterlatchcaptureandtransfersdatafrominput‘D’pintotheoutputthemasterlatch,atthesametime,becauseclockhasrisen,theslavelatchopensandbecomestransparentandallowsthedataatslavelatchinputtoappearonth‘Q’pinofthemaster-slave.Asyoucanseetheonlytimeavalidoutputappearsfrominput‘D’totheoutput‘Q’piniswhenclockrises.Thiswaythepositiveedgetriggeredmasterslaveflip-flopworks.Havinglearnabouthowtocomeupwithalatchusing2:1MUXandhowtomakeaflip-flopusinglatches,wecannowcomeupwithaflip-flopusing2:1MUXlikefollowing.

FigureMI1c.Flip-flopusing2:1MUXQuestionMI2):HowwillaflipfloprespondiftheclockandDinputofaDflipflopareshortedandclockconnectedtothisshortedinput?AnswerMI2):Onecanexpectthisflipfloptobeinmetastablestatemostofthetime.Becausewithclockanddatainputtiedtogether,everytimeclockrisesthedatawillalsoriseandwilldefinitelyviolatethesetuptimeandholdtimeforthatflipflop.Withthecontinuousviolationofsetupandholdtimewecanexpectflipfloptobeinmetastablestateforatleastverylargeamountoftime.

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QuestionMI3):Howdoyoufixtimingpathfromlatchtolatch?AnswerMI3):Latchtolatchsetuptimeviolationisfixedjustlikefloptofloppathsetuptimeviolation,whereyoueitherspeedupthedatafromlatchtolatchbyeitheroptimizinglogiccount,orspeedingupthegatedelaysand/orspeedingupwiredelays.Youcanspeedupgatesbyupsizingthemandyoucanspeedupwiresbyeitherpromotingthemtohigherlayers,orwideningtheirwidthorincreasingspacingorshieldingthem.Youcanalsofixthetimingissuesbydelayingthesamplingclockorspeedingupthegeneratingclock.Latchtolatchholdviolationshaveinherentprotectionofaphaseorhalfaclockcycle.QuestionMI4)Whatisthedifferencebetweenalatchandaflip-flop.AnswerMI4):Latchislevelsensitivedevice,whileflip-flopisedgesensitive.ActuallyaDflip-flopismadefromtwobacktobacklatches,inmaster-slaveconfiguration.AlowlevelmasterlatchisfollowedbyahighlevelslavelatchtoformarisingedgesensitiveDflip-flop.Latchismadeusingfewerdeviceshencelowerpowercomparedtoflip-flop,butflip-flipisimmunetoglitcheswhilelatchwillpassthroughglitches.QuestionMI5)Whathappenstodelayifyouincreaseloadcapacitance?AnswerMI5):Usuallydeviceslowsdownifloadcapacitanceisincreased.Devicedelaydependsonthreeparameters,1)thestrengthofdevice,whichusuallyisthewidthofthedevice2)inputslopeorslewrateand3)outputloadcapacitance.Increasingstrengthorthewidthincreasesselfloadaswell.QuestionMI6)STAtoolreportsaholdviolationonfollowingcircuit.Whatwouldyoudo?AnswerMI6)

FigureMI6.Hold/Mindelayrequirementforaflop.Ifyougothroughpreviousquestionaboutholdviolationfailure,you’llrealizethat

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holdviolationnormallyariseswhengeneratingclockandsamplingclockarephysicallyseparateclocksandbecauseusuallythereislargeclockskewbetweentheclocktothegeneratingflopandtheclocktosamplingflop.Inthisexamplewe’rereferringtotheholdviolationreportedbytoolwherethetimingpathstartsattheCLKpingoesthroughtheQpinthroughbuffer,MUXandcomesbacktoDinputpinofthesameflopandendsthere.ItisobviousthatgeneratingCLKedgeandsamplingCLKisessentiallythesameedge.Thispathwouldneverhavearealholdviolationaswe’rereferringtothesameCLKedge.ManytimesSTAtoolshavelimitationsanditdoesn’trealizethissituation.BecausethedataisreleasedbytheveryactiveedgeofCLK,againstwhichtheholdcheckisperformed,we’llneverhaveaholdviolationaslongascombineddelayforCLK->Q,bufferandMUXismorethantheintrinsicholdrequirementoftheflop.Rememberfromthepreviousquestionaboutholdtime,thatsequentials(floporlatch)haveintrinsicholdtimerequirementwhichwouldbemorethanzeropsinmostofthecases.Thekeytounderstandhereisthatwe’rereferringtothesameCLKedgehencenoCLKskewandnoholdviolation.QuestionMI7):HowmuchisthemaxfanoutofatypicalCMOSgate.Oralternatively,discussthelimitingfactors.AnswerMI7):FanoutforCMOSgates,istheratiooftheloadcapacitance(thecapacitancethatitisdriving)totheinputgatecapacitance.Ascapacitanceisproportionaltogatesize,thefanoutturnsouttobetheratioofthesizeofthedrivengatetothesizeofthedrivergate.FanoutofaCMOSgatedependsupontheloadcapacitanceandhowfastthedrivinggatecanchargeanddischargetheloadcapacitance.Digitalcircuitsaremainlyaboutspeedandpowertradeoff.Simplyput,CMOSgateloadshouldbewithintherangewheredrivinggatecanchargeordischargetheloadwithinreasonabletimewithreasonablepowerdissipation.TypicalfanoutvaluecanbefoundoutusingtheCMOSgatedelaymodels.SomeoftheCMOSgatemodelsareverycomplicatedinnature.Luckilytherearesimplisticdelaymodels,whicharefairlyaccurate.Forsakeofcomprehendingthisissue,wewillgothroughanoverlysimplifieddelaymodel.WeknowthatI-VcurvesofCMOStransistorarenotlinearandhence,wecan’treallyassumetransistortobearesistorwhentransistorisON,butasmentionedearlierwecanassumetransistortoberesistorinasimplifiedmodel,forourunderstanding.FollowingfigureshowsaNMOSandaPMOSdevice.Let’sassumethatNMOS

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deviceisofunitgatewidth‘W’andforsuchaunitgatewidthdevicetheresistanceis‘R’.Ifweweretoassumethatmobilityofelectronsisdoublethatofholes,whichgivesusanapproximateP/Nratioof2/1toachievesamedelay(withveryrecentprocesstechnologiestheP/Nratiotogetsameriseandfalldelayisgettingcloseto1/1).Inotherwordstoachievethesameresistance‘R’inaPMOSdevice,weneedPMOSdevicetohavedoublethewidthcomparedtoNMOSdevice.Thatiswhytogetresistance‘R’throughPMOSdevicedeviceitneedstobe‘2W’wide.

FigureMI7a.RandCmodelofCMOSinverter

OurmodelinverterhasNMOSwithwidth‘W’andPMOShaswidth‘2W’,withequalriseandfalldelays.Weknowthatgatecapacitanceisdirectlyproportionaltogatewidth.Letsalsoassumethatforwidth‘W’,thegatecapacitanceis‘C’.ThismeansourNMOSgatecapacitanceis‘C’andourPMOSgatecapacitanceis‘2C’.Againforsakeofsimplicityletsassumethediffusioncapacitanceoftransistorstobezero.Letsassumethataninverterwith‘W’gatewidthdrivesanotherinverterwithgatewidththatis‘a’timesthewidthofthedrivertransistor.Thismultiplier‘a’isourfanout.Forthereceiverinverter(loadinverter),NMOSgatecapacitancewouldbea*Casgatecapacitanceisproportionaltothewidthofthegate.

FigureMI7b.Unitsizeinverterdriving‘a’sizeinverter

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Nowlet’srepresentthisbacktobackinverterintermsoftheirRandConlymodels.

FigureMI7c.InverterR&Cmodel

ForthisRCcircuit,wecancalculatethedelayatthedriveroutputnodeusingElmoredelayapproximation.IfyoucanrecallinElmoredelaymodelonecanfindthetotaldelaythroughmultiplenodesinacircuitlikethis:Startwiththefirstnodeofinterestandkeepgoingdownstreamalongthepathwhereyouwanttofindthedelay.AlongthepathstopateachnodeandfindthetotalresistancefromthatnodetoVDD/VSSandmultiplythatresistancewithtotalCapacitanceonthatnode.SumupsuchRandCproductforallnodes.Inourcircuit,thereisonlyonenodeofinterest.Thatisthedriverinverteroutput,ortheendofresistanceR.InthiscasetotalresistancefromthenodetoVDD/VSSis‘R’andtotalcapacitanceonthenodeis‘aC+2aC=3aC’.Hencethedelaycanbeapproximatedtobe‘R*3aC=3aRC’Nowtofindoutthetypicalvalueoffanout‘a’,wecanbuildacircuitwithchainofbacktobackinverterslikefollowingcircuit.

FigureMI7d.Chainofinverters.ObjectiveistodriveloadCLwithoptimumdelaythroughthechainofinverters.Letsassumetheinputcapacitanceoffirstinverteris‘C’asshowninfigurewithunitwidth.Fanoutbeing‘a’nextinverterwidthwould‘a’andsoforth.

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ThenumberofinvertersalongthepathcanberepresentedasafunctionofCLandClikefollowing.TotalnumberofinvertersalongchainD=Loga(CL/C)=ln(CL/C)/ln(a)TotaldelayalongthechainD=Totalinvertersalongthechain*Delayofeachinverter.Earlierwelearnedthatforabacktobackinverterswheredriverinverterinputgatecapacitanceis‘C’andthefanoutrationof‘a’,thedelaythroughdriverinverteris3aRCTotaldelayalongthechainD=ln(CL/C)/ln(a)*3aRCIfwewanttofindtheminimumvalueoftotaldelayfunctionforaspecificvalueoffanout‘a’,weneedtotakethederivativeof‘totaldelay’withrespectto‘a’andmakeitzero.Thatgivesustheminimaofthe‘totaldelay’withrespectto‘a’.D=3*RC*ln(CL/C)*a/ln(a)dD/da=3*RC*ln(CL/C)[(ln(a)-1)/ln2(a)]=0Forthsitobetrue(ln(a)-1)=0Whichmeans:ln(a)=1,therootofwhichisa=e.Thisishowwederivethefanoutof‘e’tobeanoptimalfanoutforachainofinverters.Ifoneweretoplotthevalueoftotaldelay‘D’against‘a’forsuchaninverterchainitlookslikefollowing.

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FigureMI7e.Totaldelayv/sFanoutgraphAsyoucanseeinthegraph,yougetlowestdelaythroughachainofinvertersaroundratioof‘e’.Ofcoursewemadesimplifyingassumptionsincludingthezerodiffusioncapacitance.Inrealitygraphstillfollowssimilarcontourevenwhenyouimproveinverterdelaymodeltobeveryaccurate.Whatactuallyhappensisthatfromfanoutof2tofanoutof6thedelayiswithinlessthan5%range.Thatisthereason,inpracticeafanoutof2to6isusedwithidealbeingcloseto‘e’.Onemorethingtorememberhereisthat,weassumedachainofinverter.Inpracticemanytimesyouwouldfindagatedrivingalongwire.Thetheorystillapplies,onejusthavetofindouttheeffectivewirecapacitancethatthedrivinggateseesandusethattocomeupwiththefanoutratio.

QuestionMI8):HowisRCdelayedmodelledbytools?WhataretheRCdelaymodels?AnswerMI8):RCdelayismodeledasPimodelofvaryingdegreeofaccuracy.MostpopularmodelforRCnetworkisElmoredelaymodel.IfyouassumethatyourRCisnetworkiscomposedofPisegmentofRresistanceandCapacitance,followingrepresentstheRCstructure.

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FigureMI8.Elmoredelaymodel.

QuestionMI9):What’stheequationforElmoreRCdelay?AnswerMI9):Fortheabovementionedpicture,ElmoredelayisfollowingTotalDelayatnodeB=R1C1+(R1+R2)C2Ifthismodularstructureisextendedthandelayatthelastnodecanberepresentedasfollowing.TotalDelayatnodeN=R1C1+(R1+R2)C2+(R1+R2+R3)C3+….(R1+R2+....+RN)CNQuestionMI10):whatisStatisticalSTA?Answer:WhenwerefertostatisticalSTA,wearedifferentiatingbetweenstatisticalanddeterministicSTA.TraditionSTAisdeterministicSTA.BecauseintraditionalSTA,gatedelaysandinterconnectdelaysaredeterministicandattheendoftheanalysiswehaveadeterministicanswerofwhetherthecircuitwillrunatspecificfrequencyornot.OneissuewheretraditionalSTAisnotverygoodatis,modellingindieoronchipvariationaccurately.Withfastshrinkinggeometries,onchipvariationisbecomingmoreandmoredominant.IntraditionalSTA,worstcaseanalysisalongwithclockuncertainty,clockanddataderatingandexplicitmarginsareusedtomodelforindieoronchipvariation.Worstcaseanalysistendstobeverypessimisticasitisnotpracticaltoassumealldevicesonthedietobeattheworstcaseatthesametime.Forclocktreeordatabranchasthestagecountincreasesthevariationeffecttendstogetmitigatedoverthestagecounts.ThisiswherethestatisticalSTAcomesintopicture.StatisticalSTAtriestosolvethismodellingproblem,byprovidingastatisticalapproachtotiminganalysiswhichaddressesthepessimisminmodellingvariation.InstatisticalSTAgateandinterconnectdelaysandprimaryinputarrivaltimesarenotmodelledasdeterministicvalues,butaremodeledasrandomvariablesandresultingtimingcriticalityofthe

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circuitisexpressedintermsofprobabilitydensityfunctions.

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TableofContents

WhatisSTA? 3SetupandHoldTimeViolations. 4TimingExceptions(Overrides). 31SignalIntegrity. 38Variation. 41Clocks. 44Metastability. 52Miscellaneous. 57

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