Status – Week Status – Week 274274

Victor MoyaVictor Moya

Simulator modelSimulator model

Boxes.Boxes. Perform the actual work.Perform the actual work. A box can only access its own data, external A box can only access its own data, external

data must come through signals (time!).data must come through signals (time!). The box manages its own signals.The box manages its own signals. A box: A box:

whatever you do in 1+ cycle or whateverwhatever you do in 1+ cycle or whatever

oror what a piece of hardware doeswhat a piece of hardware does

Simulator ModelSimulator Model

Signals.Signals. Communication between boxes.Communication between boxes. Carry the simulator time: 1+ cycle latency.Carry the simulator time: 1+ cycle latency. Parameters: bandwidth, latency.Parameters: bandwidth, latency. Storage size: bw * (lat + 1).Storage size: bw * (lat + 1). Not allowed read and write with latency 0.Not allowed read and write with latency 0.

Simulator ModelSimulator Model

Wiring boxes:Wiring boxes: Global static object.Global static object. Creates and binds signals by name.Creates and binds signals by name.

StatisticsStatistics Global static object.Global static object. Boxes declare a statistic name.Boxes declare a statistic name. The statistics object manages the different The statistics object manages the different

statitistics.statitistics.

Simulator ModelSimulator Model

BOX

Signal

BOX

SignalBinder

StatisticBinder

SignalSignalSignal

Box

StatisticStatisticStatisticStatistic

Simulator ModelSimulator Model

Box1 Box2

write read

bw:2 lat: 3

ProblemsProblems

Must be 0 latency for wires Must be 0 latency for wires forbidden? => NO!forbidden? => NO!

What happens if a two boxes must What happens if a two boxes must communicate in the same cycle? communicate in the same cycle? => NOT ALLOWED!.=> NOT ALLOWED!.

ProblemsProblems How to manage multiple instances of the same Box How to manage multiple instances of the same Box

(4 vertex shaders, 8 pixel shaders).(4 vertex shaders, 8 pixel shaders). Create each instance as a different class with its own Create each instance as a different class with its own

name and signal binding.name and signal binding. Box() now has a parameter Name that defines a Box() now has a parameter Name that defines a

different name for each instance (How can we grant different name for each instance (How can we grant the names are different?).the names are different?).

How to bind signals in multiple instanced boxed (VS, How to bind signals in multiple instanced boxed (VS, PS).PS). Signal are created/binded by the signal emiter and Signal are created/binded by the signal emiter and

receiver.receiver. Prefix signal name with instance name.Prefix signal name with instance name. Add new parameters to Box() for the emiters name Add new parameters to Box() for the emiters name

instances.instances.

Vertex ShaderVertex Shader

VS 1.0 (NV20) based Vertex VS 1.0 (NV20) based Vertex Shader model.Shader model.

Multithread (multivertex?) Multithread (multivertex?) supported.supported.

No branching.No branching. No texture/vertex buffer load.No texture/vertex buffer load. No vertex kill.No vertex kill.

Vertex ShaderVertex Shader Vertex Loader

Instructions

PC

+1

IR

VIN0 VIN1 VIN2 VIN3

VTIdL

VTId

VTId

+1

+1

VThread Control

IR

TMP0

TMP1

TMP2

TMP3

Constants

Address0Address1Address2Address3

+

OP1 OP2 OP3

Swizzle

Negate

ALU

VOT0 VOT1 VOT2 VOT3

Vertex ShaderVertex Shader

VS 2.0+ (NV30) based Vertex VS 2.0+ (NV30) based Vertex Shader model.Shader model.

Multithreaded?? Implemented with Multithreaded?? Implemented with a FP array (3DLabs P10).a FP array (3DLabs P10).

Dynamic branching.Dynamic branching. No texture/vertx buffer load.No texture/vertx buffer load. No vertex kill.No vertex kill.

Vertex ShaderVertex Shader VertexLoader

Instructions

+1

IR

VTIdL

VTId

VTId

+1

+1VThread Control

IR

Constants

OP1 OP2 OP3

Swizzle

Negate

ALU

VTId

VTId

CC

CC

CC

CC

TMP0

TMP1

TMP2

TMP3

VIN0 VIN1 VIN2 VIN3

Address0Address1Address2Address3

VOT0 VOT1 VOT2 VOT3

PC

PCPCPC STACK

STACK

STACK

STACK

Vertex ShaderVertex Shader

VS 3.0 (DX9.1). Not implemented VS 3.0 (DX9.1). Not implemented yet.yet.

Hardware implementation unknown.Hardware implementation unknown. Static and dynamic branching.Static and dynamic branching. Texture/Vertex Buffer load (and Texture/Vertex Buffer load (and

store?).store?). Possible vertex kill?Possible vertex kill?

Vertex Shader ModelVertex Shader Model Instruction FetchInstruction Fetch

Sends the instruction byte code pointed by the current PC to Sends the instruction byte code pointed by the current PC to Decode/Register box (latency 1).Decode/Register box (latency 1).

Decode/RegisterDecode/Register Calculates next PC (sequential, jump, conditional jump, calls, Calculates next PC (sequential, jump, conditional jump, calls,

return, indirect) and sends it to Instruction Fetch (latency 1).return, indirect) and sends it to Instruction Fetch (latency 1). Reads up to three source operands from the register files (Vertex Reads up to three source operands from the register files (Vertex

Input, Constant, Temporary, Address) and sends them to Execute Input, Constant, Temporary, Address) and sends them to Execute with the instruction operation code (latency1).with the instruction operation code (latency1).

Gets incoming result (flags + operation result) from execute and Gets incoming result (flags + operation result) from execute and write them in the register files (flags, Vertex Output, Temporary).write them in the register files (flags, Vertex Output, Temporary).

ExecuteExecute Performes an operation with the operands received with from the Performes an operation with the operands received with from the

Decode/Register box and sends the result back to Decode/Register box and sends the result back to Decode/Register box with 1+ latency.Decode/Register box with 1+ latency.

Vertex Shader ModelVertex Shader ModelINSTRUCTION FETCH

DECODEREGISTER READ/WRITE

loadProgram(code)

instruction(iData) nextPC(PC)

loadConstant(cData)

loadVIn(vData)

vData readVOut()

EXECUTE

result (res, flags)operation(op, op1, op2, op3)

DirectX 9DirectX 9

Almost ready.Almost ready. DX 9 RC 0 just released.DX 9 RC 0 just released. ATI DX9 demos and drivers.ATI DX9 demos and drivers. GDC Presentations are available GDC Presentations are available

already.already. Introduction to VS/PS 3.0 and Introduction to VS/PS 3.0 and

beyond.beyond.

NV30NV30

Product ‘release’.Product ‘release’. Cards in February.Cards in February. Reviews in later December.Reviews in later December. 400-500 MHz.400-500 MHz. 0.13 um, 125 M Transistors.0.13 um, 125 M Transistors. FP array implements the vertex shader.FP array implements the vertex shader. 8 pixel pipes, 1 TMU.8 pixel pipes, 1 TMU. 128bit 500 MHZ DDRII.128bit 500 MHZ DDRII.