To design a remote controlled stepper motor

The pulse generator provides clock pulse to the up/down counter. The four parallel BCD outputs of the counters are converted into one of ten active high outputs by the BCD to decimal decoder. The decoded outputs are fed to the stepper motor. The 38 kHz infrared signal transmitted by the IR transmitter is received by the IR receiver to control the direction of rotation of the stepper motor. The pulse generator can control the speed of the motor.

Power supply

Pulse generaror

Up/down couner

BCD to decimal decoder

Stepper motor driver

IR transmitter

IR receiver & control circuit

Stepper motor

5V GND

: IR remote control system for stepper motor :

500mA

IC31780532

0.1uF

1000uF

230V AC 50Hz

48

7

6

2

3

5

6v

IR LED

.01uF

12

330

4.7k

.01uF

switch

IC8 NE555

: Power Supply :

: IR Transmitter :

REQUIRED COMPONENTS : IC1 TSOP1738 IR receiver module IC2 CD4013 dual D-type flip-flop IC,IC8 NE555 timer IC4 CD4029 up/down counter IC5 CD4028BCD to decimal decoder IC6 ULN2803darlington pair driver IC7 CD40106 NOT gate IC9 7805C 5V regulator T1 BC547 npn transistor D1-D10 IN4148 switching diode BR1 500mA bridge rectifier LED1 Red LED LED2 Green LED IR LED

Resistors : 1k, 10k, 3.3k, 5.6k, 12, 100k, 4.7k (in ohms)

Capacitors : 1&1000 micro farad, 16v electrolytic 0.01&0.1micro farad ceramic disc

Others : 230V AC primary to 3V-0-3V, 350mA secondary transformer Push-to-on switch 6V Battery Stepper motor

TIME SCHEDULE : 7th SEMESTER NAME OF GUIDE : Mr. Danveer Rajpal

TEAM MEMBERS : ASHOK KUMAR DIVYADEEP KACHHAWA GAJENDRA JANGID GAJESH JAIN

Here is a stepper motor system wherein the direction of rotation of the stepper motor (in clockwise and anticlockwise directions) can be controlled remotely. Besides, the speed can also be controlled locally. STEPPER MOTOR BASICS A stepper motor converts electrical pulses into specific rotational movements. The movement created by each pulse is precise and repeatable. Stepper motors have teeth on both the rotor and the stator. Torque is generated by alternately magnestising the stator teeth electrically, and the permanent magnet rotor teeth try to align u0 with the stator teeth. The coils are arranged around the circumference of the stator in such a way that if they are driven with square waves which have a quadrature phase relationship between them, the motor will rotate. A transition of either square wave causes the rotor to move by a small angular ‘step’, hence the name ‘stepper motor’. The size of this angular step is dependent on the teeth arrangement of the motor, but a common value is 1.8 degrees, or 200 steps per revolution. Speed control is achieved by simply varying the frequency of the square waves.

SYSTEM OVERVIEW

Fig. 1 shows the block diagram of the IR remote control system for the stepper motor. The pulse generator provides clock puse to the up/down counter. The four parallel BCD outputs of the counter are converted into one-of-ten active-high outputs by the BCD-to-decimal decxoder. The decoded outputs are fed to the stepper motor driver to drive the stepper motor. The 38kHz infrared signal transmitted by the IR transmitter is received by the IR receiver to control the direction of rotation of the stepper motor. The pulse generator can control the speed of the motor.

CIRCUIT DESCRIPTION

IR transmitter. Fig. 2 shows the circuit of the IR transmitter. The transmitter circuit, powered by a 6v battery, is built around timer NE555(IC8), which is wired as an astable multivibrator having a frequency of around 38kHz. The frequency of the astable is decided by resistor R10, preset VR2 and capacitor C3. Preset VR2 is used to set the frequency to 38kHz. The output of IC8 is fed to an infrared LED via current-limiting resistor R11. When switch S3 is pressed, the IR LED transmits 38kHz modulated infrared signal.

RECEIVER-CUM-STEPPER MOTOER DRIVER- Fig. 3 shows the circuit of the receiver-cum-stepper motor driver. The transmitted 38kHz modulated signal is received by infrared receiver module TSOP1738(IC1) and it outputs a clock pulse to D-type flip-flop CD4013(IC2) via transistor T1. IC2 accepts data when its clock input is low and transfers it to the output on the positive-going edge of the clock. IC2 is cofigured as a toggle flip-flop as its Q output is connected to ‘D’ input. Thus when TSOP1738 receives a signal from the transmitter, it clocks IC2 and its Q output changes from high to low and vice versa on alternate clock inputs. Consequently, the state of Q output of IC2 controls the direction of the stepper motor. When Q output is high the stepper motor rotates in clockwise direction, and when Q output is lo9w the stepper motor rotates in anti-clockwise direction. The direction of rotation can also be controlled manually by setting Q output high or low with the help of switches S2 and S1, respectively. Set and Reset pins( pins 4 and 6) are normally pulled down by resistors R4 and R5, respectively. These are also connected to switches S1 and S2, respectively. SED1 and LED2 indicate the clockwise and antivlockwise direction of rotation of the stepper motor. The Q output of IC2 controls the up/down pin and parallel input pins P0 and P3 of IC4 (CD4029). Timer NE555 (IC3) is cofigured as an astable multivibrator whose frequency is determined by resistors R8 and R9, preset VR1 and capacitor C1. Preset VR1 is used to vary the frequency and consequently the speed of the stepper motor. IC3 provides clock input to up/down counter IC CD4029 (IC4). IC CD4029 is a presettable up/down counter that counts in either binary or decade mode depending on the voltage level applied at its B/K pin. The B/D input (pin9) of IC4 is grounded to configure it as decade counter. Counter IC4 advances one count for low-to-high transition of the clock pulse when its CE and PL pins are low. It counts up when its up/down input is high, and vice versa. The count-enable input(pin 5) and preset inputs P1 and P2 are grounded, while the parallel-load input pin(PL) is controlled by Q4 and Q5 output pins of IC5. Q0 through Q3 outputs of IC4 are connected to A0 through A3 inputs of IC5(CD4028). IC CD4028 is a 4-bit BCD-to-one-of-ten active-high output decoder. BCD inputs A0 through A3 make the selected output high, while the other nine outputs remain low. When the Q output of IC2 goes high, the counter (IC4) is enabled for up counting with parallel inputs P0 and P3 going low. Decoder(CD4028) outputs Q0 through Q3 go high one after another according to IC4 outputs. When Q4 output of IC5 goes high, the 0000H parallel input data at P0 through P3 pins is loaded into the CD4028(IC4). The counter starts counting afresh in up mode. When Q output of IC2 goes low, the counter (IC4) is configured for down counting and its parallel inputs P0 and P3 become high. In down counting mode, Q9

down through Q6 outputs of the decoder (IC5) go high one after another. As soon as Q5 output of the decoder goes high, the 1001H parallel input data is loaded into the counter and it again starts counting down from Q9 through Q6. The four outputs Q0 through Q3, and Q6 through Q9, of IC5 are ORed via diodes D1 through D8 driving the stepper motor in clockwise or anticlockwise direction. The four ORed outputs of IC5 are connected to eight input pins (two each in parallel) of ICULN 2803. The combined Waveforms for clockwise and anti-clockwise rotation are shown in Fig.9. IC ULN2803 consists of eight Darlington-pair driver transistors. It is basically an inverter that when fed with positive input generates negative output. Stepper motor coils A, B, C and D are connected to output pins17-18, 15-16, 13-14 and 11-123 of ULN2803, respectively, with their common terminal E connected to the 5V power supply. The low output of IC ULN2803 provides path for the current and the coils energise one by one to rotate the stepper motor in clockwise/anticlockwise direction.

POWER SUPPLY- Fig.4 shows the circuit of the power supply. The AC mains is stepped down by transformer X1 to deliver a secondary output of 3V-0-3V, 350mA. The transformer output is rectified by bridge rectifier BR1, filtered by capacitor C5 and regulated by IC9 to provide 5V regulated supply. Capacitor C6 bypasses any ripple in the regulated output.

CONSTRUCTION-

Actual-size, single-side PCB layouts for the IR transmitter and receiver-cum-stepper motor driver circuits(Figs 2 and 3) are shown in Figs 5 and 7, and their component layouts in Figs 6 and 8, respectively. Mount bases for ICs on the PCB so that these can be removed easily when required. Normally, six wires of different colors are available for connection to the stepper motor. The colors code for connecting the stepper motor coils to the driver outputs is shown in Fig.3.

Timer NE/SA/SE555/SE555C

DESCRIPTION The 555 monolithic timing circuit is a highly stable controller capable of producing accurate time delays, or oscillation. In the time delay mode of operation, the time is precisely controlled by one external resistor and capacitor. For a stable operation as an oscillator, the free running frequency and the duty cycle are both accurately controlled with two external resistors and one capacitor. The circuit may be triggered and reset on falling waveforms, and the output structure can source or sink up to 200 mA.

FEATURES• Turn-off time less than 2 ms• Max. operating frequency greater than 500 kHz• Timing from microseconds to hours• Operates in both astable and monostable modes• High output current• Adjustable duty cycle• TTL compatible• Temperature stability of 0.005% per °C

APPLICATIONS• Precision timing• Pulse generation• Sequential timing• Time delay generation• Pulse width modulation

Trigger Pulse Width Requirements and TimeDelaysDue to the nature of the trigger circuitry, the timer will trigger on the negative going edge of the input pulse. For the device to time out properly, it is necessary that the trigger voltage level be returned to some voltage greater than one third of the supply before the time out period. This can be achieved by making either the trigger pulse sufficiently short or by AC coupling into the trigger. By AC couplingthe trigger, see Figure 6, a short negative going pulse is achieved when the trigger signal goes to ground. AC coupling is most frequently used in conjunction with a switch or a signal that goes to ground which initiates the timing cycle. Should the trigger be heldlow, without AC coupling, for a longer duration than the timing cyclethe output will remain in a high state for the duration of the lowtrigger signal, without regard to the threshold comparator state. Thisis due to the predominance of Q15 on the base of Q16, controllingthe state of the bi-stable flip-flop. When the trigger signal thenreturns to a high level, the output will fall immediately. Thus, theoutput signal will follow the trigger signal in this case.

Another consideration is the “turn-off time”. This is the measurementof the amount of time required after the threshold reaches 2/3 VCCto turn the output low. To explain further, Q1 at the threshold inputturns on after reaching 2/3 VCC, which then turns on Q5, which turnson Q6. Current from Q6 turns on Q16 which turns Q17 off. Thisallows current from Q19 to turn on Q20 and Q24 to given an outputlow. These steps cause the 2 s max. delay as stated in the datasheet.Also, a delay comparable to the turn-off time is the trigger releasetime. When the trigger is low, Q10 is on and turns on Q11 which turnson Q15. Q15 turns off Q16 and allows Q17 to turn on. This turns offcurrent to Q20 and Q24, which results in output high. When thetrigger is released, Q10 and Q11 shut off, Q15 turns off, Q16 turns onand the circuit then follows the same path and time delay explainedas “turn off time”. This trigger release time is very important indesigning the trigger pulse width so as not to interfere with theoutput signal as explained previously

CD4013BM/CD4013BC Dual D Flip-FlopGeneral DescriptionThe CD4013B dual D flip-flop is a monolithic complementaryMOS (CMOS) integrated circuit constructed with N- andP-channel enhancement mode transistors. Each flip-flophas independent data, set, reset, and clock inputs and ``Q''and ``Q'' outputs. These devices can be used for shift registerapplications, and by connecting ``Q'' output to the datainput, for counter and toggle applications. The logic levelpresent at the ``D'' input is transferred to the Q output duringthe positive-going transition of the clock pulse. Setting orresetting is independent of the clock and is accomplishedby a high level on the set or reset line respectively.

FeaturesY Wide supply voltage range 3.0V to 15VY High noise immunity 0.45 VDD (typ.)

Y Low power TTL fan out of 2 driving 74Lcompatibility or 1 driving 74LSApplicationsY Automotive Y Alarm systemY Data terminals Y Industrial electronicsY Instrumentation Y Remote metering

Y Medical electronics Y Computers

Absolute Maximum Ratings (Notes 1 & 2)If Military/Aerospace specified devices are required,please contact the National Semiconductor SalesOffice/Distributors for availability and specifications.DC Supply Voltage (VDD) b0.5 VDC to a18 VDCInput Voltage (VIN) b0.5 VDC to VDD a0.5 VDCStorage Temp. Range (TS) b65§C to a150§CPower Dissipation (PD)Dual-In-Line 700 mWSmall Outline 500 mWLead Temperature (TL)(Soldering, 10 seconds) 260§C

OCTAL PERIPHERALDRIVER ARRAYS ULN2803

The eight NPN Darlington connected transistors in this family of arraysare ideally suited for interfacing between low logic level digital circuitry (suchas TTL, CMOS or PMOS/NMOS) and the higher current/voltagerequirements of lamps, relays, printer hammers or other similar loads for abroad range of computer, industrial, and consumer applications. All devicesfeature open–collector outputs and free wheeling clamp diodes for transientsuppression.The ULN2803 is designed to be compatible with standard TTL families

while the ULN2804 is optimized for 6 to 15 volt high level CMOS or PMOS.

Synchronous up/down counter,binary/decade counterHEF4029BMSI

DESCRIPTIONThe HEF4029B is a synchronous edge-triggered up/down 4-bit binary/BCD decade counter with a clock input (CP), an active LOW count enable input (CE), an up/down control input (UP/DN), a binary/decade control input (BIN/DEC), an overriding asynchronous active HIGH parallel load input (PL), four parallel data inputs (P0 to P3), four parallel buffered outputs (O0 to O3) and an activeLOW terminal count output (TC). Information on P0 to P3 is asynchronously loaded into the counter while PL is HIGH, independent of CP. The counter is advanced one count on the LOW to HIGH transition of CP when CE and PL are LOW. The TC signal is normally HIGH and goes LOW when the counterreaches its maximum count in the UP mode, or the minimum count in the DOWN mode provided CE is LOW. Fig.1 Functional diagram. Fig.2 Pinning diagram.HEF4029BP(N): 16-lead DIL; plastic (SOT38-1) HEF4029BD(F): 16-lead DIL; ceramic (cerdip) (SOT74) HEF4029BT(D): 16-lead SO; plastic (SOT109-1) Package Designator North America