Strips Architecture Status and Plans FY15 to FY18 & beyond

Mitch Newcomer for the Strips Architecture Group

Strips Readout: The Big PicturePrototype versions of the HCC and ABC130 have been submitted and tested successfully.

• HCC, a Penn responsibility, was designed in collaboration with CERN, RAL and UCSC.

• RAL/UCL showed HCC has satisfied basic functionality.

• HCC is being used with ABC130 to populate modules for prototype stave and pedal tests.

• The ABC130 and HCC design cycle started around 2012. During that time higher bandwidth requirements emerged from the trigger DAQ community.

• 200KHz L1 readout 1MHz L1 readout & New proposal: readout at 1MHZ L0 rate.

• The Star (parallel ABC) Readout Architecture was introduced to meet new bandwidth requirements.

• ABC130 and HCC chipset will be used for stave and endcap prototyping while developing the STAR readout chip set.

• Penn and LBL are collaborating on a Parametric tester for HCC’s. Penn will focus on understanding the parametric limits of the design, LBL will use the tester to characterized HCC die for prototype modules.

• UK and US Simulation efforts in place to validated Strips Readout Architecture meets latency and band width requirements.

• Projected ABC* submission March/April 2016 HCC * follows by 3 months.

• Availability of Star Chipset:• Success oriented projection mid- FY17• Pessimistic ( real world experience driven) FY18

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Star Readout development planDefine Hybrid Command/Control/Readout Architecture with sufficient precision to allow the ABC specification to proceed.

Design to be informed by detailed bandwidth and latency simulations performed by Mark Sutton (ITK detector level) and Keisuke Yoshihara (Hybrid level).

• ABC* specification to be completed in the Fall 2016. • Should be versatile enough to allow a continuing refinement of HCC control/readout within

foreseeable triggering and readout rate parameters.

• ABC* design effort led by Francis Anghinolfi at CERN with help from • Chinese collaborators Libo, Weiguo, Joel Dewitt and Penn• Proposed ABC* tape out Spring 2016.

• Dedicated Stave Communications MPW organized/designed largely by Penn with input from the community Prototype Stave Command, Control / Data readout techniques will help validate HCC designs. • These tests are not expected to compromise ABC* specifications• Tape out September/October depending on MOSIS schedule.

SLAC US-ITK meeting July 2015 3

HCC* Control Path

To ABCs

Control lines: TBDMulti-level data flow

L0, L1, R3, CMD….

Decode

Trig Gen

L0L1

L1 FIFO

Com decoder

CommandR3s

R3 FIFO

Trigger Policy

Buffer

Occ’s

Bookkeeping

4

Includes L0 readoutoption @ 1MHz

L0 – BC sync. PIPELINE transfer to RAMR3 – Regional Readout RequestL1 – Detector Readout

SLAC US-ITK meeting July 2015

HCC* Design

Control Path

Input Channel

Input Channel

Input Channel

Input Channel

12 Input Channels

OutputChannel

Multi –DropFrom EOS (GBT)

Bused to ABCsIndependent ABC Serial readout @160Mbps

Point to Point Data TransmissionUp to 640Mbps

5SLAC US-ITK meeting July 2015

HCC* Data Input Channel

Dese

rializer

RTL FIFO64x2(L1)

RTL FIFO64x2(R3)

64

R3WrEn

L1WrEn

64

RTL FIFO16x4(L1)

RTL FIFO16x4(R3)

64SRAM 64x128

7 AddressWrEn RdEn

L1Empty

16

L1RdEn

R3Empty

R3RdEn

Channel Controller

Event Framing

16

16

16

L1Done

L1Next

R3Done

R3Next

L1R3

RTL FIFO64x4(Reg)

6

ABC Data

SLAC US-ITK meeting July 2015

Star Readout Development Plan ( HCC* ) FY15 Design of internal HCC functional blocks begun. Need a believable, not necessarily final version of the HCC to vet ABC* specification.

HCC* ABC* Multi-level control logic ( much of the design parallels HCC) ABC* HCC* Input channel design ( preliminary version exists)HCC* Stave data readout (less critical TBD)

FY16 HCC* HCC* Specification completed as necessary for ABC* designthen completed/frozen with respect to stave side communications

• Work on HCC Blocks continues in parallel with communications MPW. • Floorplan and Place & Route continuously updated during design. • Design Review in December/January with nearly completed Specification• HCC* tape out May / June FY16.

SLAC US-ITK meeting July 2015 7

Motivations for considering alternative Stave Bus Communication Approaches

Primary: Test ideas/options for increasing stave bus cmd/control throughput.Current: Multi-drop control lines: R3/L1, CMD/L0 40MHz DDR

Issues to be addressed:

1) HCC/ABC* needs robust non-disruptive L0 counter synchronization with outside.

Extra microstrip pair? Rollover reset is least disruptive but ‘L0’ is BC independent.

2) Strong motivation for a low latency module specific region of interest request.

Present module specific serialized R3 command is 27 bits long. (675ns)

Double Data TX rate? Add microstrip pair? Both?Adding a new multi-drop line simplifies the control structure and allows for a synchronous update of the L0 counter. Requires extra width on stave bus and makes multi-drop connection to HCC difficult or impossible.

Higher bandwidth allows more logical channels on one control line. But..

Signals like L0 must be highly reliable. We need to guarantee robust operation.

SLAC US-ITK meeting July 2015 8

Example Proposal for Clock and Control Lines

BC: 40 MHz

80 MHz Locally Synthesized

L0/L0sync40 MHz DDR

L1/CMD/R380 MHz DDR

L0 L0sync L0 L0sync L0 L0sync

C R3 L1R3 C R3 L1R3 C R3L1 R3

This approach minimizes the additional bandwidth required to keep the same number of physical lines.

SLAC US-ITK meeting July 2015 9

Multi-drop stave micro-strip simulationNear (green) and Far (red) Stave signals

No PreComp PreComp - No boost current

10 bits @ 160Mbps

SLAC US-ITK meeting July 2015 10

Communications focused MPW motivation Test balanced code advantages on multi-drop lines for robust operation:

• Transition time on the stave bus is a maximum of 5ns.

• Is a 10 bit balanced code the optimal answer when the bit time is 6.25ns?

MPW makes possible a “use case” study of receiver signal shaping techniques, deglitching circuits and the importance of balanced code using a GBT drive and HCC receivers on a close to final multi-drop stave.

• A detailed study of signal shapes on the bus can be useful to influence the detailed of the design of the lossy micro strip transmission line.

Additional benefits:

• Point to Point Data Transmission study at 640Mbps HCC to Stave. Test out improved pre-compensation, Understand benefit of 8b10b or other balanced code approaches.

Implement a Memory, Serializer and Driver with balanced code options.

Realistic Test with HCC drive over stave bus to GBT will provide significant experience with a realistic readout.

Test out RTL designed memory for HCC input channel? SLAC US-ITK meeting July 2015 11

HCC* First Prototype

Technology: IBM ( now Global Foundries ) 130nm CMOS

Design team

Penn: Nandor Dressnandt, Paul Keener, Aditya Narayan, Mitch Newcomer (Staff) 1-

2 MSEE Students

UCSC: Joel Dewitt

HCC* chip design:

• Experience from HCC Floor planning, Place & Route and block and chip level DRC checks already being implemented to prepare for submission of HCC.

• Much of the HCC Design can be re-used or updated and re-used.

• Blocks are being designed in parallel with ongoing architecture definition.

• Biggest issue may be in knowing when to switch from design definition to implementation.

SLAC US-ITK meeting July 2015 12

HCC* PnR

• Floor planning nearly finalized• Power/ground design completed: (Power/gnd distribution)

• All macros placed (Pll, regulator, bandgap, Delay Blocks, AM, POR, etc)

• Awaiting agreement with hybrid designers on final pad locations

• Sufficient room reserved for synthesized logic

• Encounter PnR script-driven • Scripts updated from proven HCC design

• Tools updated

• Final checks and tape-out from Virtuoso

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* Size: 5.2mm x 3.2mm* Primary Power/gnd on top* Additional gnd’s all sides* Hybrid services on bottom* Stave services on top

Room for RTL LogicRoom for RTL Logic

HCC* Evolving Layout

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FY17 – 18 … and beyond

FY17 - 18

• Design of an HCC* tester base on HCC parametric tester.

• Modification of STAR prototypes, Preparation for the production ready ASICs.

• Participate in the design or lead development of a specialized ASIC with monitoring and LV power control.

• Acquire a readout module at Penn based on Star readout to gain experience with the design and serve as a training ground for students to participate in studies at CERN.

Beyond….

Help plan for installation and commissioning bringing perspectives from commissioning the TRT.

Participate in installation and commissioning

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