study of asymmetrical effects of silicon submicron transistors
TRANSCRIPT
Study of asymmetrical effects of silicon submicron transistors
Ashraf Uddin*, Tay Yee Siong
School of Materials Engineering, Nanyang Technological University, Singapore, Singapore 639798
Received 18 March 2004; revised 19 April 2004; accepted 26 April 2004
Abstract
We studied the asymmetrical effect of submicron channel length NMOS silicon transistors. The threshold voltage of transistor was
determined by transconductance ðgmÞ extraction method and constant-current (CC) method. The effective channel length ðLeffÞ was
determined by ‘shift and ratio’ methods. The short channel and reverse short channel effect were observed from the threshold voltage ðVtoÞ
versus channel width ðWÞ curve. The I –V curves were not shown significant asymmetry of drain and source. The results showed that the
asymmetry of drain and source increased with reducing the channel length. The standard deviation of threshold voltage and effective channel
length were increased with decreasing channel length.
q 2004 Elsevier Ltd. All rights reserved.
Keywords: Transistor; Short channel effect; Threshold voltage; Effective channel length
1. Introduction
Metal oxide semiconductor field effect transistor (MOS-
FET) is the most important fundamental device for ultra
large scale integrated circuits [1]. New advanced technology
with smaller channel length transistor is coming to the
market in every few years. The effect of channel length on
asymmetrical of drain and source become important and
imperative to study [2–6].
The objective of this work is to study the effect of
asymmetry of drain and source of silicon MOS transistor
with different submicron channel lengths over the wafer.
This work is divided into two parts. The first part is focused
on threshold voltage measurement with transconductance
extraction and constant-current (CC) methods for different
channel length MOS transistors, such as 0.18, 0.13 and
0.09 mm. In the transconductance ðgmÞ extraction method,
the threshold voltage is determined by extrapolating the
gmð¼ dIds=dVgÞ2 Vg relation in the low ON current region
as shown in Fig. 1. The typical drain current Id; gm versus
gate voltage Vg curve that was used to determine the
threshold voltage Vto by gm extraction method. The constant
current method is obtained by measuring the gate voltage at
which a specific small drain current ( ¼ 0.1 mA) flows at
source–drain bias Vds ¼ 0:1 V and this gate voltage is
defined as threshold voltage Vtlin:
The effective channel length ðLeffÞ was determined by
using ‘shift and ratio’ methods instead of conventional
channel resistance methods. It is found that the standard
deviation of threshold voltages and effective channel length
were increased with decrease of transistor channel length.
2. Experimental
The silicon MOS transistors were fabricated in the eight
inch size wafer by Chartered Semiconductor Manufacturing
Company. The NMOS transistor used in this experiment
were a retrograded twin well implant. The COSi2 was used
for shallow trench isolation (STI) to reduce the series
resistance. Three different channel lengths of 0.18, 0.13 and
0.09 mm transistors were used for this investigation. The
intermediate type channel width (W ¼ 0:3 mm) transistors
were mainly used for this investigation. For 0.18 mm size
devices, the conventional nitride spacer was used. For 0.13
and 0.09 mm size devices, the L-shape spacer was formed.
Transistors from all over the wafer were characterized for
this investigation.
The HP4155A semiconductor parameter analyzer was
used to measure the threshold voltage of transistors. Each
transistor was measured twice by swapping drain and source
0026-2692/$ - see front matter q 2004 Elsevier Ltd. All rights reserved.
doi:10.1016/j.mejo.2004.04.010
Microelectronics Journal 35 (2004) 641–645
www.elsevier.com/locate/mejo
* Corresponding author. Tel.: þ61-6790-4867; fax: þ61-6790-9081.
E-mail address: [email protected] (A. Uddin).
voltages. The ‘shift and ratio’ method was used to measure
the effective channel length, Leff : All the Leff values were
measured within the gate voltage range 1–5 V. In order to
get consistent results, Vto;Vtlin and Leff measurements were
always started from drain side, and then swapped to source
side immediately. It is important to understand the effect of
electrical stress on Vto and Leff : The reverse measurement
was examined at different locations. Each die was measured
three times, i.e. source to drain, drain to source and source to
drain again. The electrical stress does not change the values
of Vto and Leff :
3. Results and discussions
The typical I –V characteristic curves of drain current
ðIdÞ versus gate voltage ðVgÞ are shown in Fig. 2 for channel
length 0.18, 0.13 and 0.09 mm NMOS transistors. Each
transistor was measured twice by swapping the drain and
source bias voltage. The threshold voltage ðVtoÞ decreased
as the channel length ðLÞ decreased from 0.18 to 0.09 mm.
There are supposed to be a ‘roll-up’ then followed by a ‘roll-
off’ effect of reverse short channel effect (RSCE) in
the threshold voltage of transistor [3,4]. This is one of the
most important phenomena of submicron MOSFET while
compared with long channel (L . 1:0 mm) MOSFET that
the Vto is independent of L [2]. The two I –V curves were
overlapped each other after swapping the drain and source
bias for the same transistor. The overlapped I –V curves
show no significant asymmetry of drain and source as shown
in Fig. 2.
The subthreshold current ðIDSTÞ increased more rapidly
than linearly as L decreased and subthreshold swing ðStÞ
increased with decreasing L: IDST is the small drain current
which flows in the MOSFET channel below threshold (i.e.
in weak inversion). In general, the value of St ¼ 60 mV/dec
is considered as good performance and St , 60 mV/dec is
considered as bad performance of submicron transistor. In
the long channel MOSFET, normally, the IDST increases
linearly as L decreases and St is independent of L: The St
was approximately same after swapping of drain and source
bias for the same size transistor, though St increased with
decreasing L: In most applications small leakage current
ðIOFFÞ (at Vg ¼ 0:0 V) is useful as a drive current. However,
it can represent an unwanted leakage current, especially in
integrated circuits (ICs) designed for low power appli-
cations. It can also give rise to premature discharging of
memory-cell capacitors or dynamic-logic circuit nodes,
preventing these circuits from operating properly. For many
applications especially, those requiring low standby-power
dissipation, subthreshold leakage current ðIOFFÞ must be
well characterized so that the total IC leakage current of the
chip can be predicted during the design phase of the product.
The logarithmic scale of drain/source current ðIdÞ versus
gate voltage ðVgÞ is shown in Fig. 3 for 0.18, 0.13 and
0.09 mm size transistors. The 90 nm channel length
transistor has the highest IOFF current (1027 A) compare
to 0.13 and 0.18 mm channel length transistors, which is
considered as a large leakage current. The reverse short
channel effect (RSCE) is responsible for this high leakage
current. Fig. 4 shows the Vto roll-up and roll-off effects of
RSCE of transistors with channel length 0.18, 0.13 and
Fig. 1. A typical Id; gm vs Vg curves for a NMOS transistor show how the
threshold voltage Vto is determined from the extrapolation. The drain
voltage Vd ¼ 100 mV was applied for this measurement.
Fig. 2. The Id versus Vg curves for transistors with channel length L ¼ 0:18;
0.13 and 0.09 mm. The drain bias was Vd ¼ 0:1 V. The threshold voltages
Vto are 507.4, 479.4 and 334.6 mV for transistors with channel length 0.18,
0.13 and 0.09 mm, respectively.
Fig. 3. The logðIdÞ versus Vg curves for transistors with channel length
L ¼ 0:18; 0.13 and 0.09 mm. The drain bias was Vd ¼ 0:1 V. The leakage
currents IOFF (at Vg ¼ 0:0 V) are around 1 £ 10210, 3 £ 10210 and
7 £ 1028 A for transistors with channel length 0.18, 0.13 and 0.09 mm,
respectively.
A. Uddin, T.Y. Siong / Microelectronics Journal 35 (2004) 641–645642
0.09 mm. The possible reasons of RSCE are: (i) lateral
dopant non-uniformity at the channel Si–SiO2 interface,
which arising from enhanced diffusion of channel dopants
caused by interstitial injection during salicide formation, or
implant damages; (ii) the boron segregation to implant
damaged regions at the edge of the channel; (iii) the
transient enhanced diffusion of channel dopants to
the silicon surface arising from implant damage; and (iv)
the silicon interstitial capture in the gate oxide.
3.1. Threshold voltage from gm method
The threshold voltages, Vto of three different transistors
were measured by using gm method as shown in Fig. 1.
Some trends are found from wafer map pattern to analyze
the geometric symmetry of drain and source by swapping
the drain and source bias. Table 1 shows the summary of
measurement of transistors over the wafer. We have
measured the drain side ðVtoDÞ and source side ðVtoSÞ
threshold voltages for all transistors. The sample size was
large enough to estimate the standard deviation of threshold
voltage. The standard deviation of VtoD and VtoS were very
close value. The average threshold voltage Vto½¼ ðVtoD þ
VtoSÞ=2� were estimated from the mean value of VtoD and
VtoS: The statistical variation of DVtoð¼ VtoD 2 VtoSÞ was
measured for all samples. The standard deviation of Vto of
transistors of 0.18, 0.13 and 0.09 mm sizes were estimated
and are recorded in Table 1. The standard deviation of Vto
was increased for advanced technologies as L decreased.
The control of asymmetry of drain and source is a problem
for the smaller transistor.
3.2. Threshold voltage from CC method
The threshold voltages ðVtlinÞ of 0.18, 0.13 and 0.09 mm
size transistors were measured by using constant-current
(CC) method. From the definition, Vtlin was determined by
Vg when Ids ¼ 0:1 mAx(W/L). However, due to the project
time constraint, Vtlin measurements were simplified to vary
gate voltage ðVgÞ from 0 to 1 V with 1 mV/step, while
DVtlinð¼ VtlinD 2 VtlinSÞ results were varied from few mV to
less than 1 mV. Therefore, Vtlin results were actually
determined by rounding off to the nearest Vg of correspond-
ing Ids: Nevertheless, the difference of Vtlin was insignificant
due to the rounding off errors to determine the Vtlin values.
The statistical variation of drain side VtlinD and source side
VtlinS were measured for all transistors. The mean threshold
voltage Vtlin½¼ ðVtlinD þ VtlinSÞ=2� was estimated for all
transistors and is recorded in Table 2. The average value
of Vtlin is about 100 mV lower than the Vto values for all
transistors. The standard deviation of Vtlin was also
estimated for all transistors. The standard deviation of
threshold voltages was increased for advanced technologies
as channel length becomes smaller. The control of
Fig. 4. The threshold voltage Vto versus channel width W plot for transistors
with channel length L ¼ 0:18; 0.13 and 0.09 mm. The roll-up and then roll-
off effects of reverse short channel effect are observed in all transistors.
Table 1
The threshold voltage Vto of NMOS transistors with channel length 0.18,
0.13 and 0.09 mm are listed from gm method
Transistor
type (mm)
Vto Mean
Vto (mV)
Average value
of Vto (mV)
Standard deviation
of Vto (mV)
0.18 VtoD 501.0 501.1 8.6
VtoS 501.2
0.13 VtoD 471.3 470.7 11.3
VtoS 470.2
0.09 VtoD 335.8 335.5 28.7
VtoS 335.2
The average value of Vto½¼ ðVtoD þ VtoSÞ=2� is estimated. The standard
deviation of Vto was estimated from the measured values of VtoD and VtoS
over the wafer. The standard division of Vto is increased with decrease of
transistor channel length.
Table 2
The threshold voltages Vtlin of NMOS transistors with channel length 0.18,
0.13 and 0.09 mm are listed from the CC method
Transistor
type (mm)
Vtlin Mean
Vtlin (mV)
Average value
of Vtlin (mV)
Standard deviation
of Vtlin (mV)
0.18 VtlinD 415.8 415.9 13.7
VtlinS 415.9
0.13 VtlinD 379.2 378.7 25.5
VtlinS 378.3
0.09 VtlinD 236.5 235.6 56.6
VtlinS 234.8
The average value of Vtlin½¼ ðVtlinD þ VtlinSÞ=2� is estimated. The
standard deviation of Vtlin was estimated from the measured values of VtlinD
and VtlinS over the wafer. The standard division of Vtlin is increased with
decrease of transistor channel length.
A. Uddin, T.Y. Siong / Microelectronics Journal 35 (2004) 641–645 643
geometrical asymmetry of drain and source become a new
challenge in design for the smaller transistor.
3.3. Effective channel length
Channel length is a key parameter in CMOS technology
for circuit modeling, device design and process monitoring.
Channel length usually differs from the mask gate length by
an amount depending on the gate lithography and the etch
process, as well as the lateral source–drain diffusion.
Extraction and physical interpretation of MOSFET channel
lengths are becoming increasingly difficult in the deep
submicron region due to strong variation of mobility with
gate voltage, more pronounced effects of graded source–
drain doping profiles, and line width-dependent lithography
bias near the optical resolution limit.
Fig. 5 shows schematically how various channel lengths
are defined. Lmask is the design length on the poly-silicon
gate mask. It is reproduced on the wafer as Lgate through
lithography and etching processes. Depending on the
lithography and etching biases, Lgate can be either longer
or shorter than Lmask: Lmet is defined as the distance between
the metallurgical junctions of the source and drain diffusions
at the silicon surface. Usually, Lmet is shorter than Lgate by a
certain amount due to the lateral straggle of ion implantation
and the lateral source–drain diffusion in the process. The
effective channel length ðLeffÞ is different from all other
channel lengths discussed above. It is defined through some
electrical characteristics of the MOSFET device. Qualitat-
ively, Leff is a measure of how much gate-controlled current
a MOSFET delivers in reference to the long-channel device.
A key point to realize here is that one cannot expect to
find the metallurgical channel length by channel length
extraction. The conventional association of Leff with Lmet
originates from the over-simplified notion that the source–
drain junctions are infinitely abrupt. In reality, source–drain
doping gradients are always finite (but unknown) and the
metallurgical channel length as defined has no direct
bearing on device current.
The Leff differs for different Lmask: It is assumed that the
Lmask is related with Leff by a constant channel length DL;
i.e.
Leff ¼ Lmask 2 DL ð1Þ
All the lithography and etch biases as well as the lateral
source–drain implant straggle and diffusion are lumped into
DL: In the most commonly used method of channel length
extraction, called the channel resistance method, it is only
necessary to assume that the carrier mobility does not
change with channel length [7–9]. An improved channel
length extraction algorithm is called the ‘shift and ratio’
method. Shift and ratio (S and R) method is based on the
channel resistance concept.
The channel length Lieff (or DL) can be estimated from the
average ratio of krl;
krldmin ¼Lo
eff
Lieff
¼Lo
mask 2 DL
Limask 2 DL
ð2Þ
Note that even if DL is different between the long-channel
and the short-channel devices, a very little error is
introduced for long channel devices as DL ! Lomask; hence
Loeff < Lo
mask; insensitive to DL: For a given long-channel
reference, the above extraction procedure can be repeated
for a number of short-channel devices with different Limask:
A by-product of the process is the low-drain short-channel
threshold voltage roll-off given by dmin ¼ Voto 2 Vi
to; the
threshold voltage difference between the long and short
channel transistors.
Long channel MOSFET measurement was required for
reference to determine Leff of submicron MOSFET. By
using the krlmin value at dmin depending on the gate voltage
Fig. 5. Schematic diagram are showing the definition and relationship
among the various terms of channel length of a transistor.
Table 3
The effective channel length Leff of NMOS transistors type 0.18, 0.13 and
0.09 mm size are listed from the shift and ratio method
Transistor
type (mm)
Leff Mean
Leff (mm)
Average value
of Leff (mm)
Standard deviation
of DLeff (mm)
0.18 LeffD 0.152 0.149 0.074
LeffS 0.145
0.13 LeffD 0.120 0.118 0.092
LeffS 0.115
0.09 LeffD 0.102 0.106 0.127
LeffS 0.110
The average value of Leffð¼ ½ðLeffD þ LeffSÞ=2�Þ is estimated. The
normalized standard deviation of DLeffð¼ ðLeffD 2 LeffSÞ=LmaskÞ was also
estimated over the wafer.
A. Uddin, T.Y. Siong / Microelectronics Journal 35 (2004) 641–645644
range, Lieff is calculated from Eq. (2), i.e.
Lieff ¼
Loeff
krldmin
¼Lo
mask
krldmin
ð3Þ
The symbols of Leff measurement at drain and source sides
are represented by LeffD and LeffS; respectively. The average
value of Leffð¼ ½ðLeffD þ LeffSÞ=2�Þ was measured for all
transistors and is recorded in Table 3. The standard
deviation of normalized DLeffð¼ ðLeffD 2 LeffSÞ=LmaskÞ is
also recorded in Table 3 for all transistors. The 0.18 mm size
transistor has the lowest standard deviation compared to
0.13 mm and 90 nm, size transistors. It is expected that the
spread of the asymmetric is going to increase for smaller
size transistors. The channel length is needed to better
control for the short channel transistors by the advanced
lithography techniques.
4. Conclusion
The effect of channel length on asymmetrical of drain
and source were investigated. The standard deviation of
threshold voltages Vto and Vtlin are increased for advanced
technologies as channel length becomes smaller. The
asymmetry of drain and source is increased for the shorter
channel transistor. Moreover, due to the ‘rounding off
errors’ limitation in Vtlin measurement, statistical variation
of Vto shows the higher confidence level than Vtlin: Effective
channel length ðLeffÞ was determined by using ‘shift and
ratio’ methods. The spread of the drain and source
asymmetric is increased when the standard deviation of
DLeff increases with decrease of channel length. Besides
using gm and CC methods, other measurement methods such
as linear extraction (LE) method, square root extraction
(SRE) method, transconductance change (TC) method, etc.
are also needed to measure the threshold voltage that would
provide a widespread and accuracy prediction of the effect
of drain and source asymmetric upon advanced technology.
Acknowledgements
The authors would like to acknowledge Chartered
Semiconductor Manufacturing (CSM) for supplying wafers
with devices. We would also like to thanks Dr Lap Chan and
Mr Tee Kheng Chok, CSM for their help in this work.
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