inp bipolar transistors: high speed circuits and manufacturable submicron fabrication processes...
TRANSCRIPT
InP Bipolar Transistors: High Speed Circuits and Manufacturable Submicron Fabrication Processes
[email protected] 805-893-3244, 805-893-5705 fax
2003 European GaAs IC Conference, Munich, October
M. Rodwell, D. Scott, M. Urteaga, M. Dahlström, Z. Griffith, Y. Wei, N. Parthasarathy, Y-M Kim,
University of California, Santa Barbara
M. Urteaga, R. Pierson , P. Rowell, B. BrarRockwell Scientific Company
Applications of InP HBTs
Optical Fiber Transceivers
40 Gb/s:InP and SiGe HBT both feasible ICs now available; market has vanished
80 & 160 Gb/s may come in timewithin feasibility for scaled InP HBT
mmWave Transmission
65-80 GHz, 120-160 GHz, 220-300 GHz LinksLow atmospheric attenuation (weather permitting).High antenna gains (short wavelengths).
10 Gb/s transmission over 500 meters with 20 cm antennas needs 4 mW transmitter power
Mixed-Signal ICs for Military Radar/Comms
direct digital frequency synthesis, ADCs, DACshigh resolution at very high bandwidths sought
Motivation for InP HBTs
Parameter InP/InGaAs Si/SiGe benefit (simplified) collector electron velocity 3E7 cm/s 1E7 cm/s lower c , higher Jbase electron diffusivity 40 cm2/s ~2-4 cm2/s lower b
base sheet resistivity 500 Ohm 5000 Ohm lower Rbb
comparable breakdown fields
Consequences, if comparable scaling & parasitic reduction: ~3:1 higher bandwidth at a given scaling generation~3:1 higher breakdown at a given bandwidth
Problem for InP: SiGe has much better scaling & parasitic reduction
Technology comparison today:Production SiGe and InP have comparable speedSiGe has much higher integration scales
Our Present Efforts Development of low-parasitic, highly-scaled, high-yield fabrication processes
Scaling
key device parameter required change
collector depletion layer thickness decrease 2:1
base thickness decrease 0.707:1
emitter junction width decrease 4:1
collector junction width decrease 4:1
emitter resistance per unit emitter area decrease 4:1
current density increase 4:1
base contact resistivity (if contacts lie above collector junction)
decrease 4:1
base contact resistivity (if contacts do not lie above collector junction)
unchanged
Required transistor design changes required to double transistor bandwidth
…easily derived from geometry / resistivity / velocity relationships
WE
WBC
WEB
x
L E
base
emitter
base
collector
WC
(C ’s, ’s, C/I ’s all reduced 2:1)
Optical Transmitters / Receivers are Mixed-Signal ICs
TIA: small-signal
aa
routebuffer
SwitchWideband Optical Transceiver
clockPLL
AD
DMUX
O/E, E/O interfaces
MUX
AD
AD
IQ
I
Q
DMUX
DMUX
mm-wave interfaces
I
Q
DA
DA
IQ
electronicor optical
Wideband mm-Wave Transceiver
Electronics for GigaHertz Communication
poweramplifier
MUX
addressdetect
PLL
Switches:network protocols,digital control, fast ICs,optical, electronic switches
Rf
Rc
Q1
Q2
I1
I2
Rf
Rc
Q1
Q2
I1
I2
LIA: often limiting MUX/CMU & DMUX/CDR:mostly digital
Small-signal cutoff frequencies (f, fmax) are ~ predictive of analog speed
Limiting and digital speed much more strongly determined by I/C ratios
Design HBTs for low gate delay, not for high f & fmax !
clock clock clock clock
inin
out
out
cexLOGIC
LOGIC
Ccb
becbi
becbC
LOGIC
IRq
kTV
V
IR
CCR
CCI
V
4
leastat bemust swing logic The
resistance base the through
charge stored
collector base Supplying
resistance base the through
charging ecapacitanc on Depleti
swing logic the through
charging ecapacitanc on Depleti
:by ermined Delay DetGate
bb
depletion,bb
depletion,
JVR
v
T
A
A
V
V
I
VC
T)V(VvεJ
CI
CCIV
f
ex
electron
C
CE
LOGIC
C
LOGICcb
cceceelectronKirk
cbC
becbCLOGIC
cb
highat low for low very bemust
22
/2
objective. design key HBTa is / High
total.of 80%-55% is
withcorrelated not well Delay
delay; totalof 25%-10y typicall)(
logic
emitter
collector
min,
2depletion full,operating ,max,
depl,
Scaling Laws, Collector Current Density, Ccb charging time
Collector Field Collapse (Kirk Effect)
Collector Depletion Layer Collapse
)2/)(/( 2 cdsatcb TqNvJV
)2/)(( 2min, cTqNV dcb
0 mA/m2
10 mA/m2
0 mA/m2
10 mA/m2
GaAsSb base InGaAs base
Collector capacitance charging time is reduced by thinning the collector while increasing current
sat
C
CECE
LOGICCLOGICcCLOGICcb v
T
A
A
VV
VIVTAIVC
2/
emitter
collector
min,collector
2min,max /)2(2 ccbcbsat TVVvJ
Technology Roadmaps for 40 / 80 / 160 Gb/s
Loss of yield at small dimensions
Scaling Challenges:
progressively harder to obtain; alternative is to decouple base & collector dimensions
progressively harder to obtain
heating, thermal resistance
decreasing breakdown
emitt
erba
seco
llect
or
key figures of merit for logic speed
Deep Submicron Bipolar Transistors for 140-220 GHz Amplification
0
10
20
30
40
10 100 1000
Tra
nsi
sto
r G
ain
s, d
B
Frequency, GHz
U
U
MSG/MAG
H21
unbounded U
-4
-2
0
2
4
6
8
140 150 160 170 180 190 200 210 220
S21
, dB
Frequency, GHz
1-transistor amplifier: 6.3dB @ 175 GHz
-30
-20
-10
0
10
140 150 160 170 180 190 200 210 220
gai
n, d
B
Frequency (GHz)
3-transistor amplifier: 8 dB @ 195 GHz
raw 0.3 m transistor: high power gain @ 200 GHz
InP-collector DHBTs: Self-Aligned Mesa Structure M Dahlström (UCSB/ONR); Fang,Lubyshev, Fastenau,. Liu (IQE)
200 nm InP collector, 30 nm InGaAs base8(1019) /cm3 base doping
1 m base contacts, 0.5 m x 7.5 m emitter junction0.7 m emitter contact
Vce=1.7 V J=3.7E5 A/cm2
0
5
10
15
20
25
30
1010 1011 1012
Ga
ins
(dB
)
Frequency (Hz)
ft=282 GHz
fmax
>400 GHz
U
H21
0
1
2
3
4
5
0 0.5 1 1.5 2 2.5 3
I C (
mA
)
VCE
(V)
emitter junction area: 0.44 m x 7.4 mIB step = 50 uA
0
0.5
1
1.5
2
2.5
3
0 1 2 3 4 5 6 7 8
Vbr,ceo=7 V
Collector / Emitter Ratio: 2.0 um / 0.5 um, 1.2 um / 0.5 um
0.7 um base contact width 0.5 um base contact width
InP DHBTs: 150 nm collector, 30 nm base
0
5
10
15
20
25
30
1010 1011 1012
Ga
ins
(dB
)
Frequency (Hz)
ft= 370 GHz
fmax
=375 GHzU
H21
MAG/MSG
0
2
4
6
8
10
0 0.5 1 1.5 2 2.5 3 3.5
J e (mA
/m
2 )
Vce
(V)
Ajbe
=0.6 x 7 m2 Ib step=0.4 mA
0
2
4
6
8
10
0 2 4 6 8 10
Ccb
/Ae (
fF/u
m2 )
Je=I
c /A
e, current density (mA/um2)
0.0 V
-0.2 V
Vcb
= -0.3 V
+0.3 V
+0.5 V
Thickness (Å) Material Doping cm-3 Description 400 In0.53Ga0.47 As 3E19 : Si Emitter Cap 800 InP 3E19 : Si Emitter 100 InP 8E17 : Si Emitter 300 InP 3E17 : Si Emitter
300 InGaAs 8E19-5E19:C Base 200 In0.53Ga0.47 As 3E16:Si Setback 240 InGaAlAs 3E16 : Si Base-Collector Grade 30 InP 3.0E18 : Si Delta doping 1000 InP 3E16 : Si Collector 250 InP 1.5E19:Si Sub Collector 125 In0.53Ga0.47 As 2E19 : Si Sub Collector 3000 InP 2E19 : Si Sub Collector Substrate SI : InP
Ccb/Ic 0.26 ps/V
3 nm InGaAs base: 8*1019/cm3→5*1019/cm3 15 nm InP collector 0.6 x 7 m emitter 0.5 m base contacts
base: 603 /squarebase contacts: 20 -m2
emitter contacts: 15 -m2
Dahlström, Griffith(UCSB/ONR); Fang,Lubyshev, Fastenau, Liu (IQE)
Mesa DHBT with 0.6 m emitter width, 0.5 m base contact widthZ. Griffith, M Dahlström
75 GHz, 80 mW Power Amplifier
2.6 pS17
0.31 pS17
0.15 pS42
2.3 pS42
0.38 pS50
0.38 pS50 0.58 pS
37
0.58 pS37
CSiN=92fF
CSiN=92fF
CSiN=44fF
CSiN=44fF
CSiN=15fF
CSiN=15fF
0.4 0.9 mm die, AE = 16 x (1m x 16 m) = 256 m2
transferred-substrate process
Bias: Ic=130 mA, Vce=4.5 V
0
5
10
15
20
0
2
4
6
8
10
-5 0 5 10 15
Po
ut (
dBm
) Gain
(dB)
PA
E (%
)
Pin (dBm)
Gain
PAE
Pout
Y. Wei
250-500 mW is feasible; UCSB designs are constrained by yield difficulties with large # of fingers
87 GHz HBT static frequency divider
InAlAs /InGaAs/InP MESA DHBT
400 Å base, 2000 Å collector,
9 V BVCEO
200 GHz ft, 180 GHz fmax
2.5 x 105 A/cm2 operation
PK Sundararajan
-0.2
-0.18
-0.16
-0.14
-0.12
-0.1
-0.08
-0.06
22 22.02 22.04 22.06 22.08 22.1 22.12 22.14
87 GHz input, 43.5 GHz output
Vo
ut (
Vol
ts)
time (nsec)
We are now designing for 150 GHz...
8 GHz ADC
Technology0.7 um InP MESA DHBT 400 Å base, 2000 Å collector, 9 V BVCEO, 200 GHz ft, 180 GHz fmax2.5 x 105 A/cm2 operation
UCSB/ONR PK Sundararajan
975 kHz FFT bin size8 GHz clock rate65.5 MHz signal64:1 oversampling ratio
Designsimple 2nd-order gm-C topologycomparator is 87 GHz MSS latchintegration by capacitive loads 3-stage comparator, RTZ gated DAC
Results133 dB (1 Hz) SNR at 74 MHzequivalent to ~8.8 bits at 200 MS/s
DINP
DINN
DOUTP
DOUTN
Vcc
Vcc
Vxpp
Vxpn
cell-1 cell-n cell-10
TISDA
TAS TAS
OC-768 Modulator Driver
30 dB gain, 40 GHz bandwidth, >10 dB S11 & S22
8 ps rise/fall (20-80%) , ~0.9 ps RMS jitter 3 Vpp single ended output, 6 V differential
Design Issues: Gain flatnessDistributed line losses, current handling & loaded Z0
Complexity of transmission-line layoutAssociated low-frequency droopEmitter follower negative resistance → peakingEfficacy of bypass capacitancesCommon-mode traveling-wave instability
K. Krishnamurti et al
InP HBT limits to yield: non-planar process
Emitter contact
Etch to base
Liftoff base metal
Failure modes
Yield quickly degrades as emitters arescaled to submicron dimensions
base contact
emittercontact
base contact
S.I. substrate
base
sub collector
S.I. substrate
base
sub collector
S.I. substrate
base
sub collector
emitter
S.I. substrate
base
sub collector
Emitter planarization, interconnects
base contact
liftoff failure:emitter-baseshort-circuit
S.I. substrate
base
sub collector
base contact
excessiveemitter undercut
S.I. substrate
base
sub collector
S.I. substrate
base
sub collector
planarization failure: interconnect breaks
Parasitic Reduction
SiO2 SiO2
P base
N+ subcollector
N-
thick extrinsic base : low resistancethin intrinsic base: low transit time
wide emitter contact: low resistancenarrow emitter junction: scaling (low Rbb/Ae)
wide base contacts: low resistancenarrow collector junction: low capacitance
At a given scaling generation, intelligent choice of device geometry reduces extrinsic parasitics
Much more fully developed in Si…
High current density 10 mA/m2
T-shaped polysilicon emitter 0.25 m junction wide contact low resistance, high yield
Thin intrinsic base: low b
Thick extrinsic base: low Rbb
Low Ccb collector junction collector pedestal CVD/CMP SiO2 planarization regrown poly extrinsic base
High-yield, planar processing high levels of integration LSI and VLSI capabilities
SiGe clock rates up to 65 GHzMuch more complex ICs than feasible in InP HBTInP HBT must reach higher integration scales or will cease to compete
Very strong features of SiGe-bipolar transistors
ManufacturableDeep SubmicronInP HBTs
Objective: speed extrinsic parasitic reductiondeep submicron scaling
Objective: yieldplanar processeliminate liftoffeliminate undercut etches
Target Applications: High speed (100-200 GHz clock)
digital & mixed signal. 160 Gb/s optical fiber transmission
Polycrystalline-Emitter (SiGe-like) HBT
Planar HBT: Dielectric Sidewall Process
N- collector
N+ subcollector
S.I. substrate
intrinsic base
extrinsic basebase contact
Si3
N4
regrown emitter *emitter contact
collector contact
N+ collectorpedestalimplant
implant ortrench isolation
N- collector
N+ subcollector
S.I. substrate
emitter-base separationby dielectric sidewall
sputter & dry-etchedW emitter contact,dry-etched emitter
Urteaga & Rodwell UCSB; Urteaga, Pierson, Rowell & Brar RSCNguyen & Nguyen, GCS
Submicron Sidewall-Spacer (S3) Process
N- collector
N+ subcollector
S.I. substrate
1) Epitaxial Growth 2) Sputter & etch tallPd/W emitter contact,dry etch emitter,form emitter sidewalls
Si3
N4
baseemitter
N- collector
N+ subcollector
S.I. substrate
baseemitter
3) trench isolationsputter base Ohmic metal
N- collector
N+ subcollector
S.I. substrate
4) Polymer planarize & etch back,etch base contact metal
N- collector
N+ subcollector
S.I. substrate
5) Strip polymer, etch basemetal and base
N- collector
N+ subcollector
S.I. substrate
6) Recess etch and depositcollector contact
N- collector
N+ subcollector
S.I. substrate
collectorcontact
isolationtrenchemitter
junction
basecontact
mesa
S3 InP Emitter: Focused-Ion-Beam Images Urteaga, Rodwell , Pierson, Rowell , Brar, Nguyen, Nguyen: UCSB, RSC, GCS
em
itte
r
ba
se
ba
se
co
lle
cto
r
co
lle
cto
r
sidewall
sidewall
W basecontact
emittermetal
emitter
base
S3 HBT: DC Performance
S3 HBT with base pad trench
1.00E-11
1.00E-10
1.00E-09
1.00E-08
1.00E-07
1.00E-06
1.00E-05
1.00E-04
1.00E-03
1.00E-02
1.00E-01
1.00E+00
0 0.2 0.4 0.6 0.8 1
Vbe (V)
I (A
)
nb= 1.6, nc = 1.0
-2.00
0.00
2.00
4.00
6.00
8.00
10.00
12.00
14.00
16.00
18.00
0.00 0.50 1.00 1.50 2.00 2.50
Vce (V)
Ic (
mA
)
~50
Emitter Area = 0.7 x 6 um2
Low-leakage submicron device: Si3N4 passivation effective base-emitter ledge
Large base ideality factor:due to base-emitter grade design not dielectric passivation
Urteaga, Rodwell , Pierson, Rowell , Brar, Nguyen, Nguyen: UCSB, RSC, GCS
S3 HBT: RF Performance
Emitter Junction
Dimensions
JE
mA/m2
Ft
GHz
Fmax
GHz
Ccb/IE
ps/V
0.4 x 3 m2 6.0 239 142 0.82
0.4 x 6 m2 6.8 257 146 0.66
0.6 x 3 m2 6.7 244 127 0.50
0.6 x 6 m2 6.9 266 133 0.40
Measurements taken at VCB = 0.4 V
Base contact: 0.5 μm on each side of emitterfmax limited by high base contact resistance (now being addressed)
High current operation and low Ccb
Urteaga, Rodwell , Pierson, Rowell , Brar, Nguyen, Nguyen: UCSB, RSC, GCS
Polycrystalline-extrinsic-emitter regrowth InP HBT
Objectives:
Eliminate emitter undercut etch
Eliminate base-emitter metal liftoff
Flared emitter → low resistance
Thick, ~2E20-doped extrinsic base → low resistance → tolerant of contact metal migration
Thin, ~3E19-doped intrinsic base → low transit time → high current gain (less Auger recombination)
Polycrystalline InAs -has low resistivity (2.5:1 higher than 1019 /cm3 lattice-matched InGaAs)
-can play same role in InP as the polysilicon emitter in Si/SiGe
N- collector
N+ subcollector
S.I. substrate
intrinsic base
extrinsic basebase contact
Si3
N4
regrown emitter *emitter contact
collector contact
N+ collectorpedestalimplant
*monocrystalline wheregrown on semiconductor,polycrystalline wheregrown on silicon nitride
D. Scott, Y. Wei
Poly-extrinsic -emitter regrowthInP HBT
Dennis Scott, Yun Wei: UCSB
N- collector
N+ subcollector
S.I. substrate
1) Epitaxial Growth 2) Deposit Ti/W base Ohmics.Encapsulate with Si3N4Etch base-collector junction
base
N- collector
N+ subcollector
S.I. substrate
base
basecontactSi
3N
4
3) Passivate with Si3N4Etch emitter window through baseForm emitter SiN sidewalls
N- collector
N+ subcollector
S.I. substrate
basecontact
Si3N
4
4) Regrow polycrystalline emitter.Deposit emitter metal.Etch through emitter
N- collector
N+ subcollector
S.I. substrate
base contact
Si3N
4
regrownInAlAs/InAsemitter*
*monocrystalline wheregrown on semiconductor,polycrystalline wheregrown on silicon nitride
emitter contact
5) Recess etch and depositcollector contacts
N- collector
N+ subcollector
S.I. substrate
base contact
Si3N
4
regrownInAlAs/InAs emitter*
emitter contact
collector contact
collectorcontact
top view
emitterjunction
extrinsicemitterandcontact
basecontact
D. Scott, Y. Wei
Polycrystalline-extrinsic-emitter regrowth HBT: 0.5 x 8 um device
Base plug
emitter
collectorpolyimide
D. Scott, Y. Wei
0.3 um Intrinsic emitter
Extrinsic emitter
Base contact
Extrinsic Base
Collector contact
device without self-aligned refractory base contacts
Polycrystalline-extrinsic-emitter regrowth HBT: 0.3 x 8 um device
D. Scott, Y. Wei
0
2
4
6
8
10
0 1 2 3 4 5 6 7
J E (
mA
/um2)
VCE
(V)
AE=0.7 um x 8 um
IB_step
=200uA, =15
AE=0.3 um x 4 um
IB_step
=100uA, =20
Polycrystalline-extrinsic-emitter regrowth HBTs
Issues being addressed:leaky base-emitter junctions surface damaged by processbase resistance very high hydrogen passivation of carbon dopingmoderately high emitter resistance
without self-alignedrefractory base contacts
with self-alignedrefractory base contacts
0
5
10
15
20
25
30
0
1
2
3
4
5
6
1 10 100 1000
Gai
n (
dB)
K
Frequency (GHz)
MSG/MAG
U
h21
K
fmax
=140 GHz fT=162 GHz
D. Scott, Y. Wei
Ccb reduction by Collector Pedestal Implant
N+
N+
N- P+
W W
1000Ǻ
2000Ǻ(Cbc)ex(Cbc)ex
The extrinsic base-collector capacitance can be reduced by a factor of three.
Pedestal Ccb reduction can be incorporated into mesa, sidewall, and emitter regrowth processes
2000Ǻ
N+
P--
Si Ion Implantation
N+
2000ǺN+
1) Expitaxial growth, pattern with SiN mask, and
Ion implanted with Si 2) N doped pedestal formed
3) Collector and base regrowth 4) Process for emitter regrowth
1000Ǻ
2000Ǻ
N+
N-P+
P+
N+
Yingda Dong
InP Mesa DHBT with Collector Pedestal Implant Yingda Dong
0.0 0.2 0.4 0.6 0.8 1.0
1E-7
1E-6
1E-5
1E-4
1E-3 AjBE
= 0.5 x 6 µm2
VCB
= 0.3 V
IB, n
B=1.55
IC, n
C=1.28
I (A
)
VBE
(V)0.0 0.5 1.0 1.5 2.0 2.5 3.0
0
2
4
6
8
10
12
14
16
500 mA/µm2
AjBE
= 0.5 x 6 µm2
IB step = 100 µA
I C (
mA
)
VCE
(V)
400 kA/cm2
Present Status:
No increase in junction leakage ...good DC characteristics
Full Ccb reduction not being obtained interfacial charge at regrowth interface ...now being reduced
Indium Phosphide HBTs
Millimeter-Wave Power: InP a leading contender unsurpassed combination of bandwidth and breakdown power amplifiers at 75-110 GHz, 140-220 GHz, & beyond
Mixed-Signal and Fiber ICs: InP struggling to compete with SiGe application demands transistor counts near/beyond yield limits large emitter junctions→ high current → power near acceptable limits speed advantage from materials being squandered by inadequate scaling
Critically needed for InP HBT mixed-signal ICs highly scaled process: 0.2 m emitters, 0.4 m collectors highly planar and high-yield fabrication processes small emitter junctions (0.2 m x 0.5 m) for acceptable power
Present efforts in InP research community low-parasitic, highly-scaled, high-yield fabrication processes → 3:1 higher bandwidth at a given scaling generation → 3:1 higher breakdown at a given bandwidth Substantial risk of failure, substantial benefit if successful.
in case of questions
What HBT parameters determine logic speed ?
exCex
bbcbc
cbdiffcbje
RIqkTVR
RIV
CCC
/4 as effect,indirect strong very has
from 15% ,)( from 15% ,/ from 49%
:imes transit tand sresistanceby DelaysSorting
) (e.g. charging 24%only , charging 42% , charging 16%
:escapacitancby DelaysSorting
logic
logic
Caveats: assumes a specific UCSB InP HBT in development for 250 GHz target clock rate (0.3 um emitter width, 0.6 um wide collector of 150 nm thickness, 300 Å base thickness, 5E5 A/cm^2)
Why isn't base+collector transit time so important ?
1:10~ is which ,/
of ratioby reduced
ecapacitancdiffusion signal-Large
)(
)(Q
:Operation Signal-LargeUnder
swing. voltage/over only ...active
/
)(
)(
)(Q
:ecapacitancDiffusion
base
base
qkT
V
VV
I
I
qkT
VqkT
I
VdV
dI
I
LOGIC
LOGICLOGIC
dccb
Ccb
beCcb
bebe
Ccb
Ccb
Depletion capacitances present over full voltage swing, no large-signal reduction
Vin
Vout
Vin(t)
t
t
Vout(t)
diffusion+ depletioncapacitance
only depletioncapacitance