ICSE2004 Proc. 2004, Kuala Lumpur, Malaysia

A Study On Signature Analyzer For Design For Test (DFT)Abu Khari bin A'ain, Member, IEEE, *Chek T Lim, *Ng, Kok Hong, *Ng, Sheng Kwang, Liew Eng

Yew

Department of Electronics (INSEED)Faculty of Electrical EngineeringUniversiti Teknologi Malaysia

813 10 Skudai, Johor, MALAYSIA

Abstract This paper takes a look at the use oflinear feedback shift registers (LFSR's) as testpattern generators (TPG's) and signatureanalyzers for built-in self-test (BIST). We alsopropose a method to generate pseudorandomtest patterns. The proposed method cangenerate longer sequences of the same set oftest patterns.

Keywords: LFSR, PRBS, BIST, ATPG

I. INTRODUCTION

THE process of testing a digital circuit willconsist of applying successive sets of values tothe primary inputs, and of observing the resultingvalues appearing at the primary outputs. Eachindividual test, consisting of a set of input valuestogether with the corresponding set of correct,fault-free output values, is known as a testpattern or test vector. A complete sequence oftest patterns is called a test set. The centralproblem of testing is the derivation of anadequate test set for any particular circuit. Thisprocess is described as test pattern generation.

Built-in self-test (BIST) denotes theability of a circuit or system to test itself. It canpotentially eliminate the need for external testequipment and introduces the capability fortesting devices after the circuit is integrated in asystem in the field (online testing). BIST isgaining acceptance in the VLSI industry becauseof its many advantages [1]. For BIST in general,test patterns are generated on-chip by a testpattern generator (TPG) and the responses of thecircuit under test (CUT) is compressed andanalyzed by an on-chip signature analyzer.

There are generally three strategies oftesting:

*Chek T Lim, Ng, Kok Hong, Ng, Sheng Kwang are IwithIntel Sdn. Bhd Penang.

* Exhaustive* Deterministic* Pseudorandom

In exhaustive testing, all 2n input combinationsfor an n-input CUT are applied during the testprocess. Exhaustive testing does not face theproblem of random pattern resistant faults, and itachieves 100% stuck-at fault coverage [2].However, test time becomes too long for CUTswith large number of inputs. Test time can bereduced by partitioning the CUT into subcircuitsand then testing each subcircuit exhaustively(pseudoexhaustive method). However, the faultcoverage for pseudoexhaustive testing is lower.

Another category of testing techniques isbased on deterministic test set embedding. Indeterministic test, the circuit under test (CUT) isanalyzed prior to testing to determine theappropriate test set to be applied. After the testset has been obtained, the TPG is designed togenerate the predetennined test set. Varioustechniques have been proposed to obtain the bestseeds and LFSR characteristic polynomials tocover a deterministic test set. However, theseapproaches can only be applied to circuits withsmall size or regular structures due to highcomputational complexity of the searchprocedures [1].

Pseudorandom testing is popular due tothe simplicity of the linear feedback shiftregisters (LFSRs) used as TPGs to generate asubset of the 2n test patterns. Fault coverage isestimated by probabilistic methods. The numberof random patterns to be applied is decided bythe detection probability of the faults [3].

In terms of TPG hardware realization,two opposite architectures with respect to areaoverhead and testing time are the ROM basedarchitectures and the counter-based architectures.The later architecture uses a ROM to store thevectors generated by an external automatic test

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pattern generator (ATPG). High fault coverageand short testing times can be achieved. But thearea overhead introduced by this method is ingeneral prohibitive for practical applications.

In counter-based architectures, the testpatterns are generated by a counter, whichintroduces a small area penalty. The maindisadvantage of this method is that long testsequences may be required to achieve anacceptable fault coverage, which results in longertesting time.

The most used BIST architectures are theLFSR based architectures [4]. For thesearchitectures, good fault coverage can beachieved in most cases and several techniqueshave been proposed to reduce the test time or toincrease the fault coverage of LFSR basedarchitectures.

This paper is organized in the followingway. A brief review on previous architectures ofLFSR based TPG is presented in part II. Theproposed architecture of an LFSR-based TPGthat is used to generate pseodorandom patterns ispresented in part III. Initial experimental resultsare explained in part IV. Future work ishighlighted in part V and conclusion in part VI.

II. PREVIOUS WORK

Wang and McCluskey discussed thetheory of both standard and modular LFSRs. Ahybrid TPG design of standard and modularLFSRs is also proposed. This design is used togenerate maximum length sequences and can bereconfigured to include the all zeros state forexhaustive testing. Compared to the standard ormodular LFSR that uses m 2-input XOR gates,the hybrid design uses only (m+l)/2 XOR gates[5].

Chen and Gupta proposed a TPG designcalled "input reduction". The proposed designpartitions the inputs of a CUT into groups,similar to pseudo-exhaustive testing, where eachgroup corresponds to a test signal. However,unlike pseudo-exhaustive testing, which onlycombines unrelated inputs (inputs that are not inthe same cone) into a test signal, the proposedtechnique analyzes the CUT to determinecompatible inputs to be combined into a testsignal, even if the inputs belong to the same cone[1].

Dufaza and Chevalier presents a TPGdesign composed of a simplified LFSRassociated with an OR network and a set ofmultiplexers, called an LFSROM. The design is

able to generate a precomputed set ofdeterministic test vectors obtained with an ATPGtool [6]. It provides a relatively simple way ofgenerating deterministic test vectors withouthaving to use complex procedures. It is also ableto produce the all-zero's test vector without theneed for additional circuitry (unlike conventionalLFSR). However, the use of LFSROM requiresextra circuitry, especially for the MUX and itsrelated selector circuitry. Once implemented, theset of test patterns produced is fixed andunchangeable except by rewiring the OR gatesnetwork. This means that once embedded in thechip, the test patterns cannot be changed.

Shi and Zhang presents a reseedingtechnique for LFSR-based test patterngeneration, which can generate pseudorandomvectors in normal mode while also being able toproduce the seed of a group of test vectors injumping mode [7].

Wang and Lee present an LFSR-basedTPG that can accelerate the application ofdeterministic patterns from the LFSR to a scanchain. The target scan chain is divided intomultiple sub-chains and an LFSR-based multiplesequence generator is used to generate all thesubsequences required by the sub-chains. Ageneralized relationship between the bits in theoriginal scan chain and the state of the LFSR isderived such that the bits generated by an LFSRin any future clock cycle can be pre-generated bythe proposed TPG [8].

III. PROPOSED ARCHITECTURE

Rn-I Rn2 RIR1Fig. 1 Generic block diagram of proposed TPG

structure.

The proposed TPG structure is presentedin Figure 1. The structure is based on that of aconventional LFSR signature analyzer. The TPGoperates on two clock signals; one is the normalclock for the LFSR registers and another clocksignal, which is connected to the input D(X). The

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D(X) clock is set at a lower frequency from theregister clock.

One characteristic of this TPG structureis that it can generate longer sequences of thesame set of pseudorandom test pattems. A TPGwith an n stage LFSR can generate a maximumset of 2" _ 1 number of test vectors. Inconventional LFSR TPGs, this set of test vectorswill then produces a maximum sequence lengthof 2" - 1 patteins, before the sequence repeatsitself. In the proposed TPG, this maximumlength sequence can be extended to beyond 2" -1patterns with the manipulation of the D(X) clock.The total number of test vectors is still amaximum of 2" -1, but there will be a duplicateof certain vectors within the same sequence.Table I shows an example of the simulatedsequence generated by a conventional LFSR ascompared to the proposed TPG.

LFSR Conventional Proposed TPGclockc LFSR sequence sequence, t-2

Q2QxQo Q2QIQo

100

2-3

67 1 0 0

-8 -- 1-10- 1

10 01 111 I101123 -0 10_14 ~ ~~100 10015 1 10 01016 1 1 1 01117 011 10118 1 0 1 1 1 019 010 I 1 120 0 0 1 1 1 121 1 0 0 0 1 122 1 10 00123 I 1 1 10024 0 1 1 0 1 025 1 0 1 0 0 126 0 1 0 0 0 027 001 000

The test patterns in Table I are generatedby a TPG using a standard LFSR with acharacteristic polynomial of X3+X2+1 and aseed value of Q2QlQo = 100. The frequency ofthe D(X) clock is half of the register clock (f= 1/2or t =2).

From the table, we see that the maximumlength sequence of the conventional LFSR is 7vectors. For the proposed TPG, the sequenceextends to a total of 14 vectors before thesequence repeats itself.

Another thing to note is that theproposed TPG is able to generate the all zerosstate autonomously and is not stuck in the allzeros state.

IV. PRELIMINARY RESULTS

Preliminary testing has revealed arelationship between the register/D(X) clockratio and the maximum length of the sequencegenerated by the proposed TPG.

Taking the frequency of the registerclock as f; and the frequency of the D(X) clockasfDm, the ratio ofthe two clocks is r =fJIfDm.

Table 2 shows some different values of rand their corresponding sequence lengths, whichwere obtained through simulation. In thisexample, the LFSR used has the characteristicpolynomial ofX3+X2+1 with a maximum lengthsequence of 7.

R Sequence lengthConventional LFSR 7

2 143 214 285 356 - 427 148 5610 7014 1421 2128 28

Table 2: Different values ofr and their respectivesequence lengths

Preliminary results suggest that forvalues of r that is not multiples of 7 (themaximum length of a conventional sequence),the corresponding sequence length is a multipleof r and 7, which is the length of theconventional sequence. For r - 7, the sequence

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Table 1 Maximum length sequences generatedby TPG

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length is 14, while for r that is multiples of 7, thesequence length is equals to r. Though thenumber of test sequence is higher, it comes at thecost of testing speed which is now slower.

While the proposed TPG is capable ofcycling through the all zeros state, it does haveits own trivial sequences which will cause it tobe "stuck" in a similar manner that aconventional LFSR is stuck at the all zero state.

The occurrence ofthese trivial sequencesis on condition of certain initial states at differentvalues of r. Figure 2 shows the state diagram ofan LFSR to illustrate how this can happen.

r=3

r=4

Fig 4 Trivial sequences at differentFig 2 State diagram of LFSR with values of r

characteristic polynomial X3 + X2+ 1

If the initial state of the LFSR is Q2QIQo= 101, and at the first register clock, the input atD(X) is 0, then the next LFSR state will beQ2QIQo = 010. If at the next register clock theinput at D(X) is 1, then the LFSR will switchback to 101. Subsequently, an alternating streamof O's and l's will cause the LFSR to be stuckwithin these two states.

For an r of 2 (D(X) frequency is half ofregister clock frequency), the input at D(X) iseffectively an alternating stream of O's and l's,as shown in Figure 3 below.

Register cik

DX a X0 0 0

Fig 3 Positive edge register clock with D(X)clock at half frequency

The TPG operating at different values ofr will have different sets of trivial sequences,some of which is shown in Figure 4.

V. FURTHER WORK

Further work on this proposed TPG willinvolve further testing using different lengths ofLFSRs. LFSRs with non-primitive polynomialswill also be tried out.

At present, the D(X) uses symmetricalclock signals as input. In future, the input atD(X) will be tried out with asymmetrical inputsignals to observe their effects on the LFSRoutput.

The occurrence of trivial sequencesshould also be looked into. Seed values that willcause trivial sequences should be identified sothat they will be avoided.

Towards the end, the performance of theTPG will be evaluated by testing it onbenchmark circuits.

VI. CONCLUSION

TPG methods, which can generate longersequences of test patterns, have been proposed.This TPG architecture is derived from an LFSRbased signature analyzer, by manipulating theinput of the analyzer. Preliminary results haveshown a relationship between frequencies of the

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LFSR register clock and the input signal to theanalyzer.

ACKNOWLEDGEMENT

Thank you to Intel Penang for providing researchfund and professional guidance.

REFERENCES

[1] C.-A. Chen and S.K. Gupta, "A methodologyto design efficient test pattern generators",Proceedings of International Test Conference,pp. 814- 823 (1995)[2] I. Hamzaoglu, J.H. Patel, "Reducing testapplication time for Built-in-Self-Test testpattern generators", VLSI Test Symposium, 2000.Proceedings. 18th IEEE, pp. 369-375 (2000)[3] B. Vasudevan, D.E. Ross, M. Gala and K.L.Watson, "LFSR based deterministic hardware forat-speed BIST", Digest of Papers, EleventhAnnual 1993 IEEE VLSI Test Symposium, pp.201 -207 (1993)[4] P. Flores, H. Neto, K. Chakrabarty and J.Marques-Silva, "Test Pattern Generation For

Width Compression in BIST", Proceedings ofthe 1999 IEEE International Symposium onCircuits and Systems, 1999. ISCAS '99, Volume:1, pp. 114 -118 vol.1 (1999)[51 L.-T. Wang and E.J. McCluskey, "Hybriddesigns generating maximum-length sequences",IEEE Transactions on Computer-Aided Designof Integrated Circuits and Systems, Volume:7, Issue: 1 pp. 91 - 99 (1988)[6] C. Dufaza and C. Chevalier, "LFSROMBasic Principle and BIST Application", DesignAutomation, 1993, with the European Event inASIC Design. Proceedings. [4th] EuropeanConference on; pp 211 -216 (1993)[7] Y. Shi and Z.Zhang, "Multiple Test SetGeneration Method for LFSR-Based BIST",Proceedings of the ASP-DAC 2003. Asia andSouth Pacific Design Automation Conference,2003, pp. 863 -868 (2003)[8] W.L. Wang and K.J Lee, "Accelerated TestPattern Generators for Mixed-Mode BISTEnvironments", Proceedings of the Ninth AsianTest Symposium 2000 (ATS 2000), pp. 368 - 373(2000)

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