substrate wiring density: end of project report

This document and its content are copyright of iNEMI - © iNEMI 2013.

All rights reserved.

Substrate Wiring Density: End of Project Report

1This document and its content are copyright of iNEMI - © iNEMI 2013.


Wiring Density Project - Survey

• The first phase has been to conduct an industry survey

on current wiring density, design rule capabilities and

future requirements.

• The major goal of this phase was to get industry

feedback on which substrate design features should be

included in a roadmap in order to accurately represent

future wiring density needs from the perspective of :

– Material Set

– Low Cost Lithography/Laser

– Plating

– Inspection/Test



Survey Methodology

• The iNEMI Substrate Wiring Density Team developed a survey

in order to understand questions about substrate design

features and gaps in knowledge. The information gathered will

be used to define and prioritize project activities to address

some of the most critical technology barriers.

• The survey format was designed to provide separate groups

of questions, each targeted to specific parts of the industry

supply chain. Participants were asked to select the categories

that best described their own job responsibilities and the

survey then guided them through the set(s) of questions that

applied to the relevant supply chain segment(s).

• The survey responses were received by end of Q3 2011.

Surveyed companies included both iNEMI member companies

and non-member companies.



Survey Questionnaires

The categories of questions included:

1) Driving Forces for higher dense package and

configuration,

2) Devices requiring high density substrates,

3) Capability and future anticipated needs for Flip chip

pad pitch, Line Space per dielectric thickness, Via

diameter and Aspect ratio,

4) Materials for Dielectrics,

5) Process technologies for Photoresist exposure, Blind

Via and Buried Via formation, Copper Plating

6) Layer to layer alignment of dielectrics / solder masks.



Respondent Distribution - Supply Chain

Representative of full supply chain : Included 32 OEM/ODM/EMS, 5 Equipment

Suppliers, 10 Materials Suppliers, 11 Package Assembly houses, 13 Semiconductor

Suppliers and 20 Substrate Suppliers.

22%

11%

11%

11%

11%

9%

7%

4%

2%

Semiconductor Assembly OEM ComputerOEM Telecommunications Substrate EMSMaterial and Chemical OEM Medical ConsultantEquipment OEM Electronic Products OEM Military



Respondent Distribution - Geography

The 91 companies responding to the survey were from all major geographic regions:

North America (51 companies), Asia (33 companies) and Europe (7 companies).

57%

11%

11%

3%

1%1% 1% 1%

USA Japan Taiwan Canada Korea

UK China France Hong Kong India

Singapore South Korea Switzerland Thailand



The impact of Si architecture on wiring density



What is the minimum flip chip die pad pitch for the

following time frames?

174

160

133

125

146

116

101

93

80

100

120

140

160

180

200

2011 2014 2017 2020

OEM

Eqpt-Mat-Chem

mm



In 2014, for trace lengths greater than 12 mm, what do you think will be the minimum line

and space widths for each metal thickness?

9

11

15

25

10

12

17

27

0

5

10

15

20

25

30

<4μm 4-10μm 11-17μm >17μm

LW (µm)

SW (µm)

10

12

14

25

10

12

15

26

0

5

10

15

20

25

30

<4μm 4-10μm 11-17μm >17μm

LW (µm)

SW (µm)

In 2014, for trace lengths 12 mm or

less, what do you think will be the

minimum line and space widths for

each metal thickness?

Global routing Escape routing

Trace ThicknessTrace Thickness



What are the factors that determine the design rules for

packaging substrates?

System design19%

Die I/O density25%

Minimum die pad pitch18%

Footprint associated with the

minimum pitch12%

Core voltage or ground region of

the footprint6%

Cost (i.e. cost per I/O or other cost

metric)9%Physical Form

Factor9%

Other2%



The impact of package

architecture on wiring density



Accommodating single die I/O layout

29%

Accommodating 3D packaging

13%

Limitations on maximum build-up

layer count12%

Opportunity for reduction in number

layers13%

Reducing substrate footprint

15%

Accommodating multiple

die/component interconnect

11%Limitations on

substrate thickness5%

Other2%

What is the main driving force for increased wiring density?



What are the factors that determine the design rules for packaging

substrates?

System design19%

Die I/O density25%

Minimum die pad pitch18%

Footprint associated with the

minimum pitch12%

Core voltage or ground region of

the footprint6%

Cost (i.e. cost per I/O or other cost

metric)9%Physical Form

Factor9%

Other2%



Conclusions

• Cost complexity and wiring density tradeoff / constraints observed

• Die I/O density is king: When the number of die increases either in PoP, MCM or SDP, the number of I/O increases and driving higher wiring density

• 3D packaging may be a stress reliever for Die I/O, but this was not very clear from the responses that that were received

• Industry sectors did not agree about which had the highest wiring density. This could be due to visibility constraints of individual sectors

• Mobile/handheld device industry is leaning more to size reduction (number of layers and body size), while other industry segments may not be as sensitive to package size reduction. However, in all industries the trend is that I/O density is increasing



The impact of substrate process

capability on wiring density



What is the minimum flip chip die pad pitch you will have using the

following attachment methods?

156

133

115

94

110

8992

82

138

123

110

97

117

110

100

90

4540

3530

140

120

100

90

0

20

40

60

80

100

120

140

160

180

2011 2014 2017 2020

Solder bump on die

Solder-tipped copper column on die

Solder paste on substrate

Conductive adhesive on substrate

Microweld

Copper pillar with solder cap



What is the current and anticipated photoresist resolution (L/S)

capability for the following time frames and resist thicknesses?

54

32

10

86

6

15

11

99

21

17

1514

0

5

10

15

20

25

2011 2014 2017 2020

Ph

oto

res

ist

Res

olu

tio

n

Year

Average Photoresist Resolution vs Year for Different Resist Thicknesses

<5µm

5-10µm

11-20µm

>20µm

Resist

Thickness



What limits the maximum manufacturable layer count?

(Substrate Suppliers)

Yield40%

Reliability19%

Cost relative to competing

technologies28%

Throughput12%Other

1%



Options for Increased Wiring

Density



Identified options to increase wiring density

• Finer lines

•Additional layers

•Smaller via capture pad size giving larger channels for

routing

– Smaller vias

– Better alignment, allowing smaller pads

•Alternative methods

– Die embedding



Based on your company's technology roadmap, what do you consider

the most practical way to increase substrate wiring density?

By increasing build-up layer

count28%

By decreasing Line and Space

width65%

Other7%



Is a smaller line width a more preferred method to increase track

density over a reduction in via capture pad diameter?

Yes43%

No57%



Would an increased alignment accuracy provide enough shrinkage of the

internal via capture pad diameter leading to more space for additional tracks?

Yes86%

No14%



Which of the two options (alignment accuracy vs. smaller line width)

do you consider to be most important?

Increased alignment accuracy allowing

shrinkage of via capture pad

diameter62%

Smaller line widths to

accommodate

higher track density

38%



Summary Options for Increased Wiring Density

The preferred options to increased wiring density are in order:

1) Shrink via capture pad

2) Decrease L/S size and pitch

3) Adding layers

Alternative methods ranked below the three preferred options:

• Embedding die technology

• Novel routing schemes

• Improving die and package design (co-optimization)

• Higher speed, inter-chip communication protocols, to reduce signal trace count

• Silicon and glass interposers (more stable materials)



Technology Gap Analysis



Gap Analysis - Areas Covered

• Limiting factors for line space dimension reduction

– Dielectric Treatment

– Circuit Imaging

– Layer to Layer Alignment

– Copper Electroplating

– Final Finishes

– Process Control



What currently limits further reduction in line and space dimensions?

Vendor available equipment, material

or chemicals29%

Dielectric properties13%

Line adhesion13%

Surface roughness12%

In-house equipment availability

11%

Clean room availability

10%

Current carrying capacity

9%

Other 3%



In terms of dielectric treatment (pre-metallization) what do you see as

the critical steps required to meet the wiring density challenge?

Improvements to existing substrate

dielectric materials26%

Improvements to existing dielectric

treatment technology, for

example, desmear21%

Development of new or disruptive

substrate dielectric materials

32%

CTE / roughness / dielectric

improvement i.e. unreinforced …


dielectric treatment technology

20%

Other1%

i.e. Chemical bonding rather

thanroughness to

give smoother interfaces



In terms of circuitry imaging, what do you see as the critical steps

required to meet the wiring density challenge?

Improvements to existing dielectric

coplanarity

(thickness variation) and

warpage

24%

Improvements in chemical

treatment

(adhesion promotion)

21%

Improvements to existing imaging materials (film)

19%

Improvements to existing imaging

equipment

16%


imaging

technology18%

Other (explain below)

2%



In terms of copper electroplating, what are the critical steps required

to meet the wiring density challenge?

Improvements to existing copper plating

chemical processes22%

Improvements to existing copper plating

equipment24%

Improvements to existing materials used

for Semi-Additive Process (SAP) copper

plating, i.e, photoresist, dielectric

materials, etc.30%

Development of new or disruptive process

methods21%

Other3%



In terms of finishes, what are the critical steps required to meet the

wiring density challenge?

Improvements to existing final finish process chemistry

27%

Improvements to existing final finish process equipment

16%

Improvements to existing materials used

in connection with final finishes

25%

Development of new or disruptive process

methods31%

Other1%



In terms of process control, where is the greatest need with respect to

current substrate fabrication processing?

Build-up layer application

25%

Circuitry imaging21%

Dielectric treatment

12%Dielectric

metallization13%

Copper electroplating

13%

Final finishing6%

Solder mask8%

Other 2%



Summary Gap Analysis

While technology exists to meet the roadmap, the indication is that the technology is

currently not cost efficient

– Seems that the industry in several areas is approaching the point where current

technology/equipment starts to be too costly if requirements are tightened further

• Industry needs new and novel technologies that are cost efficient

• Holistic analysis is at least needed to optimize current approaches and in some cases drive

disruptive/new technology

– Organic substrate market is very cost sensitive, limiting interest in taking large

technology risks or making large investments in development. This may slow

down development, unless additional “push” is received through new customer

requirements

Current process steps that require most attention and affect yield most are:

– Build-up layer application

• Layer to layer registration, yield issues with multiple layers

– Circuit imaging

• Likely a yield killer today to go to smaller L/S



Summary Gap Analysis

• Decreasing capture pad size track

– Layer to layer alignment

• Improve both via formation and imaging tool

– Introduce new imaging technology

» For example: LDI with flexible alignment capability

– Co-optimize via formation tool and imaging tool

– Via size

• Thinner dielectric

• New interconnect approach

– There is some work on vertical interconnects that do not use plated vias

• New disruptive plating technology

• Moving away from CO2 laser to new laser drilling technology that gives smaller

features

– For example: pico-laser

• Finer L/S track

– Holistic approach judged to be the best way forward, including:

• More planar dielectrics

• Better chemical treatments (adhesion)

• Improved photoresists that support finer resolution and still have good

adhesion

• Improvements to imaging technology



Closing Comments

• An holistic optimization or approach is likely

necessary as no single step is deemed the most

critical by the surveyed sectors

• Industry sectors need to work together to

enable finer bump pitch and higher substrate

wiring density

• Looking for light at end of the tunnel



www.inemi.orgEmail contacts:

Mark Schaffer

[email protected]

substrate wiring density: end of project report

Documents