ASYNC Symposium, May 20091

Synthesis of multiple railSynthesis of multiple railphase encoding circuitsphase encoding circuits

Andrey Mokhov, Crescenzo D’Alessandro, Alex Yakovlev

Microelectronics System Design Group, School of EECE, Newcastle University, UK

{andrey.mokhov, crescenzo.dalessandro, alex.yakovlev} @ ncl.ac.uk

ASYNC Symposium, May 20092

Outline

Phase encoding Conditional partial order graphs Circuit synthesis

Phase detector Matrix phase encoder One hot phase encoder Binary phase encoder

Conclusions and future work

Outline

ASYNC Symposium, May 20093Phase encoding

Phase encoding• Self-synchronous data communication protocol introduced

by D'Alessandro et al [ PATMOS’05 ]PATMOS’05 ] Reliability to single event upsets High information capacity No scalable implementations of multiple rail controllers

‘abdc’ symbol

4-wire channel: 4! = 24 symbols > 24 = 16 binary symbols

log(n!) ≈ n·log(n)

sensitiveinterval

ASYNC Symposium, May 20094Phase encoding

Specification and synthesis of phase encoders

• n-wire phase encoder exhibits n! different behavioural n-wire phase encoder exhibits n! different behavioural scenariosscenarios

– STG/FSM specification size explosion: every scenario is STG/FSM specification size explosion: every scenario is specified explicitlyspecified explicitly

– State space is exponential w.r.t. the channel width n. State space is exponential w.r.t. the channel width n. Structural synthesis method is requiredStructural synthesis method is required

• Phase encoders convert data between two different Phase encoders convert data between two different domains:domains:

– Combinatorial codes, e.g. binary or one-hot encoded dataCombinatorial codes, e.g. binary or one-hot encoded data– Sequences of events ordered in timeSequences of events ordered in time

ASYNC Symposium, May 20095Phase encoding

n-wire phase encoding channel

ASYNC Symposium, May 20096

Outline

Phase encoding Conditional partial order graphs Circuit synthesis

Phase detector Matrix phase encoder One hot phase encoder Binary phase encoder

Conclusions and future work

Outline

ASYNC Symposium, May 20097

Partial orders

Conditional Partial Order Graphs

• Basic mathematical structure to describe event ordersBasic mathematical structure to describe event orders

– Concurrency can be modelledConcurrency can be modelled– Choice cannot be modelledChoice cannot be modelled

ASYNC Symposium, May 20098

Conditional Partial Order Graphs

Conditional Partial Order Graphs

[ DATE’08 ]

ASYNC Symposium, May 20099

CPOG-based synthesis flow

Conditional Partial Order Graphs

ASYNC Symposium, May 200910

Application examples

Conditional Partial Order Graphs

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Synthesis of phase encoders

Conditional Partial Order Graphs

• CPOG model can be used for phase encoding controllers specification and synthesis:

– Vertices correspond to the signal transitions in the channel– Conditional arcs determine the order of the transitions

• 2-wire phase encoder specification example:

ASYNC Symposium, May 200912

Outline

Phase encoding Conditional partial order graphs Circuit synthesis

Phase detector Matrix phase encoder One hot phase encoder Binary phase encoder

Conclusions and future work

Outline

ASYNC Symposium, May 200913Circuits synthesis

n-wire phase encoding channel

ASYNC Symposium, May 200914

Phase detector

• Decodes phase encoded symbols by detecting the relative order between all the pairs of transitions

• Consists of n(n-1)/2 mutual exclusion (mutex) elements

Circuits synthesis

ASYNC Symposium, May 200915

Outline

Phase encoding Conditional partial order graphs Circuit synthesis

Phase detector Matrix phase encoder One hot phase encoder Binary phase encoder

Conclusions and future work

Outline

ASYNC Symposium, May 200916

Matrix phase encoder

• Generates phase encoded symbols given the matrix X = {xkj} of pairwise comparisons of the output transitions

Circuits synthesis

1 → 2 → 31 → 3 → 22 → 1 → 32 → 3 → 13 → 1 → 23 → 2 → 1

ASYNC Symposium, May 200917

Matrix phase encoder (implementation)

Circuits synthesis

ASYNC Symposium, May 200918

Matrix phase encoder (implementation)

Circuits synthesis

ASYNC Symposium, May 200919

Outline

Phase encoding Conditional partial order graphs Circuit synthesis

Phase detector Matrix phase encoder One hot phase encoder Binary phase encoder

Conclusions and future work

Outline

ASYNC Symposium, May 200920

One hot phase encoder• Generates phase encoded symbols given one hot data X = {x1…xn!}

Circuits synthesis

# Control signals

Order

1 (1,0,0,0,0,0) a, b, c

2 (0,1,0,0,0,0) a, c, b

3 (0,0,1,0,0,0) b, a, c

4 (0,0,0,1,0,0) b, c, a

5 (0,0,0,0,1,0) c, a, b

6 (0,0,0,0,0,1) c, b, a

ASYNC Symposium, May 200921

One hot phase encoder (logic optimisation)• The synthesised CPOG can be optimised

Circuits synthesis

ASYNC Symposium, May 200922

One hot phase encoder (controller)

Circuits synthesis

ASYNC Symposium, May 200923

Speed-independent one hot phase encoder

Circuits synthesis

ASYNC Symposium, May 200924

Outline

Phase encoding Conditional partial order graphs Circuit synthesis

Phase detector Matrix phase encoder One hot phase encoder Binary phase encoder

Conclusions and future work

Outline

ASYNC Symposium, May 200925

Binary phase encoder

Circuits synthesis

• Data is normally given in binary form• Binary phase encoder generates phase encoded

symbols given binary encoded data

ASYNC Symposium, May 200926

Outline

Phase encoding Conditional partial order graphs Circuit synthesis

Phase detector Matrix phase encoder One hot phase encoder Binary phase encoder

Conclusions and future work

Outline

ASYNC Symposium, May 200927

Conclusions and future work

Conclusions and future work

• The work presents a scalable approach for synthesis of multiple rail phase encoding circuits

• The approach uses the CPOG model in order to avoid exponential explosion of STG specifications due to duplication of events

• Phase encoders are synthesised for matrix, one hot, and binary source encodings, but the approach can be easily adapted for the other encodings, e.g. m-of-n encoding

• The future work includes the development of automated synthesis tools based on the presented theoretical techniques

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End

Thank you!Questions?

ASYNC Symposium, May 200929

STG specification explosion

x1 x2 Handshake sequence

1 0 1 -> 2

0 1 2 -> 1

ASYNC Symposium, May 200930

STG specification explosion

x1 x2 Handshake sequence

1 0 1 -> 2

0 1 2 -> 1

ASYNC Symposium, May 200931

STG specification explosion

First scenario

ASYNC Symposium, May 200932

STG specification explosion

First scenario

Second scenario

Event duplication!

ASYNC Symposium, May 200933

STG specification explosion

+ Reduces event duplication

+ Can be synthesised

automatically (e.g. Petrify)

– Difficult for manual design

– Not visual

– Contains a lot of additional

places to track the choices

– Very time consuming to

generate

ASYNC Symposium, May 200934

End

Thank you!More Questions?