System on Chip (SOC)

SOCSOC consists of at least two or more complex micro-electronic macro components previously integrated into different single diesComplex functionalities that previously required heterogeneous components to be connected on a PCB, are integrated within one single silicon chip

SOC:EvolutionTechnologies implementing embedded systems evolved from micro-controllers and discrete components to fully integrated SOCReason: advances in Silicon process technology enabling a complete system to be designed into one or few integrated devices

Space and Power reductionsIncreased Performance

Features of SOC Typically SOC incorporates

A programmable processorOn chip memoryAccelerated Functional Units (e.g. Digital Encryption Standard block, MPEG2 decoder)Peripheral devices

Often mixed technology designs integrating Analog, RF ComponentsMicro-electro-Mechanical Systems (MEMS)Optical input/output

SOC DesignTime and design effort required to integrate different types of components on a chip : a bottleneck for SOC evolutionDesign reuse to reduce time to market

Use of parts from previous designsMaking use of parts designed by third parties

Hardware and Software component model!

All for PROVEN and tested solutions, avoiding re-design and re-verification of real-time hardware and real-time software

IP based DesignIntellectual Property Cores

Parameterized components with standard interfaces facilitating high level synthesis

Cores available in three formsHard

Black box in optimized layout form and encrypted simulation model. Example: microprocessors

FirmSynthesized netlist which can be simulated and changed if needed

Soft Register transfer level HDLs; user is responsible for synthesis and layout

PlatformsEmbedded Applications built using

common architectural blocks andcustomized application specific components

Common architecturesProcessor, memory, peripherals, bus structures

Common architectures and supporting technologies (IP libraries and tools) are called Platforms and platform based designs

Platform based SOCPlatform based SOC’s are systems that contain

IP blocks like embedded CPU, embedded memory, Real world interfaces (e.g., PCI, USB),Mixed signal blocks and Software components

device drivers, real-time operating systems and application code

Classes of PlatformsFull Application Platform

Platforms that let derivative product designers create complete applications on top of hardware-software architectures

A set of hardware modulesExample: complex dual processor architecture with hierarchical bus system tailored to a specific product’s requirements

A layer of firmware and driver softwareExamples: Philip’s Nexperia, TI’s OMAP

Classes of Platforms(2)Processor Centric Platforms

Typically centered on specific processorsKey software services like real-time OS kernel made available through librariesExamples: ARM Micropack, ST Microelectronics ST100

Communication Centric PlatformCommunication fabric optimized for specific applicationFabrics often bundled with specific processorsExamples: ARM AMBA, IBM CoreConnect bus architecture

Classes of Platforms(3)Configurable(Programmable) platform

Programmable logic added to the platform allows consumers to customize using both hardware and softwareField programmable gate array(FPGA) added to hard-coded processor centric platformsExample: Altera Excalibur platform with ARM cores, Xilinx VertexII Pro

Multi-processor SOC (MPSoC)

Full application platformMultiple processors.

CPUs, DSPs, etc.Hardwired blocks.Mixed-signal.

Custom memory system.Lots of software.

Philips NexperiaMultimedia applications: set-top box, etc.2 CPUs, 3 busses, several accelerators,I/O devices.

MIPSTrimedia

bridge

to SDRAM

bridge

bridge

I/O I/O

acce

lera

tors

Acknowledgement: Wayne Wolf

TI OMAPTargets communications, multimedia.Multiprocessor with DSP, RISC.

C55x DSP

OMAP 5910:

ARM9

MMU

Memory ctrl

MPUinterface

SystemDMA

control

bridge

I/O

Acknowledgement: Wayne Wolf

ST NomadikTargets mobile multimedia.

A multiprocessor-of-multiprocessors.

ARM9

Mem

ory

syst

em

I/O

bri

dges

Audioaccelerator

Videoaccelerator

heterogeneousmultiprocessors

Acknowledgement: Wayne Wolf

OMAP

Open Multimedia Applications Platform

OMAPOMAP Application processor has a dual-core architecture: ARM 9 + TMS320C55 OMAP design chain includes

Software IP: OMAP supports several RTOS’s to suit different applicationsApplication and Middleware: Ported applications and middleware like MPEG-4 decoding and audio playback

Design Chain for OMAP

From: A Design Chain for Embedded System, G. Martin & F. Schirrmeister, IEEE Computer, March 2002

OMAP Hardware Architecture

From: Dedicated Systems Magazine 2001 Q2 Jamil Chaoi

OMAP Hardware ArchitectureARM RISC core is well suited for control code (OS, User Interface, OS applications)DSP best suited for signal processing applications like video, speech processing, audioPower efficient because signal processing task on DSP consumes much less power than on ARM

Example ApplicationVideo-conferencing

C55x DSP can process in real time full video conferencing application (audio and video at 15 images/sec) using only 40 p.c of the available computational capability

Can manage other applications concurrently

ARM processor can handle OS operations and other OS applications (may be Word, Excel, etc.)Less power consumption on the whole

How the Architecture Works?Both processors utilize an instruction cache to minimize external accesses

Both core uses MMU for virtual to physical memory translation and task-to-task memory protection

Uses two external memory interfaces and one internal memory port

External interfaces support to synchronous (DRAMS) or asynchronous memory (SRAM, FLASH)

Configured as 16 or 32 bit wide

Internal memory port for on-chip memory access for critical OS routines or LCD frame bufferAllow concurrent access from either processor or DMA unit

PeripheralsIncludes numerous interfaces to connect peripherals or external devices from either the DSP or GPPSome interfaces

Camera and Display interfaces Serial unidirectional compact camera port, 8-bit parallel interface, 8 bit/16 bit bi-directional display interface, OMAP internal LCD controller

Several Serial interfacesSPI, McBSP, I2C, USB, UART

Software ArchitectureDefines an interface scheme that allows GPP to be the system master

Called the DSP/BIOS Bridge

DSP/BIOS Bridge provides communications between GPP tasks and DSP tasksHigh level application developers use a set of DLL’s and drivers

OMAP2Includes multiple engines executing multiple tasksAn ARM 11 based microprocessor runs the OS and performs supervisory controlDSP core focusses on audio codecs, echo cancellation and noise suppression3D graphics engine enables sophisticated graphics renderingVideo/imaging accelerator handles streaming MPEG4 video and mega pixel-resolution cameraDigital baseband processor implements network communications as a cellular modem handling voice and data

OMAP 2 Architecture

From: www.TI.com

OMAP2All blocks operate simultaneously

No degradation in quality of any serviceDevices remain highly responsive

To conserve power each of these subsystems can be shut down when not usedSOC suited for implementation of Smart Phone

Digital Media ProcessorFunctionalities expected in a portable media system

Live preview : Capture, process, displayLive video capture: CompressesLive image capture: CompressesLive audio capture: CompressesVideo decode/playbackStill image decode/displayAudio decode/playbackPhoto printing

Several of these modes operate concurrently

DM 310 Media ProcessorFour subsystems: imaging/video, DSP, coprocessor, ARM coreImaging/Video system: CCD controller, preview engine, onscreen display, video encoderDSP: TMS32054X operating at 72 Mhz (max.) performs bulk of audio/image/video processing operationsCo-processors: SIMD engine(8 or 16 bit), Quantization, Variable length coder working concurrentlyARM Core: manages system level tasks, controls all components on chip except DSP and its co-processors

DM 310 Architecture

From: Anatomy of digital media processor, IEEE Micro, March-April 2004

Application: Still Camera Engine

From: Anatomy of digital media processor, IEEE Micro, March-April 2004

Reconfigurable Platforms

Configurable SOCConsisting of

Processor MemoryOn-chip reconfigurable hardware parts for customization to application

Fine-grained and coarse-grained reconfigurability

FPGA vs network of processors

Towards application specific programmable products

Reconfigurable Computing (RC)What is it?

Compute by building a circuit rather than executing instructions.Efficient for long running computations

Video and image processingDSPNetwork processing

Z[i] = a.X[i] + b.Y[i]

//program

Load rx, X

Mpy r1, rx, ra

Load ry, Y

Mpy r2, ry, rb

Add r3, r1, r2

Store r3, Z +

X

* a

Y

* b

Z

Advantages of RC Program

No instruction fetch, no I-cache etc.

Bit width and constantsAssume X & Y are 8 bitsAssume a = 0.25 and b =0.5Much smaller circuit!

+

X

*a

Y

*b

Z

8 8

6 7

8

/4 /2

Delay From two shift operations

and one addition, all on 32-bits

To one 8-bit addition (shifts are free in hardware)

FPGA-based RC

Programmable fabric that can be dynamically reconfiguredMapping to FPGA

Only the time consuming computations are mappedComputation expressed in HDL

StructureFPGA + Memory

Programmable Platforms

Several products incorporate microprocessor and FPGA on one chip

Con

fig

ura

ble

log

ic

Micro-controller and other processing elements

Memory

Triscent A7 SOC

CSL: performs basic combinational and sequential logic functions

Source: CSOC, Jurgen Becker, Proc. SBCCI’02

Xilinx Virtex II ProPowerPC based

1 to 4 PowerPCs4 to 16 gigabit transceivers

12 to 216 multipliers

3,000 to 50,000 logic cells

200k to 4M bits RAM

204 to 852 I/O

Config.

logic

Up to 16 serial transceivers• 622 Mbps to 3.125 Gbps622 Mbps to 3.125 Gbps

Pow

erP

Cs

Courtesy of Xilinx

Coarse grained RC: Multiple ALUs connected Operand routing with a hierarchical connection networkRegisters are distributedConfigure once and then run

no I-cache

Potentially an instruction level parallelism of 100 and moreNo branch instruction

XPP :eXtreme Processing Platform

Adaptive reconfigurable data processing architectureProcessing array elements organised as processing arrays

Source: CSOC, Jurgen Becker, Proc. SBCCI’02

Configurable processorsConfigurability:

Processor parameters (cache size, registers, etc.)Instructions.

Result:HDL model for processor.Software development environment.

Application-specific instruction processors

An ASIP is a stored-memory CPU whose architecture is tailored for a particular set of applications.Programmability allows changes to implementation, use in several different products, high data-path utilization.Application-specific architecture provides smaller silicon area, higher speed.

Retargetable compilation

microarchitecturalmodel

for (i=0; i<N; i++) c[i] = func1(a[i],b[i]);

applicationcode

front end

codegeneration

object code

from ASIP core synthesis

instructionset definition

Acknowledgement: Wayne Wolf

SummaryWe have learnt about SOCLooked at OMAP in some detailGot an introduction to the concept of Reconfigurable computing