system-on-chip test: methodology & experiences
TRANSCRIPT
System-on-Chip Test:Methodology & Experiences
Y. Zorian, D. Burek, LogicVisionS. Mukherji, Fujitsu Microelectronics
2 LogicVision, Inc., 1998, V 1.5 DB
System-on-Chip Test - P1500
Contents
❐ Introduction❐ SOC Test Requirements❐ SOC Test Architecture❐ SOC Test Methodology❐ Case Study❐ P1500 Standardization❐ Conclusions
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System-on-Chip Drivers
❐ Primary SOC Market Drivers - ConsumerElectronics:• complex products• shrinking market windows• cost sensitivity• high reliability• miniaturization
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System-on-Chip Paradigm
❐ Emergence of -• Very large transistor counts on a single chip• Mixed technologies on the same chip
➺ Logic, Analog, Memory, Processor
• Creation of Intellectual Property (IP)• Reusable core-based design
➺ Cores replacing standard parts, such as DSP,DRAM, MCU, Flash, and FPGA
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System-on-Chip Evolution
OriginalLogicDesign
SRAM
ROM
ReusedLogicDesign
UDL Analog
ROM
ReusedLogicDesign(IP Core)
UDL
DRAM uP(IP Core)
ATM(IP Core)
MPEG(IP Core)
DSM ASIC Block-Based SOC Core-Based Plug & Play SOC
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Contents
❐ Introduction❐ SOC Test Requirements❐ SOC Test Architecture❐ SOC Test Methodology❐ Case Study❐ P1500 Standardization❐ Conclusions
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SOC Test Specifics
❐ SOC realization processanalogous to SOB usingstandard parts
❐ SOC cores and UDL notmanufactured and nottested individually
❐ Cores and UDL aretested simultaneously
❐ SOC test integrationrequires test dataprovided with each coreand core test integrationmethodology and tools
System-on-Board (SOB)Process
System-on-Chip (SOC)Process
IC Design
IC Manuf. ASIC Manuf.
ASIC Design
SOB Manuf.
SOB Test
Core Design
SOB Design
UDL Design
SOC Integration
IC Test ASIC Test
SOC Manuf.
SOC Test
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SOC Test Requirements
1 Deeply Embedded Cores♦ access to core ports limited
⇒ need Test Access Mechanism to transport test from source tocore and from core to sink
2 Mixing Technologies on Same Process♦ cause yield limitations
⇒ allow different types of testability: logic, analog, memory,processor
⇒ debug and diagnosis modes for each technology type
3 More, Higher-Performance Core Pins than SOC Pins♦ limited SOC I/O bandwidth⇒ need source/sink that scales to bandwidth
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SOC Test Requirements
4 Ability to reuse same core in different SOCs♦ efficiency obtained by ease of plug-and-play
⇒ need reusable core test solution
5 High-Performance Operation♦ increased yield loss due to guard-banding
⇒ need at-speed test execution using system clock
6 Protection of Intellectual Property♦ limited core design knowledge by chip integrator
⇒ need self-contained test without need for core designknowledge
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SOC Test Requirements
7 Cost of ATE - Clustered or Multiple Insertion♦ substantially more expensive than conventional ATE
⇒ need more cost-effective solution to complement singleinsertion on existing ATE
⇒ reduce test time by time sharing (core test parallelism)
8 Cost Sensitivity of SOC Market♦ low-cost consumer products
⇒ need cost-effective testability solution that optimizesimplementation (space sharing)
9 Multiple Hardware Description Levels for Cores♦ Behavioral, RTL, and layout (soft, firm, hard cores)⇒ allow core testability at different levels (flexibility)
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SOC Test Requirements
10. Hierarchical Reuse of Cores♦ vertical integration: chip becomes next generation core
⇒ need hierarchical core test integration for testing complex cores,chips, and beyond
11. Limited Time-to-Market Window♦ tighter schedules for SOC development
⇒ need automation for core test preparation and SOC test integration
12. Numerous Core Providers and SOC Test Developers♦ diverse core test interfaces and information models
⇒ need standardized test interface between core and UDL (User-Defined Logic)
⇒ need standardized core test information model
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Summary of Test Requirements
❐ Sockets and Test Access Mechanisms❐ Bandwidth-Scalable Test Mechanism❐ Test Solutions for Different Technology Types❐ Automation of Core Test and SOC Test❐ Different Core Testability Techniques❐ Debug and Diagnosis❐ Hierarchical Core Test Integration
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Contents
❐ Introduction❐ SOC Test Requirements❐ SOC Test Architecture❐ SOC Test Methodology❐ Case Study❐ P1500 Standardization❐ Conclusions
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Summary of Test Requirements
❐ Sockets and Test Access Mechanisms❐ Bandwidth-Scalable Test Mechanism❐ Test Solutions for Different Technology Types❐ Automation of Core Test and SOC Test❐ Different Core Testability Techniques❐ Debug and Diagnosis❐ Hierarchical Core Test Integration
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SOC Test Architecture
❐ Core or UDL• random logic often with Test-Enabling (scan, test points)
• memory, analog, & processor require no Test-Enabling
❐ Source• provide test stimulus from either on-chip or off-chip ATE
❐ Sink• provide test response to either on-chip or off-chip ATE
❐ Socket• isolation and access
• connect core terminals to Test Access Mechanism
❐ Test Access Mechanism• transport patterns from source to core, from core to sink
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SOC Test Architecture
S/S : Source/SinkTAM: Test Access Mechanism
Socket
CoreSink
Off-chip S/S
On-chip S/S
TAMSource TAM
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Legacy Core Socket
From Chip
LegacyCore
FF
FF
FF
SI
SO
PinsTo Chip
Socketed Core
FromFF
FF
FF
SO
SI
Pins
To UDLUDL
❐ Selectable SocketElements Per-Pin
❐ Scan ChainSegmentation
❐ Socket ElementGrouping
❐ Capture-By-Domain
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Memory Socket
From BISTController
MemoryCore
FF
FF
SI
SO
Socketed Core
Functional
FF
Address
Control
DataIn DataOut
FF
Inputs
bistOn
❐ XOR Tree for AddressObservation (selectable width)
❐ XOR Tree for ControlObservation (selectable width)
❐ Shared DataIn Observationwith DataOut Control (per bit)
❐ Random Variable for MuxSelect (bistOn signal)
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Summary of Test Requirements
❐ Sockets and Test Access Mechanisms❐ Bandwidth-Scalable Test Mechanism❐ Test Solutions for Different Technology Types❐ Automation of Core Test and SOC Test❐ Different Core Testability Techniques❐ Debug and Diagnosis❐ Hierarchical Core Test Integration
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Embedded ATE
Reduced Pin-Count, Low Bandwidth External Interface
High-Bandwidth Internal Interfaces
EmbeddedATE
(on chip)
Pattern GenerationResult Compression
Precision TimingDiagnostics
Power ManagementTest Control
Support forBoard-Level Test
System-Level Test
(about 10k gates)
Logic
Processor, I/O, Audio,Video, Glue Logic, etc.
Mixed-Signal
PLL, ADC/DAC, Filter,Power Supplies, etc.
Low-CostExternal
ATE
Memory
SRAM, DRAM, ROM, Flash,FIFO, CAM, etc.
I/Os & Interconnects
Drivers/Receivers,Boundary Scan, etc.
Very Deep Submicron Chip, SOC, Board or SystemAt-Speed Test Using Only a Low-Cost Digital Tester with
Limited Speed and Accuracy !
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Summary of Test Requirements
❐ Sockets and Test Access Mechanisms❐ Bandwidth-Scalable Test Mechanism❐ Test Solutions for Different Technology Types❐ Automation of Core Test and SOC Test❐ Different Core Testability Techniques❐ Debug and Diagnosis❐ Hierarchical Core Test Integration
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Different Technology Types
Random Logic
System CK
PPRRPPGG
SI SM
SOSI SM
SOSI SM
SOSI SM
MMIISSRR
CK3SOSI
Control &Control &At-SpeedAt-SpeedTimngTimng SMSM
System CK
System CK
CK3
CK2
LogicLogic C3 C3
LogicLogic C1 C1LogicLogic C2 C2
ENTM
boundary scan Embedded Memories
MemoryBISTCtrl
BISTCtrl
bbEN
go/nogo
done
comparator status
control
address
control
address
data-in
BIST data-out
data-in
bb
Ctrl
Addr
DinDout
(optional - diagnostics)
BISTBIST CollarCollar
TM
bb
scaninscanout Async
Interface
ADC
adcBIST Test Access
fS
Analog Logic
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Summary of Test Requirements
❐ Sockets and Test Access Mechanisms❐ Bandwidth-Scalable Test Mechanism❐ Test Solutions for Different Technology Types❐ Automation of Core Test and SOC Test❐ Different Core Testability Techniques❐ Debug and Diagnosis❐ Hierarchical Core Test Integration
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Automation
Design Analysisand
Specification
Generation of
Design Objects
Assemblyand
Integration
Verificationand
Test Data Generation
❐ Design Analysis and Specification• Rules checking, default configurations• Flexibility based on test requirements
➺ Area, coverage, performance, test autonomy, IP protection
❐ Generation of Design Objects• RTL Objects, scripts, high-level description
• Modular interfaces (supports test hierarchy and scalability)
❐ Assembly and Integration• Supports test resource sharing
❐ Verification and Test Data Generation• Protocol Migration for core level to chip level• Supports design verification and manufacturing test
❐ Diagnostic Test Data Generation• Supports Manufacturing Test / Failure Analysis
Diagnosis
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Summary of Test Requirements
❐ Sockets and Test Access Mechanisms❐ Bandwidth-Scalable Test Mechanism❐ Test Solutions for Different Technology Types❐ Automation of Core Test and SOC Test❐ Different Core Testability Techniques❐ Debug and Diagnosis❐ Hierarchical Core Test Integration
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Core Testability Techniques
1: Legacy Cores• Access and Isolation (socket)
2: ATPG Enabled• Scan Chain Insertion
3: Reusable ATPG• Access and Isolation (socket)• Test Pattern Generation (reusable)
4: BIST Enabled• Scan Chain and Test Point Insertion
5: Embedded BIST• BIST Controller Insertion
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1: Legacy Cores
❐ Analyze/Specify• socket segments
• socket type
❐ Generate• socket elements
❐ Assemble• socket core
❐ Verify• functional vectors through
socket elements
From Chip
LegacyCore
FF
FF
FF
SI
SO
PinsTo Chip
Socketed Core
FromFF
FF
FF
SO
SI
Pins
To UDLUDL
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2: ATPG Enabled
❐ Analyze/Specify• scan design rules
❐ Assemble• scan chains
❐ Verify• scan vectors through
simulation
Co
mb
log
ic
FF
FF
FF
FF
FF
FF
Co
mb
log
ic
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
Co
mb
log
ic
ATPG Enabled CoreC
om
b lo
gic
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3: Reusable ATPG
❐ Analyze/Specify• core interface
❐ Generate• socket
❐ Assemble• scan chains• socket and core
❐ Verify• reusable scan vectors
through simulation
SO: external chainsSO: internal chains
Socketed Core
FF
FF
FF
FF
FF
FF
SI: internal chainsSI: external chains
Co
mb
log
ic
FF
FF
FF
FF
FF
FF
Co
mb
log
ic
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
Co
mb
log
ic
ATPG Enabled CoreC
om
b lo
gic
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4: BIST Enabled - Random Logic
❐ Analyze/Specify• scan design rules• test point candidates
❐ Assemble• scan chains
• test points
❐ Verify• scan vectors through
simulation
Co
mb
log
ic
FF
FF
FF
FF
FF
FF
RL BIST Enabled CoreC
om
b lo
gic
TPTP
TPTP
Co
mb
log
ic
Co
mb
log
ic
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
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4: BIST Enabled - Memory
❐ Analyze/Specify• serial test or parallel test
❐ Generate• sockets
❐ Assemble• socket memories
• route socket control
❐ Verify• memory BIST through
simulation
Co
mb
log
ic
FF
FF
FF
FF
FF
FF
Co
mb
log
ic
FF
FF
FF
FF
FF
FF
FF
Co
mb
log
ic
Core
MEM2
MEM1
FF
CL
Memory BISTSocket Control
FFCL
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5: Embedded Memory BIST
❐ Analyze/Specify• serial test or parallel test
❐ Generate• memory BIST controller
• sockets
❐ Assemble• socket memories
• instantiate controller
❐ Verify• memory BIST through
simulation
Co
mb
log
ic
FF
FF
FF
FF
FF
FF
Co
mb
log
ic
FF
FF
FF
FF
FF
FF
FF
Co
mb
log
ic
Core
MEM BIST
MEM2
MEM1
FF
CL
Memory BISTControl
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2: ATPG Enabled4: Memory BIST Enabled
❐ Analyze/Specify• scan design rules
• serial or parallel memory test
❐ Generate• sockets
❐ Assemble/Generate• insert scan chains
• socket memories
❐ Verify through Simulation• scan vectors
• memory BIST
Co
mb
log
ic
FF
FF
FF
FF
FF
FF
Co
mb
log
ic
FF
FF
FF
FF
FF
FF
Co
mb
log
ic
ATPG Enabled CoreFF
FFFF
MEM2
FFFF
MEM1
FF
CL
Memory BISTSocket Control
FFCL
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2: ATPG Enabled5: Embedded Memory BIST
❐ Analyze/Specify• scan design rules• serial or parallel test
❐ Generate• sockets (collars)
• memory BIST controller
❐ Assemble• insert scan chains
• socket memories
• instantiate BIST controller
❐ Verify through Simulation• scan vectors
• memory BIST
Co
mb
log
ic
FF
FF
FF
FF
FF
FF
Co
mb
log
ic
FF
FF
FF
FF
FF
FF
Co
mb
log
ic
ATPG Enabled CoreFF
MEM BIST
MEM2
MEM1
FF
CL
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3: Reusable ATPG5: Embedded Memory BIST
❐ Analyze/Specify• core interface
❐ Generate• socket (wrapper)
❐ Assemble• insert scan chains• socket memories and RL
Core
❐ Verify• simulate scan vectors
• simulate memory BISTSO: external chainsSO: internal chains
Socketed Core
FF
FF
FF
FF
FF
FF
SI: internal chainsSI: external chains
Co
mb
log
ic
FF
FF
FF
FF
FF
FF
Co
mb
log
ic
FF
FF
FF
FF
FF
FF
FF
Co
mb
log
ic
ATPG Enabled Core
MEM BIST
MEM2
MEM1
FF
CL
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4: Random Logic BIST Enabled5: Embedded Memory BIST
RL BIST Enabled Core
TP
Co
mb
log
ic
Co
mb
log
ic
FF
FF
FF
FF
FF
FF
Co
mb
log
ic
TP
TPFF
FF
FF
FF
FF
FF
FF
MEM BIST
MEM2
MEM1
FFTP
❐ Analyze/Specify• scan design rules• serial or parallel test
❐ Generate• memory sockets
• memory BIST controller
❐ Assemble• scan chains and test points
• socket memories
• instantiate BIST controller
❐ Verify• simulate scan vectors
• simulate memory BIST
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5: Embedded Random Logic BIST5: Embedded Memory BIST
❐ Analyze/Specify• socket segments
• socket type
❐ Generate• socket elements
• BIST controllers• Embedded Test Manager
❐ Assemble• integrate design objects
with core
❐ Verify• BIST through simulation
FF
FF
FF
FF
FF
FF
E T MLogic BIST
Socketed Core
T A M
Co
mb
log
icRL BIST Enabled Core
TP
TPTP
Co
mb
log
ic
Co
mb
log
ic
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FFFFFFMEM BIST
FFFF
MEM2
FFFF
MEM1
FFTP
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Summary of Test Requirements
❐ Sockets and Test Access Mechanisms❐ Bandwidth-Scalable Test Mechanism❐ Test Solutions for Different Technology Types❐ Automation of Core Test and SOC Test❐ Different Core Testability Techniques❐ Debug and Diagnosis❐ Hierarchical Core Test Integration
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Logic BIST Diagnostics
Signature 1Signature 1
Signature 2Signature 2
Signature 3Signature 3
Signature 4Signature 4
Signature nSignature n
...
PRPGPRPG
MISRMISR
scan chain
scan chain
scan chain
scan chain
scan chain
logicBISTcontrol &
timing
Step 1:Compare signatureson a vector by vectorbasis
PRPGPRPG
MISRMISR
scan chain
scan chain
scan chain
scan chain
scan chain
logicBISTcontrol &
timing
Chain dumpChain dump
Step 2:Dump all flip-flopvalues of failing vector
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Memory BIST Diagnostics
TAP
TAP
m
TDO
TDI
TCKTMS
TRST
Co
llar
SRAM/DRAM
SOC Chip
Stop-On-Nth-Error
memBIST-ICController
AddressAddress
DataData
Algo phaseAlgo phase
TAP
TAP
mTDO
TDI
TCKTMS
TRST
Co
llar
SRAM/DRAM
SOC Chip
ParallelStatus Lines
memBIST-ICController
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Summary of Test Requirements
❐ Sockets and Test Access Mechanisms❐ Bandwidth-Scalable Test Mechanism❐ Test Solutions for Different Technology Types❐ Automation of Core Test and SOC Test❐ Different Core Testability Techniques❐ Debug and Diagnosis❐ Hierarchical Core Test Integration
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Star Control Mechanism
Bo
un
dar
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can
Ch
ain
Bo
un
dar
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can
Ch
ain
1149.1 TAP
TDI TDOTCK TMS TRST
Logic BIST Embedded Test Manager Chain Router
Socketed Core
BIST Enabled Core
TP
M BIST
Logic BIST T A METM
LegacyCore
Socketed Core
Memory BIST
Socketed Core
ATPG Enabled Core
MEM BIST
UDL BIST Enabled Core BIST Enabled Core
UDL
Test Access Mechanism
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Daisy Chain Control Mechanism
Bo
un
dar
y S
can
Ch
ain
Bo
un
dar
y S
can
Ch
ain
1149.1 TAP
TDI TDOTCK TMS TRST
ManagerLogic BIST Embedded Test
Socketed Core
BIST Enabled Core
TP
M BIST
Logic BIST T A METM
LegacyCore
Socketed Core
Memory BIST
Socketed Core
ATPG Enabled Core
MEM BIST
UDL BIST Enabled Core BIST Enabled Core
UDL
Test Access Mechanism Manager
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Star Test Access Mechanism (TAM)
Bo
un
dar
y S
can
Ch
ain
Bo
un
dar
y S
can
Ch
ain
1149.1 TAP
TDI TDOTCK TMS TRST
ManagerLogic BIST Embedded Test Test Access Mechanism
Socketed Core
BIST Enabled Core
TP
M BIST
Logic BIST T A METM
LegacyCore
Socketed Core
Memory BIST
Socketed Core
ATPG Enabled Core
MEM BIST
UDL BIST Enabled Core BIST Enabled Core
UDL
Manager
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Daisy Chain TAM
Bo
un
dar
y S
can
Ch
ain
Bo
un
dar
y S
can
Ch
ain
1149.1 TAP
TDI TDOTCK TMS TRST
ManagerLogic BIST Embedded Test Test Access Mechanism
Socketed Core
BIST Enabled Core
TP
M BIST
Logic BIST T A METM
LegacyCore
Socketed Core
Memory BIST
Socketed Core
ATPG Enabled Core
MEM BIST
UDL BIST Enabled Core BIST Enabled Core
UDL
Manager
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Contents
❐ Introduction❐ SOC Test Requirements❐ SOC Test Architecture❐ SOC Test Methodology❐ Case Study❐ P1500 Standardization❐ Conclusions
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SOC Test Process
• Sources/Sinks• TAM/ETM
SO
C T
est P
repa
ratio
nC
ore T
est P
reparatio
n
SOC Decomposition
Core Test EnablingCore Test EnablingCore Test EnablingUDL Test EnablingUDL Test Enabling
Core Test Augmentation•Wrapper
Core Test Augmentation•Wrapper
Core Test AugmentationCore Test Augmentation• Wrapper
SOC Test Integrator
Merged Cores Non-Merged Cores
SOC Test Merger
• Sources/Sinks• TAM/ETM
Core Test Augmentation Core Test Augmentation• Wrapper
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Contents
❐ Introduction❐ SOC Test Requirements❐ SOC Test Architecture❐ SOC Test Methodology❐ Case Study❐ P1500 Standardization❐ Conclusions
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SOC Case Study
❐ Chip Contains:• 250K gates of digital logic
• 2 distinct Cores, 5 additional Blocks
• 29 embedded memories
❐ CORE 1(VD): 100 K gates, 10 embedded memories❐ CORE 2(GPIO): Legacy Core, functional patterns exist
❐ BLOCK MIU: < 40 K gates, 10 embedded memories
❐ BLOCK TSD: < 20 K gates, 3 embedded memories
❐ BLOCK AO: < 20 K gates, 3 embedded memories
❐ BLOCK VO: < 20 K gates, 3 embedded memories❐ BLOCK ICC: < 10 K gates
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Set-Top-Box (JSAT) System
TunerTuner QPSKQPSK ViterbiDecoder
ViterbiDecoder
Read-Solomon
Read-Solomon
RAMRAM CPUCPU SDRAMSDRAM
DescramblerDescrambler
MPEGVideo
MPEGVideo
TransportDemux
TransportDemux
MPEGAudio
MPEGAudio
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MPEG2(MB86372)/JSAT3Test Architecture
Introduction :This presentation describes a test architectureproposal for the MPEG2/JSAT3 chip design. Thisdesign is a pilot project for validating conceptsdescribed in the Socket Program.
Objective:The objective of the Socket Program is todemonstrate a SOC test methodology and toprovide a vehicle to prove in silicon test techniquesfor core-based designs.
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Pre-Test Inserted Chip Core
Core 1
RAM
RAM RAM
RAM
Core 2
VO
RAM RAM
MIU
RAM
RAM RAM
RAM
ICC
TSD
RAM RAM
AO
RAM RAM
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CORE 1 (VD): Memory BIST Insertion
❐ Analyze/Specify• Serial test or parallel test
❐ Generate• generate controller
• generate sockets (collars)
❐ Assemble• replace RAM with socketed
RAM
• instantiate controller
❐ Verify• simulate memory BIST
Memory BIST
Core 1Socket
RAM
Socket
RAM
Socket
RAM
Socket
RAM
Block 3
Core 1
Block 1
Core 2
Block 2
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CORE 1(VD): Scan/Test Point Insertion
❐ Analyze/Specify• scan design rules
❐ Generate• generate Test Points
❐ Assemble• insert scan chains
• insert test points
❐ Verify• generate and simulate
scan vectors
Memory BIST
Core 1Socket
RAM
Socket
RAM
Socket
RAM
Socket
RAM
Sca
n c
hai
n
Sca
n c
hai
n
Block 3
Core 1
Block 1
Core 2
Block 2
55 LogicVision, Inc., 1998, V 1.5 DB
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CORE 1(VD): Logic BIST Insertion
❐ Analyze/Specify• socket segments
• socket type
❐ Generate• socket elements
• Logic BIST controller
❐ Assemble• integrate design objects
with core
❐ Verify• generate and simulate logic
BIST vectors
Chain Router
Logic BIST controller
Memory BIST
Core1Socket
RAM
Socket
RAM
Socket
RAM
Socket
RAMSca
n c
hai
n
Sca
n c
hai
n
Socket Elements
Block 3
Core 1
Block 1
Core 2
Block 2
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CORE 2 (GPIO): Legacy Socket Insertion
❐ Analyze/Specify• socket segments
• socket type
❐ Generate• socket elements
❐ Assemble• integrate core with socket
elements
❐ Verify• retarget functional vectors
through socket elements
Socket Elements
Core 2
Block 3
Core 1
Block 1
Core 2
Block 2
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BLOCK MIU: Memory BIST Insertion
❐ Analyze/Specify• Serial test or parallel test
❐ Generate• generate controller
• generate sockets (collars)
❐ Assemble• replace RAM with socketed
RAM
• instantiate controller
❐ Verify• simulate memory BIST
Memory BIST
Block 1Socket
RAM
Socket
RAM
Socket
RAM
Socket
RAM
Block 3
Core 1
Block 1
Core 2
Block 2
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BLOCK MIU: Scan/Test Point Insertion
❐ Analyze/Specify• scan design rules
❐ Generate• generate Test Points
❐ Assemble• insert scan chains
• insert test points
❐ Verify• generate and simulate
scan vectors
Memory BIST
Block 1Socket
RAM
Socket
RAM
Socket
RAM
Socket
RAM
Sca
n c
hai
n
Sca
n c
hai
n
Block 3
Core 1
Block 1
Core 2
Block 2
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BLOCK TSD: Memory Collar Insertion
Block 2Socket
RAMSocket
RAM
❐ Analyze/Specify• Serial test or parallel test
❐ Generate• generate sockets (collars)
❐ Assemble• replace RAM with socketed
RAM
❐ Verify• simulate memory BIST
Block 3
Core 1
Block 1
Core 2
Block 2
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BLOCK TSD: Scan/Test Point Insertion
❐ Analyze/Specify• scan design rules
❐ Generate• generate Test Points
❐ Assemble• insert scan chains
• insert test points
❐ Verify• generate and simulate
scan vectors
Block 2
Socket
RAMSocket
RAM
Sca
n c
hai
n
Sca
n c
hai
n
Block 3
Core 1
Block 1
Core 2
Block 2
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BLOCK AO: Memory Collar Insertion
Block 2Socket
RAMSocket
RAM
❐ Analyze/Specify• Serial test or parallel test
❐ Generate• generate sockets (collars)
❐ Assemble• replace RAM with socketed
RAM
❐ Verify• simulate memory BIST
Block 3
Core 1
Block 1
Core 2
Block 2
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BLOCK AO: Scan/Test Point Insertion
❐ Analyze/Specify• scan design rules
❐ Generate• generate Test Points
❐ Assemble• insert scan chains
• insert test points
❐ Verify• generate and simulate
scan vectors
Block 2
Socket
RAMSocket
RAM
Sca
n c
hai
n
Sca
n c
hai
n
Block 3
Core 1
Block 1
Core 2
Block 2
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BLOCK VO: Memory Collar Insertion
Block 2Socket
RAMSocket
RAM
❐ Analyze/Specify• Serial test or parallel test
❐ Generate• generate sockets (collars)
❐ Assemble• replace RAM with socketed
RAM
❐ Verify• simulate memory BIST
Block 3
Core 1
Block 1
Core 2
Block 2
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BLOCK VO: Scan/Test Point Insertion
❐ Analyze/Specify• scan design rules
❐ Generate• generate Test Points
❐ Assemble• insert scan chains
• insert test points
❐ Verify• generate and simulate
scan vectors
Block 2
Socket
RAMSocket
RAM
Sca
n c
hai
n
Sca
n c
hai
n
Block 3
Core 1
Block 1
Core 2
Block 2
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BLOCK ICC: Scan/Test Point Insertion
Block 3
Core 1
Block 1
Core 2
❐ Analyze/Specify• scan design rules
❐ Generate• generate Test Points
❐ Assemble• insert scan chains
• insert test points
❐ Verify• generate and simulate
scan vectors
Block 2
Block 3Scan chain
Scan chain
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Core Flow: Memory BIST Insertion
❐ Analyze/Specify• Serial test or parallel test
❐ Generate• generate controller
❐ Assemble• instantiate controller
• route control signals
❐ Verify• simulate
Core 1
MIU
Core 2
Memory BIST
ICC
VO AOTSD
Memory BIST
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Core Flow:Scan/Test Point Insertion
Core 1
MIU
Core 2
Memory BIST
ICC
VO AOTSD
Memory BIST
❐ Analyze• merge core random logic
• scan design rules
❐ Generate• generate Test Points
❐ Assemble• insert scan chains
• insert test points
❐ Verify• generate and simulate
scan vectors
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Top Flow
❐ Analyze/Specify• Boundary Scan Cell types, segments
• Test Schedule
❐ Generate• Boundary Scan elements
• Logic BIST controller• Test Access Port
❐ Assemble• integrate design objects with core
❐ Verify• generate and simulate
69 LogicVision, Inc., 1998, V 1.5 DB
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Top Flow (cont’d)
Bo
un
dar
y S
can
Ch
ain
Bo
un
dar
y S
can
Ch
ain
logic BISTcontroller
Chain Router
1149.1 TAP
TDI TDOTCK TMS
Core 1
MIU
Core 2
Memory BIST
ICC
VOAOTSD
Memory BIST
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Contents
❐ Introduction❐ SOC Test Requirements❐ SOC Test Architecture❐ SOC Test Methodology❐ Case Study❐ P1500 Standardization❐ Conclusions
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P1500 Standardization
❐ At-Speed Testing❐ Diagnostics and Failure Analysis❐ Test Reuse: Board, System, and Field❐ Interface Standards: Embedded Test Manager❐ Legacy Core Test Data Format (STIL?)❐ On-Chip-Bus (OCB) for Test Access❐ Routability, Signal Integrity, and Cross Talk❐ BIST Friendly Architecture
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Contents
❐ Introduction❐ SOC Test Requirements❐ SOC Test Architecture❐ SOC Test Methodology❐ Case Study❐ P1500 Standardization❐ Conclusions
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Conclusions
❐ SOC test technologies are as varied as the coresin the chip.
❐ An integrated set of different test technologiesoffers the most effective SOC test solution.
❐ SOC complexity requires a hierarchical, reusabletest architecture.
❐ Embedded ATE provides bandwidth scalabilityand at-speed testing.