tames2-workshop r&d for embedded analogue testing diego vázquez garcía de la vega instituto de...

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R&D for R&D for Embedded Analogue Embedded Analogue

TestingTesting

Diego Vázquez García de la Vega

Instituto de Microelectrónica de Sevilla (IMSE-CNM)[email protected]

Diego Vázquez IMSE-CNM

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Outline

• A panoramic view

• Analogue and MS Test. Current Status

• External Testing. Fundamental Problems

• Solutions

• Conclusions


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A Panoramic View

FROM ASICs to SOCs

RF circuitryPower

ManagementPassive

ComponentsNext SOCs

And… increased performance in terms of speed, bandwidth, accuracy, power, voltage supply, etc…

MS SoC (00’s)

DSP

Memory

Wired Communication

Wireless Communication

Audio & Video

Glue Logic

Processor MemoryDigital SoC (90’s)

Application Specific Logic

ASIC (80’s)


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A Panoramic View

System-On-Board (SOB)System-On-Board (SOB)

• Dedicated technologies• Pre-tested ICs (dedicated tester)• Board level test

uPMemory

MixedSignaldigital

RF

FunctionalTester

LogicTester

MemoryTester

Mixed-SignalTester

RFTester


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A Panoramic View

System-On-Chip (SOC)System-On-Chip (SOC)

• Mixed technologies on the same chip

• Pre-designed blocks (not tested)

• Core and IC level Test required

uP Memory

MixedSignal

digitalRF

uPMemory

MixedSignaldigital

RF

System-On-Board (SOB)System-On-Board (SOB)

• Dedicated technologies

• Pre-tested blocks

• Board level test


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A Panoramic View


uP Memory

MixedSignal

digitalRF

Different cores with different modeling, different test requirements, different tester languages, etc.

Std Blocks IP Blocks

FunctionalTester

LogicTester

MemoryTester

Mixed-SignalTester

RFTester


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A Panoramic View

uP Memory

MixedSignal

digitalRF

IP Core-Based System

Design and Test Development

Design and Test Development

Manufacturing

Test

Co

re p

rovi

der

Sys

tem

in

teg

rato

r

IP-C

ore-B

ased ap

pro

achIP

-Co

re-Based

app

roach

Core Provider may not know:Which test method, tolerancemargins, etc. to use.

System integrator may have:Very limited knowledge of the adopted core.

Test of embedded IP cores:Joint responsibility of both

core provider and system integrator.


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A Panoramic View


uP Memory

MixedSignal

digitalRF

More to Test !!!!!

0,0E+00

2,0E+07

4,0E+07

6,0E+07

8,0E+07

1,0E+08

1,2E+08

1997 1999 2001 2003 2006 2009 2012

# Trans/Sq cm

Source: SIA Roadmap


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A Panoramic View


uP Memory

MixedSignal

digitalRF

Less Test Access !!!!!

100

1000

10000

100000

1000000

1997 1999 2001 2003 2006 2009 2012

#Trans/pin

Source: SIA Roadmap


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A Panoramic View


uP Memory

MixedSignal

digitalRF

Increased Bandwidth !!!

Source: SIA Roadmap

0

20

40

60

80

100

120

140

1997 1999 2001 2003 2006 2009 2012

fT Device (GHz)


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Analogue and MS Test Current Status

FUNCTIONAL TEST

Stimuli Generator CUT Response

Interpreter

Specification-Based Test

The Circuit Complies Specs

• The CUT is considered as a black box

•All interesting I/O relationship must be

checked out

•Tests may overlap and be redundant

• It takes long time

• It requires different instrumentation

•Tests do not guarantee defect-free ICs

I/O

Beh

avio

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• Analog Circuit classes:– Filters– ADCs– DACs– PLLs– RF Transceivers– Signal Conditioners– etc

• Testing methods is circuit dependent:– Filters

• Frequency domain, Passband, Rejection band, Distortion, Dynamic Range, etc.

– Data Converters• Time domain, Linearity

(INL, DNL), SNR, ENB, etc.

– PLLs• Frequency Domain,

Stability, Capture Range, Jitter, etc.

– Basic Blocks (OTAs, Opamps, etc)

• DC, AC, Transient, etc.

Combined into an IC requires different test techniques:

Test stimuli Response analysis


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• Specification-based (functional) tests: Tractable and does not need an analog fault model.

– Long test development time– Expensive ATE– Long test time.

• Test stimuli: – Multiple types– Dependence wrt to the involved circuit

• Test evaluation:– Multiple types (DC, AC, Transient, etc.)– Requires accurate and complex post-processing

• Separate test for functionality and timing impossible.


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uP Memory

MixedSignal

digitalRF

SUPER TESTER

• Large Pin-Count• Large Data Volume• High Frequency Features• High Accuracy Features• etc

Stimuli generation Precision timing DiagnosticTest control

Power management Large deep memory Slow throughput etc.


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Analogue and MS TestAlternative Approach


Interpreter

STRUCTURAL TEST

Defect-Oriented Test

There are no defects

• The CUT structure must be known

• Minimal test showing up defects

• It takes shorter times

• It requires simple instrumentation

• Tests do not guarantee Specs

Defect E

ffects


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Analogue and MS Test Alternative Approaches

FUNCTIONAL TEST


Interpreter

Specification-Based Test

The Circuit Complies Specs

• The CUT is considered as a black box

•All interesting I/O relationship must be

checked out

•Tests may overlap and be redundant

• It takes long time

• It requires different instrumentation

•Tests do not guarantee defect-free ICs

I/O

Beh

avio

r

STRUCTURAL TEST

Defect-Oriented Test

There are no defects

• The CUT structure must be known

• Minimal test showing up defects

• It takes shorter times

• It requires simple instrumentation

• Tests do not guarantee Specs

Defect E

ffects

Bothapproaches

arecomplementary


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Fundamental problems with External Testing

More to Test but Less Test Access

uP Memory

MixedSignal

digitalRF

More Devices and less Pin/Device


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More to Test but Less Test AccessYield Losses

Source: SIA Roadmap

Device speed+30% per year

Tester accuracy12% per year

ProjectedYield lossesIf current trends continue,

in less than ten years,

tester timing errors will

approach the cycle time

of the fastest devices.


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More to Test but Less Test Access

Yield LossesATE Cost

Accuracy, Bandwidth,

noise, pin-count, socket

performance, memory,

etc. accordingly to CUT.

If current trends continue, it may cost more to test a transistor than to manufacture the transistor (by 2014).


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SolutionsLines of interest

• Standardized Test Access Mechanism» 1149.4» P1500*

• Structured Test planning» Enable hierarchical testing» Enable the re-use of on-chip resources (DSP, uP, etc.)» Facilitate parallel testing» etc.

• Re-usable and structured DfT & BIST techniques» Provide accessing to embedded cores,» Reduce I/O data rate requirements,» Enable low pin count testing, and» Reduce the dependence on expensive instruments.


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SolutionsStandard Test Access efforts

1149.4 (started at the end of 1991)– Standard Mixed-Signal test bus to be used at device,

sub-assembly and system levels.» Aims to increase the observability and controllability of

Mixed-Signal designs and support MS-BIST structures.

P1500 (started in 1995)– Standard test method for embedded cores.

» Focused on Standardized Core Test Language (CTL) and configurable & scalable test wrapper for easy test access to the core.

» Need extension to mixed-signal.


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SolutionsDfT & BIST

• Re-usable and structured DfT & BIST techniques. A DfT Technique is not a Test Technique. An optimum strategy requires a synthesis of different

DFT & BIST techniques.

Physical

Electrical

Block

System

Layout Rules & guidelines

Support for specif. meas.

isolation & accessing

Pre/Post processing tech.

Partial / full BIST

On-line Test

General

CircuitSpecific

HierarchyTechniques


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SolutionsDfT & BIST

• Re-usable and structured DfT & BIST techniques.

An optimum strategy requires a synthesis of different DFT & BIST techniques.

Physical

Electrical

Block

System




On-Chip techniques

Partial / full Self-Test

Concurrent TestHierarchy

Techniques

Layout Optimization

Design for Iddq

Sw-opampStandard Test Bus (1149.4)

ADCBIST, PLLBISTMADBIST, HBIST

Circuit Reconfiguration

Self-Checking archit.

On-Line Archit.

Examples


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SolutionsDfT & BIST

• Re-usable and structured DfT & BIST techniques.

Physical

Electrical

Block

System




On-Chip techniques

Partial / full Self-Test

Concurrent TestHierarchy

Techniques

Layout Optimization

Design for Iddq

Sw-opampStandard Test Bus (1149.4)

ADCBIST, PLLBISTMADBIST, HBIST

Circuit Reconfiguration

Self-Checking archit.

On-Line Archit.

ExamplesStructuralStructural

FunctionalFunctionalAccessingAccessing


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SolutionsBIST

MAIN ADVANTAGES– Test the untestable:

• Embedded cores• Measure functions faster

than ATE

– IP protection– Re-usability:

• Along IC life cycles: wafer, board, field

– Reduce ATE requirements

– Reduce test develop.&Applic. time

REQUIREMENTS– Put ATE functions into

the chip:• Test stimuli generation• Output response

analysis• Test control

– Support for Board and System levels.

– Extra Area– Design Efforts


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SolutionsBIST

• TECHNIQUES:

– Functional: Meas Specs. Params

– Structural: Signature analysis to detect faults and predict yield problems.

EXAMPLES

• HBIST [Ohletz91]

• MADBIST[Toner&Roberts,93]

• adcBIST [LogicVision]

• PLLBIST [LogicVision]

• adcBISTmaxx [Opmaxx]

– OBIST (filters, ADCs, DACs, SD-mod, etc.)

– Reconfiguration (filters, SD-mod, Pipeline ADCs, etc.)

– Etc.


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SolutionsTest Stimuli Generators

Available techniques

– Sinusoidal oscillators– Relaxation oscillators– Digital synthesizers– SD–based Bit-streams

generators– White noise generators– PWM generators– Etc.

Constrains

– Precission & Resolution

– Frequency range– Multi-tone capability– Linearity (ramps)– Calibration– Programmability– Area– Etc.


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SolutionsOutput Response Analyzers

Available techniques

– Histograms– FFT– Bandpass digital filters– SD Signature analyzer– Sinewave correlation– Etc.

ADDSP(FFT)

0.0 519 .5 103 9.1 155 8.6 207 8.1 259 7.6 311 7.2F re q u en cy (H z)

-15 0.0

-13 0.0

-11 0.0

-9 0.0

-7 0.0

-5 0.0

-3 0.0

-1 0.0

dB

V

G L O B A L R E SU L T S

AD

Passband

DIGITALFILTER

Reject Band

Signal Power

Noise Power


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Conclusions DfT&BIST vs External ATE

Reasons for DfT&BIST

– Portable: reusable along IC life cycle

– The only solution for embedded blocks

– Reduce cost of external ATE

– At-Speed Test– Solves SOCs problems

(accessing, IP protection)– Simplifies Test Program

Development– External accessing to

embedded blocks may impact performance

Reasons for External ATE

– External ATE can do more testing

– BIST increase IC complexity

– BIST may impact performance

– BIST increase design efforts & time

– BIST may increase yield loss.


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Conclusions

• Further Research required:DfT & BIST techniques for analogue embedded cores

Many companies and researchers are providing since some years good solutions for a diversity of cores (PLLs, ADCs and DACs, filters, memories, etc.).

However, the industry has only adopted standards (1149.4) & functional solutions (adc-BIST, adcBISTmaxx, etc.)

Structural techniques not widely accepted, but they are a clear potential solution that need to be further explored.


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On-ChipTest Manager

Stimuli generation Result compression Precision timing Diagnostic Power manager Test Control Support for board & system level

Memory (BISTed)

Memory (BISTed)

Logic (BISTed)Logic

(BISTed)

Mixed-Signal (BISTed)

Mixed-Signal (BISTed)

I/O & Interconnects (BISTed)

I/O & Interconnects (BISTed)

ICIC

ConclusionsDfT & BISTed ICs

NEED!!: Dedicate part of the IC area to include DfT and BIST facilities

External ATE

Digital TesterLow cost-per-pin

Limited speedLimited accuracy

External ATE

Digital TesterLow cost-per-pin

Limited speedLimited accuracy

High Bandwidth internal interfaces

Low Bandwidth external interfaces

Ideal concept:DfT & BISTed IC

tames2-workshop r&d for embedded analogue testing diego vázquez garcía de la vega instituto de...

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