Testing of Digital Systems:Testing of Digital Systems:An IntroductionAn Introduction

Testing of Digital Systems:Testing of Digital Systems:An IntroductionAn Introduction

Dr. Aiman H. El-Maleh

Computer Engineering Department

King Fahd University of Petroleum & Minerals

Dr. Aiman H. El-Maleh

Computer Engineering Department

King Fahd University of Petroleum & Minerals

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OutlineOutlineOutlineOutline

Introduction Manufacturing Cost Defects, Faults, Fault Models Automatic Test Pattern Generation Scan Testing Methodology Built-In Self Test Conclusions

Most figures used in this presentation are taken from Design-for-Test for Digital IC’s and Embedded Core Systems by Alfred L. Crouch.

Introduction Manufacturing Cost Defects, Faults, Fault Models Automatic Test Pattern Generation Scan Testing Methodology Built-In Self Test Conclusions

Most figures used in this presentation are taken from Design-for-Test for Digital IC’s and Embedded Core Systems by Alfred L. Crouch.

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VLSI Realization ProcessVLSI Realization ProcessVLSI Realization ProcessVLSI Realization Process

Determine requirements

Write specifications

Design synthesis and Verification

FabricationManufacturing test

Chips to customer

Customer’s need

Test development

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DefinitionsDefinitionsDefinitionsDefinitions

Design synthesis: Given an I/O function, develop a procedure to manufacture a device using known materials and processes.

Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function.

Test: A manufacturing step that ensures that the physical device, manufactured from the synthesized design, has no manufacturing defect.

Design synthesis: Given an I/O function, develop a procedure to manufacture a device using known materials and processes.

Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function.

Test: A manufacturing step that ensures that the physical device, manufactured from the synthesized design, has no manufacturing defect.

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Verification vs. TestVerification vs. TestVerification vs. TestVerification vs. Test

Verifies correctness of design.

Performed by simulation, hardware emulation, or formal methods.

Performed once prior to manufacturing.

Responsible for quality of design.

Verifies correctness of manufactured hardware.

Two-part process:• 1. Test generation: software

process executed once during design

• 2. Test application: electrical tests applied to hardware

Test application performed on every manufactured device.

Responsible for quality of devices.

Verification Test

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Definition of TestingDefinition of TestingDefinition of TestingDefinition of Testing

A known input stimulus is applied to a unit in a known state, and a known response can be evaluated.

A known input stimulus is applied to a unit in a known state, and a known response can be evaluated.

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ExampleExampleExampleExample

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Reasons for TestingReasons for TestingReasons for TestingReasons for Testing

Detection: Determination whether or not the device under test (DUT) has some fault.• Measurement of defects and quality level

• Reliability requirement

Diagnosis: Identification of a specific fault that is present on DUT.

Device characterization: Determination and correction of errors in design and/or test procedure.

Failure mode analysis (FMA): Determination of manufacturing process errors that may have caused defects on the DUT.

Detection: Determination whether or not the device under test (DUT) has some fault.• Measurement of defects and quality level

• Reliability requirement

Diagnosis: Identification of a specific fault that is present on DUT.

Device characterization: Determination and correction of errors in design and/or test procedure.

Failure mode analysis (FMA): Determination of manufacturing process errors that may have caused defects on the DUT.

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Product Manufacturing CostProduct Manufacturing CostProduct Manufacturing CostProduct Manufacturing Cost

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Product Manufacturing CostProduct Manufacturing CostProduct Manufacturing CostProduct Manufacturing Cost

Reduction of silicon cost • increasing volume and yield

• die size reduction (process shrinks or more efficient layout)

Reduction of packaging cost • increasing volume,

• shifting to lower cost packages if possible (e.g., from ceramic to plastic),

• reduction in package pin count

Reduction in cost of test • reducing vector data size

• reducing the cost of the tester

• reducing test time

Reduction of silicon cost • increasing volume and yield

• die size reduction (process shrinks or more efficient layout)

Reduction of packaging cost • increasing volume,

• shifting to lower cost packages if possible (e.g., from ceramic to plastic),

• reduction in package pin count

Reduction in cost of test • reducing vector data size

• reducing the cost of the tester

• reducing test time

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Main Difficulties in TestingMain Difficulties in TestingMain Difficulties in TestingMain Difficulties in Testing

Miniaturization Physical access difficult or impossible.

Increasing complexity Large amount of test data.

Number of access ports remains constant Long test application time.

High speed High demand on tester’s driver/sensor mechanism and more complicated failure mechanism.

Testing accounts up to 50% of product development efforts.

The key to successful testing lies in the design process.

Miniaturization Physical access difficult or impossible.

Increasing complexity Large amount of test data.

Number of access ports remains constant Long test application time.

High speed High demand on tester’s driver/sensor mechanism and more complicated failure mechanism.

Testing accounts up to 50% of product development efforts.

The key to successful testing lies in the design process.

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Main Difficulties in TestingMain Difficulties in TestingMain Difficulties in TestingMain Difficulties in Testing

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Costs of TestingCosts of TestingCosts of TestingCosts of Testing

Design for testability (DFT)• Chip area overhead and yield reduction

• Performance overhead

Software processes of test• Test generation and fault simulation

• Test programming and debugging

Manufacturing test• Automatic test equipment (ATE) capital cost

• Test center operational cost

Design for testability (DFT)• Chip area overhead and yield reduction

• Performance overhead

Software processes of test• Test generation and fault simulation

• Test programming and debugging

Manufacturing test• Automatic test equipment (ATE) capital cost

• Test center operational cost

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Cost of Manufacturing TestCost of Manufacturing TestCost of Manufacturing TestCost of Manufacturing Test

0.5-1.0GHz, analog instruments,1,024 digital pins:• ATE purchase price= $1.2M + 1,024 x $3,000 = $4.272M

Running cost (five-year linear depreciation)• = Depreciation + Maintenance + Operation

• = $0.854M + $0.085M + $0.5M

• = $1.439M/year

Test cost (24 hour ATE operation)• = $1.439M/(365 x 24 x 3,600)

• = 4.5 cents/second

0.5-1.0GHz, analog instruments,1,024 digital pins:• ATE purchase price= $1.2M + 1,024 x $3,000 = $4.272M

Running cost (five-year linear depreciation)• = Depreciation + Maintenance + Operation

• = $0.854M + $0.085M + $0.5M

• = $1.439M/year

Test cost (24 hour ATE operation)• = $1.439M/(365 x 24 x 3,600)

• = 4.5 cents/second

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Automatic Test Equipment ComponentsAutomatic Test Equipment ComponentsAutomatic Test Equipment ComponentsAutomatic Test Equipment Components

Powerful computer Powerful 32-bit Digital Signal Processor (DSP) for

analog testing Test Program (written in high-level language) running

on the computer Probe Head (actually touches the bare or packaged

chip to perform fault detection experiments) Probe Card or Membrane Probe (contains electronics

to measure signals on chip pin or pad)

Powerful computer Powerful 32-bit Digital Signal Processor (DSP) for

analog testing Test Program (written in high-level language) running

on the computer Probe Head (actually touches the bare or packaged

chip to perform fault detection experiments) Probe Card or Membrane Probe (contains electronics

to measure signals on chip pin or pad)

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ADVANTEST Model T6682 ATEADVANTEST Model T6682 ATEADVANTEST Model T6682 ATEADVANTEST Model T6682 ATE

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LTX FUSION HF ATELTX FUSION HF ATELTX FUSION HF ATELTX FUSION HF ATE

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Manufacturing Test BoardManufacturing Test BoardManufacturing Test BoardManufacturing Test Board

The chip will be accessed by the tester at its pins only

A custom (load) board will be made for this purpose

Each pin has a limited number of bits available (e.g., 2 MB)

Test program (set of vectors and tester control) applied at tester speed (may be less than actual chip speed)

Primary goal of manufacturing test is structural verification

The chip will be accessed by the tester at its pins only

A custom (load) board will be made for this purpose

Each pin has a limited number of bits available (e.g., 2 MB)

Test program (set of vectors and tester control) applied at tester speed (may be less than actual chip speed)

Primary goal of manufacturing test is structural verification

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Design For TestabilityDesign For TestabilityDesign For TestabilityDesign For Testability

To take into account the testing aspects during the design process so that more testable designs will be generated.

Advantages of DFT• Reduce test efforts.

• Eases generation of test vectors• Eases diagnosis & debugging

• Reduce cost for test equipments (ATE).

• Shorten turnaround time.

• Increase product quality.

Disadvantages of DFT• Adds complexity to design methodology

• Impacts design area, power, speed and package pins

To take into account the testing aspects during the design process so that more testable designs will be generated.

Advantages of DFT• Reduce test efforts.

• Eases generation of test vectors• Eases diagnosis & debugging

• Reduce cost for test equipments (ATE).

• Shorten turnaround time.

• Increase product quality.

Disadvantages of DFT• Adds complexity to design methodology

• Impacts design area, power, speed and package pins

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DefectsDefectsDefectsDefects

Defects: physical problems that occur in silicon Common Silicon CMOS defects:

• Gate-oxide shorts

• Insufficient doping

• Process or mask errors

• Metal trace opens

• Metal trace bridges

• Open and plugged vias

• Short to power (Vdd) or Ground (Vss)

Defects: physical problems that occur in silicon Common Silicon CMOS defects:

• Gate-oxide shorts

• Insufficient doping

• Process or mask errors

• Metal trace opens

• Metal trace bridges

• Open and plugged vias

• Short to power (Vdd) or Ground (Vss)

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DefectsDefectsDefectsDefects

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FaultsFaultsFaultsFaults

Fault is a model of failure mode of defect that relates defect to circuit behavior.

Example• Gate-Oxide short shorts transistor’s

source to drain (S2D)

• Modeled by connecting gate to 0 or 1

• Transistor Stuck-on or Stuck-off

Behavior resulting from these models may be a high current, a high impedance state or intermittent behavior.

Fault is a model of failure mode of defect that relates defect to circuit behavior.

Example• Gate-Oxide short shorts transistor’s

source to drain (S2D)

• Modeled by connecting gate to 0 or 1

• Transistor Stuck-on or Stuck-off

Behavior resulting from these models may be a high current, a high impedance state or intermittent behavior.

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Common Fault ModelsCommon Fault ModelsCommon Fault ModelsCommon Fault Models

Single stuck-at faults Transistor open and short faults Bridging faults Delay faults (transition, path) Memory faults PLA faults (stuck-at, cross-point, bridging) Functional faults (processors) Analog faults

Single stuck-at faults Transistor open and short faults Bridging faults Delay faults (transition, path) Memory faults PLA faults (stuck-at, cross-point, bridging) Functional faults (processors) Analog faults

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Single Stuck-at Fault ModelSingle Stuck-at Fault ModelSingle Stuck-at Fault ModelSingle Stuck-at Fault Model

Failures represented as an individual wire shorted to Vdd (stuck-at-1) or Vss (stuck-at-0).

Covers many of physical defects.

Number of faults small. Independent of

technology. Can be used to model

other type of faults.

Failures represented as an individual wire shorted to Vdd (stuck-at-1) or Vss (stuck-at-0).

Covers many of physical defects.

Number of faults small. Independent of

technology. Can be used to model

other type of faults.

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ExampleExampleExampleExample

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Multiple Stuck-at FaultsMultiple Stuck-at FaultsMultiple Stuck-at FaultsMultiple Stuck-at Faults

A multiple stuck-at fault means that any set of lines is stuck-at some combination of (0,1) values.

The total number of multiple stuck-at faults in a circuit with k single fault sites is 3k-1.

A single fault test can fail to detect the target fault if another fault is also present, however, such masking of one fault by another is rare.

Statistically, single fault tests cover a very large number of multiple faults.

A multiple stuck-at fault means that any set of lines is stuck-at some combination of (0,1) values.

The total number of multiple stuck-at faults in a circuit with k single fault sites is 3k-1.

A single fault test can fail to detect the target fault if another fault is also present, however, such masking of one fault by another is rare.

Statistically, single fault tests cover a very large number of multiple faults.

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Transistor (Switch) FaultsTransistor (Switch) FaultsTransistor (Switch) FaultsTransistor (Switch) Faults

MOS transistor is considered an ideal switch and two types of faults are modeled:• Stuck-open -- a single transistor is permanently stuck in the

open state.

• Stuck-short -- a single transistor is permanently shorted irrespective of its gate voltage.

Detection of a stuck-open fault requires two vectors. Detection of a stuck-short fault requires the

measurement of quiescent current (IDDQ).

MOS transistor is considered an ideal switch and two types of faults are modeled:• Stuck-open -- a single transistor is permanently stuck in the

open state.

• Stuck-short -- a single transistor is permanently shorted irrespective of its gate voltage.

Detection of a stuck-open fault requires two vectors. Detection of a stuck-short fault requires the

measurement of quiescent current (IDDQ).

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Stuck-Open ExampleStuck-Open ExampleStuck-Open ExampleStuck-Open Example

Two-vector s-op testcan be constructed byordering two s-at testsA

B

VDD

C

pMOSFETs

nMOSFETs

Stuck-open

1

0

0

0

0 1(Z)

Good circuit states

Faulty circuit states

Vector 1: test for A s-a-0(Initialization vector)

Vector 2 (test for A s-a-1)

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Stuck-Short ExampleStuck-Short ExampleStuck-Short ExampleStuck-Short Example

A

B

VDD

C

pMOSFETs

nMOSFETs

Stuck-short

1

0

0 (X)

Good circuit state

Faulty circuit state

Test vector for A s-a-0

IDDQ path infaulty circuit

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Delay FaultsDelay FaultsDelay FaultsDelay Faults

Some defects do not manifest a logical incorrect behavior but appear as an increase in delay

Example• Small metal open on a connection trace

• Logic value still propagates

• Propagation of value is slowed down

Some defects do not manifest a logical incorrect behavior but appear as an increase in delay

Example• Small metal open on a connection trace

• Logic value still propagates

• Propagation of value is slowed down

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ExampleExampleExampleExample

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Fault CoverageFault CoverageFault CoverageFault Coverage

Used as measure of test quality Used as measure of test quality

FaultsofNumber

FaultsDetectedCoverageFault

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Types of TestingTypes of TestingTypes of TestingTypes of Testing

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Automatic Test Pattern Generation Automatic Test Pattern Generation Automatic Test Pattern Generation Automatic Test Pattern Generation

Eases generation of test vectors.

Reduces cost of test • More efficient test vectors

• Reduction in cycle time

Provides a deterministic quality metric.

Eases generation of test vectors.

Reduces cost of test • More efficient test vectors

• Reduction in cycle time

Provides a deterministic quality metric.

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Detectable FaultDetectable FaultDetectable FaultDetectable Fault

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Undetectable FaultUndetectable FaultUndetectable FaultUndetectable Fault

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Fault EquivalenceFault EquivalenceFault EquivalenceFault Equivalence

All faults that produce the same faulty function are equivalent.

If one fault is detected, all equivalent faults are detected.

Fault selection only needs to target one of the equivalent faults.

All faults that produce the same faulty function are equivalent.

If one fault is detected, all equivalent faults are detected.

Fault selection only needs to target one of the equivalent faults.

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Fault Equivalence ExampleFault Equivalence ExampleFault Equivalence ExampleFault Equivalence Example

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Stuck-At Fault ATPGStuck-At Fault ATPGStuck-At Fault ATPGStuck-At Fault ATPG

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Path Sensitization Method Circuit ExamplePath Sensitization Method Circuit ExamplePath Sensitization Method Circuit ExamplePath Sensitization Method Circuit Example

Fault Sensitization Fault Propagation Line Justification

Fault Sensitization Fault Propagation Line Justification

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Path Sensitization Method Circuit ExamplePath Sensitization Method Circuit ExamplePath Sensitization Method Circuit ExamplePath Sensitization Method Circuit Example

Try path f–h–k–L blocked at j, since there is no way to justify the 1 on i

Try path f–h–k–L blocked at j, since there is no way to justify the 1 on i

10

D

D1

1

1DD

D

D=1/0 D=0/1

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Path Sensitization Method Circuit ExamplePath Sensitization Method Circuit ExamplePath Sensitization Method Circuit ExamplePath Sensitization Method Circuit Example

Try simultaneous paths f–h–k–L and g–i–j–k–L blocked at k because D-frontier (chain of D or D) disappears

Try simultaneous paths f–h–k–L and g–i–j–k–L blocked at k because D-frontier (chain of D or D) disappears

1

DD D

DD

1

1

1

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Path Sensitization Method Circuit ExamplePath Sensitization Method Circuit ExamplePath Sensitization Method Circuit ExamplePath Sensitization Method Circuit Example

Final try: path g–i–j–k–L test found! Final try: path g–i–j–k–L test found!

0

D D D

1 DD

1

0

1

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Transition Delay Fault ATPGTransition Delay Fault ATPGTransition Delay Fault ATPGTransition Delay Fault ATPG

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Fault Simulation ExampleFault Simulation ExampleFault Simulation ExampleFault Simulation Example

1. Create multiple copies of the netlist for each fault.

2. Apply same vectors to each copy.

3. Compare each copy to good simulation (expected response).

4. Fault is detected if bad circuit and good circuit differ at a detect point.

1. Create multiple copies of the netlist for each fault.

2. Apply same vectors to each copy.

3. Compare each copy to good simulation (expected response).

4. Fault is detected if bad circuit and good circuit differ at a detect point.

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Test Compaction and CompressionTest Compaction and CompressionTest Compaction and CompressionTest Compaction and Compression

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Sequential CircuitsSequential CircuitsSequential CircuitsSequential Circuits

A sequential circuit has memory in addition to combinational logic.

Test for a fault in a sequential circuit is a sequence of vectors, which

• Initializes the circuit to a known state• Activates the fault, and• Propagates the fault effect to a primary output

Methods of sequential circuit ATPG• Time-frame expansion methods• Simulation-based methods

A sequential circuit has memory in addition to combinational logic.

Test for a fault in a sequential circuit is a sequence of vectors, which

• Initializes the circuit to a known state• Activates the fault, and• Propagates the fault effect to a primary output

Methods of sequential circuit ATPG• Time-frame expansion methods• Simulation-based methods

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Example: A Serial AdderExample: A Serial AdderExample: A Serial AdderExample: A Serial Adder

FF

An Bn

Cn Cn+1

Sn

s-a-0

11

1

1

1X

X

X

D

D

Combinational logic

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Time-Frame ExpansionTime-Frame ExpansionTime-Frame ExpansionTime-Frame Expansion

An Bn

FF

Cn Cn+1

1X

X

Sn

s-a-011

1

1

D

D

Combinational logicSn-1

s-a-011

1

1 X

D

D

Combinational logic

Cn-1

1

1

D

D

X

An-1 Bn-1 Time-frame -1 Time-frame 0

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Concept of Time-FramesConcept of Time-FramesConcept of Time-FramesConcept of Time-Frames

If the test sequence for a single stuck-at fault contains n vectors,

• Replicate combinational logic block n times• Place fault in each block• Generate a test for the multiple stuck-at fault using

combinational ATPG with 9-valued logic

If the test sequence for a single stuck-at fault contains n vectors,

• Replicate combinational logic block n times• Place fault in each block• Generate a test for the multiple stuck-at fault using

combinational ATPG with 9-valued logic

Comb.block

Fault

Time-frame

0

Time-frame

-1

Time-frame-n+1

Unknownor given

Init. state

Vector 0Vector -1Vector -n+1

PO 0PO -1PO -n+1

Statevariables

Nextstate

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Example of Sequential CircuitExample of Sequential CircuitExample of Sequential CircuitExample of Sequential Circuit

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Improving Controllability & ObservabilityImproving Controllability & ObservabilityImproving Controllability & ObservabilityImproving Controllability & Observability

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Regular vs. Scan Flip-FlopRegular vs. Scan Flip-FlopRegular vs. Scan Flip-FlopRegular vs. Scan Flip-Flop

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Example Scan Circuit with Scan ChainExample Scan Circuit with Scan ChainExample Scan Circuit with Scan ChainExample Scan Circuit with Scan Chain

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Scan Element OperationsScan Element OperationsScan Element OperationsScan Element Operations

Scan cell provides observability and controllability of the signal path:

Operate: allows normal transparent operation of the element.

Scan Load/Shift: used to serially load/shift data into the scan chain while simultaneously unloading the last sample.

Scan Data Apply: allows the scan element to control the value of the output, thereby controlling the logic driven by Q.

Scan Sample: gives observability of logic that fans into the scan element.

Scan cell provides observability and controllability of the signal path:

Operate: allows normal transparent operation of the element.

Scan Load/Shift: used to serially load/shift data into the scan chain while simultaneously unloading the last sample.

Scan Data Apply: allows the scan element to control the value of the output, thereby controlling the logic driven by Q.

Scan Sample: gives observability of logic that fans into the scan element.

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Scan Test TimingScan Test TimingScan Test TimingScan Test Timing

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Multiple Scan ChainsMultiple Scan ChainsMultiple Scan ChainsMultiple Scan Chains

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Multiple Scan ChainsMultiple Scan ChainsMultiple Scan ChainsMultiple Scan Chains

Using multiple scan chains:• Reduces required tester memory per channel• Reduces test application time

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Stuck-At Scan DiagnosticsStuck-At Scan DiagnosticsStuck-At Scan DiagnosticsStuck-At Scan Diagnostics

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Scan Testing MethodologyScan Testing MethodologyScan Testing MethodologyScan Testing Methodology

Advantages• Direct Controllability & Observability of Internal Nodes

• Enables Combinational ATPG

• More Efficient Vectors

• Higher Potential Fault Coverage

• Deterministic Quality Metric

• Efficient Diagnostic Capability

• AC and DC Compliance

Concerns• Power Consumption

• Clock Skew

• Design Rule Impact on Budgets

Advantages• Direct Controllability & Observability of Internal Nodes

• Enables Combinational ATPG

• More Efficient Vectors

• Higher Potential Fault Coverage

• Deterministic Quality Metric

• Efficient Diagnostic Capability

• AC and DC Compliance

Concerns• Power Consumption

• Clock Skew

• Design Rule Impact on Budgets

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Boundary Scan ArchitectureBoundary Scan ArchitectureBoundary Scan ArchitectureBoundary Scan Architecture

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Built-In Self Test (BIST)Built-In Self Test (BIST)Built-In Self Test (BIST)Built-In Self Test (BIST)

BIST is the capability of a circuit (chip, board, system) to test itself.

BIST architectures consist of• Test pattern generators (TPGs)

• Output response analyzers (ORAs)

• Circuit under test (CUT)

• Distribution system for transmitting data from TPGs to CUTs and from CUTs to ORAs

• BIST controller

BIST is the capability of a circuit (chip, board, system) to test itself.

BIST architectures consist of• Test pattern generators (TPGs)

• Output response analyzers (ORAs)

• Circuit under test (CUT)

• Distribution system for transmitting data from TPGs to CUTs and from CUTs to ORAs

• BIST controller

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Built-In Self Test ExampleBuilt-In Self Test ExampleBuilt-In Self Test ExampleBuilt-In Self Test Example

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Advantages of BISTAdvantages of BISTAdvantages of BISTAdvantages of BIST

Fast, efficient and hierarchical - same hardware is capable of testing chips, boards and systems.

No need of expensive ATE (cost >= $10 milion) Testing during operation and maintenance Uniform technique for production, system and maintenance

tests Dynamic properties of the circuit can be tested at speed Can be used for delay testing as it can be used in real

time

Fast, efficient and hierarchical - same hardware is capable of testing chips, boards and systems.

No need of expensive ATE (cost >= $10 milion) Testing during operation and maintenance Uniform technique for production, system and maintenance

tests Dynamic properties of the circuit can be tested at speed Can be used for delay testing as it can be used in real

time

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ConclusionConclusionConclusionConclusion

With increasing design complexity, testing cost has increased dramatically.

Testing must be addressed early in the design process.

Design engineers must have good testing and design for testability knowledge.

Testing introduced in Computer & Electrical Engineering Curriculum in many universities• COE 464: Testing of Digital Circuits

• COE 571: Digital System Testing

With increasing design complexity, testing cost has increased dramatically.

Testing must be addressed early in the design process.

Design engineers must have good testing and design for testability knowledge.

Testing introduced in Computer & Electrical Engineering Curriculum in many universities• COE 464: Testing of Digital Circuits

• COE 571: Digital System Testing