The Anatomy of a Power MOSFET Dr. Phil Rutter

May 10th 2017IEEE Electron Devices Society Webinar

Dr. Phil RutterPowerMOS Technology Architect

nexperia.com2

Dr. Phil Rutter is the Power MOSFET technology architect at Nexperia and is based in Manchester, UK where has worked at since 1996. His career has involved a wide spectrum of power devices ranging from high voltage DMOS, SOI LDMOS, and GaNHEMTs, to low voltage Schottky diodes and trench MOSFETs. As manager of the Advanced Devices group he is currently responsible for developing next generation power MOSFETs with primary focus on voltages ≤100V. His research interests involve optimising both technology and design to specific applications, which arose from his team’s work in bringing the world’s first DrMOS product to market in 2004.

Phil gained a MEng in Electronics at Southampton University, UK in 1992 and was awarded, an MSc and PhD in Semiconductor Devices at University of Manchester in 1993 and 1995 respectively. He has co-authored many peer reviewed papers and currently holds 20 granted US patents. He is currently serving on the Low Voltage Technical Committee of the ISPSD and the program committee of the Power Supply on Chip Workshop.

Nexperia is a dedicated global leader in Discrete, Logic and MOSFET devices. We became independent from NXP Semiconductors at the beginning of 2017. Nexperia is headquartered in Nijmegen, The Netherlands and ships over 85bn products annually with revenues over 1.1 billion US$ (2016).

The aim of this Webinar is to:

•Understand what makes a high performing low voltage Power MOSFET

• What is important for the application?

• How does this impact the device structure?

• Examine performance indicators and their trade-offs

• How device design can impact performance

• What limits device performance, now and in the future?

• Focus on predominantly on n-channel 30V VDS

3. nexperia.com

Power MOSFET Market and Applications• Power MOSFET market ≈$6 billion (3.4% CAGR)1

• Approximately 40% of this market is in• Automotive (5% CAGR)• Computing & Storage

• ≤40V VDS is the largest voltage segment (≈40%)

• Many Low Voltage Power MOSFET vendors• Nexperia (formerly NXP Semiconductors)• Infineon (International Rectifier)• On Semiconductor (Fairchild)• Toshiba• Renesas• Vishay• Alpha & Omega Semiconductor• etc.

4. nexperia.com

1Yole Développement

Typical Power Distribution Architechture

5. nexperia.com

Power MOSFET Requirements: Or-ing• Or-ing application

• Allows for system to keep operating if one power supply fails

• MOSFET is permanently turned on• Only turned off if fault develops in the

power supply

• Low RDS(on) critical for application• All other parameters not important

Low Specific RDS(on) required

6.

Specific RDS(on) = RDS(on) Area

nexperia.com

Power MOSFET Requirements: Hot-Swap• Allows equipment to be added to a system without first removing power

• Low RDS(on) critical as like Or-ingdevice spends majority of its lifetime turned on

• But MOSFET switched on very slowly (≈1-100ms) to control inrush currents• Power MOSFETs vulnerable to thermal

runaway in these conditions

Low Specific RDS(on) required

Robust Linear Mode Capability

7. nexperia.com

Power MOSFET Requirements: Point of Load• POLs are high frequency DC-DC converters with two MOSFETs in a half bridge configuration

• Switching and RDS(on) are critical

• Important parameters includeSp.RDS(on)

QGRDS(on) ; QGD RDS(on) ; QOSS RDS(on) ; Qrr

QGD1/QGS1 (i.e. dVDS/dt immunity)Low VDS voltage overshootsLS (package source inductance)

8. nexperia.com

Start-stop System

Auxiliary Pumps / fans

Steering Systems Braking Systems

Hybrid DC-DC

Double Clutch

Efficient Alternator

Power MOSFET Requirements: Automotive• High Reliability (<1ppm failure rate)

• Wide range of operating temperatures

• High Level of Robustness & Reliability• Avalanche Ruggedness• Linear Mode Capability

• High Current Capability

• Applications predominantly involve Motor Control• Linear Mode Critical• Switching less important

9. nexperia.com

Power MOSFET Technology Considerations Many requirements, often conflicting!

10.

Energy Efficiency • Low RDSon• Low QGDRDS(on),, &• Low QGRDS(on)• Low QOSS RDS(on)• Low Qrr• Low Gate Resistance• Low Package Parasitics• Low Thermal Impedance

Cost• Low Sp.RDS(on)• Process Complexity• Yield• Choice of device structure• Optimising for application• Volume Manufacturing

Size• Low Sp.RDS(on)• Low Package Resistance• Die Design Efficiency• Small low profile packages• Package footprint:max diesize ratioQuality &

LegislationAEC-Q101 (Auto)

RoHS(e.g. Pb & Halogen Free)Defectivity Screens

(Zero Defects)

Robustness• High SOA (Linear Mode)• High avalance capability• High current capability• Low Voltage Overshoot• Gate Bounce Immunity (QGD1/QGS1)• ESD

nexperia.com

A Power MOSFET

nexperia.com

PACKAGE INTERCONNECT DIE DESIGN

STRUCTURE (& PROCESS)

Solderable Metal

Metallisation

Passivation

Substrate

MOSFET

11.

Through Hole

Packaging

nexperia.com12

Surface Mount Low Inductance Multiple Die Very Small

-5

0

5

10

15

20

25

250 275 300

Switc

h N

ode

Volta

ge (V

)

Silicon

Not applicablePackage

Circuit

Why Low Package Inductance?

• For discrete packages switching times are determined by total circuit & package inductance and COSS - not QGD!

• Further discussion on the effect of package source inductance can be found in [Elbanhawy 2003][Yang 2005][Black 2007]

What limits the switching speed of a power MOSFET?

nexperia.com13.

PSMN6R0-30YLD

RDS(on) 6.7mΩ

QGS2 1nC

QGD 1.8nC

QG(tot) 6.5nC

VGS(th) 1.8V

VGS(pl) 2.7V

VDS, VIN 12V

IG 1.5A

ID 15A

VG 5V

Lpackage 0.5nH

Ltotal 2.5nH

fosc 110MHz

𝑑𝑑𝐼𝐼𝐷𝐷𝑑𝑑𝑑𝑑

=𝐼𝐼𝐷𝐷 𝐼𝐼𝐺𝐺𝑄𝑄𝐺𝐺𝐺𝐺𝐺

≈ 45𝐴𝐴/𝑛𝑛𝑛𝑛

𝑑𝑑𝐼𝐼𝐷𝐷𝑑𝑑𝑑𝑑

=𝑉𝑉𝐺𝐺 − 𝑉𝑉𝐺𝐺𝐺𝐺(𝑝𝑝𝑝𝑝)

𝐿𝐿𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃≈ 4.5𝐴𝐴/𝑛𝑛𝑛𝑛

𝑑𝑑𝐼𝐼𝐷𝐷𝑑𝑑𝑑𝑑

=𝑉𝑉𝐼𝐼𝐼𝐼𝐿𝐿𝑇𝑇𝑇𝑇𝑇𝑇𝑃𝑃𝑝𝑝

≈ 4.8𝐴𝐴/𝑛𝑛𝑛𝑛𝑑𝑑𝑉𝑉𝐷𝐷𝐺𝐺𝑑𝑑𝑑𝑑

= 𝑉𝑉𝐼𝐼𝐼𝐼 2𝜋𝜋𝑓𝑓𝑇𝑇𝑜𝑜𝑃𝑃 ≈ 8.3𝑉𝑉/𝑛𝑛𝑛𝑛

𝑑𝑑𝑉𝑉𝐷𝐷𝐺𝐺𝑑𝑑𝑑𝑑

=𝑉𝑉𝐼𝐼𝐼𝐼 𝐼𝐼𝐺𝐺𝑄𝑄𝐺𝐺𝐷𝐷

≈ 10𝑉𝑉/𝑛𝑛𝑛𝑛

(1)

(2)

IOut

Switching waveform from a DC-DC Buck converter showing turn-on of the highside MOSFET

(1) dID/dt – current rises in the highside MOSFET

(2) dVDS/dt – voltage falls across the highside device

fosc is a function of COSS and total inductance

Package Integration• For significant improvements in switching performance to occur both

package and PCB inductance must reduce

• This is driving integration• DrMOS (Driver & MOSFETs) [Rutter 2006]

• Asymmetric Duals

• Embedded die etc.

• Example shown is an Asymmetric Dual (in half bridge configuration)• Gate loop is outside of main current path so no effect of LS on switching

• As current switches from HS to LS the di/dt cancels → effective inductance=0

• Input capacitors easily placed next to and under package for low inductive path within the PCB

14.

HS FET

Gate DriveReturnVIN

GND

S-Node

LS FET

HS current

LS current

nexperia.com

404

S-NodeVINGND

Lowside MOSFET (flipped) Highside MOSFET (flipped)

Passivation• Passivation Layer

• Buffer between the silicon die and package• Protects device from mechanical damage (e.g. scratches)• Contamination• Moisture & Corrosion

• Typically Consists of• A combination of Silicon Dioxide & Silicon Nitride and/or Polyimide

• However• Can be liable to cracking especially under temperature cycling• Can cause device failure if they propagate into the active device

15.nexperia.com

Passivation Cracks [Ackaert 2013 & 2015]

MetalPassivation

Passivation Cracks• Passivation cracks are due to mismatch of different materials

• Coefficient of Temperature Expansion (CTE)

• Young's modulus (E)

• Tends to occur at corners and edges of devices where thermomechanical stress is greatest

• Aluminium’s large CTE and low Young’s modulus means that under temperature cycling it deforms much more that the SiN passivation. Large stresses build up in the nitride until it cracks• Known as “ratcheting plastic deformation” [Huang 2000][Huang 2002][Zhang 2006]

• Stress builds up along the length of the nitride and most likely to occur where nitride covers large areas of metal rather than narrow tracks• Reduced nitride width, thicker nitride, and thinner metal help to minimise cracking

16.

[Ackaert 2001]

1

23

Device after temperature cyclingRegion 1: Large nitride overlap – Large cracksRegion 2: Wide metal track – Small cracksRegion 3: Narrow metal track – No cracks

[Yahya 2012 ]

nexperia.com

Strategies to Avoid Passivation Cracks• Narrow or passivation cracks slotted tracks [Zhang 2006]

• Use of polyimide [Qian 2007] [Alpern 2009]

• Improved metal edge profile [Ackaert 2011] [Ackaert 2015]

• Multilayer metal (Al/TiN/Al) [Alpern 2009]• But if metal too stiff, cracks in underlying TEOS can occur

• Trenches in Leadframe [Ackaert 2013]

17.

[Zhang 2006][Ackaert 2011] [Ackaert 2013][Ackaert 2015]

[Alpern 2009]

nexperia.com

Pattern Shift• A related issue is pattern shift

• Constant deforming of metal causes a physical shift in position of metal tracks• Passivation layer helps to reduce this effect• Large dies most susceptible• Slotted metal tracks advantageous (commonly used in power ICs)

18.

Example of pattern shift: Metal shift of ≈5µm following TMCL. Nitride layer severely cracked & Metal profile distorted

nexperia.com

Metallisation• Role of Metallisation

• Reduce spreading resistance

• Protect underlying structure from interconnect (clip attach & wirebond)

• Typically• AlSi

• For wider geometries, silicon helps prevent spiking; often TiN layer used as additional spiking barrier

• AlCu• Compatible with IC processes where Cu inhibits electromigration. Used in more advanced processes with W-plug

• Thickness ≈2µm to 6µm

• Additional Cu plating may be used

• Solderable top metal• TiNiVAg (sputtered); TiNiAg (evaporated)

• Ti and Ni provide adhesion to underlying aluminium; Ag prevents oxidation of the Ti & Ni and dissolves in the solder to form a high quality stable solder join

• Cu plating

• NiAu

19.

Damage to TiNW barrier layer leading to significant Al spiking from the AlCumetallisation

Example of wet etched Al with dry etched barrier layer

nexperia.com

Metallisation – High Current Avalanche• Key requirement in some automotive applications is high current avalanche

• Significant metal degradation observed under high current avalanche leading to increased RDS(on)

• Also observed in high current power cycling [DuPont 2007]

• Passivation can suppress effect [Bernoux 2009]

• Note other degradation mechanisms also occur due to hot carrier injection [Rutter 2009][Alatise 2010]

20.

[Martineau 2009]Testa 2008 [Alatise 2011]

nexperia.com

Split Gate with Schottky Diode

Device StructureThere are many different Power MOSFET Structures in use today….(VDS 25-40V)

nexperia.com21.

Split Gate

Split Gate withMOS Controlled Diode

High Cell Density Trench Superjunction Trench

1µm

Pseudo LateralD

LV Superjunction [Rutter 2011] Charge Balance [Goarin 2007]

Device Structure• RESURF technologies extensively used to achieve both low Sp.RDS(on) and switching FOMs

• Charge Balance most common <100V; Superjunction most common >400V

22.nexperia.com

• RESURF structures use capacitors that extend into the drift region

• The depletion of the drift region by these capacitors when drain voltage is applied increases the electric field throughout the drift region thereby increasing the breakdown voltage

• Thus for a given breakdown voltage rating a lower resistance drift region can be used

Switching FOM (QG)

23.

Cell Pitch

Rsubstrate ignored for simplicity; W=total channel width (i.e active area / cell pitch)

)()( DriftChannelGonDSG RRQRQ +ť

)(2 thGSoxnschannel VVCW

LR−⋅⋅⋅

≈µ

nsChannel

DriftonDSg

LRR

RQµ

2

)( 1

+ť

GSoxG VCWLQ ⋅⋅⋅⋅≈ 2

nexperia.com

• RDS(on) is the combination of the resistance of the channel i.e. (along the trench) and the resistance of the drift region, which is used to block voltage

• However, only the channel resistance contributes to gate charge, QG

• A low FOM requires a short channel length and a low drift resistance• RESURF devices have good FOM as they

achieve a low RDrift

DriftRegion

Ch

ann

el

L

Switching FOMs & Scaling

• If, for example, cell pitch is halved for a conventional device we can now fit two trenches into the same area therefore:• RChannel halves• QG doubles• Rdrift remains the same

• Therefore QG•RDS(on) increases• Low switching losses are not compatible with achieving low RDS(on)

by reducing cell pitch!

• Is this situation unavoidable?

24.

Cell Pitch ½ Cell Pitch

)()( DriftChannelGonDSG RRQRQ +ť

nexperia.com

Switching FOMs & Scaling - RESURF• RESURF Structures

• As cell pitch is reduced, the optimum doping in the drift region, Nopt, increases

• Therefore within a single cell RChannel, Rdrift, and QG

remain constant• QG•RDS(on) is maintained

• Sp.RDS(on) is reduced

• A reduction in channel length whilst reducing cell pitch would deliver an improvement in QG•RDS(on)

• Superjunction• Nopt≈ (cell pitch)-8/7

• Charge Balance• Nopt≈ (tox wmesa)-4/7

25.

ND 2ND

wmesa

tox

nexperia.com

Cell Pitch ½ Cell Pitch

nsChannel

DriftonDSg

LRR

RQµ

2

)( 1

+ť

Improving QG & QGD FOMs

• For QGD the gate to drain overlap is most critical as bottom of trench CGD is low due to thick oxide at bottom of trench (or converted to CGS in split-gate)

• Therefore trench depth control is a critical process step

• For QG there is the additional capacitances of CGS to the p-body and n+ source• CGS of p-body is ultimately limited by short channel effects

• CGS of n+ source is mainly process limitation

• Note split-gate structure converts CGD at bottom of trench to CGS. As there is no reduction of this capacitance with VDS then QG is higher for split gate but CGD/CGS ratio is improved

• Typically, due to current flow out of the channel there is always a trade-off between Sp.RDS(on) and QG / QGD FOM

26.

[Rutter 2010]

[Alatise 2011b]

nexperia.com

Importance of Sp.RDS(on) for Miniaturisation• The optimum RDS(on) is related to the trade-off of switching and conduction losses

• As QG & QOSS FOMs improve, the optimum RDS(on) for lowest efficiency reduces

• Low Sp.RDS(on) is important to ensure the optimum device can fit into the required footprint• Hence achieving low FOM by sacrificing RDS(on) is not always a good strategy!

27.

[Paolucci 2011]

Low

[Rutter 2011]

𝐴𝐴𝐴𝐴𝑑𝑑𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝑂𝑂𝑝𝑝𝑇𝑇 =𝐼𝐼𝑇𝑇𝑓𝑓

𝑆𝑆𝑆𝑆.𝑅𝑅𝐷𝐷𝐺𝐺(𝑇𝑇𝑜𝑜)

𝑄𝑄𝐺𝐺 𝐹𝐹𝑂𝑂𝐹𝐹 + 𝑄𝑄𝑂𝑂𝐺𝐺𝐺𝐺(𝐹𝐹𝑂𝑂𝐹𝐹)

nexperia.com

Gate Oxide• Balance between

• RDS(on) - thinner

• QG/QGD FOM – thicker (small effect)

• Reliability – thicker• Application dependent;

• +/-20V max most common

• Joins between different oxides and areas of thin oxide need attention• Local oxide thinning in these areas are usually limiting factor for gate breakdown

• Example shows 5mn thinner oxide at bottom of the gate (in a split-gate structure)

• Reliability• Wear-out of gate oxide occurs when operated with F-N tunnelling (≈0.7V/nm)

• Assuming Oxide screen at 80% of gate breakdown; Oxide breakdown of 1V/nm; Max field of 0.6V/nm• Require 2.1x Gate Rating of Oxide thickness (nm)

• More detailed assessment requires TDDB analysis (especially for Auto 0ppm)

28.

Tunnelling

Oxide Breakdown

Screening required to remove defectives for high quality levels

nexperia.com

TDDB• Detailed TDDB analysis is difficult for power devices due to thick oxide and long lifetime (especially on low test fields)

• Require combination of different stress fields and voltages

• Can predict oxide thickness needed for required quality level and application requirements

• ‘E’ model generally recommended [McPherson 1985]

29.

[Efthymiou 2015]

nexperia.com

Gate Oxide - ESD• The high input capacitance of Power MOSFETs means

ESD protection is not usually required

• As QG FOM reduces, ESD sensitivity increases

• ESD failure occurs when gate oxide is charged to its breakdown voltage

• 𝑉𝑉𝐸𝐸𝐺𝐺𝐷𝐷 ≈ 𝐵𝐵𝑉𝑉𝑇𝑇𝑜𝑜𝐶𝐶𝐼𝐼𝐼𝐼𝐼𝐼𝐶𝐶𝐸𝐸𝐼𝐼𝐸𝐸

+ 1 where CISS is at 0V, (CESD=100pF for HBM)

• CISS is related to QG FOM (where VDS=0V)• Best technologies are 20mΩnC

• Products > ≈6mΩ typical at VGS=4.5V estimated to be class 0 HBM (<250V)

• Current technologies are on the verge of becoming ESD sensitive for a number of applications previously considered to be ESD insensitive• ESD not usually quoted on datasheets

30.

ESD Fail – Single cell

HMB ESD Classification

10 15 20 25 30 35 400

250

500

750

1000

1250

15008mO6mO4mO2mO

QG*RDS(on) (RDS(on)@4.5V, QG @ VDS=0, VGS=4.5V)

Max

imum

HB

M E

SD V

olta

ge

CurrentBenchmark

Class 0

Calculation of minimum performance HBM. ESD performance as function of QG FOM (VDS=0V, VGS=4.5V).Assumptions:1) ESD limited by breakdown of the

gate oxide2) Worst case GOx is 80% of typical

BV of 34V

nexperia.com

Gate Resistance• Internal Gate Resistance is the most important aspect of the

design when designing for high switching efficiency• Poor design can lead to high switching losses [Lefebvre 2002]

• Poor design can make a great QGD FOM technology appear mediocre

• Internal metal busbars often used• Often conflicts with wiring & current spreading restrictions

• Silicided gate sometimes used but difficult to integrate

• Often L-C-R meters used to give ‘average’ RG for a datasheet• Does identify a ‘poor’ design with poor internal network

• Due to high CISS compared to LS phase angle is close to 90o, which may lead to errors in RG extraction

• Network Analyser gives more information

[Elferich 2005]

VNA measurements of designs in D2Pak with and without busbar with extracted network

31.nexperia.com

Silicided Gate for low RG. Needs recessed poly to prevent IGSS source shorts

[Moore 2016]

Gate Resistance• Simulated RC delay across a die showing ‘fast’ & slow parts of the die. At turn-on, device will act like a low

QGD MOSFET with negligible RG and switch quickly (up to inductance limit) increasing voltage overshoots. At turn-off device acts as if it has very large RG

• Use of busbars is essential to improve turn-off. Good design of internal RG network is arguably more important than low QGD FOM.

32.

1ns after 5V applied 1BB design already significantly above Vt

2.25 ns after 5V centre of no BB design just reaching Vt

nexperia.com

Gate Bounce (CdVDS/dt induced Turn-on)

• Fast transient on the drain gives rise to VGS spike (VGS on die not always indicative of VGS on die)• Capacitive Gate Bounce related to : QGS1/QGD1

• Inductive gate bounce: Ls, RG, QGS1

• See for example [Bai 2003][Black 2007][Tolle 2003]

• Reducing QG FOM by just reducing QGSincreases susceptibility to gate bounce

33.

[Bai 2003]

K=dVDS/dt

Example of gate bounce –observed in VDS waveforms by the change in slope of switch-node voltage

nexperia.com

COSS & Spiking• With RESURF structures, depletion regions form and grow quickly

• COSS becomes more nonlinear with voltage

• This amplifies voltage overshoots in the application• Spikes can easily exceed VDS rating of MOSFET when switching becomes

circuit inductance limited

• Solutions include• Add additional constant COSS [Rutter 2013]

• But impacts QOSS FOMs

• Introduce resistance in the source connection of a split-gate structure [Roig 2014][Chen 2015]

• But if too large can lead to gate turn on due to dVDS/dt[Nishiwaki 2014][Roig 2014]

34.

[Chen 2015]

nexperia.com

𝐶𝐶𝑂𝑂𝑆𝑆𝑆𝑆(𝑉𝑉𝐷𝐷𝑆𝑆) = 𝐶𝐶𝑂𝑂𝑆𝑆𝑆𝑆(𝑉𝑉𝐷𝐷𝑆𝑆 = 0𝑉𝑉) 𝐴𝐴𝑗𝑗

𝐴𝐴𝑗𝑗 + 𝑉𝑉𝐷𝐷𝑆𝑆𝑚𝑚

[Rutter 2013]

BV stability• A drawback of charge balance devices is that BVdss can be sensitive to

charge especially during avalanche

• Fixed oxide charge can either increase or decease BVdss depending on whether the drift region is under or over charged [Yedinak 2011]

• Instabilities due to edge termination design also occur and can cause BVdss to increase or decrease according to the amount of RESURF [Hossain 2014]

35.

a) b)

Comparison of device with and without instabilities measured on a curve tracer, in (b) it can be seen parts of device jumping in and out of avalanche [Yedinak 2011][Hossain 2014]

[Yedinak 2010]

nexperia.com

Body Diode Reverse Recovery• Reverse recovery charge is low in ≥30V MOSFETs due to thin epi and use of the body-effect [Dolny 2004][Lopez 2006]

• Qrr is datasheets is dominated by QOSS component. Stored charge, QS is small

• However, although small, and QS does contribute to voltage overshoots so needs to be minimised

• Schottky Diodes & Schottky-Like structures often used

• Drawback is higher leakage & increased active area• High leakage makes it more difficult to screen out manufacturing defects

• Generally sized to improve low load efficiency 5-10% area sacrificed

36.

Qs

Simulation of reverse recoveryQrr=14.7nC, only 3% (3.1nC) is stored charge, rest is QossExample of device with in built Schottky Diode

ActiveMOSFETSchottky

nexperia.com

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

0 5 10 15 20 25 30

PSMN4R0-30YLD IDSS@25CFDMS7672AS IDSS @ 25CBSC0904NSI IDSS @25C

VDS

I DSS

MOSFETs with Schottky

MOSFET without Schottky

Example of MOSFET using different gate oxide thickness for the ‘Schottky’ trench

Exploiting the Body Effect (1)• Body effect can be used to create a pseudo-Schottky diode, the thinner the

oxide the lower the Vf and Qrr [Williams 98]

• Significant improvement seen by using different gate oxide thicknesses for the MOSFET and Schottky [Häberlen 2015]

37.

[Hirler 2010]

[Elferich 2006]

nexperia.com

Diode current flow in a SJ MOSFET. Due to body effect, current is dominated by majority carrier channel current resulting in low stored charge

CurrentFlow

ElectronConcentration

Exploiting the Body Effect (2)• A similar effect can occur if VGS is

biased just below threshold rather than 0V [Elferich 2006]• This means if deadtime can be reduced to

zero, then stored charge can be eliminated

• Not everthing needs to be fixed in the silicon!• Concept used in MOSFET driver for PIP212-12M (DrMOS)

38.

[Elferich 2006] [Rutter 2006] Reducing deadtime to ensure 0<VGS<Vth reduces reverse recovery (Thick Blue trace)

0 10 20 30 40 50 60 70 8015

10

5

0

5

10

15

20

25 Turn On Power LossDeadtime 30= ns

Sync_FET 0.21= WCont_FET 0.31= W

Reduction 0= %

t [ns] 0 10 20 30 40 50 60 70 8015

10

5

0

5

10

15

20

25 Turn On Power LossDeadtime 14= ns

Sync_FET 0.14= WCont_FET 0.3= W

Reduction 16.8−= %

t [ns]

0 10 20 30 40 50 60 70 8015

10

5

0

5

10

15

20

25 Turn On Power LossDeadtime 10= ns

Sync_FET 0.09= WCont_FET 0.27= W

Reduction 31.9−= %

t [ns] 0 10 20 30 40 50 60 70 8015

10

5

0

5

10

15

20

25 Turn On Power LossDeadtime 4= ns

Sync_FET 0.01= WCont_FET 0.19= W

Reduction 62.2−= %

t [ns]

Linear Mode Operation• Power MOSFETs are vulnerable to thermal runaway when used in linear mode as operation is almost

always below the zero temperature coefficient (ZTC point) due to very high gain• See [Spirito 2002&05][Consoli 2000][Alatise 2010c][Dibra 2011][Ferrara 2013]

• Combination of low Sp.RDS(on) and high linear mode capability is required in applications like hotswap

39.

TVVV

LCWVV

TLCW

TI th

thGSox

thGSoxD

∂∂

•−⋅⋅⋅

−−∂∂

•⋅

=∂∂ )(2)( 2 µµ

th

DDS ZT

IV 1≤

∂∂ Stability Criteria

[Spirito 2005]

Large die with low cell density advantageous

[Chang 2016] Deterioration in Linear Mode capability for same die size vs technology progression

nexperia.com

Derating due to thermal runaway

ZTC

Safe Operating Area & Transfer Characteristic of PSMN6R0-30YLD

Linear Mode Failure on wirebondeddevice in high current part of die but away from the local cooling of the bondwires

Linear Mode Stability• Although vulnerable to thermal runaway a perfectly uniform device will be stable

• However local differences in Zth and small manufacturing variations will occur across a design

• Failures occur in areas with medium current density but poor local Zth

• Techniques to improve capability• Improve Zth: Copper metallisation, Thicker Package Heatsink, thinner wafers

• Reduce conduction in thermally poor areas of die [Zawischka 2015][Chang 2016]

• Reduced channel width; longer channel; increased drift resistance etc.

40.

GatePad

Current Flow Temperature

Hotspots vulnerable to linear mode failure

Electrothermal Simulation [Chang 2016]

nexperia.com

[Heuval 2003]

Cell Layout - Mobility• In VDMOS cellular cell structures, such as hexagonal, gives highest cell

density and lowest RDS(on) [Hu 1984].

• In a trench MOSFET, mobility (and therefore channel resistance) depends on the crystal plane [Yahata 1997][Heuval 2003]. • In a hexagon structure only two faces can have the optimum mobility

• Cellular structures have additional gate capacitance increasing QG &QGD FOM. But squares sometimes used for p-ch where RDS(on) main concern

• For trench devices silicon substrate is orientated so trenches horizontal and perpendicular to flat have 100 sidewall

41.

Test Pattern A aligned to 100Test Pattern B aligned to 110

AB

Vt Sp.RdsonVgs=4.5V

Sp.RdsonVgs=10V

A 1.57 4.7mΩmm2 4.4mΩmm2

B 1.6 7.8mΩmm2 6.4mΩmm2

Diff 2.9mΩmm2

(62%)2.0mΩmm2

(45%)

nexperia.com

[Su 2011]

Mobility Improvements• Good hygiene around the trench

• sacrificial rounding oxidations etc.

• Low epi doping in the channel• Epi doping in RESURF devices is high and needing even higher doping

to create the channel – mobility falls with the high doping concentrations used in RESURF devices

• Intrinsic cap layer [Su 2011]

• Use of ACCUFET structure [Katoh 2014]

• Strained Enhanced Mobility• In charge balance devices [Moens 2007] [Reggiani 2009]

• 20% reduction in drift resistance

• SiGe channel [Saxena 2008][Sun 2011]

• Alternate materials like GaAs

42.

[Katoh 2014]

[Sun 2011]

nexperia.com

Substrate• Substrates either Arsenic (2.5mΩ.cm - 1.8mΩ.cm) or Phosphorus (1.5mΩ.cm – 0.8mΩ.cm)

• Whilst Phosphorus substrates are lowest resistance they more problematical to use…..• Increased outdiffusion (> 10x Arsenic) that creates a portion of silicon higher resistance

• Possibility of defects for very low resistance Phosphorous substrates (<0.8mΩ.cm) but this also depends on epi thickness

• Increased risk of autodoping of during epi growth and other high temperature process

• Benefit of Phosphorus is small once wafers are background to 50µm due to lower outdiffusion resistance of Arsenic

43.

Outdiffusion of a highly doped Phosphorous substrate during processing of a Power MOSFET

Crystal defect that can occur with very high Phosphorous doping; these defects ultimately limit the lowest resistance achievable

Comparison of Arsenic & Phosphorous outdiffusion. Arsenic has lower outdiffusion resistance (simulated)

nexperia.com

• Backgrinding a technology with Sp.RDS(on) of 5mΩmm2 on a 150µm 1mΩ.cm Phosphorus substrate to 50µm gives a 25% reduction in Sp.RDS(on) and switching FOMs• Also improved Zth and energy handling

1. Temporary bonding on rigid carrier• Less mechanically stable, unsuitable for high temperature processing, sharp edges

• Increased cost of consumables

2. Taiko (‘drum’) process• Only grinds centre of wafer leaving ≈3mm rim around edge

• Aids mechanical stability for handling & back metal processing

• BUT suffers from reduced die per wafer due to the rim

• Thin wafer challenges• Wafer sawing / chipping [Bhadda 2012]

• Die pick-up (& die warp) [Abdullah 2012]

Wafer Thickness

44.nexperia.com

• Whilst ≈50µm wafer thickness is commonplace for low voltage MOSFETs, feasibility for much thinner substrates have been demonstrated• 20µm Taiko & 10µm direct bonding [Kohlmann 2009]

• 7µm & 50µm Cu plating on backside [Wang 2008/9]

• For very thin wafers a doubling of energy handling in avalanche has been reported (due to very low Zth) and a reduction in channel resistance of 16% due to stress enhance mobility [Wang 2009]

Wafer Thickness

45.

10µm via temporary bonding20µm Taiko[Kohlmann 2009]

nexperia.com

[Wang 2008]

Package Structure (& Process) Design

Excellence in all three are critical for success !!!

ConclusionA POWER MOSFET is combination of

nexperia.com46.

References

Further Reading• IEEE Transactions on Electron Devices – Special Issue on Power Semiconductor Devices and Smart Power IC Technologies, March 2017.

In particular:• “The Trench Power MOSFET: Part I—History, Technology, and Prospects”, Williams et al.• “The Trench Power MOSFET: Part II—Application Specific VDMOS, LDMOS, Packaging, and Reliability”, Williams et al.

nexperia.com48

http://assets.nexperia.com/documents/user-manual/nexperia-engineers-handbook.pdf

49.

Figures of Merit / Application

Rutter 2011 "Low voltage superjunction power MOSFET: An application optimized technology”; P. Rutter, S.T. Peake; APEC 2011, pp. 491-7

Paolucci 2011 “Advanced design for fast switching power MOSFETs”; M.Paolucci, J.Schoiswohl, L. Görgens; Educational Seminar, IEEE Applied Power Electronics Conference, 2011

Lopez 2011 “Voltage regulators for next generation microprocessors”; T. Lopez, R. Elferich, E. Alarcon, Springer 2011

Orabi 2008 “Coss Contribution to Synchronous Buck Converter Losses”; M. Orabi, A. Abou-Alfotouh, and A. Lotfi, PESC 2008

Reusch 2013 “Understanding the Effect of PCB Layout on Circuit Performance in a High Frequency Gallium Nitride Based Point of Load Converter”; D. Reusch and J. Strydom; APEC 2013

Elbanhawy 2003 “Effects of parasitic inductances on switching performance”; A. Elbanhawy; PCIM Eur., May 2003, pp. 251–255.

Yang 2005 “Effect and utilization of common source inductance in synchronous rectification”; B. Yang, J. Zhang; APEC’05, Mar. 2005, vol. 3, pp.1407–1411

Elferich 2006 “Impact of Gate Voltage Bias on Reverse Recovery Losses of Power MOSFETs”; R.Elferich & T.Lopez ; APEC 2006

Bai 2003 “Analysis of dv/dt Induced Spurious Turn-on of MOSFET”; Y. Bai, D. Pattanayak, A. Q. Huang; CPES Annual Seminar 2003

Black 2007 “Impact of Source Inductance on Synchronous Buck Regulator FET Shoot Through Performance”; A.G. Black; PESC 2008

Rutter 2006 “Design Considerations for Integrated Powertrains”; PwrSoc 2006

Tolle 2003 “De-embedding of reverse recovery losses in fast switching VRM applications”; T. Tolle; T. Duerbaum; R. Elferich; APEC 2003

nexperia.com

50.

Passivation

Huang 2000 “Thin film cracking and ratcheting caused by temperature cycling”; M. Huang and Z. Suo; J. Mater. Res., Vol. 15, No. 6, Jun 2000

Huang 2002 “Plastic ratcheting induced cracks in thin film structures”;M. Huang, Z. Suo, Q. Ma; Journal of the Mechanics and Physics of Solids 50 (2002) 1079 – 1098

Barti 2007 “USING SUBMODELING TECHNIQUE TO UNDERSTAND PASSIVATION CRACKS IN MICROELECTRONIC DEVICES Pre-processing with ANSA”; E. Barti, M. Stecher; 2nd ANSA & μETA International Congress, June 14-15, 2007 p241

Liu 2006 “Reliability Study of Interconnect Structures in IC Packages”; Yong Liu, Yumin Liu, Scott Irving, Timwah Luk and Don Desbiens; 7th. Int. Conf. on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems, EuroSimE 2006

Alpern 2009 “On the Way to Zero Defect of Plastic-Encapsulated Electronic Power Devices—Part I to Part III”; P. Alpern, P. Nelle, E. Barti, H. Gunther, A. Kessler, R. Tilgner, and M. Stecher; IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 9, NO. 2, JUNE 2009, p279, p269, & p288

Qian 2007 "Analysis of the Impact of Polyimide Coating on Passivation Reliability by Simulation” Q. Qian,Y. Liu, S. Irving, T. Luk; Electronic Components and Technology Conference, 2007, p264

Zhang 2006 “Methodology for Avoidance of Ratcheting-Induced Stable Cracking (RISC) in Microelectronic Devices”;Z. Zhang, Z. Suo,Y. Liu, S. Irving, T. Luk and D. Desbiens; 2006 Electronic Components and Technology Conference p1434

Ackaert 2011 “On the impact of the edge profile of interconnects on the occurrence of passivation cracks of plastic-encapsulated electronic power devices”; J. Ackaert, D. Vanderstraeten, B. Vandevelde; IEEE International Conference on IC Design & Technology (ICICDT) 2011

Ackaert 2015 “Metallization scheme optimization of plastic-encapsulated electronic power devices”; J. Ackaert; T. Colpaert; A. Malik; M. Gonzalez ; International Conference on IC Design & Technology (ICICDT) 2015

Ackaert 2013 "Impact of the leadframe profile on the occurrence of passivation cracks of plastic-encapsulated electronic power devices“; J. Ackaert, A. Malik, D. Vanderstraeten; International Conference on IC Design & Technology (ICICDT), 2013

nexperia.com

51.

High Current Avalanche Ruggedness

Dupont 2007 “Failure modes on low voltage power MOSFETs under high temperature applicationL. Dupont, S. Lefebvre, M. Bouaroudj, Z. Khatir, J.C. Faugieres”; Microelectronics Reliability 47 (2007) p1767–1772

Testa 2008 “Stress Analysis and Lifetime Estimation on Power MOSFETs for Automotive ABS Systems”; A. Testa, S. De Caro, S. Panarello, S. Patane; Power Electronics Specialists Conference 2008

Martineau 2009 “Characterization of ageing failures on power MOSFET devices by electron and ion microscopies”D. Martineau, T. Mazeaud, M. Legros, Ph. Dupuy, C. Levade, G. Vanderschaeve; Microelectronics Reliability 49 (2009) p1330–1333

Bernoux 2009 “Source electrode evolution of a low voltage power MOSFET under avalanche cycling”; B. Bernoux, R. Escoffier, P. Jalbaud, J.M. Dorkel; Microelectronics Reliability 49 (2009) 1341–1345

Rutter 2009 “High current repetitive avalanche of low voltage trench power MOSFETs”; P. Rutter, K. Heppenstall, A. Koh, G. Petkos, G. Blondel, ISPSD 2009, p112–115.

Alatise 2010a “Repetitive Avalanche Cycling of Low-Voltage Power Trench n-MOSFETs”;O. Alatise, I. Kennedy, G. Petkos, K. Heppenstall, K. Khan, J. Parkin A. Koh, & P. Rutter; Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2010

Alatise 2010b “The Impact of Repetitive Unclamped Inductive Switching on the Electrical Parameters of Low-Voltage Trench Power nMOSFETs”; O. Alatise, I. Kennedy, G. Petkos, K. Heppenstall, K. Khan, J. Parkin, A. Koh, P. Rutter; IEEE Transactions on Electron Devices 2010, Vol 57, Issue 7

Alatise 2011 “Reliability of Repetitively Avalanched Wire-Bonded Low-Voltage Discrete Power Trench n-MOSFETs”; O. Alatise, I. Kennedy, G. Petkos, and A. Koh; IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 11, NO. 1, MARCH 2011 p157

Bach 2012 “Failure Mechanisms of Low-Voltage Trench Power MOSFETs Under Repetitive Avalanche Conditions”; K. H. Bach, M. Asam, W. Kanert; ISPSD 2012 p. 113

Testa 2012 “A Reliability Model for Power MOSFETs Working in Avalanche Mode Based on an Experimental Temperature Distribution Analysis”; A. Testa,, S. De Caro, & S. Russo; IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 6, JUNE 2012 p3093

nexperia.com

52.

Structure

Yahya 2012 “Noble Failure Analysis Procedure for Trench MOSFET Technology Devices Through Detail Electrical Parameter Characterization and Unique Fault Isolation Technique”; A. K. Yahya, N. T. Yusof, Y. M. Yusof; IEEE IPFA, 2012

Chang 1991 “Trench gate structure with thick bottom oxide”; H.-R., Chang; U.S. Patent 4 992 390, Feb. 12, 1991

Darwish 2003 “A new power W-gated trench MOSFET (WMOSFET) with high switching performance,”; M. Darwish, C. Yue, K. Lui, F. Giles, B. Chan, K. Chen, D. Pattanayak,Q. Chen, K. Terrill, and K. Owyang; ISPSD, 2003, pp. 24–27.

Goarin 2007 “Split-gate Resurf Stepped Oxide (RSO) MOSFETs for 25V applications with record low gate-to-drain charge”; P. Goarin, R van Dalen, G.E.J.Koops, C. Le Cam, and J. Saby, ISPSD 2007, pp61-64

Alatise 2011b “Modeling the Impact of the Trench Depth on the Gate–Drain Capacitance in Power MOSFETs”; O. Alatise, N.-A. Parker-Allotey, M. Jennings, P. Mawby, I. Kennedy, and G. Petkos; IEEE ELECTRON DEVICE LETTERS, VOL. 32, NO. 9, Sept 201,1 p1269

Rutter 2010 “Low voltage TrenchMOS combining low specific RDS(on) and QG FOM”; P. Rutter; S. T. Peake ; ISPSD 2010

Shen 2004 “Lateral Discrete Power MOSFET: Enabling Technology for Next-Generation, MHz-Frequency, High-Density DC/DC Converters”; Z.J. Shen, D.N. Okada, F. Lin, S. Anderson, and X. Cheng, APEC, 2004

Rutter 2011 "Low voltage superjunction power MOSFET: An application optimized technology”; P. Rutter, S.T. Peake; APEC, 2011, pp. 491-7

Kawashima 2010 “Narrow-pitch n-channel superjunction UMOSFET for 40-60 V automotive application”; Y.Kawashima, H.Inomata, K.Murakawa, Y.Miura; ISPSD, 2010, pp329-332

Lopez 2006 "Reverse recovery in high density trench MOSFETs with regard to the body-effect“; T.Lopez, R.Elferich, N.Koper; ISPSD, 2006

Dolny 2004 “The influence of body effect and threshold voltage reduction on trench MOSFET Body Diode Characteristics”; G.M. Dolny , S. Sapp, A. Elbanhaway, C. F. Wheatley; ISPSD, 2004, pp217-220

Häberlen 2015 “95% DC-DC Conversion Efficiency by Novel Trench Power MOSFET with Dual Channel Structure to cut Body Diode Losses”; O. Häberlen, M. Pölzl, J. Schoiswohl, M. Rösch, S. Leomant, G. Nöbauer, W. Rieger; ISPSD 2015

Williams 1998 “PSEUDO-SCHOTTKY DIODE”; R. K. Williams, R. Blattner; US Patent 5,818084 1998

Hirler 2010 “Semiconductor Device and manufacturing method therefor”; F.Hirler US Patent 2010/0301410

nexperia.com

53.

Cell Layout / Mobility / Gate Resistance (1)

Hu 1984 "Optimum design of power MOSFET's“; C. Hu, M.-H. Chi, V.M.Patel; IEEE Transactions on Electron Devices, page(s): 1693 - 1700 Volume: 31, Issue: 12, Dec 1984

Heuvel 2003 “An improved method for determining the inversion layer mobility of electrons in trench MOSFETs”; M.G.L. van den Heuvel, R.J.E. Hueting, E.A. Hijzen and M.A.A. in't Zand; ISPSD 2003

Yahata 1997 “Exact evaluation of channel mobility for trench MOSFET using split C-V method”; A. Yahata , T. Inoue, H. Ohashi; Applied Surface Science 117/118 (1997) 181-186

Sun 2011 “Performance of Trench Power MOSFET With Strained Si/SiGe Multilayer Channel”;S. Sun; J.-S. Yuan; Z. J. Shen; IEEE Transactions on Electron Devices Year: 2011, Volume: 58, Issue: 5

Katoh 2014 “High channel mobility double gate trench MOSFET”; S. Katoh, Y. Kawaguchi, A. Takano; ISPSD 2014

Su 2011 “Investigation of performance optimized power Trench MOSFETs With Double-Epilayer”; X. Su, Q. Feng; International Conference on Advanced Power System Automation and Protection 2011

Moens 2007 “Stress-Induced Mobility Enhancement for Integrated Power Transistors”; P. Moens, J. Roig, F. Clemente, I. De Wolf, B. Desoete, F. Bauwens and M. Tack; IEDM 2007

Reggiani 2009 “Theoretical Analysis of the Vertical LOCOS DMOS Transistor with Process-induced Stress Enhancement”; S. Reggiani, M. Denison, E. Gnani, A. Gnudi, G. Baccarani, S. Pendharkar, R. Wise; European Solid State Device Research Conference, 2009. (ESSDERC '09), page(s): 161 - 164

Lefebvre 2002 “Influence of the Gate Internal Impedance on Losses in a Power MOS Transistor Switching at a High Frequency in the ZVS Mode”;S. Lefebvre et al., IEEE Trans. Power Electronics, vol 17, no 1, p33-39, 2002

Roig 2014 “Internal Self-Damping Optimization in Trench Power FETs for High-Frequency Conversion”; J. Roig et al; APEC 2014, p137-142

Chimento 2006 “Modelling and Simulation of Low-Voltage MOSFETs Accounting for the Effect of the Gate Parasitic-RC Distribution”; F. Chimentoet al.; Industry Applications Conference, 2006, p1443-1449

Nishiwaki 2014 “Design criteria for shoot-through elimination in Trench Field Plate Power MOSFET”; T. Nishiwaki, et al., ISPSD 2014, p382-385

nexperia.com

54.

Cell Layout / Mobility / Gate Resistance (2)

Elferich 2005 “Accurate Behavioural Modelling of Power MOSFETs Based on Device Measurements and FE-Simulations”; R.Elferich, T. Lopez, N. Koper; EPE 2005

Rutter 2013 “ Low Voltage MOSFET Optimized for low VDS Transient Voltages”; P.Rutter, S.Peake, A.Elford ; ISPSD 2013

Chen 2015 “Design Optimal Built-in Snubber in Trench Field Plate Power MOSFET for Superior EMI and Efficiency Performance”; J. Chen; SISPAD 2015

nexperia.com

Breakdown Instability

Yedinak 2010 “Optimizing Oxide Charge Balanced Devices for Unclamped Inductive Switching (UIS)”; J. Yedinak, D. Probst, G. Dolny, A. Challa, J. Andrews ; ISPSD 200

Yedinak 2011 “Avalanche Instability in Oxide Charge Balanced Power MOSFETS”; J. Yedinak, R. Stokes, D. Probst*, S. Kim*, A. Challa*, S. Sapp; ISPSD 2011

Boksteen 2015 “Impact of Interface Charge on the Electrostatics of Field-Plate Assisted RESURF Devices”; B.K. Boksteen, A. Ferrara, A. Heringa, P.G. Steeneken, and R.J.E. Hueting; IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 8, AUGUST 2014 p 2859

Hossain 2014 “Process & Design Impact on BVDSS Stability of a Shielded Gate Trench Power MOSFET”; Z. Hossain, B. Burra, J. Sellers, B. Pratt, P. Venkatraman, G. Loechelt, A. Salih; ISPSD 2014

Siemieniec 2006 “A New Fast and Rugged 100 V Power MOSFET”; R. Siemieniec; F. Hirler; A. Schlogl; M. Rosch; N. Soufi-Amlashi; J. Ropohl; U. Hiller; Power Electronics and Motion Control Conference, 2006. EPE-PEMC 2006.

55.

Linear Mode Operation

Consoli 2000 “Thermal instability of low voltage power-MOSFETs”; A. Consoli, F. Gennaro, A. Testa, G. Consentino, F. Frisina, R. Letor, and A. Magri; IEEE Trans. Power Electron., vol. 15, no. 3, pp. 575–581, May 2000.

Dibra 2011 “On the Origin of Thermal Runaway in a Trench Power MOSFET”; D. Dibra, M. Stecher, S. Decker, A. Lindemann, J. Lutz, and C. Kadow; IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 10, OCTOBER 2011

Spirito 2002 “Analytical model for thermal instability of low voltage power MOS and S.O.A. in pulse operation,” P. Spirito, G. Breglio, V. d’Alessandro, and N. Rinaldi; ISPSD 2002, pp. 269–272

Spirito 2005 “Modeling the Onset of Thermal Instability in Low Voltage Power MOS: an Experimental Validation” P. Spirito, G. Breglio and V. d’Alessandro; ISPSD 2005

Breglio 1999 “Electrothermal Instability in Low-voltage Power MOS: Experimental Characterization”; G. Breglio, F. Frisina, A. Magrì, and P. Spirito; ISPSD 1999, pp. 233-236

Alatise 2010c “Understanding Linear-Mode Robustness in Low-Voltage Trench Power MOSFETs”; O. Alatise; I. Kennedy; G. Petkos; K. Khan; A. Koh; P. Rutter ; IEEE Transactions on Device and Materials Reliability 2010

Ferrara 2013 “The Safe Operating Volume as a General Measure for the Operating Limits of LDMOS transistors”; A. Ferrara, P.G. Steeneken, A. Heringa, B.K. Boksteen, M. Swanenberg, A.J. Scholten, L. van Dijk, J. Schmitz, R.J.E. Hueting, IEDM 2013

Chang 2016 "Optimizing the Trade-Off Between the RDS(on) of Power MOSFETs and Linear Mode Performance by Local Modification of MOSFET Gain”; M-H Chang, P. Rutter; ISPSD 2016

Zawischka 2015 “Automatic Layout Optimization of DMOS Transistors for Lower Peak Temperatures and Increased Energy Capability”; T. Zawischkaet al.; ISPSD 2015, p.189-192

Chen 2012 W.-Y. Chen and M.-D. Ker, “Characterization of SOA in time domain and the improvement techniques for using in high-voltage integrated circuits”; IEEE Trans. Device Mater. Rel., vol. 12, pp. 382–390, Jun. 2012.

Jamborhazi 2015 “Effect of the trench depth on the linear mode capability of trench technologyMOSFETs”; S. Jamborhazi1, A. Czett1, M. Rencz; Thermenic 2015

nexperia.com

56.

Reliability

Yahya 2012 “Noble Failure Analysis Procedure for Trench MOSFET Technology Devices Through Detail Electrical Parameter Characterization and Unique Fault Isolation Technique”; A. K. Yahya, N. T. Yusof, Y. M. Yusof; IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) 2012

Efthymiou 2015 “A Methodology for Projecting SiO2 Thick Gate Oxide Reliability on Trench Power MOSFETs and its application on MOSFETs VGS Rating”; E. Efthymiou, P. Rutter, P Whiteley; Microelectronics, Dec 2015

McPherson 1985 “Acceleration factors for thin oxide breakdown”; J.W. McPherson and D.A Baglee; Journal of Electrochemistry Society., Vol. 132, p.1903. (1985)

Moore 2016 “Highly-Accelerated WLR Learning Cycles for Development of a Trench MOSFET: Method and Case Study”; D. Moore, G.D.R. Hall, M. Suzuki, P. Burke; IEEE International Reliability Physics Symposium (IRPS), 2016

Wafer Thinning

Kohlmann 2009 “Approaches to thin PowerMOS Wafers to less than 20 μm” K. Kohlmann, J. Burggraf; Proceedings of "be-flexible" workshop, 2009, Munich, Germany

Wang 2008 “Power Trench MOSFET Devices on Metal Substrates”; Q.Wang, M. Li, Y. Sokolov, A. Black, H. Yilmaz, J. V. Mancelita, and R. Nanatad; IEEE ELECTRON DEVICE LETTERS, VOL. 29, NO. 9, 2008

Wang 2009 "Enhanced electrical and thermal properties of trench metal-oxide-semiconductor field-effect transistor built on copper substrate”; Q. Wang , I. Ho and M. Li; IEEE Electron Device Lett. , vol. 30 , no. 1 , pp.61 -63 , 2009

Abdullah 2012 “Die Attach Capability on Ultra Thin Wafer Thickness for Power Semiconductor”;Z. Abdullah, L. Vigneswaran, A. Ang, G. Z. Yuan; Electronic Manufacturing Technology Conference, 2012

Dhadda 2012 “Processing of Ultrathin Wafers for Power Chip Applications”; A. Dhadda, R. Montgomery, P. Jones, J. Heirene, R. Kuthakis, F. Bieck; IEEE 14th Electronics Packaging Technology Conference 2012

nexperia.com