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Electromagnetic spectrum

COMINT & ELINT applications

All-to-all architecture

3U & 6U OpenVPX SIGINT reference designs

Future of multi-channel signal analysis

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DEFENSE SOLUTIONS TEC

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The Challenge of Monitoring the Modern SpectrumReal estate within the Electromagnetic Spectrum (EMS) has never been at a higher premium than today in terms of utilization per hertz per unit of geographical area. This trend will continue for the foreseeable future. Cooperative frequency allocation is in itself a big enough challenge, and contested EMS in not-so-friendly situations presents even greater challenges, especially given the lineup of sophisticated nation state competitors.

Physical payloads on standoff Intelligence, Surveillance and Reconnaissance (ISR) or Electronic Warfare (EW) platforms haven’t suddenly been afforded more volume, weight, and power. However, emitter signal density in active regions is higher than ever and the transmitted waveforms are more advanced than ever before in terms of their resiliency and evasiveness. Fortunately, technological innovation continues to do more with less. In this white paper, we will explore why yesterday’s solution falls short today, how technological advances in multi-channel signal analysis have provided new levels of RF emitter tracking, and how Curtiss-Wright Defense Solutions and DRS Signal Solutions plan to continue to break through game changing barriers.

Pervasive Coverage of the Electro Magnetic Spectrum with a next generation COMINT/ELINT Signal Analysis Methodology, the All-to-All Architecture

SATCOM

Ground Forces

Ground Station

Aircraft

New technologies enable deeper communication with All-to-All architecture

Yesterday’s Solution: Insufficient for today’s problemIn the not-so-distant past, super-heterodyne RF tuners designed for Signal Intelligence (SIGINT), specifically Communications Intelligence (COMINT) and Electronic Intelligence (ELINT) applications were available in 6U VME and 3U CompactPCI form factors. RF channel density for 6U VME cards was restricted to one or two channels, only covering a frequency range of 20 MHz to 3 GHz; and IF outputs were analog with a maximum 40 MHz instantaneous bandwidth. Digitization in an analog-to-digital converter (ADC) with associated processing would occupy another separate slot, further increasing system size and decreasing overall performance. Housing the tuners needed to cover the RF channels necessary for a minimum number of target emitters over a limited portion of the spectrum required a full-size chassis (or more).

Analog IF digitization often occurred on dedicated boards or mezzanine daughter cards with FPGAs performing digital down conversion (DDC) and/or Fast Fourier Transformation (FFTs). The cards would hand off their data to Single Board Computers (SBCs) or Digital Signal Processors (DSPs) for signal identification, geolocation, and additional information extraction. SBCs would usually house a single processor with a single CPU core, while DSPs could have as many as four processors. However, processing was often measured in MFLOPS or single digit GFLOPS totals. Operating systems were often proprietary Real-time Operating System (RTOS) software platforms. Digitized IF, processed data, and control was over proprietary, or even custom, digital protocols and transport media.

State-of-the-Art Multi-Channel Signal AnalysisFast-forward to 2017 and we observe great strides in terms of improved RF channel density given the same volume, weight, and power envelope. For instance, DRS Signal Solutions has released its Vesper SI-9173; shown in Figure 2. This 6U OpenVPX™ tuner has eight to 10 RF channels per slot while maintaining the same performance levels of narrowband systems. This is four to five times the capacity of previous solutions, while more than doubling the IF

instantaneous bandwidth (100 MHz). A transmit channel can also be realized within the same tuner adjacent to the receive channels. Finally, with up to five slots of LO distribution, the Vesper enables high channel count interferometry and time difference of arrival (TDOA) applications and techniques. For those applications where physical payload constraints dictate 3U OpenVPX, the 3U version of the Vesper realizes up to five RF channels per slot, 100 MHz IF IBW, and LO distribution of up to four slots. The 3U version of Vesper is configurable with up to four receive channels and a transmit channel if desired.

In addition to the greatly improved channel densities and bandwidth, digitization and associated processing are accomplished within the single slot Vesper tuner itself. The high bit resolution ADCs sample the analog IF from the multiple channels, and feed it into a large Xilinx FPGA (i.e. Virtex 7 690T) where digital down conversion or other digital signal processing functions can occur. The included Texas Instruments Keystone II DSP SoC can further aid in signal identification, and even perform demodulation. Packetized in the VITA-49 VRT standards-based format, these IF and baseband streams, can exit the tuner over 10 Gigabit Ethernet.

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Figure 2: DRS SI-9173 Vesper OpenVPX Tuner/Exciter

Figure 3: Curtiss-Wright CHAMP-XD2 Dual Xeon D OpenVPX Processor

Representing a similar quantum leap forward in terms of density and capability as with the Vesper, a comparable evolution has occurred within the CHAMP™ processor DSP modules from Curtiss-Wright. As an example, the CHAMP-AV4 VME board once boasted a total of 40 GFLOPS peak processing, produced by four 7448 PowerPCs, each with a single CPU core. Fast-forward to today, the CHAMP-XD2 OpenVPX board (shown in Figure 3) achieves 1,152 GFLOPS from two Intel® Xeon™ D processors, each with 12 cores. This represents over a 28x improvement. Memory capacity leaps forward from 2 GBytes of DDR on the CHAMP-AV4, to 64 GBytes of DDR4 on the CHAMP-XD2. Memory will prove critical in terms of supporting the increased channel count, and enabling the storing of longer snapshots in time. For example, having the capability to “reach back” and take a second look at an emitter or event that triggered significant interest. An alternate variant of the CHAMP-XD2, the CHAMP-XD2M, gives up one of the two Xeon D nodes for 128 GBytes of DDR4 for a single processor, thereby providing the extreme contiguous memory capacity required for even longer reach back time periods.

The DRS Vesper tuners output digitized IF and baseband over VITA-49 VITA Radio Transport (VRT) Ethernet packets. The CHAMP-XD2 also supports 10 or 40 Gigabit Ethernet over the OpenVPX data plane. An ideal third “building block” would have an OpenVPX switch that also speaks 10 and 40 Gigabit Ethernet over the OpenVPX data plane enabling extreme architectural flexibility when connecting Vesper tuners to CHAMP-XD2 Xeon D modules. The VPX6-6802 (shown in Figure 4) from Curtiss-Wright performs this role perfectly. High throughput, low latency VITA-49 VRT packets use a UDP RDMA based transport. The interconnect is

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highly flexible and is entirely based on standards including VITA-49, Ethernet, and Linux®, which runs on the CHAMP-XD2’s Xeon D nodes.

These three modules are ushering in a new generation of multi-channel signal analysis subsystems enabling higher levels of EMS coverage and simultaneously tracked emitters. Scalability exists across multiple leverage points including the number of RF channels, number of DSP processing cores, and between 3U and 6U OpenVPX form factors, all at a lower cost per channel than ever before. Next, let’s examine a superset architecture that uses these building blocks to their full potential in a full size OpenVPX chassis.

6U OpenVPX SIGINT “All-to-All” Reference DesignWe have examined the individual OpenVPX modules that represent the cutting edge of technology required for constructing a high channel count ELINT/COMINT system. Now, let’s examine an optimal architecture that maximizes a full 6U OpenVPX chassis. Refer to Figure 5 for a high level concept of the All-to-All Architecture. Sensors, such as the Vesper multichannel RF tuners/exciters, inject their IF/baseband results over a high rate, low latency multicast data fabric, which can then in turn forward the data from any RF channel to any processor core. Alternatively, and in unison, data can be routed to recorders for post mission analysis.

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Figure 4: Curtiss-Wright VPX6-6802 10/40 GigabitEthernet OpenVPX Switch

Figure 5: Curtiss-Wright VPX6-6802 10/40 GigabitEthernet OpenVPX Switch

Sensors Processors

Recorders

Recorders

Multicast Data

Fabric

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Let’s apply the previously introduced modules to this construct. Referring to Figure 6, six 9-Receiver (Rx) Channel Vesper tuners output their digitized IF/baseband using the VITA-49 VRT transport standard across their UDP/IP 10 Gigabit Ethernet links. The VPX6-6802 switch intercepts the 10 Gigabit Ethernet at which point it can route packets to any subset of endpoints via a multicast transmission. Endpoints include any combination of up to 12 Xeon D processors housed on 6 CHAMP-XD2 boards, in addition to 10 GigE SSD recorder channels. In effect, this All-to-All Architecture provides for complete interconnectivity between 54 RF receive channels and 144 Intel Xeon D processing cores all in a single OpenVPX chassis!

As displayed in Figure 6, two 6802 switches are required to complete the All-to-All interconnectivity. 10GbE ports are used for Vesper tuner ingest and 10GbE SSD recorder egress. 40GbE ports are used to connect all of the CHAMP-XD2 ports as well as the 40Gb Ethernet trunks between VPX6-6802 switches. The red arrows in the diagram provide an example where Ethernet channel #1 on Vesper Tuner #2 is multicast to all Xeon D processors across all CHAMP-XD2 Ethernet channels. In addition to Tuner ingest, the 40GbE CHAMP-XD2 links on the VPX6-6802s are also used for

all CHAMP-XD2 intercommunication, which is critical for algorithms where time correlated data and results need to be passed between Xeon D nodes. It should be noted the CHAMP-XD2s use the Mellanox® ConnectX®-3 protocol adaptors to convert 10/40 Gigabit Ethernet to/from PCI Express® (PCIe) Gen. 3, which is the Intel Xeon D’s native high speed fabric. The ConnectX-3 devices provide CPU offload and complex RDMA functionality, which effectively leaves the Xeon D cores unencumbered and focused on the application.

Given this hyper-interconnectivity, complex data flow, and 144 Intel cores across 12 Xeon D processors, the software infrastructure and development environment is particularly

Figure 6: All-to-All Data Flow Architecture Diagram

critical. Curtiss-Wright employs its OpenHPECTM Accelerator Suite, which leverages elite tools from the supercomputing world and embeds them into High Performance Embedded Computing (HPEC) applications such as the system above. High throughput, low latency, and determinism are all prerequisites of course. OpenHPEC’s great value lies in the coordination and arbitration of complex data flow paradigms. Standard middleware, such as Message Passing Interface (MPI), can be optimized by profiling and benchmarking using the latest in visualization techniques.

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3U OpenVPX SIGINT “All-to-All” Reference DesignAlthough 6U OpenVPX undoubtedly provides superior connectivity, there are many platforms with SWaP restricted payloads. In these cases, 3U OpenVPX is often the preferred solution. Both DRS Signal Solutions and Curtiss-Wright have 3U variants of their Vesper Tuner and CHAMP-XD products. Figure 7 demonstrates a 3U OpenVPX system with twenty RF channels and four D-1559 Xeon D processors that provide 32 AVX2 Intel cores in total. In this architectural example, the 3U Vesper tuners output their digitized IF over generation 3 PCIe to an associated Xeon D module, the CHAMP-XD1. All four CHAMP-XD1 modules are interconnected over 10Gb Ethernet to a centralized switch, the VPX3-687. This once again enables an All-to-All architecture in that all Xeon Ds can share IF, baseband, and processed data over low latency, high throughput, standard 10Gb Ethernet.

Analog RF

100Gb Ethernet

3U VPX3-68710GbE Switch

3U Vesper Tuner

Digitized IF x4 PCIe Gen 3

3U Champ-XD1 12c Xeon D

Figure 7: 3U OpenVPX Vesper - CHAMP System

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CURTISSWRIGHTDS.COM© 2017 Curtiss-Wright. All rights reserved. Specifications are subject to change without notice. All trademarks are property of their respective owners. W92.0317

Author

Marc Couture M.Eng,

Senior Product Manager,

Curtiss-Wright Defense Solutions

Conclusion The Future of Multi-Channel COMINT/ELINT Signal Analysis 2017 will be an exciting year for multi-channel signal analysis due to major strides in product development by Curtiss-Wright Defense Solutions and DRS Signal Solutions. Game changing barriers have been broken in terms of RF channel count, signal fidelity, bandwidth coverage, processing core count, and fabric interconnect flexibility. All of this has been achieved within the pre-existing confines of SWaP-C payload envelopes that remain unchanged.

DRS Signal Solutions and Curtiss-Wright are engaged on multiple joint efforts and programs together where these technologies will be integrated, characterized, and tested in both the 3U and 6U OpenVPX form factors, utilizing both air and conduction cooled thermal management methodologies. Extensive generic benchmark data will be generated in addition to the creation of demonstrator systems. Evaluation units and Quick Start Kits (QSKs) will be made available and discussed a follow-on white paper.

The Curtiss-Wright CHAMP-XD Xeon D Processors, coupled with DRS Vesper Tuners/Exciters, leverage open standards such as OpenVPX, Intel processing, Linux, Ethernet, and VITA-49 VRT to create a key capability in the EW and ISR arena, especially within COMINT/ELINT. EMS Spectrum dominance has never been more front and center for the war fighter and stand-off platforms. Omnipresent coverage and extreme flexibility will be required to adapt to an ever increasingly evolving theatre.

Middleware, such as Message Passing Interface (MPI), can be optimized by profiling and benchmarking using the latest in visualization techniques.

For the full list of 3U and 6U Vesper configurations, please contact SSsales@drs.com.

For the full list of 3U and 6U CHAMP-XD configurations, please contact us via the Curtiss-Wright website.

Learn moreProduct: CHAMP-XD2

Product: Vesper Family

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