the esa music project breadboard hw partitioning and asic design
DESCRIPTION
The ESA MUSIC Project Breadboard HW Partitioning and ASIC Design. Advanced Mobile Satellite Systems & Technologies presentation days ESA./ESTEC – 14-15 November 2000. Outline. MUSIC Receiver Implementation MUSIC RX FPGA Complexity FPGA Design Flow HW/SW Partitioning EC-BAID ASIC - PowerPoint PPT PresentationTRANSCRIPT
The ESA The ESA MUSICMUSIC ProjectProject
Breadboard HW Partitioning Breadboard HW Partitioning andand ASIC Design ASIC Design
Advanced Mobile Satellite Systems & Technologies presentation days
ESA./ESTEC – 14-15 November 2000
AMSST Presentation Days – 14-15 November 2000
Outline
• MUSIC Receiver Implementation– MUSIC RX FPGA Complexity– FPGA Design Flow– HW/SW Partitioning
• EC-BAID ASIC– ASIC Design Flow– ASIC Architecture– ASIC Features
AMSST Presentation Days – 14-15 November 2000
MUSIC RX Functional Block Diagram
ADCDCO
I
Q
N-stage Integrator
Decimation
In-Phase Front-End
N-stage Comb
Compensation Filter / CMF
CIC
fs fs fd fd=4R c
f ̂
N-stage Integrator
Decimation
Quadrature Front-End
N-stage Comb
Compensation Filter / CMF
CIC
fs fs fd
fs
fs
2
n s=4
Interp.
n s=2
2R c
fd=4R c 2
n s=4
Interp.
n s
2R
I/Q Soft DataL
CCTU
CCAU
Prompt-I
Prompt-Q
E/L-I
E/L-Q
E/L
EC-BAID Unit
I/Q Correlator
FED
Pilot Channel Code
Traffic Channel Code
Demux-I
Demux-Q
Rc
Rc
Rs
Rs
SNIR Estimation
SNIRRs
Symbol Start
Signal Detect / Demod. Enable
AFC Loop Filter
Int. Clock 8Rc
IF Input
fIF=70 MHz
Rc
Rc
Rc
Code epoch
Sync AGC
Symb. Clock
BER Measurem.
P Interface
BER
fs
IFd=4.464 MHzf
AMSST Presentation Days – 14-15 November 2000
MUSIC RX Implementation
FLEX10K100ACPLD
ST18952RAM FLASH
RAM
MAX7032
JTAGRESET
VCXO
DIG.INP. CON 24SIMM xRAM
78S05
78S05
LM317T
LM317T
+12 V +5 V
CON 40 CON 40
ICD2053BProg.CLK
AD5323DAC
CY7B991ROBOCLK
CON40
CON40
CON40
CON 40
CON40
CON40
OPA2681
OPA2681
ADS807ADC
TL7702 POR
LED
ADS807ADC
74LCX245BUFFERS
74LCX245BUFFERS
74LCX245BUFFERS
ICD2053BProg.CLK
FLEX10K100ACPLD
TO LOGICANALYZER
TO LOGICANALYZER
EXT. BOARD PROG.CON 8
BIT BLASTER
CON 10
AGC1 VC
AGC2 VC
IF / I IN
Q IN
AD5323DAC
AFC VC
EXT. CLK
QS3238BUS SW
LEDLED LED LEDLED LED
EXT. CLK
AMP. & ADC
BUFFERING
MASTER CLK GEN.
LOGIC100K Gates CPLD
ANALOGAGC
POWER SUPPLY & P-ON RESET
LOGIC100K Gates CPLD
DSP + Glue Logic
MEMORY Extension (SRAM or DRAM)
AD S807
FPGAs - ALTERA 10K100
ST 18952 DSP
ASIC
ADCDCO
I
Q
N-stage Integrator
Decimation
In-Phase Front-End
N-stage Comb
Compensation Filter / CMF
CIC
fs fs fd fd=4R c
f ̂
N-stage Integrator
Decimation
Quadrature Front-End
N-stage Comb
Compensation Filter / CMF
CIC
fs fs fd
fs
fs
2
n s=4
Interp.
n s=2
2R c
fd=4R c 2
n s=4
Interp.
n s
2R
I/Q Soft DataL
CCTU
CCAU
Prompt-I
Prompt-Q
E/L-I
E/L-Q
E/L
EC-BAID Unit
I/Q Correlator
FED
Pilot Channel Code
Traffic Channel Code
Demux-I
Demux-Q
Rc
Rc
Rs
Rs
SNIR Estimation
SNIRRs
Symbol Start
Signal Detect / Demod. Enable
AFC Loop Filter
Int. Clock 8Rc
IF Input
fIF=70 MHz
Rc
Rc
Rc
Code epoch
Sync AGC
Symb. Clock
BER Measurem.
P Interface
BER
fs
IFd=4.464 MHzf
AMSST Presentation Days – 14-15 November 2000
AD S807
FPGAs - ALTERA 10K100
ST 18952 DSP
MUSIC RX Implementation (Intermediate)
ADCDCO
I
Q
N-stage Integrator
Decimation
In-Phase Front-End
N-stage Comb
Compensation Filter / CMF
CIC
fs fs fd fd=4R c
f ̂
N-stage Integrator
Decimation
Quadrature Front-End
N-stage Comb
Compensation Filter / CMF
CIC
fs fs fd
fs
fs
2
n s=4
Interp.
n s=2
2R c
fd=4R c 2
n s=4
Interp.
n s
2R
I/Q Soft DataL
CCTU
CCAU
Prompt-I
Prompt-Q
E/L-I
E/L-Q
E/L
EC-BAID Unit
I/Q Correlator
FED
Pilot Channel Code
Traffic Channel Code
Demux-I
Demux-Q
Rc
Rc
Rs
Rs
SNIR Estimation
SNIRRs
Symbol Start
Signal Detect / Demod. Enable
AFC Loop Filter
Int. Clock 8Rc
IF Input
fIF=70 MHz
Rc
Rc
Rc
Code epoch
Sync AGC
Symb. Clock
BER Measurem.
P Interface
BER
fs
IFd=4.464 MHzf
AMSST Presentation Days – 14-15 November 2000
MUSIC RX FPGA Design FlowRequirement
FORTRANFloating Point Model
FORTRANSimulation
FORTRANTest Bench
OK?yes
no
FORTRANBit True Model
FORTRANSimulation
OK?yes
no
VHDLRTL Model
VHDLSimulation
OK?yes
no
Macro Cell (RAM, ROM)VHDL Model
VHDLTest Bench
VHDLRTL Model
LogicSynthesis
VHDL FPGAGate Level Netlist
VHDL Gate LevelSimulation
OK?yes
no
OK?yes
no
Device Programming
VHDL Test Bench
ALTERA Library
Synthesis Constraints
ALTERA Library
Device Fitting
Interconnection Delay
VHDL FPGAGate Level Netlist
VHDL Gate LevelSimulation
OK?yes
no
VHDL Test Bench
ALTERA Library
AMSST Presentation Days – 14-15 November 2000
MUSIC RX FPGA Complexity
Circuit LC EABFront-End 3341 0Interp 433 0DCO 40 2Master 66 0DSP/IF_1 154 0DSP/IF_2 289 0Debug 310 0CTAU 1262 3CCTU 1546 0AFC 640 0AGC 1018 0EC-BAID 6098 16Total cell count 15530 21
Altera 10K100A LC EAB4992 12
AMSST Presentation Days – 14-15 November 2000
MUSIC RX FPGA Partitioning1st CPLD LC EABFront-End 3241 0Interp 433 0DCO 40 2AFC 640 0Master 66 0DSP/IF_1 154 0Total cell count 4574 2Utilization 91% 14%
2nd CPLD LC EABCTAU 1262 3CCTU 1546 0Debug 310 0AGC 1018 0DSP/IF_2 289 0Total cell count 4425 3
PRO
TEO
#1
Utilization 88% 23%
3rd CPLD LC EABEC-BAID_1 2728 12Total cell count 2728 12Utilization 54% 95%
4th CPLD LC EABEC-BAID_2 3370 4Total cell count 3370 4PR
OTE
O #
2
Utilization 67% 22%
Altera 10K100A LC EABAvailable Cell 4992 12
AMSST Presentation Days – 14-15 November 2000
MUSIC RX Implementation (Intermediate)
AD S807
FPGAs - ALTERA 10K100
ST 18952 DSP
1st
2nd
3rd/4th
ADCDCO
I
Q
N-stage Integrator
Decimation
In-Phase Front-End
N-stage Comb
Compensation Filter / CMF
CIC
fs fs fd fd=4R c
f ̂
N-stage Integrator
Decimation
Quadrature Front-End
N-stage Comb
Compensation Filter / CMF
CIC
fs fs fd
fs
fs
2
n s=4
Interp.
n s=2
2R c
fd=4R c 2
n s=4
Interp.
n s
2R
I/Q Soft DataL
CCTU
CCAU
Prompt-I
Prompt-Q
E/L-I
E/L-Q
E/L
EC-BAID Unit
I/Q Correlator
FED
Pilot Channel Code
Traffic Channel Code
Demux-I
Demux-Q
Rc
Rc
Rs
Rs
SNIR Estimation
SNIRRs
Symbol Start
Signal Detect / Demod. Enable
AFC Loop Filter
Int. Clock 8Rc
IF Input
fIF=70 MHz
Rc
Rc
Rc
Code epoch
Sync AGC
Symb. Clock
BER Measurem.
P Interface
BER
fs
IFd=4.464 MHzf
AMSST Presentation Days – 14-15 November 2000
PROGRAMMINGFLAT CABLE
CONNECTIONBY FLAT CABLE
1st CPLD 2nd CPLD 3rd CPLD 4th CPLD
PROTEO #1 PROTEO #2
MUSIC RX Implementation (Intermediate)
AMSST Presentation Days – 14-15 November 2000
1st CPLD
2nd CPLD
3rd CPLD
4th CPLD
PROTEO #1
PROTEO #2
AMSST Presentation Days – 14-15 November 2000
MUSIC RX Implementation (Final)
PROGRAMMINGFLAT CABLE
EC-BAID
extra CPLD
CONNECTIONBY FLAT CABLE
1st CPLD 2nd CPLD EC-BAIDASIC
PROTEO #1EC-BAIDBOARD
AMSST Presentation Days – 14-15 November 2000
EC-BAID ASIC Design FlowRequirement
FORTRANFloating Point Model
FORTRANSimulation
FORTRANTest Bench
OK?yes
no
FORTRANBit True Model
FORTRANSimulation
OK?yes
no
VHDLRTL Model
VHDLSimulation
OK?yes
no
Macro Cell (RAM, ROM)VHDL Model
VHDLTest Bench
VHDLRTL Model
LogicSynthesis
Synthesis Constraints
VHDL Gate Level Netlist
VHDL Gate LevelSimulation
ST HCMOS7 Library
OK?yes
no
OK?yes
no
EC-BAID ASIC Back-End
VHDL Post-LayoutSimulation
OK?yes
no
EC-BAID ASIC Foundry Run
VHDL Test Bench
ST HCMOS7 Library
VHDL Test Bench
ST HCMOS7 Library
Parasitic Delay
AMSST Presentation Days – 14-15 November 2000
The MUSIC core: EC-BAID 1/3
AMSST Presentation Days – 14-15 November 2000
The MUSIC core: EC-BAID 2/3
eTee
Lb yxc
11
11
eeT
ee
Lrr
rbrr
1
ee ccyy
xx
1*
*
111
)1()1(
)1()()1(
011 eTe xc
AMSST Presentation Days – 14-15 November 2000
Correlation Receiver
The
MU
SIC
cor
e: E
C-B
AID
3/3
1/Tc
1/Ts
1/Ts
yie
c1,i
1/Tc
L
1
L3
1
3/Tc
1/Ts
+
+
3/Tc
3/Tc
3/T
MUX3
MUX2
b1
AGCloop
( )*.
b1'
3/Tc
memcontrol
muxcontrol
1/Ts
3/Tc
+-
(1-F)
c1,i
1/Ts
3/Tc
3/Tc
x1,wn.o. x1,w
+ -+ +
( )x1,wn.o. · c1
Lc1,i
hardware-multiplexing area
Y RAM
128 x 42
X RAM
384 x 46
AMSST Presentation Days – 14-15 November 2000
0.001
2
3
4567
0.01
2
3
4567
0.1
2
3
4567
1
BE
R
109876543210
Eb/N0 (dB)
WH+E-GOLDL=32N=16
C/I = -6 dB Unif. Asynch. MAI
EC_BAID: = 2-13
WLEN = 2trans / tx = 20 / 70 Ksymb.
EC-BAID (floating point)
EC-BAID (bit true)
EC-BAID Bit-true Simulation
• WH=E-GOLD sequences
• L=32
• ideal chip timing and carrier
frequency/phase recovery
• asynchronous MAI with evenly-distributed
delays on one symbol period
• adaptation step = 2-13 or 2-15
• N=L/2 active users with C/I=-6 dB each
AMSST Presentation Days – 14-15 November 2000
Shortened Programmable Observation Window
Optimization of the EC-BAID: Window Length 1/2
y1y0y-1
Maximum Observation Window (3L chips)
wC wC
AMSST Presentation Days – 14-15 November 2000
Optimization of the EC-BAID: Window Length 2/2
10 -5
10 -4
10 -3
10 -2
10 -1
10 0
BER
4.03.53.02.52.01.51.00.50.0
W
K=10Eb/N0=8dB
=6 10-4
=3 10-4
=1 10-4
=5 10-5
Optimum Length: 2 symbol intervals (0.5+1+0.5)
AMSST Presentation Days – 14-15 November 2000
0.0001
0.001
0.01
0.1
1
BE
R
10008006004002000
Normalized Time (KSymbols)
timing error = 0 timing error = -0.05 Tc
L = 64, N = 32 C/I = -6 dB
unif. Asynchr. MAI Eb / N0 = 10. dB
BAID = 2-13
The EC-BAID Long-term BER Drift
AMSST Presentation Days – 14-15 November 2000
Adaptive EC-BAID with Leakage
kBAIDkk exx 1
kBAIDkk exx 1
Standard EC-BAID
x k1 1 BAID xk BAIDek
Leakage factor
EC-BAID with Leakage
AMSST Presentation Days – 14-15 November 2000
0.001
2
3
4567
0.01
2
3
4567
0.1
BE
R
-20 -19 -18 -17 -16 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0
Log2(Lfactor)
timing error = -0.05 T c NO timing error Theory (NO timing error & NO leakage)
L = 64, N = 32, C/I = -6 dBunif. Asynch. MAI
BAID= 2-13
Leak = (1 - Lfactor BAID)tran / tx = 500 / 1000 KSymb.
Leak Factor Optimization
AMSST Presentation Days – 14-15 November 2000
ST HCMOS7 0.25 m Technology
• Key Features
– 2.5 V operating voltage, 3.3 V I/O
– Gate Density: 35 Kgates/mm2
– 500 MHz systems clock
– 6 levels of metal with minimum enclosures, stacked contacts and VIAs
– Ultra low power dissipation: 0.1 W/MHz/gate/std load
– In production since June 1998
AMSST Presentation Days – 14-15 November 2000
EC-BAID ASIC Results
Max Clock Frequency 40 MHzMax Chip Rate 5 Mchip/s
Gate complexity 27 Kgates
Macro CellRAM 384 46 = 17664 bit
RAM 128 43 = 5504 bit
Fault coverage 96.19 %
Core Area 1.3 mm2
Estimated PowerConsumption @ 16 MHz 45 mW
Number of input/outputdata pins 47 pins
ASIC Package 64 TQFP
AMSST Presentation Days – 14-15 November 2000
EC-BAID ASIC pinout
1
1
7
Enable_8Rc
Reset_N
BAID_sym_en
Prompt_I
Prompt_Q
1
7
fs
fs
8Rc
4BAID_Q
4BAID_I
Rs
Rs
1Symb_strobe
Rs
1CPRU_lock
L_se
l
Test
_En
3
Gam
ma_
BA
ID
2 1
Par
am
Rac
k
Req
Bac
t
1 1 1 1
Test
_In
1
4CR_Q
4CR_I
Rs
Rs
Clockfsa
1 STM & TEAM
EC-BAID
INPUTSYNC.
INPUTDATA
CONFIG TESTING
OUTPUTDATA
OUTPUT SYNC.MONITOR
AMSST Presentation Days – 14-15 November 2000
EC-BAID ASIC pinout cont.Name IN/OUT From/To #bit Rate Description
Clock In Clock generator 1 fsa Master Clock (fsa=16.384 MHz)
Enable_8Rc In Master control 1 8Rc Static 8Rc Enable Strobe
Reset_N In Master control 1 Global Reset (active low)
BAID_symb_en In CCTU 1 Rs Start of Symbol Strobe
INPUTSYNC.
Prompt_I In Interpolator 7 Rc Prompt In-Phase signal
Prompt_Q In Interpolator 7 Rc Prompt In-Quadrature signalINPUTDATA
Bact In N.C. 1 Bist Activate
Test_In In N.C. 1 Test Input
Test_En In N.C. 1 Test Enable
TESTING
Gamma_BAID In Master Control 3 EC_BAID Control Loop
L_sel In Master Control 2 Code Length Select
Param In DSP 1 Serial Transmission Data
Req In DSP 1 Serial Trasmission Request
Rack Out DSP 1 Serial Trasmission Acknowledgement
CONFIG.
BAID_I Out DSP 4 Rs In-phase soft output ( EC_BAID )
BAID_Q Out DSP 4 Rs In-quadrature soft output ( EC_BAID )
CR_I Out DSP 4 Rs In-phase soft output ( CR )
CR_Q Out DSP 4 Rs In-quadrature soft output ( CR )
OUTPUTDATA
Symb_Strobe Out DSP 1 RsOutput Symbol Strobe OUTPUT
SYNC.CPRU_lock Out DSP 1 CPRU Lock Flag MONITOR
AMSST Presentation Days – 14-15 November 2000
EC-BAID ASIC Layout
RAM384 x 46
RAM128 x 43
2
mm2
AMSST Presentation Days – 14-15 November 2000
EC-BAID ASIC Main Features• Robust Blind Interference Mitigation Detector ASIC
– Programmable Code Length: L=32, 64 and 128– 5 Mchip/sec Maximum Chip Rate– Programmable Convergence Speed– Low complexity: 27 Kgates + 23 Kbit RAM– Low power consumption: 45 mW @ 16 MHz clock - 2 Mchip/s– Reduced I/O pin number: 47
• Embedded Phase Recovery Unit– Switchable on/off– Programmable Loop Filter Parameters (BW and DF)– Programmable Lock Detector
• ASIC Design-reuse approach allows for:– re-design to meet other system specification: higher chip rates,
different I/O interfaces, etc.– re-targeting to different silicon technologies as ASSP– integration in more complex System-on-Chip design