the essence of polis/felix/vcc project: virtual component co-design
DESCRIPTION
1988:. The Essence of Polis/Felix/VCC Project: Virtual Component Co-design. 1. 2. System Behavior. System Architecture. Describe & verify product behavior Describe product architectures Explore HW/SW design tradeoffs Map behavior to architecture Use performance simulation - PowerPoint PPT PresentationTRANSCRIPT
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Describe & verify product behaviorDescribe & verify product behavior Describe product architecturesDescribe product architectures Explore HW/SW design tradeoffsExplore HW/SW design tradeoffs
Map behavior to architectureMap behavior to architecture Use performance simulationUse performance simulation Perform communication refinementPerform communication refinement
Integrated flow to implementation Integrated flow to implementation
SystemSystemBehaviorBehavior
SystemSystemArchitectureArchitecture
MappingMapping
Flow To ImplementationFlow To Implementation
CommunicationRefinement
BehaviorBehaviorSimulationSimulation
PerformancePerformanceSimulationSimulation
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3
4
The Essence of Polis/Felix/VCC Project: Virtual The Essence of Polis/Felix/VCC Project: Virtual Component Co-designComponent Co-design
1988:1988:
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The next level of Abstraction …The next level of Abstraction …
abst
ract
Transistor ModelCapacity Load
1970’s
cluster
abst
ract
Gate Level ModelCapacity Load
1980’s
RTL
cluster
abst
ract
SDFWire Load
1990’s
IP Blocks
cluster
abst
ract
IP Block PerformanceInter IP Communication Performance Models
RTLClusters
SWModels
Year 2000 +
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Architectural ChoicesArchitectural Choices
P
Prog Mem
MACUnit
AddrGenP
Prog Mem
P
Prog Mem
SatelliteProcessorDedicated
Logic
Satellite
Processor
SatelliteProcessor
GeneralPurpose
P
Software
DirectMapped
Hardware
HardwareReconfigurable
Processor
ProgrammableDSP
Flex
ibili
tyFl
exib
ility
1/Efficiency (power, speed)1/Efficiency (power, speed)
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OMAP™ Block DiagramOMAP™ Block Diagram
I-MMU D-MMU
I-Cache
RISC Core
MMU
I-Cache Internal RAM/ROM
DSP Core+
Appl Coprocessors
DMA
Memory & Traffic Controller
ProgramMemory SDRAM
PeripheralsLCD Controller, Interrupt Handlers, Timers, GPIO, UARTs, ...
ARM9 coreARM9 core
16KB I-cache16KB I-cache
8KB D-cache8KB D-cache
2-way set 2-way set associativeassociative
150 MHz150 MHz
C55x DSP coreC55x DSP core
16KB I-cache16KB I-cache
8KB RAM set8KB RAM set
2-way set 2-way set associativeassociative
200 MHz200 MHz
D-Cache
55
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Hardware Platforms Not Enough!Hardware Platforms Not Enough!
Hardware platform Hardware platform has to be abstractedhas to be abstracted
Interface to the application software is the Interface to the application software is the “API”“API”
Software layer performs abstraction:Software layer performs abstraction:Programmable cores and memory subsystem “hidden” Programmable cores and memory subsystem “hidden”
by RTOS and compilersby RTOS and compilersI/O subsystem with Device DriversI/O subsystem with Device DriversNetwork with Network Communication SoftwareNetwork with Network Communication Software
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Software PlatformsSoftware Platforms
Output DevicesInput devicesHardware Platform
I OHardware
Software
network
Software Platform
Application SoftwarePlatform API
API
RTOS
BIOSDevice Drivers
Netw
ork
Com
mun
icat
ion
Comp iler
88
MiddlewareJavaTV, TVPAK, OpenTV, MHP/Java, proprietary ...
Applications
Nexperia HardwareNexperia Hardware
Streaming andStreaming and Platform SoftwarePlatform Software K
erne
l: pS
OS
, Win
-CE
, Ja
vaO
S
Nexperia-DVP SoftwareNexperia-DVP Software
Nexperia™ -DVP Software ArchitectureNexperia™ -DVP Software Architecture Supports multiple OSs and Supports multiple OSs and
middleware softwaremiddleware software Abstracts platform functionality via Abstracts platform functionality via
consistent APIsconsistent APIs
Nexperia™-DVP Streaming SoftwareNexperia™-DVP Streaming Software Encapsulates implementation of Encapsulates implementation of
streaming media components streaming media components (hardware and software)(hardware and software)
Nexperia™ Platform SoftwareNexperia™ Platform Software OS independent device drivers for on-OS independent device drivers for on-
chip and off-chip deviceschip and off-chip devices
99
HW layer
SW Platform layerSW Platform layer(> 60% of total SW)(> 60% of total SW)
Application Platform layerApplication Platform layer((10% of total SW)10% of total SW)
Controllers Library
OSEKRTOS
OSEKCOM
I/O drivers & handlers(> 20 configurable modules)
Application Programming Interface
Boot Loader
Sys. Config.
Transport
KWP 2000
CCP
ApplicationSpecificSoftware
Speedom
eterTachom
eterW
ater temp.
Speedom
eterTachom
eterO
dometer
---------------
ApplicationLibraries
Nec78k HC12HC08 H8S26 MB90
SW SW Platform Platform ReuseReuse> 70%> 70%
of total SWof total SW
CustomerLibraries
MOSAIC SW Architecture & Components for Automotive Dashboard and Body Control
1010
PlatformsPlatforms
PlatformDesign-Space
Exploration
PlatformSpecification
Architectural Space
Application Space
Application Instance
Platform Instance
SystemPlatform
1111
PlatformsPlatforms
A platform is, in general, an abstraction that covers a A platform is, in general, an abstraction that covers a number of possible refinements into a lower level. number of possible refinements into a lower level. For For every platform, there is a view that is used to map the every platform, there is a view that is used to map the upper layers of abstraction into the platform and a view upper layers of abstraction into the platform and a view that is used to define the class of lower level abstractions that is used to define the class of lower level abstractions implied by the platform. implied by the platform.
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PlatformsPlatforms
Platform
Mapping Tools
Platform
Platform stack{
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Application example:Application example:
Automotive Power-Train Control Design: from car manufacturer Automotive Power-Train Control Design: from car manufacturer specs to software design to architecture selection to IC specs to software design to architecture selection to IC implementationimplementation
Project in collaboration with Cadence, Magneti-Marelli, ST Project in collaboration with Cadence, Magneti-Marelli, ST Microelectronics, AccentMicroelectronics, Accent
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Power-Train Control SystemPower-Train Control System
Electronic device controlling an internal combustion engine and a gearboxElectronic device controlling an internal combustion engine and a gearbox
The goalThe goal offer appropriate driving performance (e.g. torque, comfort, safety)offer appropriate driving performance (e.g. torque, comfort, safety) minimize fuel consumption and emissions minimize fuel consumption and emissions
Relevant characteristics Relevant characteristics strictly coupled with mechanical partsstrictly coupled with mechanical parts hard real-time constraintshard real-time constraints complex algorithms for controlling fuel injection, spark ignition, throttle position, gear complex algorithms for controlling fuel injection, spark ignition, throttle position, gear
shift … shift … 135,000 lines of C code with no comments135,000 lines of C code with no comments
First Step was to re-design software with methodology to map into different First Step was to re-design software with methodology to map into different hardware platforms with little effort!hardware platforms with little effort!
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System SpecificationsSystem Specifications
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Fast NegativeForce Transient
min f(D, Mfuel) < max
Force Tracking
Fast PositiveForce Transient
Speed Tracking
n=n(.) n=n(.)
Idle &Trasm On
.G>0 | t>
. .G < GB| B=1
.G<0 | t>
. .G > GA
G > 0
G = 0
T > 0
T=0 T=0
(G>0)&(T>0)
T=0
fI(n) = 0 & G=0
fI(n,G) > 0
.G=0 & C=1
.G > 0| B = 1
T > 0
T=0
OUTPUT:
n - Engine Speedn - Engine SpeedFFG G - Generated ForceVVGG - Vehicle Speed - Vehicle Speed
n=n(G)FG=0
Rpm Trackingn=argmin(Mfuel)
Idle
FG=0
VG= VG(.)
Stopn=0
FG=0
Startup
FG=0n= .
G > 0G = 0
(n < nmin)| (K=Off) n > nstartup
K = Start
(n < nmin)| (K = Off)
FG=FG(G,T,n)FG=FG(G,T,n)
max D < max
min
FG=FG(G,T,n)Mfuel < Mmax; D>Dmin
T>0 &G=0
INPUTS:
G - Gas PedalG - Gas PedalT - Clutch Pedal & Gear StickT - Clutch Pedal & Gear StickB - Brake PedalB - Brake PedalC - Cruise ControlC - Cruise Control
K - Key
D - Comfort
fI(n) = 0 & G=0
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GoalGoal
Develop guaranteed properties control algorithms for all Develop guaranteed properties control algorithms for all power-train modespower-train modes
Implement control strategies on embedded controllers Implement control strategies on embedded controllers “optimally” with respect to production cost, design time, “optimally” with respect to production cost, design time, reliability, safetyreliability, safety
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Model of Power-trainModel of Power-train
Manifold(continuous system)
Engine sub-system
Drive-line (continuous system with changing dynamics)
Throttle opening angle
Spark timing Torque
Manifold pressure
Clutch Insertion/Release
Gear change
Vehicle Speed
Simple?
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CTSCTS
CTSCTS
Engine and Drive-lineEngine and Drive-line
2020
Engine and Drive-lineEngine and Drive-line
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Single Cylinder Hybrid ModelSingle Cylinder Hybrid Model
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Mean-Value Model: accurate over a longer time windowMean-Value Model: accurate over a longer time windowregulation control problemsregulation control problems low performance transient problemslow performance transient problems
Hybrid Model: cycle accurateHybrid Model: cycle accurate transient control problems transient control problems stability of delay-sensitive control algorithmsstability of delay-sensitive control algorithmshigh performance control algorithmshigh performance control algorithms
Hybrid Model vs Mean-Value ModelHybrid Model vs Mean-Value Model
2323
Output DevicesInput devices
Hardware Platform
I O
Hardware
network
DUAL-CORER
TOS
BIOS
Device Drivers
Net
wor
k C
omm
unic
atio
n
DUAL-CORE
Architectural Space (Performance)
Application Space (Features)
PlatformsPlatforms
Platform Instance
Application Instances
System Platform(no ISA)
Platform Design Space Exploration
PlatformSpecification
Platform API
Software Platform
Output DevicesInput devices
Hardware Platform
I O
Hardware
network
HITACHIR
TOS
BIOS
Device Drivers
Net
wor
k C
omm
unic
atio
n
HITACHI
RTO
S
BIOS
Device Drivers
Net
wor
k C
omm
unic
atio
n
Output DevicesInput devices
Hardware Platform
I O
Hardware
network
ST10R
TOS
BIOS
Device Drivers
Net
wor
k C
omm
unic
atio
n
ST10
Application Software
Application Software
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Janus-PARADES 2000 ArchitectureJanus-PARADES 2000 Architecture
Interrupt Based Peripherals
ARM7TDMIA
ARM7TDMIB
Peripheral Bus
High Speed Peripheral Bus
ETU CAN SCI
ADC CLB
DMA Based Peripherals
RAMA
RAMB
FLASH A
FLASH B
XBAR
IO su
b sy
stem
IRC
Deb
ug U
nit
IRC
PARADES
2525
The Dual-Arm ArchitectureThe Dual-Arm Architecture
A symmetric dual processor architecture with a high-bandwidth A symmetric dual processor architecture with a high-bandwidth interconnection network among processors, memory, and I/O sub-interconnection network among processors, memory, and I/O sub-systems systems
11 Million Tr., 4% more area than single processor solution but 11 Million Tr., 4% more area than single processor solution but twice the performance on applicationtwice the performance on application
Most performing architecture for Power-train applications, Most performing architecture for Power-train applications, designed to be re-used over two generations (3-4 years cycles) of designed to be re-used over two generations (3-4 years cycles) of system products or moresystem products or more
Entirely designed using the methodology in less than 1 3/4 year Entirely designed using the methodology in less than 1 3/4 year from conception (March 99) to first silicon (Jan 01)from conception (March 99) to first silicon (Jan 01)
In production by 2002, shipments to car manufacturer 2003In production by 2002, shipments to car manufacturer 2003
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Design “Practice”Design “Practice”
2727
Design Science: Build upon solid foundationsDesign Science: Build upon solid foundations
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Design of Communication Media
Design of Function Blocks
Design of Architecture Components
Metropolis Infrastructure• Model of computation• Design methodology - Abstraction levels - Refinement• Base tools - Design imports - Simulation
Metropolis: Synthesis/Refinement• Compile-time scheduling of concurrency• Communication-driven hardware synthesis• Protocol interface generation• Latency insensitive protocols
Metropolis: Analysis• Static timing analysis of reactive systems• Invariant analysis of sequential programs• Refinement verification• Three-valued simulation• Delay estimation using object code
ETROPOLIS (20+ from Academia (UCB,CMU) and Industry (Intel, ST,BMW, Cadence))