the flipped voltage follower (fvf) - electrical & …s-sanchez/607 lect 5 flipped voltage... ·...

1

The Flipped Voltage Follower (FVF)

A useful cell for low-voltage, low-power circuit design

part of this material was provided by Profs. A.Torralba1 J. Ramírez-Angulo2, R.G.Carvajal1, A. López-Martín3,

ELEN 607 (ESS)

2

OUTLINE

1. Introduction.2. The Basic FVF.3. FVF Structures.4. Applications.5. Conclusions.

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The Basic Flipped Voltage Follower (FVF)

gm1 gm2 ro1

gm1

gout

= 1IbHIGHb) FVF< 1HIGHIba) ConventionalAvSinkingSourcing

a) Conventional

Voltage Follower

[Ramirez-Angulo’92] J.Ramírez-Angulo, R.G.Carvajal, A.Torralba, J.Galán, A.P.VegaLeal, and J.Tombs. “The Flipped Voltage Follower: a useful cell for low-voltage low power circuit design,” Proc. ISCAS’02, vol. 3, pp. 615-618, 2002.

b) (FVF)Ib

M1

M2

vo

vi

4

FVF transistors voltage limits to keep them in saturation

5

The Basic FVF Analysis

I b

M1

VoX

rb

M 2

Cc

Vi

Vr

Y Compensation

Dc gainAOL = Vr / Vi = - gm2 ROLYROLY = rb || gm1 ro1 ro2 ,ROLX ≈ (1+rb/ro1)/gm1 || ro2

Dominant PoleAt Y: wpY = 1 / CY ROLY

Non-Dominant PoleAt X: wpX = 1 / CX ROLX

Gain-Bandwidth ProductGB = gm2 / CY

Open Loop Analysis

CX parasitics at node X (incl. LOAD)CY parasitics at node Y (incl. Cc if any)

6

Stability Criterion: wpX > 2 GB

• For Ib a simple current mirror (rb≈ ro1)

• For Ib a cascode current mirror(rb ≈ gm1 ro1 ro2)

usually requires compensation

2. The Basic FVF

I b

M1

VoX

rb

M 2

Cc

Vi

Vr

Y

2

1

4gmgm

CC

Y

X <

Stability Analysis

CX parasitics at node X (incl. LOAD)CY parasitics at node Y (incl. Cc if any)

22

1rogmC

C

Y

X <

wpX = 1 / CX ROLX

7

Closed Loop Output Resistance

• For Ib a simple current mirror (rb ≈ ro1)

• For Ib a cascode current mirror (rb ≈ gm1ro1 ro2)

The Basic FVF

b

M1

M2

vovi

X

Y

( )2112

211

||

||11

1 rorogmrgm

roror

gmA

RRb

b

OL

OXCLX

⎟⎟⎠

⎞⎜⎜⎝

⎛+

≈+

=

121

1rogmgm

RCLX →

ACL ≈ 1 and RCLX is only a few Ohms (20 – 100) in all cases

121

2rogmgm

RCLX →

8

DC considerations

• VDDMIN = VGS

MIN + VDSsat ≈ 0.8 V for

0.6μm CMOS technology. It is a low-voltage cell.

The Basic FVF

[Chung-Chih’95] H.Chung-Chih, H.Changku, M. Ismail, “CMOS low-voltage rail-to-rail V-I converter,” Proc. 38th MWSCAS, vol.2, pp. 1337-1340, 1995.

M1

M2

X

Y

vo

vi

M3

Ib

Ib1

High-voltage version

• But, for large VDD, biasing M2 in saturation is difficult for low vi. A high-voltage version includes a voltage shifter in the feedback loop[Chung-Chih’95]

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3-terminal cell (strong inv.)

• For M2 in saturation

• For M2 in ohmic

The Basic FVF

b

M1

M2

vX

vZ

X

Y

ZiZ

vY

iyvY

iX

( )

( ) ( ) ( )( )

0

2,;,,,

,

1

=

−+==

+=

Z

Mp

YbTpYbZYXbY

YbZX

i

LWkiIViIfviiIgv

iIfvv

( ) ( )( )

2

2,,,Mp

XYbTpDDZYXb LWk

iiIVVviiIg −−−−=

The most interesting case is for iY = 0

( ) ( ) XMp

XYbXTpDDZYXb vLWk

iiIvVVviiIg 12

,,,2

⋅−−

−−−=M1 in saturation

Const

Relation

= 0

10

FVF Structures for different applications

Current sensor (FVF-CS)

in

5

out

2

1

b

b

Y

X

M2 saturation

I out

(uA)

M2 ohmic

M5 saturation

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FVF Structures

Non-Symmetrical Class-AB Differential Pair (FVF-NDP)

0

2.5

5.0

7.5

10.0 DM3

I b

(mV)V3V1-

12

3.FVF Structures

Symmetrical Class-AB Pseudo Differential Pair (FVF-PDP)

vinCM=(v3+v4)=V1

13

Flipped voltage follower applicationsFlipped voltage follower applications

Class A DifferentialPair

Class AB pseudoDifferntial pair

Comparison

I(D1) I(D2)

0

2.5

5.0

7.5

10.0

12.5

-400 -200 0 200 400VIN (mV)

DC

TRA

NS

FER

CU

RV

ES

(uA

)

M1 M2

iD1

Ib

V1 V2

iD2

X

M1 M2

iD1

V1 V2

iD2

X

Ma

M3

Ib

Va

I(D1P)

I(D2P)

I(D2P)

I(D1P)

satDSTPDD VVV ,min, 2+=

"A new Class AB differential Input stage for implementation of low voltage high slew rate op-amps and linear transconductors," J. Ramirez-Angulo, R. Gonzalez-Carvajal, A. Torralba and Carlos Nieva, IEEE International Symposium on Circuits an Systems, May 6-9, Sidney Australia

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3.FVF Structures

Symmetrical Class-AB DifferentialPair (FVF-SDP)

0

2.5

5.0

7.5

10.0 DM3

I b

(mV)V3V1-

DM6

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3.FVF Structures. SummaryCurrent sensor (FVF-CS)

Iin

M5

Iout

M2

M1

Ib

Vb

Non-SymmetricalClass-AB

Differential Pair(FVF-NDP)


V1M1M3

I b

V3

M2

M4 V4

X

IDM3 IDM4

Symmetrical Class-AB Differential Pair (FVF-SDP)

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Iin

M5

Iout

M2

M1

Ib

Vb




V1M1M3

I b

V3

M2

M4 V4

X

IDM3 IDM4


Current sensor (FVF-CS)

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Iin

M5

Iout

M2

M1

Ib

Vb




V1M1M3

I b

V3

M2

M4 V4

X

IDM3 IDM4


X

Y



18


Iin

M5

Iout

M2

M1

Ib

Vb




V1M1M3

I b

V3

M2

M4 V4

X

IDM3 IDM4


X


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4.FVF-CS ApplicationsCurrent sensor (FVF-CS)

Low voltage current mirrors

iIN

IB

V1

M2

M1

M5

IB

IOUT

[Rijns’93] J.J.F. Rijns, “54 MHz switched-capacitor video channel equalizer” Electr.Lett.,

vol. 29, no. 25, pp. 2181-2182, Dec. 1993[Ramirez-Angulo’04] J. Ramírez-Angulo, R.G.Carvajal,

A.Torralba, “Low-supply voltage high-performance CMOS current mirror with low input and output voltage requirements,”

IEEE TCAS-II, vol.51, no. 3, pp. 124-129, March 2004.• Vin

MIN = VDSsat• Very low input resistance(a few Ohms)

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Low voltage current mirrors

[Torralba’02] A. Torralba, R.G.Carvajal, J.Ramírez-Angulo, “Output stage for low supply voltage CMOS current mirrors” Electr.Lett., vol. 38, no. 24, pp. 1528-1529, Nov. 2002

A few OhmsInput impedance

≈ 1 GOhmOutput impedance

-66dBTHD (10 μA pp, @10KHz)

20nsSettling time (1%, 4 μA step)

1.5 pA/√HzInput referred noise(@10MHz)

120 MHzBandwidth

10 KOhmLoad resistor

1 VMinimum supply voltage

0,35μm CMOS AMSTechnology

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Other applications

[Docudray’03] G.O.Ducodray, R.G.Carvajal, J.Ramírez-Angulo, “A high-speed dynamic current sensor scheme for IDD test using a FVF” Proc. SSMSD, pp. 50-53, 2003

[Karthikeyan’01] S. Karthikeyan, A. Tamminneedi, E.K.F.Lee, “Design of low-voltage front-end interfaces for switched-opamp circuits,” IEEE TCAS-II, vol.48, no. 7, pp. 722-726, July 2001.

[Rout’00] S. Rout, E.K.F.Lee, “Design of 1 V switched-current cells in standard CMOS process,” Proc. ISCAS, vol.2, pp. 421-424, 2000

M 2

M1

Iin

M 5

Φ

ΦI out

IbIbΦ= HIGH)(

MB1 MB2

IDD TEST CURRENT SENSOR

LINEAR V-I CONVERTER

SI Circuits

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4.FVF-NDP Applications

[Peluso’00] V.Peluso, P. Vancorenland, A.M.Marques, M.S.J.Steyaert, W.Sansen, “A 900mV low-power ΔΣ A/D converter with 77dB dynamic range,” IEEE J.Solid-State Circuits, vol. 35, no. 4, pp. 632-636, April 2000.

[Carvajal’02] R.G.Carvajal, A. Torralba, J.Ramírez-Angulo, J.Tombs, F. Muñoz, “Compact low-power high slew-rate CMOS buffer for large capacitive loads,” Electron. Lett., vol.38, no. 32, pp. 1348-1349, Oct. 2002.

NON-LINEAR CLASS_ABTRANSCONDUCTOR

Non-Symmetrical Class-AB Differential Pair (FVF-NDP)

I b

V1

I b

V1

V2

M2b

M1aM3a M1bM3b

Ioa I ob

M4a

Vo1Vo2

M2a M4b

M8b M9b

M7b

M8aM9a

M7a VbVb

CLASS-AB OUTPUT BUFFER

I b

I b

V i Vo

M1PM3P

M3NM1N

M2P

B

2N

A

M

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4. FVF-NPD Applications

More than 100uA max. output current with 30uA total quiescent current !

2 V supply, 10pF capacitor load, 250 KHz input signal

time (s)

Out

put t

rans

isto

rcu

rren

t (A

)O

utpu

t vol

tage

(V)

CLASS-AB OUTPUT BUFFER

I b

I b

V i Vo

M1PM3P

M3NM1N

M2P

B

2N

A

M[Carrillo’04] J.M.Carrilo R.G.Carvajal,, A. Torralba, J.Duque-Carrillo, “Rail-to-rail, low-power high slew-rate CMOS analog buffer,” Electron. Lett., vol.40, no. 14, July 2004.

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4.FVF-NPD Applications

CLASS-AB OUTPUT STAGE

Moutp

Vout

Moutn

Io

X

Io

+-

+-

Y

W

Z

M1p

M1n M2n

M2p

α:1

α:1

VABVAB

MoutnI

MoutpI

M3p

M3n

25/1 25/1

50/1

8/1 8/1

16.5/1 165/1

500/1

3,75 uA

3,75 uA

Biasing STAGE

2-STAGE AMPLIFIER

[Torralba’00] A. Torralba, R.G.Carvajal, J. Martínez-Heredia, J.Ramírez-Angulo, “Class-AB output stage for low voltage CMOS op-amps with accurate quiescent current control,” Electron. Lett., vol.36, no. 21, pp. 1753-1754, Oct. 2000.

Rc Cc

Min2Min1

I = 100 uAdp

+

Output Stage(figure 13a)

-

VVout

X

V

a)

500/1 500/1

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4.FVF ApplicationsCLASS-AB OUTPUT STAGE in a 2-STAGE OP-AMP

500µAPeak output current * (@ 0.3 V peak)

10V/µsSlew Rate * (@ 0.3 V peak)

21nV2/HzInput referred noise (100kHz)

65dBTHD (1kHz)

45dBCMRR

38dBPSRR

218(µA)Supply current

38(µA)Minimum current through output transistors

76(µA)Quiescent output current

15MHzUnity Gain frequency

75ºdeg (o)Phase Margin

65dBDC Gain

VDD=1.5 V, CL=10pF, 0.8 μm CMOS (Vt ≈ 0.85 V)Op-amp comp. CC=10pF, RC=500Ω

Unitary feedback

Non-inverting Gain= 5 with 2 internalresistors

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4.FVF-PDP Applications

Ib

M1 M2

M5

Ma1

V2Va

Ib

M3 M4

M6

MbV1Vb

Vb'Va'

ID4ID3ID2ID1

I D1 I D3 ID2 ID4+ +

[Ramirez-Angulo’00] J.Ramírez-Angulo, R.G.Carvajal, J.M.Martínez-Heredia, “1.4V supply, wide swing, high frequency CMOS analogue multiplier with high current efficiency,” Proc. ISCAS, vol. 5, pp. 533-536, 2000[Ramirez-Angulo’03] J.Ramírez-Angulo, S.Thoutam, A.López-Martín, R.G.Carvajal, “Low voltage CMOS analogue four quadrant multiplier based on Flipped-Voltage-Followers,” Electron. Lett., vol.39, no. 25, Dec. 2003.

CLASS-AB LINEAR MULTIPLIERS

Symmetrical Class-AB Pesudo-Differential Pair (FVF-PDP)

-50

-30

-10

10

30

50

-300 -100 100 300

(uA

)

a)

b)

Vd12=V1 -V2

-300 mV=Va- Vb

(uA

)I D

2+I D

4-

-I D

1I D

3I o

ut=

50

70

30

-10

10

-30

-50-500 -100 300 700

ID2+ID4- -ID1 I D3

ID2+ID4+ +ID1 I D3

+ID1 I D3

ID1+ ID3- -ID2 I D4

+ID2 I D4

Vd12=V1 -V2

300 mV=Va- Vb

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• [Carvajal’02] R.G.Carvajal, J.Galán, J.Ramírez-Angulo, A. Torralba, “Low-power, low voltage differential class-AB OTAs for SC circuits,” Electron. Lett., vol.38, no. 22, pp. 1304-1305, Oct. 2002.• [Galan’02] J.Galán, A.P. VegaLeal, F. Muñoz, R.G.Carvajal, A.Torralba, J.Tombs, J. Ramírez-Angulo, “A 1.1V very low-power SD modulator for 14-b 16 KHz A/D conversion using a novel class AB transconductance amplifier,” Proc. ISCAS, vol. 2, pp. 616-619, 2002.

NON-LINEAR CLASS_AB TRANSCONDUCTORS

V i+Vi -

I b

M4

Vcasn

Vcasp

M 3 M2M1 Vo+Vo -

Mon -

Mop -

M on+

M op+V CM

MCMc MCMcVCMc

M cas M cas

M casM cas

VCMc

Vb

MCM VCMMCM

VDD

V SS

451

451

451

301

101

101

10110

1

101

101

101

101

101

101

301

30130

1

301

301

451

=1u

301

301

101

301

301

101

VcaspVcaspVcasp

Vcasn Vcasn Vcasn

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4. FVF-PDP Applications

10 V/usec SR with only 11 uA total quiescent current ! (0.35 μm CMOS)

time (s)

( V )

Diff

eren

tial V

olta

geO

utpu

t tra

nsis

tor

Cur

rent

( A

)

1.1 V, SC Integrator. 1pF capacitor load, 2MHz switching frequency

29


gm-C Filter

+ +

_ _ +

+_

_

+ +

_ _ +

+_

_gm1 gm2 gm3 gm4

C1

C1

C2

C2

Vo+

Vo-

Vin+

Vin-

+ +

_ _gm5

(Va - Vb)fo

(Va - Vb)Q

CMFB1 CMFB2

0.7 MHz

30


gm-C Filter

0.8 μm CMOSTechnology

42 dBCMRR (@ 10.7 MHz)

39 dBPSRR (@ 10.7 MHz)

8 dBmIIP3

46 dBIM3 (@10.7MHz)

45 dBSNR

−40dB@200 mVppTHD (@10.7MHz)

1.18−1.8 mWPower consumption range

14 mVVo,CM variation in the entire tuning range

4−501Q range (@10.7MHz)

300 kHz−32 MHzFrequency tuning range

1.44 mm2Chip area

2 VPower supply

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gm-C VCO

• [Galan’03] J.Galán, R.G.Carvajal, F. Muñoz, A.Torralba, J. Ramírez-Angulo, “A low-power low-voltage OTA-C sinusoidal oscillator with more than two decades of linear tuning range,” Proc. ISCAS, vol. 1, pp. 677-680, 2003.• [Galán’04] J. Galan, R. G. Carvajal, A. Torralba, F. Muñoz, and J. Ramirez-Angulo, A low-power, low-voltage OTA-C simusoidal oscillator with a large tuning range. IEEE Trans. On CAS-II. (to appear)

150

250

350

450

550

650

750

850

250 260 270 280 290 300 310

Vtuning (Gm3) (mV)Am

plitu

de (m

Vpp)

32

4.FVF Applications

1.12% / 0.66%THD (2 / 25 MHz) @200 mVpp

−67 dBc/HzPhase Noise at 10kHz offset

1.05−1.58 mWPower consumption range

1 MHz−25 MHzFrequency tuning range

25 mV−500 mVVtuning control

0.8 μmTechnology

0.63 mm2Chip area

2 VPower supply

gm-C VCO

Symmetrical Class-AB Pseudo-Differential Pair (FVF-PDP)

33


Iin

M5

Iout

M2

M1

Ib

Vb




V1M1M3

I b

V3

M2

M4 V4

X

IDM3 IDM4


Y


34

4.FVF-SDP Applications

[Baswa’04] S. Baswa, A. López-Martín, R.G.Carvajal, J.Ramírez-Angulo, “Low voltage micro-power super class-AB CMOS OTA,” Electron. Lett., vol.40, no. 4, Feb. 2004.


V1

M2

M1M3

I b

V3

Y

M5

M4

Ib

M6

R R

Ibo Ibo

SUPER CLASS_AB TRANSCONDUCTORS

Quiescent power consumption = 120 uWSR = 78 V/us, 1% settling time = 110 nsTHD (@100 kHz) = 0.15 %

0.5 μCMOS, VDD = 2 V, CL = 80pF2 MHz square input signal

35

4.Other Applications

• A.J. López-Martín and A. Carlosena, “Current-mode multiplier/divider circuits based on the MOS translinear principle”, Analog Integrated Circuits and Signal Processing, vol. 28, no. 3, pp. 265-278, 2001.• A.J. López-Martín and A. Carlosena, “Systematic design of compandingsystems by component substitution”, Analog Integrated Circuits and Signal Processing, vol. 28, no. 1, pp. 91-106, 2001.• A.J. López-Martín and A. Carlosena, “A 3.3V CMOS RMS-DC converter based on the MOS Translinear principle”, VLSI Design, 2002

Translinear loops, Geometric Mean, Square-Root Domain Filters, etc.

36

4. FVF-NPD ApplicationsCLASS-AB OUTPUT BUFFER

[Carrillo’04] J.M.Carrilo R.G.Carvajal,, A. Torralba, J.Duque-Carrillo, “Rail-to-rail, low-power high slew-rate CMOS analog buffer,” Electron. Lett., vol.40, no. 14, July 2004.

37

Conclusions

1. A new cell, called Flipped Voltage Follower (FVF) has been identified.

2. For low-voltage, low power, class AB operation.

3. Different applications have been reviewed(current mirror, voltage buffer, mixer, OTA, transconductance multiplier and op-amp output stage, filters, VCO, SD modulators…).

4. Simulation and experimental results have been presented that show the potential of the so-called FVF structure.

the flipped voltage follower (fvf) - electrical & …s-sanchez/607 lect 5 flipped voltage... ·...

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