The Impact of Silicon Etch Dislocations on EEPROM Cell Reliability

David PetryZMD America Inc., Melville, New York

dpetry@zmda.com

Abstract

The relationship between silicon etch dislocations and EEPROM cell reliability will be discussed in this paper. The point of view is from ZMD’s own floating gate EEPROM design, process yield, field experience and failure analysis efforts. Silicon dislocations occur naturally in CMOS semiconductor processes but have a greater impact on IC reliability at high operating temperatures. The use of wafer level high temperature screens will be discussed focusing on their use to reduce PPM defect levels. A detailed review of an EEPROM cell failure will be discussed and how this evaluation utilized the 8D approach to aid problem solving and the development of subsequent corrective actions.

1. EEPROM Reliability Considerations

ZMD is a manufacturer of mixed signal CMOS integrated circuits for Industrial, Communications, Personal / Medical and Automotive applications. Highly reliable CMOS integrated circuits for these applications contain EEPROM memory cells (electrically erasable programmable read only memory) that are typically evaluated for endurance and data retention. In practical terms, endurance is a measure of the number of times the EEPROM array can be safely erased and reprogrammed. Conditions for reprogramming are more „safe“ and reliable if a controlled set of criteria is met. This is due to the high voltage nature of EEPROM programming. Assuming that this criteria is generally followed by the user, semiconductor manufacturers of these products need to focus on 1) long term reliability tests for endurance and 2) wafer level screens to ensure that the weak cells are removed prior to delivery. The life test for endurance is generally done in two parts. One is the repetition of endurance cycles in the order of 10k, 100K or over 1 Million cycles. The next step is data retention which is programming followed by a long term high temperature life test.

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See Figure 1 for an example of endurance qualification results.

Figure 1

Traditional reliability estimates can be applied to the results of the EEPROM qualification. Figure 2 shows the calculation based on the above data results using the Arrhenius model and chi-squared factors. The confidence level is a conservative 90% with a resulting failure rate below 10 FIT. This result is acceptable for a wide range of applications.

Figure 2

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2. Example of EEPROM Failure Evaluation

ZMD typically uses a data retention bake to weed out weak EEPROM cells.This is based on industry benchmarking, comparison, review of the CMOS process and qualification results and customer input. However for our high reliability applicationsis this really good enough? We had a customer who experienced a single failing EEPROM cell that was not able to be read properly. The cell value was flipping between „0“ and „1“ depending on the conditions. Flipping of the bit was determined to be possible by lowering the device temperature. High temperature stress was also applied to further understand the nature of the failure mode. The Eight Disciplines or 8D problem solving approach was used to identify the root cause of the failure and to select the permanent corrective actions. Key to the 8D approach is the idea that you have truly identified the failure source if you can toggle it on and off like a switch. This is a rigorous process that requires total understanding of the root cause. The defective die was prepared for physical failure analysis using various techniques. Figure 3 to 8 show the steps.

Figure 3

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Figure 4

Figure 5

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Figure 6

Definition of Dislocation:

Dislocations are defects in crystalline materials like silicon. Where dislocations intersect a surface, a feature called an etch-pit can form after etching the silicon. The pit formation is due to the enhanced etching rate at lattice defects.

Dislocations are an expected occurance in silicon based microelectronic devices and usually are not a problem due to the purity and quality of the Si wafers used.

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Failure mode found and DOE results

Figure 7 – Cell Layout

The failure mechanism for the single bit failure was caused by electrical overstress (EOS) in the bit line circuitry at the read select transistor of the floating gate cell. There is physical evidence of this EOS damage; see Figure 8. The added resistance from the Gate to Drain on the select transistor caused the "1" to be read as a "0" since it creates a voltage divider with the Drain to Source impedance. This theory was proven by subsequent simulations. The most probable failure mode is that a dislocation transformed into an EOS site after thermal shock test resulting in the changed circuit characteristic.

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Figure 8 – Failure Mechanism Found

Figure 9 – Corrective Actions

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Figure 10 – Containment

Figure 11 – Design of Experiment (DOE ) results

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3. Industry Studies on Dislocations

There are several technical publications describing dislocations and their relationship to EEPROM cells. Intel researchers in Malaysia1 found that sub-micron CMOS devices can be impacted by subtle source drain leakage. This leakage can be caused by dislocations. Using a memory array rastering technique, the failing location was found at high supply voltage (Vcc) and high temperature (+95C). To avoid damaging the failure location, Hong of Intel recommends a well characterized and well controlled Wright Jenkins etch for 30 seconds to image the dislocation site. Note, as corrective action, Hong and team reduced the source drain implant energy to eliminate implant induced dislocations. This and other required changes improved the wafer yield by 70%.

Researchers in Bologna, Italy and ST Microelectronics found2 that 0.18 micron CMOS technologies can exhibit a higher failure rate due to dislocations. They explain that crystal defects like dislocations are very harmful to CMOS devices since they are the cause of source drain leakage currents. The effect grows worse with shrinking line geometries.The key finding of their study was:

Dislocations act as an anomalous dopant diffusion site which results in a resistive path.

Defect formation results from the interaction between mechanical stress and implantation damage.

To minimize dislocation density, use a suitable annealing step before the oxidation process and use a high annealing temperature such as 900C or higher.

Information extracted from a Microchip application note also gives us insight into the behavior and reliability aspects of EEPROMs3. They state that single cell EEPROM failures usually occur early in the parts life and that typical activation energy has been estimated at 0.12ev. Memory failure rates are due to dislocations, imperfections in oxide, silicon-oxide interface or poor silicon manufacturing process controls. Useful as an infant mortality screen, programming temperature is useful as a wear out accelerator. The combination of temperature and high voltage is effective for early defect detection. Another key to „weeding out“ weak cells is writing all zeros to the EEPROM cells as a more stressful and effective test than the traditional alternating „checkerboard“ pattern.

Other technical references4 support the connection between MOS device leakage currents and dislocations. Some of the dislocations are produced by device fabrication stress and some are produced by furnace stress. Bulk micro defects are also a factor in dislocation generation. It has been reported that dislocations can be electrically active and can result in junction leakage currents when decorated with metallic impurities. Therefore, enhancing raw wafer quality is a key factor in removing silicon dislocations, thereby improving EEPROM failure rates.

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4. Conclusions

In summary, silicon defects and dislocations can have a subtle impact on CMOS device gate leakage currents and thus can negatively impact the reliability of EEPROM memories. However, one can develop robust wafer level screens for early detection and removal of weak memory cells.

If you encounter a field failure, use the 8D process to organize, document and resolve your failure analysis evaluation. You can also use Design of Experiments (DOE) to significantly reduce the frequency of dislocations. However, you must proceed cautiously when making major process changes so as not to introduce a greater problem than the one you wanted to correct.

Bibliography

1. Yeoh Eng Hong, et. al.,“Source Drain Leakage: A Potential Problem in Sub-micron CMOS Devices“. SPIE Vol. 2874, p. 232-237, 1996.

2. Isabella Mica, et. al.,“Dislocation Generation in Device Fabrication Process“. Trans Tech Publications, 3-908450-82-9, 2003.

3. „Everythink a System Engineer Needs to Know about Serial EEPROM Endurance“, Microchip AN537, 1992.

4. Garth K. Su, et. al,“Effects of Dislocation and Bulk Micro Defects“, Semicon, Taiwan 2001.

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