The Verilog® Hardware

Fifth Edition

Description Language

Donald Thomas • Philip Moorby

The Verilog® Hardware Description Language Fifth Edition

Donald Thomas Philip Moorby Carnegie Mellon University Sigmatix Pittsburgh, PA South Hampton, NH USA USA

Library of Congress Control Number: 2008932529 Printed on acid-free paper. Hardcover Edition © 2002 Springer Science+Business Media, LLC ISBN-13: 978-1-4020-7089-1 (Hardcover) ISBN-13: 978-0-387-84930-0 (Paperback) e-ISBN-13: © 2008 Springer Science+Business Media, LLC (Paperback Edition) All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, Inc., 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. 9 8 7 6 5 4 3 2 1 springer.com

978-0-387-47666-2

To 8andie,

and John and Holland,

and Jill.

Preface From the Old to the New Acknowledgments

X V

xvii xx|

Verilog -

A Tutorial Introduction Getting Started 2

A Structural Description 2 Simulating the binaryToESeg Driver 4 Creating Ports For the Module 7 Creating a Testbench For a Module 8

Behavioral Modeling of Combinational Circuits 11 Procedural Models 12 Rules for Synthesizing Combinational Circuits 13

Procedural Modeling of Clocked Sequential Circuits 14 Modeling Finite State Machines 15 Rules for Synthesizing Sequential Systems 18 Non-Blocking Assignment ("<--") 19

Module Hierarchy 21 The Counter 21 A Clock for the System 21 Tying the Whole Circuit Together 22 Tying Behavioral and Structural Models Together 25

Summary 27 Exercises 28

Logic Synthesis 35

Overview of Synthesis 35 Register-Transfer Level Systems 35 Disclaimer 36

Combinational Logic Using Gates and Continuous Assign 37

Procedural Statements to Specify Combinational Logic 40 The Basics 40

viii The Verilog Hardware Description Language

Complications u Inferred Latches Using Case Statements Specifying Don't Care Situations Procedural Loop Constructs

Inferring Sequential Elements Latch Inferences Flip Flop Inferences Summary

Inferring Tri-State Devices Describing Finite State Machines

An Example of a Finite State Machine An Alternate Approach to FSM Specification

Finite State Machine and Datapath A Simple Computation A Datapath For Our System Details of the Functional Datapath Modules Wiring the Datapath Together Specifying the FSM

Summary on Logic Synthesis Exercises

42 43 44 46 4 8 48 5O 52 5 2 5 3 53 56 5 8 58 58 60 61 63 6 6 6 8

Behavioral Modeling 73

Process Model If-Then-Else

Where Does The ELSE Belong? The Conditional Operator

Loops Four Basic Loop Statements Exiting Loops on Exceptional Conditions

Multi-way Branching If-Else-If Case Comparison of Case and If-Else-If Casez and Casex

Functions and Tasks Tasks Functions A Structural View

Rules of Scope and Hierarchical Names Rules of Scope Hierarchical Names

7 3 7 5 80 81 8 2 82 85 8 6 86 86 89 9O 91 93 97

100 1 0 2 102 105

Summary Exercises

106 106

Concurrent Processes 109

Concurrent Processes Events

Event Control Statement Named Events

The Watt Statement A Complete Producer-Consumer Handshake ~Comparison of the Wait and While Statements Comparison of Wait and Event Control Statements

A Concurrent Process Example A Simple P|pelined Processor

The Basic Processor Synchronization Between Pipestages

Disabling Named Blocks Intra-Assignment Control and Timing Events Procedural Continuous Assignment Sequential and Parallel Blocks Exercises

109 111 112 113 116 117 120 121 122 128 128 130 132 134 136 138 140

Module Hierarchy 143

Module Instantlat ion and Port Specifications Parameters Arrays of Instances Generate Blocks Exercises

143 146 150 151 154

x The Verilog Hardware Description Language

Logic Level Modeling 157

Introduction Logic Gates and Nets

Modeling Using Primitive Logic Gates Four-Level Logic Values Nets A Logic Level Example

Continuous Assignment Behavioral Modeling of Combinational Circuits Net and Continuous Assign Declarations

A Mixed Behavioral/Structural Example Logic Delay Modeling

A Gate Level Modeling Example Gate and Net Delays Specifying Time Units Minimum, Typical, and Maximum Delays

Delay Paths Across a Module Summary of Assignment Statements Summary Exercises

157 158 159 162 163 166 171 172 174 176 180 181 182 185 186 187 189 190 191

Cycle-Accurate Specification 195

Cycle-Accurate Behavioral Descriptions Specification Approach A Few Notes

Cycle-Accurate Specification Inputs and Outputs of an Always Block Input/Output Relationships of an Always Block Specifying the Reset Function

Mealy/Moore Machine Specifications A Complex Control Specification Data and Control Path Trade-offs

Introduction to Behavioral Synthesis Summary

195 195 197 198 198 199 202 203 204 204 209 210

Advanced Timing 211

Verilog Timing Models Basic Model of a Simulator

Gate Level Simulation Towards a More General Model Scheduling Behavioral Models

Non-Deterministic Behavior of the Simulation Algorithm

Near a Black Hole It's a Concurrent Language

Non-Blocking Procedural Assignments Contrasting Blocking and Non-Blocking Assignments Prevalent Usage of the Non-Blocking Assignment Extending the Event-Driven Scheduling Algorithm Illustrating Non-Blocking Assignments

Summary Exercises

211 214 215 215 218

220 221 223 226 226 227 228 231 233 234

User-Defined Primitives 2:39

Combinational Primitives Basic Features of User-Defined Primitives Describing Combinational Logic Circuits

Sequential Primitives Level-Sensitive Primitives Edge-Sensitive Primitives

Shorthand Notation Mixed Level- and Edge-Sensitive Primitives Summary Exercises

240 240 242 243 244 244 246 246 249 249

xii The Verilog Hardware Description Language

Switch Level Modeling 251

A Dynamic MOS Shift Register Example Switch Level Modeling

Strength Modeling Strength Definitions An Example Using Strengths Resistive MOS Gates

Ambiguous Strengths Illustrations of Ambiguous Strengths The Underlying Calculations

The miniSim Example Overview The miniSim Source Simulation Results

Summary Exercises

251 256 256 259 260 262 263 264 265 270 270 271 28O 281 281

Projects 283

Modeling Power Dissipation Modeling Power Dissipation What to do Steps

A Floppy Disk Controller Introduction Disk Format Function Descriptions Reality Sets In... Everything You Always Wanted to Know about CRC's Supporting Verilog Modules

Appendix A: Tutorial Questions and Discussion Structural Descriptions Testbench Modules Combinational Circuits Using always

283 284 284 285 286 286 287 288 291 291 292

293 293 303 303

oo0 X I I I

Sequential Circuits Hierarchical Descriptions

Appendix B: Lexical Conventions White Space and Comments Operators Numbers Strings Identifiers, System Names, and Keywords

Appendix C: Verilog Operators Table of Operators . Operator Precedence Operator Truth Tables Expression Bit Lengths

Appendix D: Verilog Gate Types Logic Gates BUF and NOT Gates BUFIF and NOTIF Gates MOS Gates Bidirectional Gates CMOS Gates Pullup and Pulldown Gates

Appendix E: Registers, Memories, Integers, and Time

Registers Memories Integers and Times

Appendix F: System Tasks and Functions Display and Write Tasks Continuous Moni tor ing Strobed Moni tor ing File Output Simulation Time Stop and Finish Random Reading Data From Disk Files

Appendix G: Formal Syntax Definition Tutorial Guide to Formal Syntax Specification

305 308

309 309 310 310 311 312

315 315 320 321 322

323 323 325 326 327 328 328 328

329 329 330 331

333 333 334 335 335 336 336 336 337

339 339

xiv The Verilog Hardware Description Language

I n d e x

Source text Declarations Pr imit ive instances Module and generated instant ia t ion UDP declarat ion and instant iat ion Behavioral statements Specify section Expressions General

343 346 351 353 355 355 359 365 370

3 7 3

Preface

The Verilog language is a hardware description language that provides a means of specifying a digital system at a wide range of levels of abstraction. The language sup- ports the early conceptual stages of design with its behavioral level of abstraction, and the later implementation stages with its structural abstractions. The language includes hierarchical constructs, allowing the designer to control a description's complexity.

Verilog was originally designed in the winter of 1983/84 as a proprietary verifica- tion/simulation product. Later, several other proprietary analysis tools were developed around the language, including a fault simulator and a timing analyzer. More recently, Verilog has also provided the input specification for logic and behavioral synthesis tools. The Verilog language has been instrumental in providing consistency across these tools. The language was originally standardized as IEEE standard #1364-1995. It has recently been revised and standardized as IEEE standard #1364-2001. This book presents this latest revision of the language, providing material for the beginning student and advanced user of the language.

It is sometimes difficult to separate the language from the simulator tool because the dynamic aspects of the language are defined by the way the simulator works. Fur- ther, it is difficult to separate it from a synthesis tool because the semantics of the lan- guage become limited by what a synthesis tool allows in its input specification and produces as an implementation. Where possible, we have stayed away from simulator- and synthesis-specific details and concentrated on design specification. But, we have included enough information to be able to write working executable models.

xvi The VerUog Hardware Description Language

The book takes a tutorial approach to presenting the language. Indeed, we start with a tutorial introduction that presents, via examples, the major features of the lan- guage and the prevalent styles of describing systems. We follow this with a detailed presentation on using the language for synthesizing combinational and sequential sys- tems. We then continue with a more complete discussion of the language constructs.

Our approach is to provide a means of learning by observing the examples and doing exercises. Numerous examples are provided to allow the reader to learn (and re- learn!) easily by example. It is strongly recommended that you try the exercises as early as possible with the aid of a Verilog simulator. The examples shown in the book are available in electronic form on the enclosed CD. Also included on the CD is a simulator. The simulator is limited in the size of description it will handle.

The majority of the book assumes a knowledge of introductory logic design and sof~are programming. As such, the book is of use to practicing integrated circuit design engineers, and undergraduate and graduate electrical or computer engineering students. The tutorial introduction is organized in a manner appropriate for use with a course in introductory logic design. A separate appendix, keyed into the tutorial introduction, provides solved exercises that discuss common errors. The book has also been used for courses in introductory and upper level logic and integrated circuit design, computer architecture, and computer-aided design (CAD). It provides com- plete coverage of the language for design courses, and how a simulator works for CAD courses. For those familiar with the language, we provide a preface that covers most of the new additions to the 2001 language standard.

The book is organized into eleven chapters and eight appendices. The first part of the book contains a tutorial introduction to the language which is followed by a chap- ter on its use for logic synthesis. The second part of the book, Chapters 3 through 6, provide a more rigorous presentation of the language's behavioral, hierarchical, and logic level modeling constructs. The third part of the book, Chapters 7 through 11, covers the more specialized topics of cycle-accurate modeling, timing and event driven simulation, user-defined primitives, and switch level modeling. Chapter 11 suggests two major Verilog projects for use in a university course. One appendix pro- vides tutorial discussion for beginning students. The others are reserved for the dryer topics typically found in a language manual; read those at your own risk.

Have fun designing great systems...

always, Donald E. Thomas Philip R. Moorby March 2002

From the Old to the New

This book as been updated so that the new features of lEEE Std. 1364-2001 are always used even though the "old ways" of writing Verilog (i.e. IEEE Std. 1364-1995) are still valid. In this preface, we show a few side-be-side examples of the old and new. Thus, this section can stand as a short primer on many of the new changes, or as a ref- erence for how to read "old code." Throughout this preface, cross references are made to further discussion in the earlier parts of the book. However, not all changes are illustrated in this preface.

Ports, Sensitivity Lists, and Parameters Port declarations can now be made in "ANSI C" style as shown in Example P.1. In the old style, the port list following the module name could only contain the identifi- ers; the actual declarations were done in separate statements. Additionally, only one declaration could be made in one statement. Now, the declarations can be made in the opening port list and multiple declarations can be made at the same time. Multiple declarations are illustrated in the declaration of eSeg being an "output reg" in the new standard; previously this took two statements as shown on the right of the example (See Section 5.1). This style of declaration also applies to user defined primitives (See chapter 9). These two module descriptions are equivalent.

xviii The Verilog Hardware Description Language

module bin aryTo ES eg_B ehavioral (output reg eSeg, input A, B, C, D);

always @(A, B, C, D) begin eSeg = 1; if (~A & D)

eSeg = O; if (~A & B &, ~C)

eSeg = 0; if (~B & ~C & D)

eSeg = 0; end

endmodule

Example E1 2001 Standard (Left); Previous 1995 (Right)

module binaryToESeg_Behavioral (eSeg, A, B, C, D); output- eSeg; input A, B, C, d; reg eSeg;

always @(A or B or C or D) begin

eSeg = 1; if (~A & D)

eSeg = 0; if (~A & B & ~C)

eSeg = 0; if (~B & ~C & D)

eSeg - 0; end

endmodule

Example R1 also shows a simpler way to describe sensitivity lists. Previously, the list was an or-separated list of identifiers as shown on the right of the figure. Now, the list can be comma-separated (See Section 4.2.1). Additionally, if the intent is to describe a combinational circuit using an always block, the explicit sensitivity list can replaced with a @(*) as illustrated in Example R2. The module descriptions in Examples R1 and R2 describe equivalent functionality. (See Section 2.3.1.)

If the module is parameterized, then the list of parameters is introduced and declared before the port list so that some of the port specifications can be parame- terized. (See Section 5.2.)This is illus-

module binaryToES eg_Behavioral (output reg eSeg, input A, B, C, D);

always @(*) begin eSeg = 1; if (~A & D)

eSeg = 0; if (~A & B & ~C)

eSeg = 0; if (~B & ~C & D)

eSeg = 0; end

endmodule

Example P.2 Sensitivity List Using @(,)

trated in Example P.3. The new standard also allows for parameters to be over-ridden by name. The old style of instantiating module xorx of Example P.3 would be

xorx #(7, 12) xl(a, b, c);

where the new value of width is 7 and delay is 12. With the new style, individual parameters can be overridden m

xix

module xorx #(parameter width = 4,

delay = 10) (output [1:width] xout, input [1:width] xinl, xin2);

module xorx (xout, xinl, xin2); parameter width = 4,

delay = 10; output [l:width] xout; input [1:width] xinl, xin2;

assign #(delay) xout = xinl ^ xin2;

assign #(delay) xout = xinl ^ xin2;

endmodule endmodule Example P.3 Parameter Definition with 2001 Standard (Left) and 1995 (Right)

xorx #(.delay(8)) x2 (a, b, c);

where delay is changed to 8 and width remains at 4.

Functions and tasks may also be declared using the combined port and declaration style. Using the 1995 style, a function with ports would be defined as

function [11:0] multiply; input [5:0] a, b;

~ 1 7 6 1 7 6

endfunction

The new 2001 style allows the definition within the port list; declarations may be of any type (See Section 3.5).

function [11:0] multiply (input [5:0] a,b); ~ 1 7 6 1 7 6

endfunction

Other Changes Many of the other changes are illustrated throughout the book. They are referenced here.

�9 Functions may now be declared recursive, constant, and signed (Section 3.5). �9 Tasks may now be declared automatic (Section 3.5). �9 Initial values may now be specified in declarations (See Section 1.4.1).

�9 Implicit net declarations are now applied to continuous assignments (Section 6.3). Also, they may now be disabled (Section 6.2.3) with keyword none.

�9 Variable part-selects (Section 3.2).

xx The Verilog Hardware Description Language

* Arrays may now be multidimensional and of type net and real. Bit and part-selects are allowed on array accesses (Section E.2).

* Signed declarations. Registers (Section E.1), nets (Section6.2.3), ports (Section 5.1), functions (Sections 3.5.2), parameters (Section 5.2) and sized num- bers (Section B.3) may be signed, signed and unsigned system functions have been added (Section C.1).

�9 Operators. Arithmetic shift operators and a power operator have been added (Section C.1).

�9 Parameters. Local parameters may now be defined. Parameters may now be sized and typed. (Section 5.2)

�9 Attributes have now been added to specify additional information to other tools (Section 2.3.4). Details of using attributes is left to the user manuals of the tools that define them. Attribute specification is left out of the BNF illustrations in the running text. However they are included in appendix G.

�9 Generate blocks have now been added to aid in iterative specification. (Section 5.4)

Acknowledgments

The authors would like to acknowledge Accellera (http://www.accellera.org), whose role it is to maintain and promote the Verilog standard, and the many CAD tool developers and system designers who have contributed to the continuing development of the Verilog language. In particular, the authors would like to thank Leigh Brady for her help in reviewing earlier manuscripts.

The authors would also like to thank JoAnn Paul for her help and suggestions on the introduction and the the chapter questions, John Langworthy for helping us focus the tutorial material in appendix A toward students in a sophomore course, Tom Martin for his help in developing the exercises in chapter 11, and H. Fatih Ugurdag for providing us with Example 7.5. We also acknowledge many practicing engineers, faculty and students who have used the book and provided feedback to us on it. Finally, we wish to acknowledge Margaret Hanley for the cover and page format designs.

The Institute of Electrical and Electronics Engineers maintains the Verilog Hard- ware Description Language standard (IEEE #1364-2001). We wish to acknowledge their permission for including the formal syntax specification in appendix G. Com- plete copies of the standard may be obtained through http://standards.ieee.org.