THz & nm Transistor Electronics: It's All About The Interfaces.

rodwell@ece.ucsb.edu 805-893-3244, 805-893-5705 fax

PCSI Conference, January 15, 2008, Santa Fe

M. Rodwell, Art Gossard University of California, Santa Barbara

C. Palmstrøm,University of MinnesotaM. Fischetti University of Massachusetts Amherst

Collaborators (III-V MOS)A. Gossard, S. Stemmer, C. Van de Walle University of California Santa Barbara P. Asbeck, A. Kummel, Y. Taur, University of California San Diego J. Harris, P. McIntyre,Stanford University

TeraHertz and nanoMeter Electron DevicesHow do we make very fast electron devices ?

...by scaling

What are the limits to scaling ?attainable contact resistivities,attainable thermal resistivitiesattainable contact stabilities and for FETs, attainable capacitance densities

How can the materials growth community help ?work on interfaces (contacts and gate dielectrics) !

Guidance of utility of other device structures / featuresnanowire pillar devicesaccess resistances & capacitancesrelevance and irrelevance of mobility

THz & nm SemiconductorDevice Design...

... is scaling

Frequency Limitsand Scaling Laws of (most) Electron Devices

bottomR

topR

widthlengthlog

lengthpower

thickness / area

length stripe/1

area/thickness/area

thickness

2limit-charge-space max,

T

I

R

RC

bottom

contacttop

To double bandwidth, reduce thicknesses 2:1reduce width 4:1, keep constant lengthcurrent density has increased 4:1

PIN photodiode

applies to almost all semiconductor devices:transistors: BJTs & HBTs, MOSFETS & HEMTs, Schottky diodes, photodiodes, photo mixers, RTDs, ...

high current density, low resistivity contacts, epitaxial & lithographic scaling

THz semiconductor devices

bottomR

topR

capacitanceresistance transit time

device bandwidth

FETs only: high ro/D dielectrics

Why aren't semiconductor lasers R/C/ limited ?

dielectric waveguide mode confines AC field away from resistive bulk and contact regions.

AC signal is not coupled through electrical contacts

+V (DC)

N+

N-

I

P-

P+

metal

metal

opticalmode

-V (DC)

AC outputfield

high r

dielectric mode confinement is harder at lower frequencies

Bipolar Transistor Design

Bipolar Transistor Design is SimpleeW

bcWcTbTnbb DT 22

satcc vT 2

ELlength emitter

cccb /TAC

eex AR /contact

2through-punchce,operatingce,, /)( cesatKirkc TVVAvI

contacts

contactsheet 612 AL

WL

WRe

bc

e

ebb

e

e

E WL

LPT ln1

HBT scaling lawseW

bcWcTbT

Goal: double transistor bandwidth when used in any circuit → keep constant all resistances, voltages, currents → reduce 2:1 all capacitances and all transport delays

vTDT bnbb /22 vTcc 2

ELlength emitter

cccb /TAC

ecex AR /2

, / ceKirkc TAI

contacts

c

e

bcs

e

esbb AL

WLWR

612

→ thin base ~1.414:1

→ thin collector 2:1

→ reduce junction areas 4:1→ reduce emitter contact resistivity 4:1

(current remains constant, as desired )

→ reduce base contact resistivity 4:1

reduce widths 2:1 & reduce length 2:1 → constant Rbb reducing widths 4:1, keep constant length → reduced Rbb

EInPe

e

EInP LKP

WL

LKPT

ln

need to reduce junction areas 4:1reduce widths 2:1 & reduce length 2:1 → doubles Treducing widths 4:1, keep constant length→ small T increase ✓

✓✓✓

Linewidths scale as the inverse square of bandwidth because thermal constraints dominate.

Bipolar Transistor Scaling Laws

parameter changecollector depletion layer thickness decrease 2:1base thickness decrease

1.414:1emitter junction width decrease 4:1collector junction width decrease 4:1emitter contact resistance decrease 4:1current density increase 4:1base contact resistivity decrease 4:1

Changes required to double transistor bandwidth:

Linewidths scale as the inverse square of bandwidth because thermal constraints dominate.

0

100

200

300

400

500

600

700

800

0 100 200 300 400 500 600 700 800

Teledyne

UIUC DHBT

NTT

ETHZ/SFU

UIUC SHBT

UCSB DHBT

NGST

Pohang

HRL

IBM SiGe

Vitesse

f max

(GH

z)

ft (GHz)

500 GHz400 GHz300 GHz200 GHz maxff

Updated Sept. 2007

600 GHz

Status of Bipolar Transistors : September 2007

)( ),/( ),/( ),/(

hence , :digital

gain, associated ,F :amplifiers noise low

mW/ gain, associated PAE,

:amplifierspower

)11(

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cb

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clock

ττVIRVIRIVC

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:metrics better much

:metrics popular

250 nm

600nm

350 nm

250 nm

256 nm GenerationInP DHBT

0

10

20

30

109 1010 1011 1012

109

1010

1011

1012

dB

Hz

f = 560 GHz

fmax

= 560 GHz

U

H21

0

10

20

30

40

109 1010 1011 1012

dB

Hz

UH21

f = 424 GHz

fmax

= 780 GHz

0

5

10

15

20

0 1 2 3 4V

ce

mA

/m

20

10

20

30

40

109 1010 1011 1012

dB

Hz

U

H21

ft = 660 GHz

fmax

= 218 GHz

0

10

20

30

0 1 2 3

mA/

m2

Vce

150 nm thick collector

70 nm thick collector

60 nm thick collector

200 GHz master-slavelatch design

340 GHz, 70 mW amplifier design

Z. Griffith, E. Lind, J. Hacker, M. Jones

-20

-15

-10

-5

0

5

10

220 240 260 280 300 320

freq. (GHz)

S21,

S11

, S22

(dB)

S21

S22

S11

4.7 dB Gain at 306 GHz.

from one HBT

emitter 512 256 128 64 32 nm width16 8 4 2 1 m2 access

base 300 175 120 60 30 nm contact width, 20 10 5 2.5 1.25 m2 contact

collector 150 106 75 53 37.5 nm thick, 4.5 9 18 36 72 mA/m2 current density4.9 4 3.3 2.75 2-2.5 V, breakdown

f 370 520 730 1000 1400 GHzfmax 490 850 1300 2000 2800 GHz

power amplifiers 245 430 660 1000 1400 GHz digital 2:1 divider 150 240 330 480 660 GHz

InP Bipolar Transistor Scaling Roadmap

industry university→industry

university2007-8

appearsfeasible

maybe

How Can Material Scientists Help ?

To build a 5-THz bipolar Transistor...

...we need 0.25 -m2 Ohmic contacts,

& these must be stable at 300 mA/m2.

...Can you help ?

Ohmic Contacts

Ex-Situ Ohmic Contacts are a Mess

Surface contaminated by semiconductor oxides On InGaAs surface: Indium and Gallium Oxides, elemental As

Metals Interdiffuse with Semiconductor TiPtAu contacts: Ti diffusion. Pt contacts: reaction. Pd contacts: reaction

textbook contact with surface oxide with metal diffusion

Interface is degraded → poor conductivityInterface is badly-controlled→ hard to understand→ hard to improve

Wafer first cleaned in reducing

Pd & Pt react with III-V semiconductor

Penetrate surface oxide

Provide ~5 -m2 resistivity (InGaAs base, 8*1019/cm3)

reaction depth is a problem for HBT base

Our HBT Base Contacts Today Use Pd or Pt to Penetrate Oxides

Reacted region

Pt

InGaAs

Au

Pt

Reacted region

InGaAs

Pt Contact after 4hr 260C Anneal

Pt/Au Contact after 4hr 260C Anneal

TEM : Lysczek, Robinson, & Mohney, Penn State Sample: Urteaga, RSC

Chor, E.F.; Zhang, D.; Gong, H.; Chong, W.K.; Ong, S.Y. Electrical characterization, metallurgical investigation, and thermal stability studies of (Pd, Ti, Au)-based ohmic contacts. Journal of Applied Physics, vol.87, (no.5), AIP, 1 March 2000. p.2437-44.

Improvements in HBT Emitter Access Resistance

125 nm generation requires 5 - μm2 emitter resistivities

65 nm generation requires 1-2 - μm2

Recent Results ErAs/Mb MBE in-situ 1.5 - μm2 Mo MBE in-situ 0.6 - μm2

TiPdAu ex-situ 0.5 - μm2

TiW ex-situ 0.7 - μm2

Degeneracy contributes 1 - μm2

10-3

10-2

10-1

100

101

102

-0.3 -0.2 -0.1 0 0.1 0.2

J(m

A/u

m^2

)

Vbe

-

Fermi-Dirac

Equivalent series resistance approximation

Boltzmann

20 nm emitter-base depletion layer contributes 1 - μm2 resistance

)()(

xqnJ

xxE fn

Te=0 nm

Te=100 nm

10 nm steps

U. SingisettiA. CrookS. BankE. Lind

In-situ ErAs-InGaAs Contacts

III Er As

Approximate Schottky barrier potential

D. O. Klenov, Appl. Phys. Lett., 2005

1J.D. Zimmerman et al., J. Vac. Sci. Technol. B, 2005

InAlAs/InGaAs

S.R. Bank, NAMBE , 2006

Epitaxially formed, no surface defects, no Fermi level pinning (?) In-situ, no surface oxides, coherent interface, continuous As sublattice Thermodynamically stable ErAs/InAs Fermi level should be above conduction band

Results nevertheless disappointing: 1.5 - μm2

Low-Resistance Refractory Contacts to N-InGaAs

in-situ Mo contact

Results initially by luck: control samples for ErAs experiments

Mo contacts: deposition by MBE immediately after InGaAs growth

TiW contacts: sputter deposition after UV-Ozone & 14.8-normality ammonia soak

Both give ~ 1 -m2 resistitivity

ex-situ TiW contact

Coherent Epitaxial Metal Semiconductor Contacts ?

Chris Palmstrom suggests materials such asFe3Ga, CoGa, NiAl

It might be possible to grow these with low interfacial densities on InGaAs or InAs.

Key question: what resistivity would we expect for a zero-defect, zero-barrier metal-semiconductor interface ?

If we introduce a small difference in Fermi Level between metal and semiconductor, what current do we compute from integration of N(E) v(E)F(E)T(E) ?

Shape as Substitute for Low-Resistance Contacts: SiGe HBTs

SiO2 SiO2

P base

N+ subcollector

N-thick extrinsic base : low resistancethin intrinsic base: low transit time

wide emitter contact: low resistancenarrow emitter junction: scaling (low Rbb/Ae)

wide base contacts: low resistancenarrow collector junction: low capacitance

Wr

LR bulkbulk

2ln2

LrR c

contact 2

These are planar approximations toradial contacts:

extrinsic base

extrinsicemitter

N+ subcollector

extrinsic base

→ reduced access resistance

should help less with small devices: ...widths scale faster than thicknesses→ trench fringing capacitance dielectric trench conducts heat badly

Field-Effect Transistors

Simple FET Scaling Goal double transistor bandwidth when used in any circuit → reduce 2:1 all capacitances and all transport delays

→ keep constant all resistances, voltages, currents

All lengths, widths, thicknesses reduced 2:1

S/D contact resistivity reduced 4:1

/~/~

/)/(~/~

/~

gchdds

oxgggsm

g

WCG

TWLCg

vL

If Tox cannot scale with gate length, Gds/gm increases

oxgggs TLWC /~

ggdfgs WCC ~~,

subcgdbsb TLWCC /~~

If Tox cannot scale with gate length, Cparasitic / Cgs increases, gm / Wg does not increasehence Cparasitic /gm does not scale

Well-Known: Si FETs no longer Scale WellEOT is not scaling as 1/Lg

(ITRS roadmap copied from Larry Larson's files)

High-K gate dielectrics: often significant SiO2 interlayer, can limit EOT scaling

S/D access resistance also a challenge: about 1 -m2 required for 20 nm

Because gate equivalent thickness is not scaling, present devices scale badlyoutput conductance is degrading with scalingother capacitances are not scaling in proportion to Cgs

hence are starting to dominate high frequency performance

How Can Materials Scientists Help ?

High K-dielectrics for Si CMOS are still extremely important

Self-aligned (Salicide-like) contacts of very low resistivity are needed

...for 2 mA/micron operation at 700 mV gate overdrive,we want ~300 Ohm-micron lateral access resistivity→ about 0.7 Ohm-micron^2 resistivity in a 25 nm wide contact

Why consider III-V (InGaAs/InP) CMOS ?

Challenge:Low density of states

Cox Cdos

Low access resistance: 1 -m2 , 10 -mLight electron→ high electron velocity (thermal or Fermi injection)

→ increased Id / Wg at a given oxide thickness (?) → decreased Cgs /gm at a given gate length

3.4 F/cm2

@ 1 nm EOT~3 F/cm2

ballistic case2

*2

mqCdos

limits ns to ~ 6*1012 /cm2

limits Id / Wg limits gm /Wg

Challenge:filling of low-mobilitysatellite valleys

limits ns to ~ 8*1012 /cm2

limits Id / Wg

Challenge:light electron limits vertical scaling~1.5-2.5 nm minimum

mean electron depth

III-V MOS: What might be accomplished

r

well

implantisolated

sub-wellbarrier

P+ InGaAs

N+ N+

SRC Nonclassical CMOS Research Center

Layer Composition Optimization for Highest Ballistic Current

Trade-offs between DOS and injection velocity:

• More InGaAs: higher injection velocity, lower overall mass

• More InP: higher overall mass, lower injection velocity

0

1

2

3

4

5

6

7

0 0.2 0.4 0.6 0.8 1VG (V)

I_ba

llist

ic (m

A/u

m)

50% InGaAs 50% InP60% InGaAs 40% InP40% InGaAs 60% InP100% InGaAs100% InP

Drive current simulation- ideal (ballistic) assumptionsTaur & Asbeck Groups, UCSD; Fischetti Group: U-Mass: IEDM2007

under similar assumptions, silicon channels show 3-4 mA /m

intrinsic Cgs ~350 fF/mm --- comparable to fringing and stray capacitances

22 nm gate length, 5 nm thick InGaAs / InP channel

S/D Contact Process Flow For III-V MOSFETs

barrier

r

(starting material)

barrier

well

r

r

r

barrier

well

r

r

CBE in-situ etch CBE in-situselective-area regrowth

InGaAs wellInP well InP well InP well

barrier

well

r

r

InP well

electroplateS/D metal

barrier

InGaAs well

r

(starting material) recess etchnonselective regrowthin-situ S/D metal

planarize etch strip planarizationmaterial

InP well

r

r

r

r

well well well well

barrierInP well

barrierInP well

barrierInP well

barrierInP well

r

r

r

r

r

non-selective-area S/D regrowth

selective-area S/D regrowth

III-V MOSFETs Can Provide Very Low S/D Access Resistance

m- 7.0 requires thiscontacts, widenm 50 With

10%.by and reduce willresistance source m- 14

mmS/ 7 / ctancetranscondu

V 7.0)( @ mmA/ 5~/ :Objective

2c

dm

gm

thgsgd

Ig

Wg

VVWI

P + substrate

barrier

sidewall

metal gate

gL

undopedsubstrate

wT

quantum well

gatedielectric

N+ regrowth N+ regrowth

source contact drain contactoxT

undopedsubstrate

S/DL

50 nm

region. access source extrinsicpoor theof because ...resistance source m)- 100(~larger 1:10~ have HEMTsV-III Modern

Improving FETs by Developing Other Materials

Other materials may offer high mobilities but... ID

VDS

increasingVGS

Id

VgsVth

/ where

1/)(for )(

ginjection

thgsthgsinjectiongoxD

LvV

VVVVVVvWcI

→ mobilities above ~ 1000 cm2/V-s of little benefit at 22 nm Lg

increased injection velocities are of value......but not at sacrifice in density of states

Nanopillar and Nanowire Devices

Nanopillar devices might have improved 2-D electrostatics... but only if wire diameter is ~10 nm or less

Access resistances are serious issue

Capacitances to source-drain pad regions a serious concern

III-V Nanowires FETs still must address defect density dielectric-semiconductor interface

III-V nanopillar devices experience same DOS, confinement challenges as planar III-V devices

Conclusion

THz & nm Transistor Electronics is all about the interfaces

Bipolar Transistors:P and N ohmic contacts with very low resistivitystability at high current density

FETsgate dielectricscontact resistancedensity of states