timers interrupt service routines (isr)data. · pdf filen microcontroller programming ii mp6-8...

Microcontroller Programming II

MP

6-1

-G

ener

al p

urp

ose

tim

ers

-C

aptu

re a

nd c

om

par

e unit

-P

WM

unit

Mic

ro-

contr

oll

er

pro

gra

mm

ing

II

6

topics

lecture

week

Gen

eral

Pu

rpo

se T

imer

s


MP

6-2

-O

ne

of

the

mo

st i

mp

ort

ant

issu

es i

n e

mb

edd

ed

con

trol

is t

he

pro

gra

mm

ing

of timers

-W

itho

ut

accu

rate

tim

ing

, d

igit

al c

on

trol

eng

inee

ring

is n

ot

po

ssib

le –

the

con

trol

sign

als

(co

ntr

oll

er

acti

on

) h

ave

to h

appen

at

the

exac

t ri

ght

mo

men

t in

tim

e, e

.g. ti

min

g c

on

tro

l o

f an

en

gin

e, e

tc.

-L

arg

e em

bed

ded

syst

ems

are

oft

en c

entr

ed a

rou

nd

smal

l real-time kernels

wh

ich

off

er s

erv

ices

fo

r

multi-tasking a

pp

lica

tion

s; s

mal

ler

app

lica

tion

s

mak

e u

se o

f Interrupt Service Routines (ISR)

to

ach

iev

e ac

cura

te t

imin

g c

on

tro

l


MP

6-3

-T

he

Gen

eral

Pu

rpo

se T

imer

un

it o

f th

e C

16

7C

R

(GP

T1

–th

ere

are

2 s

uch

unit

s) i

s co

ntr

oll

ed t

hro

ug

h

a n

um

ber

of

Sp

ecia

l F

un

ctio

n R

egis

ters

(S

FR

)

Gen

eral

Pu

rpo

se T

imer

s


MP

6-4

-G

PT

1 c

on

sist

s o

f th

ree

16

-bit

tim

ers

(T2

, T

3,

T4

)

Gen

eral

Pu

rpo

se T

imer

s

Eac

h o

f th

ese

tim

ers

can

be

con

figu

red a

s…

… timer,

… gated timer,

… counter

and

… incremental

interface mode


MP

6-5

-In

timer mode,

th

e timer register

is i

ncr

emen

ted

wit

h e

ver

y t

ick

of

the

inte

rnal

clo

ck s

ou

rce

Gen

eral

Pu

rpo

se T

imer

s

-In

gated timer mode,

th

e (i

nte

rnal

ly i

ncr

emen

ted

)

tim

er c

an b

e sw

itch

ed o

n/o

ff v

ia a

n e

xte

rnal

sig

nal

-In

counter mode,

th

e counter register

is i

ncr

emen

ted

wit

h r

isin

g/f

alli

ng/b

oth

ed

ges

of

an e

xte

rnal

sig

nal

-T

he incremental interface mode

sup

po

rts

inte

rfac

ing

to incremental encoders;

bo

th r

ate

and

dir

ecti

on

are

det

erm

ined

an

d t

he

cou

nte

r re

gis

ter

is i

ncr

emen

ted

/

dec

rem

ente

d a

cco

rdin

gly


MP

6-6

-T

imer

s ar

e p

rob

ably

bes

t ex

pla

ined

usi

ng

th

e

foll

ow

ing

dia

gra

m:

Gen

eral

Pu

rpo

se T

imer

s

-T

he timer register

is l

oad

ed w

ith

an

in

itia

l v

alu

e; i

t

is d

ecre

men

ted

at

a fi

xed

rat

e –

the

tim

er e

lap

ses

wh

en t

he

tim

er r

egis

ter

reac

hes

0

0

0xFFFF

0x0000

Tmax

Tinit

duration

Initial value


MP

6-7

-C

ore

tim

er T

3 i

s co

nfi

gu

red

fo

r timer mode

thro

ugh

its

contr

ol

reg

iste

r T

3C

ON

Gen

eral

Pu

rpo

se T

imer

s

-S

etti

ng

T3

M (

mo

de)

to

bin

ary

00

0 p

uts

T3

in

to

tim

er m

od

e; f

ield

T3

I th

en c

on

tro

ls t

he

freq

uen

cy

wit

h w

hic

h t

he

tim

er r

egis

ter

is u

pd

ated

; T

3U

D

spec

ifie

s th

e d

irec

tion

of

this

up

dat

e (u

p/d

ow

n);

T3

UD

E e

nab

les

the

exte

rnal

con

tro

l o

f th

is d

irec

tion


MP

6-8

-T

he

tim

er c

lock

fre

qu

ency

is

gen

erat

ed b

y p

re-

scal

ing

th

e C

PU

clo

ck (

f CP

U):

Gen

eral

Pu

rpo

se T

imer

s

IT

CPU

T

ff

33

28⋅

=


MP

6-9

-T

he

tim

er i

s sw

itch

ed o

n o

r o

ff u

sin

g b

it T

3R

in

Sp

ecia

l F

un

ctio

n R

egis

ter

T3

CO

N

Gen

eral

Pu

rpo

se T

imer

s

-T

3O

E a

llo

ws

the

stat

e o

f th

e output toggle latch

(T3OTL)

to b

e d

ispla

yed

on

pin T3OUT

(= P

3.3

);

T3

OT

L c

han

ges

its

sta

te w

hen

ever

th

e ti

mer

ela

pse

s


MP

6-1

0

-A

n e

lap

sed

tim

er u

sual

ly t

rig

ger

s an

interrupt;

on

th

e

C1

67

, ev

ery

tim

er c

om

es w

ith

its

ow

n Interrupt

Control register (TxIC)

Gen

eral

Pu

rpo

se T

imer

s

-T

he

T3

IC r

egis

ter

allo

ws

a p

rio

rity

val

ue

to b

e

spec

ifie

d (

gro

up

lev

el, in

terr

upt

lev

el);

in

th

e ca

se o

f

sev

eral

sim

ult

aneo

us

inte

rrup

ts, th

is v

alue

is u

sed t

o

det

erm

ine

wh

ich

in

terr

up

t sh

ou

ld b

e se

rvic

ed f

irst


MP

6-1

1

-E

xam

ple

:

To

gg

le t

he

LE

D c

on

nec

ted

to

po

rt P

3.3

at

a fi

xed

rate

of

0.2

5 s

eco

nds

(ON

: 2

50

ms,

OF

F :

25

0 m

s)

PORT3

5V

Gen

eral

Pu

rpo

se T

imer

s


MP

6-1

2

-T

he

tab

le o

n s

lid

e M

P6

-8 i

ndic

ates

th

at t

he

fast

est

rate

, w

hic

h a

llo

ws

tim

er T

3 t

o h

ave

a p

erio

d o

f 2

50

ms,

is

15

6.2

5 k

Hz

(T3

I =

bin

ary

10

0)

Gen

eral

Pu

rpo

se T

imer

s

0 s

65535

0420 m

s250 m

s

39009

-2

50

ms

rep

rese

nts

the

frac

tio

n o

f 2

50

/42

0 ≈

59

.52

%

of

the

max

imu

m p

erio

d (

42

0 m

s);

the

init

ial

val

ue

of

the

tim

er r

egis

ter

is t

her

efo

re 6

55

35

* 0

.59

5 ≈

39

009


MP

6-1

3

#include <reg167.h>

//#define T3_RELOAD 39009 /* T3 reload value : 250 ms */

#define T3_RELOAD 100 /* T3 reload value : 250 ms */

/* Timer T3 ISR */

void T3_elapsed(void) interrupt 0x23 {

T3 = T3_RELOAD; /* reset T3 */

P2 ^= 0x0001; /* toggle P2.1 */

} /* main program */

void main(void) {

DP2 |= 0x0001; /* P2.1 : output */

P2 |= 0x0001; /* initially: LED off */

(…)

Declares function T3_elapsed as Interrupt Service Routine (ISR) with

interrupt vector number 0x23;this causes the compiler to install its

starting address as entry 0x23 in the interrupt vector jump table

Gen

eral

Pu

rpo

se T

imer

s


MP

6-1

4

#include <reg167.h>

//#define T3_RELOAD 39009 /* T3 reload value : 250 ms */

#define T3_RELOAD 100 /* T3 reload value : 250 ms */

/* Timer T3 ISR */

void T3_elapsed(void) interrupt 0x23 {

T3 = T3_RELOAD; /* reset T3 */

P2 ^= 0x0001; /* toggle P2.1 */

} /* main program */

void main(void) {

DP2 |= 0x0001; /* P2.1 : output */

P2 |= 0x0001; /* initially: LED off */

(…)

Each tim

e T3 underflows a T3 interrupt is triggered; the system

then

saves its current state and diverts program execution to this ISR,

which has to reload the timer register to m

ake the process cyclic

Gen

eral

Pu

rpo

se T

imer

s


MP

6-1

5

(…)

T3 = T3_RELOAD; /* load initial timer value T3 */

/* T3 in timer mode, counting down, pre-scale factor 128, period: 420 ms */

/* alternate output function disabled */

/* T3CON = 0000.0000.1000.0100 = 0x0084 */

T3CON = 0x0084;

T3IC = 0x0044; /* enable T3 interrupt, ILVL = 1, GLVL = 0 */

IEN = 1; /* allow all interrupts to happen */

T3R = 1; /* start timer (T3CON |= 0x0040) */

while(1); /* forever... */

} /* main */

Gen

eral

Pu

rpo

se T

imer

s

Both, T3CON and T3IC

have to be set up to m

ake this tim

er work;

T3CON is configured for timer m

ode with a pre-scale factor of 128

(maxim

um period: 420 m

s) and counting downwards; T3 interrupts

are enabled and an interrupt level (IL

VL) of ‘1’ is chosen (needs to

be different from ‘0’)


MP

6-1

6

(…)

T3 = T3_RELOAD; /* load initial timer value T3 */

/* T3 in timer mode, counting down, pre-scale factor 128, period: 420 ms */

/* alternate output function disabled */

/* T3CON = 0000.0000.1000.0100 = 0x0084 */

T3CON = 0x0084;

T3IC = 0x0044; /* enable T3 interrupt, ILVL = 1, GLVL = 0 */

IEN = 1; /* allow all interrupts to happen */

T3R = 1; /* start timer (T3CON |= 0x0040) */


} /* main */

Gen

eral

Pu

rpo

se T

imer

s

Finally, all interrupts need to be permitted at CPU level (master

switch: IE

N = 1) and the timer m

ust be started (T3R = 1); the form

er

instruction sets bit ‘IE

N’ in the Processor Status Word

which, on the

C167, is m

emory m

apped in bit-addressable m

emory –it would have

been possible to write this as PSW |= 0x0800


MP

6-1

7

Th

e st

ate

of

T3

as

wel

l as

th

e

interrupt

controller

can

be

mo

nit

ore

d

thro

ug

h

per

iph

eral

win

do

ws

Gen

eral

Pu

rpo

se T

imer

s


MP

6-1

8

Gen

eral

Pu

rpo

se T

imer

s

-S

etti

ng

a conditional breakpoint

(T3

==

1 →

i. e

.

just

bef

ore

th

e ti

mer

ela

pse

s) a

llo

ws

the

trig

ger

ing

of

the

inte

rrup

t to

be

obse

rved


MP

6-1

9

Gen

eral

Pu

rpo

se T

imer

s

-T

he

cod

e ex

ecu

tes

unin

terr

upte

d u

nti

l th

e val

ue

in

tim

er r

egis

ter

T3

has

bee

n d

ecre

men

ted

to

‘1

’

-S

ing

le s

tep

pin

g t

hro

ug

h t

he

cod

e

rev

eals

th

at t

he interrupt request

flag T3IR

com

es o

n w

hen

th

e

tim

er underruns

-T

he

tim

er T

3 interrupt service

routine

is a

ctiv

ated

–o

n t

he

C1

67

, th

is a

uto

mat

ical

ly c

lear

s

the

inte

rrup

t re

qu

est

flag


MP

6-2

0

-T

og

gli

ng

a b

it i

n C

:

P2 =P2

^0x00ff;

Logical XOR operator Mask

-E

xam

ple

: P

2 c

on

tain

s v

alu

e 0

x1

23

4

P2 =

0001.0010.0011.0100

P2 =P2 ^0000.0000.1111.1111

P2 =

0001.0010.1100.1011

P2 =P2^0000.0000.1111.1111

P2 =

0001.0010.0011.0100

-T

he

abo

ve

lin

e ca

n b

e ab

bre

via

ted

as

foll

ow

s:

P2 ^=0x00ff;

Gen

eral

Pu

rpo

se T

imer

s

bits differ

→ →→→result is ‘1’

bits the same

→ →→→result is ‘0’

Cap

ture

an

d C

om

par

e u

nit


MP

6-2

1

-C

aptu

re a

nd

Co

mp

are

un

its

(CA

PC

OM

) ar

e si

mil

ar

to g

ener

al p

urp

ose

tim

ers

/ co

un

ters

in

a s

ense

th

ey

mo

nit

or

inte

rnal

/ e

xte

rnal

ev

ents

(e.

g. a

risi

ng

edg

e

on

an

ass

oci

ated

inpu

t li

ne,

etc

.);

on

ce t

he

spec

ifie

d

nu

mb

er o

f ev

ents

has

bee

n o

bse

rved

, th

ey t

rig

ger

an

inte

rru

pt

or

dir

ectl

y m

od

ify

th

e st

ate

of

an o

utp

ut

pin

-T

hes

e u

nit

s ar

e u

sual

ly u

sed

fo

r h

igh

-sp

eed

tim

ing

op

erat

ion

s (e

.g.

wav

efo

rm g

ener

atio

n, et

c.)

wit

h a

min

imu

m a

mo

un

t o

f so

ftw

are

ov

erh

ead

; oth

er

con

troll

ers

oft

en o

ffer

sim

ilar

mec

han

ism

s u

nd

er

slig

htl

y d

iffe

ren

t n

ames

(e.g. Output Compare timer)


MP

6-2

2

Th

e C

AP

CO

M u

nit

s

of

the

C1

67

CR

–

ther

e ar

e tw

o s

uch

un

its

wit

h a

to

tal

of

32

ch

ann

els

–is

bas

ed o

n t

imer

s T

0,

T1

, T

7 a

nd

T8

; th

e

un

it i

s co

ntr

oll

ed

thro

ug

h a

nu

mb

er o

f

Sp

ecia

l F

un

ctio

n

Reg

iste

rs (

SF

R)

Cap

ture

an

d C

om

par

e u

nit


MP

6-2

3

Capture function:

Tri

gg

ered

by

an

exte

rnal

ev

ent

on

the

asso

ciat

ed p

in;

cau

ses

the

curr

ent

tim

er c

on

ten

ts t

o

be

latc

hed

in

to t

he

asso

ciat

ed r

egis

ter

→ use

d t

o measure

durations

Cap

ture

an

d C

om

par

e u

nit


MP

6-2

4

Compare function:

Tri

gg

ered

by

a

mat

ch b

etw

een

th

e

curr

ent

con

ten

ts o

f

the

tim

er a

nd

on

e

of

the

CA

PC

OM

reg

iste

rs;

may

cau

se a

sig

nal

tran

siti

on

on

th

e

asso

ciat

ed p

in →

signal generation

Cap

ture

an

d C

om

par

e u

nit


MP

6-2

5

-T

imer

s T

0/T

7 a

nd

T1

/T8

pro

vid

e tw

o i

ndep

end

ent

hig

h r

eso

luti

on

tim

e b

ases

fo

r th

e ca

ptu

re /

co

mp

are

reg

iste

rs o

f ea

ch u

nit

Cap

ture

an

d C

om

par

e u

nit

The timers can

operate of either

of three clock

sources:

A pre-scaled

CPU clock,

underflows of

GPT2 tim

er T6

or external

events on an

associated input


MP

6-2

6

-T

he

fun

ctio

n o

f ea

ch CAPCOM timer

is c

on

troll

ed

by

a S

pec

ial

Fu

nct

ion

Reg

iste

r (S

FR

): t

he

low

er

hal

f o

f T01CON

con

tro

ls t

imer

T0

, th

e u

pp

er h

alf

con

trols

T1

; a

sim

ilar

pai

r ex

ists

fo

r T

7 a

nd

T8

-T

he

pu

rpo

se a

nd

mea

nin

g o

f ea

ch o

f th

ese

bit

gro

ups

is s

imil

ar t

o t

hat

of

the

Gen

eral

Pu

rpo

se T

imer

s

Cap

ture

an

d C

om

par

e u

nit


MP

6-2

7

-C

AP

CO

M t

imer

s co

un

t u

pw

ard

s; w

hen

a t

imer

ov

erfl

ow

s, i

t is

reloaded

wit

h i

ts r

esp

ecti

ve

relo

ad

val

ue

fro

m T

xR

EL

-T

he

per

iod

of

the

CA

PC

OM

tim

er d

epen

ds

on

this

relo

ad v

alu

e:

Cap

ture

an

d C

om

par

e u

nit

CPU

TxI

Tx

f

TxREL

P3

16

2)

2(+

⋅−

=

0

0xFFFF

0x0000

Tmax

Tinitduration

TxREL


MP

6-2

8

-3

2 capture/compare registers CCx

are

use

d t

o s

tore

the

16

-bit

val

ues

of

a ca

ptu

re o

r co

mp

are

op

erat

ion;

the

asso

ciat

ion

bet

wee

n a

CCxregister

and

an

y o

f th

e

CA

PC

OM

tim

ers

is d

etai

led

in t

he

so-c

alle

d

capture/compare mode control registers(CCMx)

-T

he

mo

de

of

each

ch

ann

el i

s d

efin

ed b

y 4

bit

s

Cap

ture

an

d C

om

par

e u

nit

CCM0 controls channels CC0 –CC3; CCM1 …

CC4 –CCM7, etc.


MP

6-2

9

-C

aptu

re/c

om

par

e o

per

atin

g m

od

es (

CC

MO

Dx

)

Cap

ture

an

d C

om

par

e u

nit


MP

6-3

0

-Capture mode

allo

ws

the

con

tents

of

the

sele

cted

tim

er t

o b

e ca

ptu

red

in

th

e as

soci

ated

CC

xre

gis

ter

wh

en a

n e

xte

rnal

sig

nal

has

a r

isin

g/f

alli

ng

ed

ge;

this

mo

de

is c

om

mo

nly

use

d t

o m

easu

re d

ura

tio

ns

Cap

ture

an

d C

om

par

e u

nit

-T

he

asso

ciat

ed I

/O p

in m

ust

be

pro

gra

mm

ed a

s in

put


MP

6-3

1

-Compare mode

allo

ws

inte

rru

pts

to

be

trig

ger

ed

and

/or

I/O

pin

s to

be

tog

gle

d w

hen

th

e se

lect

ed t

imer

mat

ches

th

e v

alu

e o

f th

e as

soci

ated

CC

xre

gis

ter;

this

mo

de

is c

om

mo

nly

use

d f

or

wav

efo

rm g

ener

atio

n

Cap

ture

an

d C

om

par

e u

nit


MP

6-3

2

-E

xam

ple

: Compare mode 0

Pu

lse

seq

uen

ce g

ener

ated

by

tri

gg

erin

g i

nte

rru

pts

at

use

r p

rog

ram

mab

le t

imes

(co

ntr

oll

ed t

hro

ug

h t

he

com

par

e v

alu

es cv1

and

cv2

); u

po

n r

each

ing

lev

el

cv1

, th

e C

Cx

reg

iste

r is

mo

dif

ied

to

cv2

, u

po

n

reac

hin

g cv2 C

Cx

is r

eset

to

cv1

Cap

ture

an

d C

om

par

e u

nit


MP

6-3

3

#include <reg167.h>

#define PERIOD (1.68 -

1)/1.68*0xFFFF /* 1 second */

#define cv1 (0xFFFF -

PERIOD/4) /* 1/4 of this period */


PERIOD/4*2) /* 2/4 of this period */

/* CAPCOM CC0 ISR */

void CC0_event(void) interrupt 0x10 {

if(CC0 == (int)cv1) CC0 = cv2;

else CC0 = cv1;

} (…)

CAPCOM tim

er count upwards; the period is therefore determined

by the duration from 1 second to 1.68 seconds –the relative fraction

of this duration (i. e. (1.68 –1)/1.68 ) is multiplied by the full scale

timer value 0xFFFF to yield the period value

A sim

ilar idea leads onto the compare values cv1

and cv2

Cap

ture

an

d C

om

par

e u

nit


MP

6-3

4

#include <reg167.h>

#define PERIOD (1.68 -

1)/1.68*0xFFFF /* 1 second */


PERIOD/4) /* 1/4 of this period */


PERIOD/4*2) /* 2/4 of this period */

/* CAPCOM CC0 ISR */

void CC0_event(void) interrupt 0x10 {

if(CC0 == (int)cv1) CC0 = cv2;

else CC0 = cv1;

} (…)

Interrupt vector number 0x10 has been reserved for CAPCOM

channel CC0; here, we use the ISR to swap compare value cv1for

cv2 and vice versa (alternate) –this could for instance be used to

program a m

ulti-channel PWM: All channels start with logic level

‘high’ and are switched off at the different compare values

Cap

ture

an

d C

om

par

e u

nit


MP

6-3

5

(…)

void main(void) {

DP2 |= 0x0001; /* P2.0 : output associated with CC0 (CC0IO) */

P2 |= 0x0001; /* set P2.0 high -> LED off */

T01CON &= 0xFF00; /* reset timer 0 (T0): Timer mode */

T01CON |= 0x0006; /* set timer frequency: T0I = binary 110 */

T0REL = PERIOD; /* set RELOAD register (timer 0) */

T0 = PERIOD; /* reset T0 register */

CCM0 &= 0xFFF0; /* reset CCMOD0 */

CCM0 |= 0x0005; /* initialize CCMOD0 : compare mode

1 */

CC0 = cv1; /* initialize CC0 with compare value 1 (cv1) */

CC0IC = 0x0044; /* enable CC0 interrupt, ILVL = 1, GLVL = 0 */

T0R = 1; /* start T0 */

IEN = 1; /* allow all interrupts */


} /* main */

Setting up of timer T0, pre-scale value: 512 (maxim

um period: 1.68 s)

Cap

ture

an

d C

om

par

e u

nit


MP

6-3

6

(…)

void main(void) {









1 */



T0R = 1; /* start T0 */



} /* main */

Mode selection for CC0 (compare mode 1);initialize CC0 with cv1

Cap

ture

an

d C

om

par

e u

nit


MP

6-3

7

(…)

void main(void) {









1 */



T0R = 1; /* start T0 */



} /* main */

CC0 interrupts are enabled, choosing an interrupt level (IL

VL) of ‘1’

Cap

ture

an

d C

om

par

e u

nit


MP

6-3

8

Th

e st

ate

of

the

CAPCOM

unit(s) and

its timers

can

be

mo

nit

ore

d

thro

ug

h

per

iph

eral

win

do

ws

Cap

ture

an

d C

om

par

e u

nit


MP

6-3

9

Th

e co

rrec

t

op

erat

ion

of

the

pro

gra

m

can

be

ob

serv

ed

wit

h a

bre

akp

oin

t

insi

de

the

ISR

Cap

ture

an

d C

om

par

e u

nit

Pu

lse

Wid

th M

od

ula

tion

(P

WM

)


MP

6-4

0

-M

ost

mic

roco

ntr

oll

ers

do

no

t co

me

wit

h i

nte

gra

ted

D/A

co

nv

erte

rs;

nev

erth

eles

s, a

nal

ogu

e ou

tput

sig

nal

s ca

n b

e g

ener

ated

by

low

-pas

s fi

lter

ing

a

Pulse-Width Modulation (PWM)

sig

nal

-P

WM

sig

nal

s ca

n b

e g

ener

ated

man

ual

ly u

sing

tim

ers

and

in

terr

upts

or,

mo

re e

leg

antl

y, b

y u

sing

a

CA

PC

OM

un

it

-P

WM

sig

nal

s p

lay

such

an

im

po

rtan

t ro

le i

n m

od

ern

emb

edd

ed c

on

trol

app

lica

tio

ns

that

mic

roco

ntr

oll

ers

no

w o

ften

co

me

wit

h d

edic

ated

PW

M u

nit

s

Pu

lse

Wid

th M

od

ula

tion

(P

WM

)


MP

6-4

1

-A

PWM signal

is a

pu

lse

trai

n w

ith

a f

ixed

per

iod

and

a v

aria

ble

duty cycle (ON:OFF ratio);

the

du

ty

cycl

e ca

n v

ary

fro

m 0

% (

off

) to

10

0%

(al

way

s o

n)

...

...

t 0t 0+ T

t 1

OFF

ON

t0x0000

threshold 1 (duty cycle)

threshold 2 (period, fixed)

0xFFFF

Pu

lse

Wid

th M

od

ula

tion

(P

WM

)


MP

6-4

2

-O

n t

he

C1

67

th

ere

are

4 i

nd

epen

den

t P

WM

un

its;

they

are

co

nfi

gu

red

th

rou

gh

a n

um

ber

SF

R:

Pu

lse

Wid

th M

od

ula

tion

(P

WM

)


MP

6-4

3

-E

ach

PW

M u

nit

has

its

ow

n 16-bit counter,

a period

register (PPx)

and

a pulse width register (PWx)

-B

oth

PP

xan

d

PW

xar

e

shad

ow

ed t

o

allo

w t

hem

to

be

mo

dif

ied

wh

ile

the

un

it

is a

ctiv

e

-T

he

PW

M c

han

nel

s ca

n b

e co

nfi

gu

red

to

tri

gg

er a

n

inte

rru

pt

to i

ndic

ate

the

beg

innin

g o

f a

new

per

iod;

this

is

spec

ifie

d i

n Interrupt Control register PWMIC

Pu

lse

Wid

th M

od

ula

tion

(P

WM

)


MP

6-4

4

-T

he operating mode

of

each

PW

M c

han

nel

is

con

troll

ed b

y t

wo

co

mm

on

co

ntr

ol

reg

iste

rs,

PWMCON0

and

PWMCON1

-F

ou

r m

od

es o

f o

per

atio

n c

an b

e ch

ose

n:

(1)Standard PWM (edge aligned)

(2)Symmetrical PWM (centre aligned)

(3)Burst mode (channel 0 acts as enable for chnl1)

(4)Single shot mode

-T

he operating mode

is s

elec

ted

in

PWMCON1:

Pu

lse

Wid

th M

od

ula

tion

(P

WM

)


MP

6-4

5

-PWMCON0

con

figu

res

the timers

and

interrupts:

Pu

lse

Wid

th M

od

ula

tion

(P

WM

)


MP

6-4

6

-PWMCON0

con

trols

th

e P

WM

tim

ers

and

in

terr

upts

Pu

lse

Wid

th M

od

ula

tion

(P

WM

)


MP

6-4

7

-T

he

clo

ck s

ou

rce

of

the

PW

M u

nit

can

be

eith

er t

he

CP

U c

lock

(f C

PU)

or

a p

re-s

cale

d v

ersi

on

ther

eof

(fC

PU/6

4)

Pu

lse

Wid

th M

od

ula

tion

(P

WM

)


MP

6-4

8

-W

ith

fC

PU

= 2

0 M

Hz

this

all

ow

s fo

r th

e fo

llo

win

g

max

imu

m /

min

imu

m P

WM

fre

qu

enci

es:

-N

ote

th

at t

he

cen

tred

PW

M o

nly

ru

ns

at h

alf

the

rate

of

the

edge

alig

ned

PW

M

-Standard PWM

is s

elec

ted

by

cle

arin

g b

it P

Mx

in

reg

iste

r P

WM

CO

N1

; th

is c

ause

s th

e co

rres

po

ndin

g

tim

er t

o c

ou

nt

up

un

til

it m

atch

es t

he

val

ue

of

the

period shadow register

Pu

lse

Wid

th M

od

ula

tion

(P

WM

)


MP

6-4

9

-U

po

n r

each

ing

th

e per

iod

, th

e timer count register

is

auto

mat

ical

ly r

eset

to 0

an

d t

he

pro

cess

sta

rts

ov

er

-T

he

asso

ciat

ed o

utp

ut

(if

enab

led

) is

kep

t ‘l

ow

’ un

til

the

tim

er h

as r

each

ed t

he

val

ue

of

the pulse width

shadow register;

up

on

rea

chin

g t

his

val

ue,

th

e o

utp

ut

latc

h i

s se

t ‘h

igh

’

Pu

lse

Wid

th M

od

ula

tion

(P

WM

)


MP

6-5

0

Th

e d

uty

cy

cle

of

an

edge aligned PWM

is c

on

tro

lled

by

th

e

corr

esp

ond

ing

PW

reg

iste

r; i

ts v

alu

e

def

ines

th

e off-phase

of

the

PW

M s

ign

al

(val

ues

lar

ger

th

an

the

per

iod

sw

itch

th

e

sig

nal

off

–se

e la

st

lin

e, P

Wx

= 8

)

-E

xam

ple

:

A s

mal

l D

C-m

oto

r is

to

be

dri

ven

usi

ng

an

ed

ge

alig

ned

PW

M s

ign

al o

n P

7.3

wit

h a

per

iod

of

10

0 m

s

and

a p

re-p

rog

ram

med

du

ty c

ycl

e

Pu

lse

Wid

th M

od

ula

tion

(P

WM

)


MP

6-5

1

PORT7

5V

0V

M

-A

per

iod

of

10

0 m

s m

ean

s a

PW

M r

ate

of

10

Hz;

th

e

tab

le o

n s

lid

e M

P6

-48

in

dic

ates

th

at t

his

can

be

ach

iev

ed w

ith

a p

re-s

cale

d c

lock

(f C

PU/6

4)

and

usi

ng

bet

wee

n 1

4 a

nd

16

bit

of

the

cou

nte

r re

gis

ter

Pu

lse

Wid

th M

od

ula

tion

(P

WM

)


MP

6-5

2

-T

he PWMCON0 r

egis

ter

is t

hu

s se

t to

0x

00

88

(bin

ary

000

0.0

000

.10

00

.100

0 –

pre

-sca

led

clo

ck o

n

PW

M c

han

nel

3, ti

mer

is

run

nin

g)

-T

he

mo

de

con

trol

reg

iste

r PWMCON1

is s

et t

o

0x

000

8 (

bin

ary

00

00

.00

00

.00

00.1

00

0 –

edg

e al

ign

ed

PW

M, o

utp

ut

pin

enab

led

)


MP

6-5

3

#include <reg167.h>

#define PERIOD (20e6/64)*100e-3 /* 100 ms */

#define OFF_PHASE PERIOD/10*9 /* duty cycle */

void main(void) {


P7 &= ~0x08; /* set P7.3 low -> motor off */

PP3 = PERIOD; /* initialize channel 3 period register */

PW3 = OFF_PHASE; /* initialize channel 3 pulse width

register */

PWMCON1 = 0x0008; /* channel 3: edge aligned PWM, o/p

enabled */

PWMCON0 = 0x0088; /* channel 3 operates of fCPU/64, T. running */


} /* main */

PERIO

D is defined in relation to the pre-scaled CPU clock (f C

PU/64);

one tick of this clock lasts for 1/(20⋅ ⋅⋅⋅106/64) ≈ ≈≈≈3.2 µ µµµs → →→→

the PERIO

D

value is 100 m

s / 3.2 µ µµµs = (20⋅ ⋅⋅⋅106/64) ⋅ ⋅⋅⋅100 ⋅ ⋅⋅⋅10-3; the PWM runs in the

background –the program does not have to do anything anymore!

Pu

lse

Wid

th M

od

ula

tion

(P

WM

)


MP

6-5

4

Th

e

op

erat

ion

of

the

PW

M u

nit

can

be

mo

nit

ore

d

thro

ug

h a

per

iph

eral

win

do

w

Cap

ture

an

d C

om

par

e u

nit

timers interrupt service routines (isr)data. · pdf filen microcontroller programming ii mp6-8...

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