title laser testing and analysis of see in ddr3 memory ... · heavy ions in previous works1 –may...

Title

Name

Laser testing and analysis of SEE in DDR3 memory components

1

P. Kohler, V. Pouget, F. Wrobel, F. Saigné, P.-X. Wang, M.-C. Vassal

[email protected]

October 09 2017 2Pierre Kohler

• Dynamic memories (DRAMs) widely used in space applications for mass storage

• DDR3 are now being considered for space applications in the coming years– Clock frequency up to 1066 MHz (2133 Mbps)– Capacity up to 8 Gb

• Interest for identification of a new radiation tolerant component in order to integrate it in space modules– DDR3L : Low power DDR3 interesting for energy saving at module level

Context & Motivation

What about DDR3L radiation effects sensitivity ?

SEE, TID…

Methodology optimization

NSREC 2017 - “Analysis of Single-Event Effects in DDR3 and DDR3L SDRAMs using Laser Testing and Monte-Carlo simulations”


• Devices under study

• Experimental setup

• Laser testing results

• Monte-Carlo simulation

• Conclusion

Outline


Devices under study

• DUTs specifications

SampleMemory

typeDensity

Max clockfrequency

Supplyvoltage

A DDR3 4 Gb 666 MHz 1.5 V

B DDR3/L 2 Gb 933 MHz 1.35 / 1.5V

C DDR3/L 4 Gb 800 MHz 1.35 / 1.5V

Sensitive area

Irradiation beam

Silicon substrateSilicon substrate e

Removed plastic• Sample preparation

– DUTs are mounted in flip-chip FBGA plastic package

– The plastic is removed by acid attack to provideaccess to the silicon substrate backside


Test bench hardware overview

• Test bench specifications

– Controlling DDR3/L SDRAMs under irradiation

– DUTs clock frequency up to 800 MHz

– Up to 8 DUTs

– Parametric tests

• Data retention time test

• Power consumption monitoring

– Functional tests

• Read/write periodic cycles

• Individual current limiting (Delatcher)

Motherboard

System on Chip (SoC)

Processing system (PS)

CPU0 CPU1

Test software

Programmable Logic (PL)

Memory

controller

Latchup

flags IP

User

interface

I2C

UART

Ethernet

Mechanical interface board

Ext. power

supply

SODIMM boardDevice Under Test

Current monitoring

Current limiting

Power supply

management board


• Laser testing facility– 2-photon laser facility of the IES lab of

the University of Montpellier

– Estimated TPA induced charge track FWHM : 0.7 µm

• Test procedure

– Tests were performed at 400 MHz

– Standard 64 ms auto-refresh interval was used (except for specific test modes)

– Laser testing methodology• Starting with low pulse energies to observe non-

destructive event

• Gradual increase of laser energy to measure SEE threshold

• Scan along Z axis to find the most sensitive depth

• 2D mapping of SEU to descramble the memory organization

Experimental setup

Asynchronous

laser shots

Initialization

Write pattern

Read/compare

End of the test

SEE ?

Irradiation

complete?

SEE report

Current monitoring

SEE report

Latchup ?


• Memory array organization

– All DDR3 SDRAMs are divided in 8 banks

– Banks in DUT A and C are divided in 4 blocks

– Banks in DUT B are divided in 2 blocks

– Each block is divided in sub-blocks

• Data bits organization

– Descrambling : Correspondence between corrupted logical address and laser spot position

– 3 tested devices exhibit very different scrambling strategies

• For DUT A and B : the 8 bits of a same word are distributed into several sub-blocks

• For DUT C, 4 bits of a same word are located in the same sub-block More prone to MBU

Laser testing results

Memory organization

DUTSize X[µm]

Size Y[µm]

Sub-blocks/row

Sub-blocks/col

Estimated bitsize [nm²]

A 100 50 8 33 104

B 68 51 12 33 104

C 72 43 8 27 5.103

Sub-blocks description

...

...

...

...

...

...

...

...

...

...

...

...

...

...

...

...

...

...

...

...

...

...

...

...

...

...

...

...

...

...

...

...

bank

B4,5,6,7

A0,1,2,3

D4,5,6,7

C0,1,2,3

F4,5,6,7

E0,1,2,3

H4,5,6,7

G0,1,2,3

J4,5,6,7

I0,1,2,3

L4,5,6,7

K0,1,2,3

N4,5,6,7

M0,1,2,3

P4,5,6,7

O0,1,2,3

A4,5,6,7

B0,1,2,3

C4,5,6,7

D0,1,2,3

G4,5,6,7

F0,1,2,3

G4,5,6,7

H0,1,2,3

I4,5,6,7

J0,1,2,3

K4,5,6,7

L0,1,2,3

M4,5,6,7

N0,1,2,3

O4,5,6,7

P0,1,2,3

DUT A

DUT B

DUT C

8 or 12 sub-blocks

27 or 33 sub-blocks

A6 A2 A7 A3 A5 A0 A4 A1

D0

F3

C6

E4

A3

C3

B0

E0

B5

D5

A7

F7

D1

F2

C7

E5

A2

C2

B1

E1

A4

F4

B6

D6

F0

D3

E6

C4

B3

E3

A0

C0

A5

F5

B7

D7

F1

D2

E7

C5

B2

E2

A1

C1

B4

D4

A6

F6


0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

0

5

10

15

20

25

30

DUT A DUT B DUT C

SE

U T

hre

shold

(n

J²)

SEU Threshold pattern 0x00 - 1.5VSEU Threshold pattern 0x00 - 1.35VSEU Threshold pattern 0xFF - 1.5VSEU Threshold pattern 0xFF - 1.35VSEFI Threshold - 1.5V

• SEU and SEFI laser energy threshold measurement

– SEUTH for 0x00 pattern and the SEFITH

are roughly the same for the 3 DUTs

– SEUTH for the 0xFF pattern differs by a factor 3 between DUT A and B

– In low power mode SEUTH is substantially lower than in normal power mode (≈ 60%)


SEE laser energy thresholds


Bitline

Stacked capacitor

CC CCCBCB

VREF

N+N+bWL

N+N+bWL

P

Metal

screen

Dielectric

screen

STI

• Unexpected result : Important ratio between SEU and SEFI thresholds

– Contrary to what was observed under heavy ions in previous works1

– May be explained by the buried word-line (bWL) technology cell architecture

– The small pitch of the bWLs (56 to 80 nm) may act as a partially reflecting virtual metal layer

1 M. Herrmann et al, "New SEE and TID test results for 2-Gbit and 4-Gbit DDR3 SDRAM devices RADECS, 2013


SEU/SEFI thresholds comparison


1

10

100

1000

0.80 1.00 1.20 1.40 1.60 1.80

MC

U m

ult

ipli

cit

y

E2/ETH2

0x00 patternA

B

C

• Laser pulse energy increase MCU multiplicity increase

• 2 phenomena may explain the significant rise of the multiplicity

– The effective laser spot size expands with energy

– Total amount of charge generated by photoelectric effect increases with laser energy diffusion towards adjacent cells

• These results may constitute behaviors under heavy ions with high LET or at grazing incidence

• Specific behavior of DUT C : with pattern 0xFF, damage threshold and correctable SEU threshold are nearly the same

1

10

100

0.80 1.00 1.20 1.40 1.60 1.80 2.00

MC

U m

ult

ipli

cit

y

E2/ETH2

0xFF patternA

B


MCU multiplicity vs E²/ETH²


• Observation : Even above SEE threshold, sporadic events detection

– Read cycle range : 1 to 10s (depending on the address range)

– Laser pulse period : 100 ms(much larger than the refresh period)

Test cycle

Laser pulse

SEE

detection

SEE detection

period


Atypical upset occurrence - Observation

• Definition : SEE detection period is the SEE average time between two SEE observations


• Hypothesis : Existence of a critical time window for generating SEUs

• From previous works1 2

– Bit-line upset : bit-line disturbance occurring during a specific read or refresh cycle state when bit-lines are placed in a floating state

1G. Schindlbeck, "Types of soft errors in DRAMs," RADECS, 20052A. Bougerol, F. Miller and N. Buard, "SDRAM Architecture & Single Event Effects Revealed with Laser“, IOLTS 2008

Equalizer

VCC/2

Precharge

VCC/2

Memory cell Sense amplifier

VCC/2

VCC/2

0 1 2 3

VREF

VREFEQPRE WL /SA SA

1

VREF+

VREF-

VREF- 0

VREF+ 1BL

/BL

Comp. DQ

1

Critical time window for bit-line upset


Atypical upset occurrence - Hypothesis

0 2 3 3


• Highlight of the critical window for SEUs in the memory array using laser testing tool

– SEU detection period vs laser pulse period

(at TREFRESH = 32 and 64 ms)

Max of TSEE when TLASER = k x TREFRESH

Existence of a vulnerable time window within each refresh cycle

SE

E d

etec

tio

np

erio

d(s

)

Laser pulse period (ms)

0

50

100

150

200

250

0 20 40 60 80 100 120 140

Refresh period : 32 ms

0

100

200

300

400

0 20 40 60 80 100 120 140

Refresh period : 64 ms

• SEU threshold vs laser pulse period supports this hypothesis

– SEUTH remains constant, regardless of the laser pulse period

These upsets are not induced by charge integration during several consecutive pulses


Evidence for bit-line upsets

8

9

10

11

12

20 40 60 80

SE

U t

hre

sho

ld (

nJ²

)

Laser pulse period (ms)

0xFF pattern

0x00 pattern


• Comparison of heavy ion SEU data obtained on DUT A in previous work1 and Monte-Carlo simulation– Simulation of only cell upsets performed with

MC-Oracle

– Bits size and organization estimated from values obtained with IR camera and laser irradiation tool

– We observe a good fit above 20 MeV.cm²/mg

• Lower part of the heavy ion data seems to confirmed the occurrence of bit-lines upsets– Lower threshold due to larger collecting nodes

– Low cross-section due to the critical time window and refresh period ratio

Monte-Carlo Simulation

1E-17

1E-16

1E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-09

1E-08

0 10 20 30 40 50 60 70 80 90

Cro

ss s

ecti

on

(cm

²/b

it)

LET (MeV.cm2/mg)

MC-Oracle

Heavy Ion data

1K. Grürmann et al., "Heavy Ion Sensitivity of 16/32-Gbit NAND-Flash and 4-Gbit DDR3 SDRAM," 2012 REDW


• Laser testing and analysis of SEE in DDR3 memory components from 3 different manufacturers using two-photon laser testing

• Specific test bench developed and validated during experimental TID, HI and laser test campaigns

• Laser testing results• Extraction of physical and technological information (bit, array organization)• SEU/SEFI thresholds measurement and comparison• MCU multiplicity vs laser energy• Demonstration of the occurrence of bit-line upsets

• Laser good complementarity tool before HI experiments and for extracting important information for SEE assessment

Conclusion

Thank you for your attention


Backup slides


Standard DRAM architecture

DRAM principles

DRAM Cell• DRAM : Dynamic Random Access Memory

• 1T/1C Cell

• Binary information stored in a capacitor connected to an access transistor

• Capacitor leakage current induces the need to periodically refresh information

• Volatile : Information are lost after power cycling

Memory array

Inputs / Outputs

Peripheral circuitry

Memory physical organization• Common standard (JEDEC)

• Manufacturer dependent elements:

– Technology node

– Memory cells scrambling (physical distribution of the cells on the chip)

– Capacitor technology

– Peripheral circuitry

VREF

Access transistor

Storage capacitor

Wo

rd li

ne (

WL)

Bit line (BL)


Motherboard

Zynq-7000 System-on-Chip



CPU0 CPU1

Bus

SEL flags IP

DDR3 controller

Refreshcontrol IP

SODIMM socketLPC connector

Current limiters DUTs

8 flags

UART

Ethernet

I2C

I2C

FIFO (Events reports)

Hardware design architecture

Refresh control IP• User control of the Refresh

command• Aim : Data retention time

measurement• Configurable time interval

SEL flags IP• Stores latchup flags in a register• “OR” logic gate asserts an output

signal when a latchup is detected

FIFO• Software CPU shared memory• Stores events reports


Software Architecture

Functionaltesting

Parametrictesting

Driver INA209

DDR3 controller

I2C Driver

I2C

Refreshcontrol IP

SEL Flags IP

Refreshcontrol

Currentlimiting

Memory write and

read

Currentmonitoring F

I

F

O

User interface

HardwareSoftware

Driver Refresh control IP

Driver SEL Flags IP

Application Drivers


Single-Event Effects

• Algorithm proposed to classify Single-Event Effects :

– SEL monitoring runs in parallel

– Identify SEU, Multiple upsets, stuck bits and different types of SEFIs

– Reveal errors in control registers

• The algorithm should evolvedepending on the test results


• Use of the two processors available in the Zynq module

– CPU0 functions• Parse ethernet user commands

• Control test program sequences

• Unqueue events reports stored in a FIFO

– CPU1 functions• Manage DUTs read/write accesses

• Check/correct SEUs

• Report events in a FIFO

• CPU1 pre-processing

– In order to prevent FIFO flooding• Add MBUs detection and correction

functions

• Add SEFIs detection functions

• Shared memory stores test parameters and commands sent fromCPU0 to CPU1

Software development


CPU1

FIFOEvents reports

CPU0

DD

R3

co

ntr

olle

r

256 kB shared memory (OCM)

UART

Ethernet

Test

Pre-processing

Debug

Report

Test commands


title laser testing and analysis of see in ddr3 memory ... · heavy ions in previous works1 –may...

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