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TSC9560 HIC Confidential Proprietary

HIC NON-DISCLOSURE AGREEMENT REQUIRED

TSC9560

Datasheet Rev1.3

CMOS Microcontroller Unit

HIC R&D Center.

TSC9560 HIC Confidential Proprietary


Revision History

Revision History

Release Number Date Author Summary of Changes

1.0 2016/06 HIC Initial version

1.1 2016/07 HIC Update USB description

1.2 2016/10 HIC add mpu,cache,pmu_rtc feature modify package information

1.3 2017/06 HIC modify package information

Section 4 RF Interface 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . …. . . . . . . . . . 29 4.2 General description. . . . . . . . . . . . . . . . . . . . . . . . . . . . …. . . . . . . . . . 30 4.3 Features and benefits . . . . . . . . . . . . . . . . . . . . . . . . . ….. . . . . . . . . . . 30 4.4 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . …. . . . .. . . . . . 31 4.4.1 Register bit behavior. . . . . . . . . . . . . . . . . . . . . . . . …. . . . .. . . . . . . 31 4.4.1.1 register overview . . . . . . . . . . . . . . . . . . . . . . . . . …. . . .. . . . . . . 33 4.4.2 Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . …. . . . .. . . . . . 34 4.4.2.1 Page0 : Command and status . . . . . . . . . . . . . . …. . . . .. . . . . . . 34 4.4.2.2 Page 1:Communication . . . . . . . . . . . . . . . . . . . . …. . . . .. . . . . . 45 4.4.2.3 Page2:Configuration . . . . . . . . . . . . . . . . . . . . . . . …. . . .. . . . . . 56 4.5 RF command set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ….. . . . . . . . . . 63 4.5.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . ….. . . . . . . . . . 63 4.5.2 General behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ….. . . . . . . 63 4.5.3 Command overview . . . . . . . . . . . . . . . . . . . . . . . . . . . ….. . . . . . . . 64

TSC9560 HICConfidential Proprietary


Section 1 Introduction

1.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Section 2 System Memory Map

2.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.2 Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Section 3 Signal Description

3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.2 Package Pinout Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.2.1 QFN68 Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.2.2 QFN76 Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.2.3 Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Appendix A Preliminary Electrical Characteristic

A.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

A.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

A.3 Electrostatic Discharge (ESD) Protection. . . . . . . . . . . . . . . . . . . . . . 25

A.4 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.5.3.1 Command descriptions . . . . . . . . . . . . . . . . . . . . …. . . . . . . . .64 4.6 Functional description. . . . . . . . . . . . . . . . . . . . . . . . . …. . . . . . . . . . . 70 4.6.1 ISO/IEC 14443 A functionality . . . . . . . . . . . . . . . . . …. . . . . . . . . . 70 4.6.2 ISO/IEC 14443 B functionality . . . . . . . . . . . . . . . . . . …. . . . . . . . . 71 4.6.3 Analog interface and contactless UART. . . . . . . . . . …. . . . . . . . . . 71 4.6.3.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ….. . . . . . . . . 71 4.6.3.2 TX p-driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . …. . . . . . . . . 72 4.6.3.3 Serial data switch . . . . . . . . . . . . . . . . . . . . . . . . . …. . . . . . . . . . 74 4.6.3.4 MFIN and MFOUT interface support . . . . . . . . . . …. . . . . . . . . . 74 4.6.3.5 CRC coprocessor . . . . . . . . . . . . . . . . . . . . …. . . . . . . . . . . . . . . 75 4.6.4 FIFO buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . …. . . . . . . . . 75 4.6.4.1 Accessing the FIFO buffer . . . . . . . . . . . . . . . . . …. . . . . . . . . . . 75 4.6.4.2 Controlling the FIFO buffer. . . . . . . . . . . . . . . . …. . . . . . . . . . . . 76 4.6.4.3 FIFO buffer status information . . . . . . . . . . . . . …. . . . . . . . . . . . 76 4.6.5 Interrupt request system. . . . . . . . . . . . . . . . . . . . …. . . . . . . . . . . . 77 4.6.5.1 Interrupt sources overview . . . . . . . . . . . . . . . . …. . . . . . . . . . . . 77 4.6.6 Timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . …. . . . . . . . . . . . 78 4.6.7 Power reduction modes . . . . . . . . . . . . . . . . . . . . . . …. . . . . . . . . . 79 4.6.7.1 Hard power-down. . . . . . . . . . . . . . . . . . . . . . . . . . . …. . . . . . . . 79 4.6.7.2 Soft power-down mode . . . . . . . . . . . . . . . . . . . . . …. . . . . . . . . 79 4.6.7.3 Transmitter Power-down mode . . . . . . . . . . . . . …. . . . . . . . . . . 80 4.6.8 Oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . …. . . . . . . . . . 80 4.6.9 Reset and oscillator start-up time . . . . . . . . . . . . . . …. . . . . . . . . . . 81 4.6.9.1 Reset timing requirements . . . . . . . . . . . . . . . . …. . . . . . . . . . . . 81 4.6.9.2 Oscillator start-up time . . . . . . . . . . . . . . . . . …. . . . . . . . . . . . . . 81 ..

Figure 1-1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 2-1 Normal Single Chip Mode Address Map . . . . . . . . . . . . . . . . . 12 Figure 2-2 Normal Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 3-1 TSC9560 QFN68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 3-2 TSC9560 QFN76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 2-1 Register Address Location Map. . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 3-1 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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1.1 Introduction

TSC9560 is a multi-purpose MCU based on the HIC central processor unit (CPU). TSC9560 is designed to act as a controller for information security and MPOS application .

The temperature range is of -25

to 85 O C.The operating frequency is 80MHz.

Chip package is:

• QFN76

• QFN68

1.2 Features

Features of TSC9560:

• HIC processor :

– 32-bit load/store reduced instruction set computer (RISC) architecture

with fixed 16-bit instruction length

– 16 entry 32-bit general-purpose register file

– Efficient 3-stage execution pipeline, hidden from application software

– Single-cycle instruction execution for many Instructions, three cycles for branches

– Support for byte/halfword/word memory accesses

– Embedded interrupt controller, support nested vector interrupts.

– Single-cycle 32-bit x 32-bit hardware integer multiplier array

3~13 cycles hardware integer divider array

• Cache

– Has two AHB bus interfaces, a master and a slave interface.

– Has a 2-way set-associative organization.

– Uses both the positive and negative edges of its single clock input

– Has an AHB bus interface to access its programmer's model.


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Introduction

• OnCE debug support

• On-chip, 64K Bytes of static random-access memory (SRAM):

– Single cycle byte, half-word (16-bit), and word (32-bit) reads and writes

• On-chip, 32K Bytes of static read only memory (ROM):

– Single cycle byte, half-word (16-bit), and word (32-bit) read access.

• On-chip 512K Bytes embedded flash (EFLASH)

– 512 Bytes page size

– Read Access Time:

50ns(max) @ EV=PV=0

200ns(max)@EV=1 or PV=1

– Endurance : 100000 Cycles(Min)

– Greater than 10 years under room temperature

– Fast Page Erase/Word Program

– Program Time of each pulse : 4.4us(Max)

– Program hold time:20ns(min)

– Mass Erase Time : 40ms(Max)

– Single cycle byte, half-word(16-bits) and word(32-bits) read access

• CPM

– Two system clock sources

Internal high speed 160MHz oscillator

Internal low speed 1MHz oscillator

– Separate clock divider

– Support for power saving mode

– Module clock can be gated separately

• Two Periodic interval timer :

– 16-bit counter with modulus "initial count" register

– Selectable as free running or count down

– 16 selectable prescalers — 2 0 to 2 15

• Watchdog timer :




– Pause option for low-power modes

• Time Counter :


– Pause option for low-power modes

• Reset :

– Separate reset in and reset out signals

– Five sources of reset:

Power-on reset

Software reset

Watchdog timer

Real Time Counter

Power Attack Detect Reset (Low and High Voltage Detect Reset)

– Status flag indicates source of last reset

• DMA Controller

– Six independently programmable DMA controller channels

– Data transfers in 8, 16, 32 ,64bits

– Support single transfer, Burst 4, 8,16 transfer, and burst always under a speical case.

– Support single cycle transfer

– Support automatic transfer mode

– Support LLI transfer mode

– Follow a fixed priority rule

• EDMAC

– Programmable transfer total number

– Programmable read buffer address and write buffer address

– Support read, write and write then read transfer

• CRC coprocessor

– Support CRC32 / CRC16 / CRC8

– Support DMAC Data from CRC

• External interrupts supported(EPORT) :

– Rising/falling edge select



Introduction

– Low-level sensitive

– Ability for software generation of external interrupt event

– Interrupt pins configurable as general-purpose I/O

• I2C Controller

– Supports 7 bit addressing.

– Supports Standard Mode, Fast Mode and High-Speed Mode

– Software option to select between High-Speed mode and Standard/Fast mode

– Compatibility with standard and fast-mode of I2C bus version 2.1 standard.

– Multiple-master operation.

– Software-programmable for one of 64 different serial clock frequencies.

– Software-selectable acknowledge bit.

– Interrupt-driven, byte-by-byte data transfer.

– Arbitration-lost interrupt with automatic mode switching from master to slave.

– Transfer completion and read configure interrupt.

– Start and stop signal generation/detection.

– Repeated START signal generation.

– Acknowledge bit generation/detection.

– Bus-busy detection.

– Option slave address receiving enable when system clock stop mode

– SCL or SDA line gpio function supported

• Serial communications interface (SCI):

– Full-duplex operation

– 13-bit baud rate prescaler

– Programmable 8-bit or 9-bit data format

– Separately enabled transmitter and receiver

– Separate receiver and transmitter CPU interrupt requests

– Two receiver wakeup methods (idle line and address mark)

– Receiver framing error detection



– Hardware parity checking

– 1/16 bit-time noise detection

– General-purpose I/O capability

• ISO7816 interface :

– Support of ISO7816-3

– Support both card and card reader mode

– Support T=0 and T=1 protocal

– Half-duplex operation

– 1 transmit buffer + 1 receive buffer

– F/D selection(31,23.25, 46.5, 93, 186, 372,744,8,12,16,32,64,128,256,512)

– 9-bit guard time counter (GTCNT)

– 24 bits waiting time counter (WTCNT)

– Programmable transmitter output polarity

– Interrupt-driven operation with seven flags:

– Transmitter empty

– Transmission complete

– Receive full

– ERROR

– Start bit detected

– Timeout on WT counter

– Answer to Reset

– Auto-character repetition on error signal detection in transmit mode

– Auto-error signal generation on parity error detection in receive mode

– Hardware parity checking

– 1/16 bit-time noise detectio

– General purpose, IO capability

• Memory Integration Module:

– Two Chip Select channel, two for external SRAM,NORFLASH and memory mapped peripherals(Only for evaluation)

– Support for swap and bootload modes



Introduction

– Bidirectional data bus with wide 16-bit and narrow 8-bit modes

– 20-bits address bus

– Bus monitor

• Serial peripheral interfaces (SPI) :

– Master mode and slave mode configurable

– Slave select output

– Mode fault error flag with CPU interrupt capability

– Double-buffered receiver

– Serial clock with programmable polarity and phase

– Control of SPI operation during wait mode

• USB

– Supports internal reference clock or external 12MHz crystal reference clock

– Compliant with USB 1.1 specification with on-chip integrated PHY

module

– Supports FS (12Mbps) modes

– Supports eight transmit/receive endpoints(ep0,ep1,ep2,ep3,ep4,ep5,ep6,ep7)

• PWM

– Programmable period

– Programmable duty cycle

– Two Dead-Zone generator

– Capture function

– Pins can be configured as general-purpose I/O

• Magnet Card Reader

– Magnet card interface

• ADC

– 12-bit, 10-bit, 8-bit or 6-bit configurable resolution

– ADC conversion time: 1.0 ms for 12-bit resolution (1 MHz), 0.88 ms conversion time for 10 bit resolution, faster conversion times can be obtained by lowering resolution.

– Programmable sampling time

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– DMA support

• RF

– RF interface

• Secure features

– Internal power on reset

– Voltage detector

– Ligth detector

– Power Glitch detector

– Metal Shield protection

– Temperature detector

– Data encryption

– Clock and reset pulse filtration

– Safe optimized routing

• SM1

– 128~256bit security key length selectable

– 128 bit system key

• Crypto Accelerator module

– Large operand size N integer arithmetic

32 * R bits

R is positive integer from 1 to 64

– Programmable scalar or modulo operation

Y = (A * B) mod M

Y = (A E ) mod M

– Discrete "sea-of-gates" implementation to protection against SPA and probing attacks

• AES module

– Support AES encryption/decryption algorithm

– Support AES algorithm with 128/192/256 bits key

– Support Electronic Code Book (ECB ) mode operation and CTR(counter)

mode operation

– Data process speed up to 60MBps@80Mhz for AES



Introduction

• SHA coprocessor

– SM3(256)

– SHA-0(160)

– SHA-1(160)

– SHA-224(224)

– SHA-256(256)

– SHA-384(384)

– SHA-512(512)

– Share hardware between different SHA processing

• SM4 module

– Support sm4 encryption/decryption algorithm.

– Support sm4 algorithm with 128 bits key

– Support ECB and CBC mode

– Support CLBBUS Interface

• DES coprocessor

– Support DES and Triple-DES encryption and decryption algorithm

– Support DES algorithm with 64(56) bits key

– Support Triple-DES algorithm with 128(112) bits or 192(168) bits key

– Support ECB mode and CBC mode

– Support MLBBUS Interface

• TRNG( random number generator)

– Rate: 250kbps

• MPU

– The number of programmable regions is configurable

– 0~n-1 programmable eflash code regions(n=4)

– 0~n-1 programmable eflash data regions(n=4)

– 0~j-1 programmable sram owner data regions(j=4)

– 0~p-1 programmable sram owner code regions(p=1)

– Regions not allowed to overlap

– Control register contains attribute of the region

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– Status register indicate the access error of the region

• PMU_RTC

– Load time data to and read time data from seconds, minutes, hours and days counters

– Support alarm settings

– Interrupt sources:second, minute, hour,day interrupts,programmable alarm interrupts ,1KHZ/32KHZ periodic interrupts .



Introduction

1.3 Block Diagram

Figure 1-1 block diagram



2.1 Introduction

The address map, shown in 2.2, includes:

• 32K Bytes of internal read only memory

• 64K Bytes of internal static random-access memory (SRAM)

• 512K Bytes Embedded Flash

• Internal memory mapped registers

2.2 Address Map

Figure 2-1 Normal Single Chip Mode Address Map

REGISTERS 0x4000_0000

0x7FFF_FFFF

0xFFFF_FFFF

INTERNAL SRAM

0x8080_0000

0x808F_FFFF EXTERNAL MEMORY

EXTERNAL MEMORY

0x8000_0000

0x0080_FFFF

0x0080_0000

0x800F_FFFF

INTERNAL FLASH 0x0047_FFFF

0x0040_0000

0x0000_7FFF

0x0000_0000

INTERNAL ROM



System Memory Map

Figure 2-2 Normal Master Mode

REGISTERS

0x0000_0000

0x4000_0000

0x7FFF_FFFF

0xFFFF_FFFF

INTERNAL ROM

INTERNAL SRAM

0x8080_0000

0x808F_FFFF EXTERNAL MEMORY

EXTERNAL MEMORY 0x8000_0000

0x0080_FFFF

0x0080_0000

0x0007_FFFF

0x800F_FFFF

INTERNAL FLASH 0x0047_FFFF

0x0040_0000



Table 2-1 Register Address Location Map 1

Address Maximum Size Usage

0x63f0_0000 16Kbyte MIM

0x63f0_4000 16Kbyte Chip configuration (CCM)

0x63f0_8000 16Kbyte Reset (RESET)

0x63f1_c000 16Kbyte SM1 (SCB2)

0x63f2_0000 16Kbyte CRYPTO

0x63f2_4000 16Kbyte EDMAC

0x63f3_8000 16Kbyte LD

0x63f4_0000 16Kbyte True Random Number Generator (TRNG)

0x635_c000 16Kbyte PGD

0x63f6_0000 16Kbyte SEC_DET

0x63f6_4000 16Kbyte SHA

0x63f8_0000 16Kbyte EFM

0x63f8_8000 16Kbyte CPM

0x00c9_0000 64Kbyte Data Encryption Standard Module (DES)

0x00cf_0000 64Kbyte AES

0x00de_0000 64Kbyte SMS4

0x0100_0000 64Kbyte USBC

0x0300_0000 64Kbyte DMAC

0x7000_0000 16Kbyte SPI1

0x7001_0000 16Kbyte SPI2

0x7002_0000 16Kbyte SPI3

0x7003_0000 16Kbyte SCI1

0x7004_0000 16Kbyte SCI2

0x7005_0000 16Kbyte Programmable interrupt timer 1 (PIT1)

0x7006_0000 16Kbyte Programmable interrupt timer 2 (PIT2)

0x7007_0000 16Kbyte TC

0x7008_0000 16Kbyte Edge Port (EPORT)

0x7009_0000 16Kbyte Watchdog timer (WDT)

0x700a_0000 16Kbyte ADC

0x700b_0000 16Kbyte I2C

0x700c_0000 16Kbyte USI1

0x700d_0000 16Kbyte USI2

0x700e_0000 16Kbyte USI3

0x700f_0000 16Kbyte ENCR1

0x7010_0000 16Kbyte MCC

0x7011_0000 16Kbyte PMU_RTC

0x7012_0000 16Kbyte PWM



System Memory Map

0x7013_0000 16Kbyte PWM1

0x7014_0000 16Kbyte PWM2

0x7800_0000 16Kbyte CRC0

0x7c00_0000 16Kbyte CRC1

0xfff0_0000 64Kbyte Cache_Config

0xffff_0000 16Kbyte MPU

0xe000_0000 16Kbyte EIC

NOTES:

1. See module sections for details of how much of each block is being decoded. Accesses to addresses outside the module memory maps(and also the reserved area) will not be responded to and will result in error exception.

Table 2-1 Register Address Location Map 1



3.1 Introduction

The TSC9560 is available in below package:

• QFN68

• QFN76.



Signal Description

3.2 Package Pinout Summary

3.2.1 QFN68 Package

Figure 3-1 TSC9560 QFN68



3.2.2 QFN76 Package

Figure 3-2 TSC9560 QFN76

Refer to:

• Table 3-1 for a brief description of each signal.



Signal Description

3.2.3 Signal Properties Summary

Table 3-1 Signal Description

Name 1 Alternate Dir. Pull 2,3 Voltage Package Function

Serial Periheral Interface(SPI1/2)(8)

mosi1 GPIO I/O Pullup 3.3v QFN68 QFN76

Serial data output from the SPI in master mode and the serial data input in slave mode.

miso1 GPIO I/O Pullup 3.3v QFN68 QFN76

Serial data input to the SPI in master mode and the serial data output in slave mode.

sck1 GPIO I/O Pullup 3.3v QFN68 QFN76

The serial clock synchronizes data transmissions between master and slave devices. SCK is an output if the SPI is configured as a master. sck1 is an input if the SPI is configured as a slave.

ss1 GPIO I/O Pullup 3.3v QFN68 QFN76

Peripheral chip select signal in master mode and is an active-low slave select in slave mode.

mosi2 GPIO I/O Pullup 3.3v QFN68 QFN76

Serial data output from the SPI in master mode and the serial data input in slave mode.

miso2 GPIO I/O Pullup 3.3v QFN68 QFN76

Serial data input to the SPI in master mode and the serial data output in slave mode.

sck2 GPIO I/O Pullup 3.3v QFN68 QFN76

The serial clock synchronizes data transmissions between master and slave devices. SCK is an output if the SPI is configured as a master. sck1 is an input if the SPI is configured as a slave.

ss2 GPIO I/O Pullup 3.3v QFN68 QFN76

Peripheral chip select signal in master mode and is an active-low slave select in slave mode.

I2C Interface(2)

scl GPIO I/O Pullup 3.3v QFN68 QFN76 I2C controller bidirection clock pin..

sda GPIO I/O Pullup 3.3v QFN68 QFN76 I2C controller bidirection data pin.

Edge Port (EPORT) (8)

gint[0]/adc_in[0] GPIO I/O Pullup 3.3v QFN68 QFN76

External interrupt source or GPIO.

ADC analog channels.
























USB2.0(2)

dp - I/O - 5v QFN68 QFN76 USB D+ signal pin.

dm - I/O - 5v QFN68 QFN76 USB D- signal pin.

RF(3)

TX1 - O - - QFN68 QFN76

Transmitter 1, delivers the modulated 13.56MHz energy carrier.

TX2 - O - - QFN68 QFN76 Transmitter 2, delivers the modulated

13.56MHz energy carrier.

RX - I Pullup - QFN68 QFN76 Receiver input.

MCC(6)

VIN1 - I - 3.3v QFN68 QFN76

Magnet card reader channel 1 pad. Vin 1 is positive port.

VCM1 - O - 3.3v QFN68 QFN76

Magnet card reader channel 1 pad. Vcm1 is negtive port.









SCI(4)




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Signal Description

txd - I/O Pullup 3.3v QFN68 QFN76

SCI transmitter data output or GPIO

rxd - I/O Pullup 3.3v QFN68 QFN76

SCI receiver data input or GPIO

txd2 - I/O Pullup 3.3v QFN68 QFN76

SCI transmitter data output or GPIO

rxd2 - I/O Pullup 3.3v QFN68 QFN76

SCI receiver data input or GPIO

Other type pins(3)

usbdet - I - 5v QFN68 QFN76

usb wake up detect pin.

is 1 will wake up system when system enter powerdown mode.

WAKEUP - I - 5v QFN68 QFN76

External wake up signal.

is1 will wake up system when system enter powerdown mode.

RF_LDO_EN - I - 5v QFN68 QFN76

RF LDO enable pad.

is 0(default), disable RF LDO;

is 1, enable RF LDO.

ISO-7816 Interface (USI2/3) (6)

isoclk2 GPIO I/O - 1.8/3/3.3 /5v

QFN68 QFN76

This signal is used for Smart Card clock signal.

isodat2 GPIO I/O - 1.8/3/3.3 /5v

QFN68 QFN76

This signal is used for Smart Card Interface data input/output.

isorst2 GPIO I/O - 1.8/3/3.3 /5v

QFN68 QFN76

This signal is used for Smart Card reset signal.

isoclk3 GPIO I/O - 1.8/3/3.3 /5v QFN68 This signal is used for Smart Card clock

signal.

isodat3 GPIO I/O - 1.8/3/3.3 /5v QFN68 This signal is used for Smart Card Interface

data input/output.

isorst3 GPIO I/O - 1.8/3/3.3 /5v QFN68 This signal is used for Smart Card reset

signal.

PWM(4)

a[8]/PWM0_2 - I/O - 3.3v QFN76 pwm0[2] data input/output signal.




SDI(8)





SDI0 - I/O - 5v QFN68 QFN76 Self-destruction detect input .




SDI4 - I/O - 5v QFN76 Self-destruction detect input .




Power Supply(17)

VDD33 - - - - QFN68 QFN76

This signal supplies 3.3V positive power output.

AVDD_MC_ADC /VREFH - - - - QFN68

QFN76 ADC power supply,3.3v

VDD33_FLASH - - - - QFN68 QFN76

This signal is the power supply for external flash.

VCCA - - - - QFN68 QFN76

This signal is the 3.3v power supply for USB analog model.

PAD_AVDD_BBAT - - - - QFN68 QFN76 RTC battery power supply.

VBAT_DET - - - - QFN68 QFN76 5V battery power detect pad.

VCC5V - - - - QFN68 QFN76 5v power supply

VDD - - - - QFN68 QFN76 1.2v Power output

VDDIO_CARDIO - - - - QFN76 Power supply for ISO7816 card.

VDDIO_CARD0 - - - - QFN68 Power supply for ISO7816 card.

VDDIO_CARD1 - - - - QFN68 Power supply for ISO7816 card.

TVSS - - - - QFN68 QFN76

This signal is the negative supply (ground) to the RF transmitter.

TVDD - - - - QFN68 QFN76

This signal is the power supply to the RF transmitter.

VMID - - - - QFN68 QFN76 RF internal reference voltage.





Signal Description

AVDD - - - - QFN68 QFN76

This signal is the power supply to the RF analog.

NFC_AVSS - - - - QFN68 QFN76

This signal is the negative supply (ground) for the RF analog.

AGND/VSS - - - - QFN76 This signal is the negative supply (ground).

Clock(7)

PAD_XTALI - I - 3.3v QFN68 QFN76

32.768KHz Oscillator input.

PAD_XTALO - O - 3.3v QFN68 QFN76 32.768KHz Oscillator output.

OSCI - I - - QFN68 QFN76 27.12MHz Oscillator input.

OSCO - O - - QFN68 QFN76

27.12MHz Oscillator output.

extal - I - 3.3v QFN76 12MHz Oscillator input.

xtal - O - 3.3v QFN76 12MHz Oscillator output

clkout - O - 5v QFN76 Internal clock output

NOTES:

1. Shaded signals are for optional bond-out for more pin count package.

2. All pullups are disconnected when the signal is programmed as an output.

3. All Not-Single-Chip I/O pins will be put into input mode and be connected to pullups





Advance Information — AppendixA

Appendix A Preliminary Electrical Characteristic

A.1 General

This section provides electrical parametrics and electrical ratings for the TSC9560 microcontroller unit.

A.2 Absolute Maximum Ratings

Maximum ratings are the extreme limits to which the Chip can be exposed without permanently damaging it. See Table A-1.

The Chip contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table.

Connect unused inputs to the appropriate voltage level, V DDH . This device is not guaranteed to operate properly at the maximum ratings. Refer to Table A-3 DC Electrical Specificatios(1.8V) for guaranteed operating conditions.

Table A-1 Absolute Maximum Ratings

Num Rating Symbol Value Unit

1 Operating temperature range T OPT -25 to +85 O C

2 Storage temperature range T STG -40 to +125 O C



Preliminary Electrical Characteristic

A.3 Electrostatic Discharge (ESD) Protection

Table A-2 ESD Protection Characteristics

Parameter 1,2,3,4,5

NOTES:

1. This report will be invalid if reproduced in whole or in part.

2. This report refers only to the specimen(s) submitted to test, and is invalid if used separately.

3. This report is ONLY valid with the examination seal and signature of this institute.

4. The tested specimen(s) will only be preserved for thirty days from the date issued, if not col- lected by the applicant.

5. The failure criteria of all ESD tests should be based on the result of parametric and functional testing conducted by the customer, which follows the statement of international standards. Thus, the judgment of the curve traces provided in this report is for reference ONLY.

Symbol Value Units

ESD target for human body model HBM 2000 V

ESD target for machine model MM 200 V

ESD charge device model CDM 1000 V

ESD latch up Latch Up 200 mA

Preliminary Electrical Characteristic DC Electrical Specifications



A.4 DC Electrical Specifications

Table A-3 DC Electrical Specificatios(1.8V)

Parameter Symbol Min Typical Max Unit

Input Low Voltage V IL -0.3 — 0.63 V

Input High Voltage V IH 1.17 — 3.6 V

Schmitt trig. Low to High Threshold point V T+ 0.94 1.05 1.13 V

Schmitt trig.High to Low Threshold point V T- 0.57 0.64 0.7 V

Schmitt Trigger Low to High Threshold Point with Pull-up Resistor Enabled

V T+PU 0.94 1.05 1.12 V

Schmitt Trigger High to High Threshold Point with Pull-up Resistor Enabled

V T-PU 0.57 0.63 0.7 V

Input Leakage Current I I — — +10 uA

Tri-state output Leakage Current I OZ — — +10 uA

Pull-up Resistor R PU 95 149 237 kW

Pull-down Resistor R PD 76 131 235 kW

Output Low Voltage V OL — — 0.45 V

Output High Voltage V OH 1.35 — — V

Low level output currernt @ V OL =max I OL(0812: 08mA)

4.8 8.6 13.8 mA


6.4 11.4 18.3 mA

High level output currernt @ V OH =min I OH(0812: 08mA)

3.3 7.4 13.7 mA


4.3 9.8 18.1 mA




Table A-4 DC Electrical Specificatios(3/3.3V)


Input Low Voltage V IL -0.3 — 0.8 V

Input High Voltage V IH 2 — 3.6 V




V T+PU 1.54 1.64 1.73 V


V T-PU 1.08 1.17 1.25 V




Pull-down Resistor R PD 34 54 92 kW


Output High Voltage V OH 2.4 — — V


9.9 15.8 4.8 mA


13.1 20.9 28.9 mA


13.7 26.5 43.8 mA


18 34.9 57.7 mA

Preliminary Electrical Characteristic DC Electrical Specifications



Table A-5 DC Electrical Specificatios(5V)


Input Low Voltage V IL -0.3 — 1 V

Input High Voltage V IH 4 — 5.5 V




V T+PU 2.44 2.69 2.94 V


V T-PU 1.94 2.17 2.41 V




Pull-down Resistor R PD - - - kW


Output High Voltage V OH 4 — — V

Low level output currernt @ V OL =max I OL(08 12: 08mA)

6.5 10.8 13.8 mA

Low level output currernt @ V OL =max I OL(08 12: 12mA)

13.1 20.6 18.3 mA

High level output currernt @ V OH =min I OH(08 12: 08mA)

6.8 19.1 13.7 mA


12.1 34.0 18.1 mA

Section 4 RF Interface

4.1

This document describes the functionality and electrical specifications of the contactless reader/writer TSC9560 Remark: The TSC9560 supports all variants of the MIFARE Mini, MIFARE 1K

and MIFARE 4K RF identification protocols. To aid readability throughout this data sheet, the MIFARE Mini, MIFARE 1K and MIFARE 4K products and protocols have the generic name MIFARE.

4.2 General The TSC9560 is a highly integrated reader/writer for contactless communication at 13.56 MHz. The TSC9560 reader supports ISO/IEC 14443 A/MIFARE mode. The TSC9560’s internal transmitter is able to drive a reader/writer antenna designed to communicate with ISO/IEC 14443 A/MIFARE cards and transponders without additional active circuitry. The receiver module provides a robust and efficient implementation for demodulating and decoding signals from ISO/IEC 14443 A/MIFARE compatible cards and transponders. The digital module manages the complete ISO/IEC 14443 A framing and error detection (parity and CRC) functionality. All protocol layers of the ISO/IEC 14443 A and ISO/IEC 14443 B communication standards are supported provided: • additional components, such as the oscillator, power supply, coil etc are correctly applied • standardized protocols, such as ISO/IEC 14443-4 and/or ISO/IEC 14443 B anticollision are correctly implemented Using this Semiconductors’ device according to ISO/IEC 14443 B may infringe third party patent rights. The CUni350S supports contactless communication using MIFARE higher baud rates at transfer speeds up to 848 kBd in both directions.

4.3 Features and benefits

• Highly integrated analog circuitry to demodulate and decode responses • Buffered output drivers for connecting an antenna with the minimum number of external components • Supports ISO/IEC 14443 A/MIFARE • Supports ISO/IEC 14443 B Read/Write modes • Typical operating distance in Read/Write mode up to 50 mm depending on the antenna size and tuning • Supports MIFARE Mini, MIFARE 1K and MIFARE 4K encryption in Read/Write mode




• Supports ISO/IEC 14443 A higher transfer speed communication at 212 kBd, 424 kBd and 848 kBd • Supports MFIN/MFOUT • Additional internal power supply to the smart card IC connected via MFIN/MFOUT • Supported host interfaces • FIFO buffer handles 64 byte send and receive • Flexible interrupt modes • Hard reset with low power function • Power-down by software mode • Programmable timer • Internal oscillator for connection to 27.12 MHz quartz crystal • 2.5 V to 3.3 V power supply • CRC coprocessor

4.4 Memory Map and Registers

This subsection describes the memory map and registers for the RF interface . The RF interface has a base address of 0. 4.4.1 Register bit behavior Depending on the functionality of a register, the access conditions to the register can vary. In principle, bits with same behavior are grouped in common registers. The access conditions are described in table 4-1

Table 4-1 Behavior of register bits and their designation

4.4.1.1 register overview Table 4-2 register

4.4.2 Register

4.4.2.1 Page0 : Command and status Reserved register 00h Functionality is reserved for future use. Table 4-3 Reserved register(address 00h);reset value:00h bit allocation

Table 4-4 Reserved register bit descriptions

CommandReg register Starts and stops command execution

Table 4-5 CommandReg register(address 01h);reset value:20h bit allocation

Table 4-6 CommandReg register bit descriptions

Table 4-7 ComlEnReg register(address 02h);reset value :80h bit allocation

Table 4-8 ComlEnReg register bit description

Table 4-8 ComlEnReg register bit description

Table 4-9 DivEnReg register(address 03h);reset value:00h bit

Table 4-10 DivEnReg register bit

Table 4-11 ComIrqReg register(address 04h);reset value:14h bit

Table 4-12 ComIrqReg register bit descriptions(All bits in the ComIrqReg register cleard by software)

Table 4-13 DivlrqReg register(address 05h);reset value:x0h bit

Table 4-14 DivlrqReg register bit descriptions(All bits in the DivlrqReg register are

by software)

Table 4-15 ErrorReg register(address 06h);reset value:00h bit

Table 4-16 ErrorReg register bit

Table 4-16 ErrorReg register bit

Table 4-17 Status1Reg register(address 07h);reset value:21h bit

Table 4-18 Status1Reg register bit


Table 4-19 Status2Reg register(address 08h);reset value:00h bit



Table 4-21 FIFODataReg register(address 09h);reset value:xxh bit

Table 4-22 FIFODataReg register bit

Table4-23 FIFOLevelReg register(address 0Ah);reset value:00h bit

Table 4-24 FIFOLevelReg register bit

Table 4-25 WaterLevelReg register(address 0Bh);reset value:08h bit

Table 4-26 WaterLevelReg register bit

Table 4-27 ControlReg register(address 0Ch);reset value:10h bit

Table 4-28 ControlReg register bit

Table 4-29 BitFramingReg register(address 0Dh);reset value:00h bit

Table 4-30 BitFramingReg register bit

Table 4-31 CollReg register(address 0Eh);reset value:xxh bit

Table 4-32 CollReg register bit

Table 4-33 Reserved register(address 0Fh);reset value:00h bit

Table 4-34 Reserved register bit

4.4.2.2 Page 1:Communication

Reserved register 10h Functionality is reserved for future use. Table 4-35 Reserved register(address 10h);reset value:00h bit


Table 4-37 ModeReg register(address 11h);reset value:3Fh bit

Table 4-38 ModeReg register bit

Table 4-38 ModeReg register bit

Table 4-39 TxMaodeReg register(address 12h);reset value:00h bit

Table 4-40 TxModeReg register bit

Table 4-40 TxModeReg register bit

Table 4-41 RxModeReg register(address 13h);reset value:00h bit

Table 4-42 RxModeReg register bit

Table 4-42 RxModeReg register bit

Table 4-43 TxControlReg register(address 14h);reset value:80h bit

Table 4-44 TxControlReg register bit

Table 4-44 TxControlReg register bit

Table 4-45 TxASKReg register(address 15h);reset value:00h bit

Table 4-46 TxASKReg register bit

Table 4-47 TxSelReg register(address 16h);reset value:10h bit

Table 4-48 TxSelReg register bit

Table 4-48 TxSelReg register bit

Table 4-49 RxSelReg register(address 17h);reset value:84h bit

Table 4-50 RxSelReg register bit

Table 4-51 RxThresholdReg register(address 18h);reset value:84h bit

Table 4-52 RxThresholdReg register bit

Table 4-53 DemodReg register(address 19h);reset value:4Dh bit

Table 4-54 DemodReg register bit

Table 4-55 Reserved register(address 1Ah);reset value:00h bit


Table 4-57 Reserved register(address 1Bh);reset value:00h bit


Table 4-59 MfTxReg register(address 1Ch);reset value:62h bit allocation

Table 4-60 MfTxReg register bit descriptions

MfRxReg register Table 4-61 MfRxReg register(address 1Dh);reset value:00h bit allocation

Table 4-62 MfRxReg register bit descriptions

Table 4-63 TypeBReg register(address 1Eh);reset value:00h bit allocation

Table 4-64 TypeBReg register bit descriptions

Table 4-64 TypeBReg register bit descriptions

Table 4-65 SerialSpeedReg register(address 1Fh);reset EBh bit allocation

Table 4-66 SerialSpeedReg register bit descriptions

4.4.2.3 Page2:Configuration

Reserved register 20h Functionality is reserved for future use. Table 4-67 Reserved register(address 20h);reset value:00h bit allocation


Table 4-69 CRCResultReg(higher bits)register(address 21h);reset value:FFh bit allocation

Table 4-70 CRCResultReg register higher bit descriptions

Table 4-71 CRCResultReg(lower bits)register(address 22h);reset value:FFh bit allocation

Table 4-72 CRCResultReg register lower bit descriptions

Table 4-73 Reserved register(address 23h);reset value:88h bit allocation


Table 4-75 ModWidthReg(higher bits)register(address 24h);reset value:26h bit allocation

Table 4-76 ModWidthReg register higher bit descriptions

Table 4-77 Reserved register(address 25h);reset value:87h bit allocation


Table 4-79 RFCfgReg register(address 26h);reset value:48h bit allocation

Table 4-80 RDCfgReg register bit descriptions

when the driver is switched on.

Table 4-81 GxNReg register(address 27h);reset value:88h bit allocation

Table 4-82 GsNReg register bit descriptions

Table 4-83 CWGsPReg register(address 28h);reset value:20h bit allocation

Table 4-84 CWGsPReg register bit descriptions

Table 4-85 ModGsPReg register(address 29h);reset value:20h bit allocation

Table 4-86 ModGsPReg register bit descriptions

Table 4-87 TModeReg register(address 2Ah);reset value:00h bit allocation

Table 4-88 TModeReg register bit descriptions

Table 4-88 TModeReg register bit descriptions

Table 4-89 TPrescalerReg register(address 2Bh);reset value:00h bit allocation

Table 4-90 TPrescalerReg register bit descriptions

Table 4-91 TreloadReg(higher bits)register(address 2Ch);reset value:00h bit allocation

Table 4-92 TreloadReg register higher bit descriptions

Table 4-93 TreloadReg(lower bits)register(address 2Dh);reset value:00h bit allocation

Table 4-94 TreloadReg register higher bit descriptions

Table 4-95 TCounterValReg(higher bits)register(address 2Eh);reset value:xxh bit

Table 4-96 TCounterValReg register higher bit descriptions

Table 4-97 TCounterValReg(lower bits)register(address 2Fh);reset value:xxh bit allocation

Table 4-98 TCounterValReg register higher bit descriptions

4.5 RF command set

4 .5.1 General description

4. 5.2 General behavior

4. 5.3 Command overview

Table 4-99 Command overview

4. 5.3.1 Command descriptions

4. 6 Functional description

The TSC9560 transmission module supports ISO/IEC 14443 A and ISO/IEC 14443 B Read/Write mode at various transfer speeds and modulation protocols.

4. 6.1 ISO/IEC 14443 A functionality

The physical level communication has two part. (1) Reader to card (TSC9560 sends data to a card).

(2) Card to reader (card sends data to the TSC9560)

. Table 4-100 Communication overview for ISO/IEC 14443 A reader/writer

Table 4-100 Communication overview for ISO/IEC 14443 A reader/writer

4. 6.2 ISO/IEC 14443 B functionality

The TSC9560 reader IC fully supports the ISO 14443 international standard which includes the communication schemes ISO 14443 A and ISO 14443 B. Refer to the ISO 14443 reference documents Identification cards - Contactless integrated circuit cards - Proximity cards (parts 1 to 4). Remark: The TSC9560 does not offer a software library to enable design-in of the ISO 14443 B protocol. 4. 6.3 Analog interface and contactless UART 4. 6.3.1 General

4.6.3.2 TX p-driver

Table 4-101 Register and bit settings controlling the signal on pin TX1


4. 6.3.3 Serial data switch Two main blocks are implemented in the TSC9560. The digital block comprises the state machines, encoder/decoder logic. The analog block comprises the modulator and antenna drivers, the receiver and amplifiers. It is possible for the interface between these two blocks to be configured so that the interfacing signals are routed to pins MFIN and MFOUT. This topology allows the analog block of the TSC9560 to be connected to the digital block of another device. The serial signal switch is controlled by the TxSelReg and RxSelReg registers. Figure 1 shows the serial data switch for TX1 and TX2.

Figure 4-1 Serial data switch for TX1 and TX2 4. 6.3.4 MFIN and MFOUT interface support The TSC9560 is divided into a digital circuit block and an analog circuit block.

concept.An external active antenna circuit can be connected to the TSC9560’s digital block.Switch MFOutSel must be configured so that the internal Miller encoded signal is sent to pin MFOUT (MFOutSel = 100b). UARTSel[1:0] must be configured to receive a Manchester signal with subcarrier from pin MFIN

4 .6.3.5 CRC coprocessor

Table 4-103 CRC coprocessor parameters

4. 6.4 FIFO buffer An 8 *64 bit FIFO buffer is used in the TSC9560. It buffers the input and output

data stream between the host and the TSC9560’s internal state machine. This makes it possible to manage data streams up to 64 bytes long without the need to take timing constraints into account. 4. 6.4.1 Accessing the FIFO buffer

buffer read pointer. The distance between the write and read pointer can be obtained by reading the FIFOLevelReg register. When the microcontroller starts a command, the TSC9560 can, while the command is in progress, access the FIFO buffer according to that command. Only one FIFO buffer has been implemented which can be used for input and output. The microcontroller must ensure that there are not any unintentional FIFO buffer accesses. 4. 6.4.2 Controlling the FIFO buffer

4. 6.4.3 FIFO buffer status information

The TSC9560 can generate an interrupt signal when:

4. 6.5 Interrupt request system The TSC9560 indicates certain events by setting the Status1Reg register’s IRq bit and, if activated, by pin IRQ. The signal on pin IRQ can be used to interrupt the host using its interrupt handling capabilities. This allows the implementation of efficient host software. 4. 6.5.1 Interrupt sources overview

Table 4-104 interrupt sources

Table 4-104 interrupt sources

4. 6.6 Timer unit The TSC9560 has a timer unit which the external host can use to manage timing

4. 6.7 Power reduction modes 4. 6.7.1 Hard power-down

4. 6.7.2 Soft power-down mode

configuration keep their current contents. After setting the PowerDown bit to logic 0, it takes 1024 clocks until the Soft power-down mode is exited indicated by the PowerDown bit. Setting it to logic 0 does not immediately clear it. It is automatically cleared by the TSC9560 when Soft power-down mode is exited. Remark: When the internal oscillator is used, time (tosc) is required for the oscillator to become stable. This is because the internal oscillator is supplied by stable. It is recommended for the serial UART, to first send the value 55h to the TSC9560. The oscillator must be stable for further access to the registers. To ensure this, perform a read access to address 0 until the TSC9560 answers to the last read command with the register content of address 0.This indicates that the TSC9560 is ready. 4. 6.7.3 Transmitter Power-down

4. 6.8 Oscillator circuit

Figure 4-2 Quartz crystal connection

The clock applied to the TSC9560 provides a time basis for the synchronous system’s encoder and decoder. The stability of the clock frequency is an important factor for correct operation. To obtain optimum performance, clock jitter must be reduced as much as possible. This is best achieved using the internal oscillator buffer with the recommended circuitry.

If an external clock source is used, the clock signal must be applied to pin OSCIN. In this case, be very careful in optimizing clock duty cycle and clock jitter. Ensure the clock quality has been verified. 4. 6.9 Reset and oscillator start-up time 4. 6.9.1 Reset timing

4. 6.9.2 Oscillator start-up If the TSC9560 has been set to a Power-down mode or is powered by a VDDX supply, the start-up time for the TSC9560 depends on the oscillator used and is shown in the figure The time (tstartup) is the start-up time of the crystal oscillator circuit. The crystal oscillator start-up time is defined by the crystal. The time (td) is the internal delay time of the TSC9560 when the clock signal is stable before the TSC9560 can be addressed The delay time is calculated by:

Figure 4-3 Oscillator start-up time

tsc9560 datasheet rev1 - hxwhic.com datasheet rev1.3 cmos ... – supports fs ......

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