tsv 기술을이용한memory stack 제품의테스트issue¡°정호.pdf · 2009-11-10 · system...
TRANSCRIPT
Trends
-DRAM Market Trend-DRAM Product Trend-DRAM Test Mission-DRAM Test Trend
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DRAM Market Trend
Memory bandwidth High facility cost
Price Up Factors Price Down Factors(dominant)
Memory bandwidth1TB/s for High End Server, Graphics
Memory density
High facility costHigh barrier to exit
Standardized featuresMemory density32GB RDIMM @ 201064GB RDIMM @ 2012
Standardized featuresLow added-value, Low barrier to entry
Chip speed, complexityDDR3 1.6Gbps,DDR4 3.2Gbps,GDDRx 10Gbps
Growing demand of cost down
Price < $1512M 3years, 1Gb 1years TTR, parallelism, cheaper tester, longer PM
Efforts for test cost reduction
No time to recover investment
High facility cost
TTR, parallelism, cheaper tester, longer PM period, reduction of test process, seamless test, reduced set-up time, adding value through test, optimum batch size,
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g yHigh barrier to entry
g , p ,selective test by grade, etc..
DRAM Product Trend
Number of transistors in a chip65nm 45nm 32nm 22nm 16nm
Number of chips in a packageMCP POP Embedded TSV65nm - 45nm – 32nm – 22nm – 16nm
High Speed IO
MCP, POP, Embedded, TSV
Medium Speed Wide IO예GDDRx 10Gbps/pin & 32 IO
Simple Function
예) 1Gbps/pin & 2048 IO
Complex FunctionSingular package
Standardized Specification
Integrated package
Custom Specific SpecificationpJEDEC
Performance 1st power 2nd
p pCustom specific
Power 1st Performance 2ndPerformance 1 , power 2
Tight budget for Test Cost
Power 1st, Performance 2nd
Tighter budget for Test Cost
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Mission of Test
Defects screening
Speed classificationSpeed classification
Yield learning
R li bili h h B IReliability through Burn-In
Enabling product
(Testable)
(Cost effective)
(Timely delivery)
Reliability through Test
Custom specific business via Test
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Custo spec c bus ess a est
Test Trend
Increasing test procedure complexityIncreasing test procedure complexity (Device customization during test)
Increasing ATE resources and test timeIncreasing ATE resources and test time(Increased interface bandwidth)
Increasing the demands for KGDIncreasing the demands for KGD
Increasing drawbacks of burn-in as technology scalinggy g
Secure reliability through probe test rather than burn-in
Increasing test interface cost
Collaboration between ATE and DFT
F/E test is everything(R li bilit Yi ld S d Yi ld L i )
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(Reliability, Yield, Speed, Yield Learning ...)
TSV 3D Stack DRAM
-TSV 3D Stack Package-Motivation of Stacked DRAMT t Fl f TSV 3D St k DRAM-Test Flow for TSV 3D Stack DRAM
-Wafer Burn-In-Probe Test
( )-TSV Forming and Stack (Via last)-Post Stack Test-Summary
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TSV 3D Stack Package
TSV 3D Stack Package
Two or more chips are stacked vertically through electrical connections with metal filled Via holeselectrical connections with metal filled Via holes.
High density, small size package
L d hi h d IOLow power and high speed IO
<TSV> Through Si Via<MCP> Multi Chip Package
2D configuration2D configuration
Source : 3D IC Report, Yole Development, 2007
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Motivation of stacked DRAM
Main MemorySystem Bandwidth / Memory capacity Core
System power budgetHomogeneous stack
Interface
Mobile applicationSystem power budgetSystem power budgetHeterogeneous vertical stack
Graphic application
Memory
Memory
MemoryGraphic applicationSystem power budgetSystem Bandwidth
y
Memory
Processor
S bForm factors of discrete graphic systemHeterogeneous vertical stack
Substrate
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Motivation of stacked DRAM
5
6System Max Memory Capa. vs. Base Density[GB] [Gb]
2
3
4
5
512
640
768
896
1024
56789
0
1
2
2009 2010 2011 2012 20130
128
256
384
512
2007 2008 2009 2010 2011 2012 2013 2014 201501234
S/E I/O TSV I/O
/O B/W T t t ti
2007 2008 2009 2010 2011 2012 2013 2014 2015
max. dimm capa(GB) Base Density(Gb)
I/O Power comparison(graphic system)
B/W : Target vs. expectationSystem Max. Memory Capacity
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Motivation of stacked DRAM
Reducing the parasitic components and signal trace on the off-chip• Signal transfer power consumption can be reduced dramatically • Due to the short signal trace, Memory access latency can be reduced
MemoryMemorySi interposer
g y y
Processor MemoryMemory
Processor MemoryProcessorMemoryMemoryMemory
PKG Sub
M/B
I/O Speed 6 ~ 8Gb/s 10Gb/s ~ 6Gb/s
# of interconnections ~512 128 ~ 4K 8 channel
B/W ~300GB/s ~ 1TB/s ~ 150GB/sCapacity 2GB 2GB ~ 16GB ~ 4GB
Interconnection Length >25mm >5mm >100mm
• Due to the limitation of • Memory capacity will be
Remarkpackage height, memory stack will be limited by 2 or less stack.
• No. of IO’s limited.
be limited by the area of processor.
• It can put more I/Os th th
• Current graphic application type.
• No. of IO’s limited.
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No. of IO s limited. than others.
Test Flow for TSV 3D Stack DRAM
. Bias control
. Dynamic Stress & Full ContactWafer B/I
Traditional Test Flow
Wafer B/I
Stack DRAM Test Flow (VIA last)
. Dynamic Stress & Full Contact
. Probing pad? TSV LP direct contact?
BIST? BIST + ATE?
Redundancy analysis
Core test (hot)
Core test (cold)
Core test (hot)
Core test (cold). Redundancy analysis
. Laser or e-fuse
. KGD core test
Repair
Post repair core test
Repair
Post repair test . KGD core test
Post repair speed test
Post repair core testPost repair test
. KGD speed test
PKG
TDBI
PKG . TSV (Via last) & Stack
. (Need to avoid stress test)
. Core test & redundancy analysis
PKT (core)
PKT (speed)
Post stack TSV test
Post stack core test
. TSV test and repair (continuity test)
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& repairPost stack speed test
Wafer Burn-In
Traditional DRAM
- KGD
TSV Stacked DRAM
V hi h q lit KGD
Target
- KGD
- Yield up
- Package Burn-In time reduction
- Stress time : several minutes
- Very high quality KGD
- Yield up
- Package Burn-In eliminationStress time : several minutes
- Reliability monitor and feedback
- Stress time : several hours
Desired termsMinimization of transistor degradation
Dynamic operation stress
Productivity (FWC Step & repeat SML)
Desired terms
Productivity (FWC, Step & repeat, SML)
Full wafer contact & Multiple Wafer Burn-In (6 or more wafers)
Efficacy of Stress
External power supply for each DRAM internal voltage
Reliability monitor
Test during wafer burn-in
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Wafer Burn-In
Dynamic operation stress
P tt t (N b f tt l th t )
To be considered
Pattern generator (Number of pattern, length, etc.),
Magnitude of Power, Heat dissipation, Bad die isolation & binning
Full wafer contact interfaceFull wafer contact interface
Cost (Reusable, # of T/D, repairable, available on multiple products)
Type of interface (u-spring, pogo, bump, polymer, MEMS wafer, etc.),
Alignment (Thermal e pansion) PlanaritAlignment (Thermal expansion), Planarity
Contact resistance & Tip force, Size of probe mark
Multiple Wafer Burn-In at the same time
Higher productivity than Package Burn-In : 6 or more wafers in a chamber
External power supply for DRAM internal voltage
Magnitude of power, Bad die isolation, Number of power supply (
Test during Wafer Burn-In
Type of failure information Correlation with ATE
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Type of failure information, Correlation with ATE
Probe Test
DRAM Core
Test through probing pad
Same as traditional DRAM test (pro)
Increased area overhead reduces number ofInterface CircuitriesProbing Pad
Increased area overhead reduces number of
net die and yield (con)
Unavailable to test CMD & DATA paths (con)
DRAM Core
TSV LP
Test through direct contact TSV LP
Available to test CMD and DATA paths (pro)
Minimized area overhead increases number of
net die and yield (pro)
Uneasy to contact fine pitch TSV LP (con)
Application Main Memory Mobile Graphic
Number of Via and test frequency
Number of Vias < 1K > 1K > 7K
Number of IO Vias 0.25K 0.5K 2K ~ 4K
Test Frequency (Core) 100Mhz 100Mhz 100Mhz
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Test Frequency (Speed) 400Mhz ~ 800Mhz 200 ~ 400Mhz 800Mhz ~ 1Ghz
Probe Test
Direct contact TSV LP (Probe Card ?)
TSV Landing PadDRAM Core
Interface CircuitriesProbing Pad
Contactless probing ?
10u~20u
40 ~ 50u
CircuitriesProbing Pad
TSV LP
40 ~ 50uDRAM Core
Pad material : AL
Barriers
Number of TSV LP : 100s ~ 1000s
Fine pitch : 40um ~ 50um
Small Parallelism due to limited ATE IO channels
Narro Data E e due to ske and jitter of IOs
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Narrow Data Eye due to skew and jitter of IOs
Small driving current
TSV Forming and Stacking (Via last)
Probe Test
Front Side Bumping
Wafer ThinningCarrier wafer
TSV Forming
TSV TestTest to screen failures during wafer thinning and TSV forming. How to test?
Die Sawing & Stacking
S
Memory
Memory
Memory
Memory
Memory
Memory
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Post Stack TestMemory
Processor
Substrate
Memory
Memory
Post stack test
Case of 4H stack Damage/contamination
-Loading and unloading
-Socket pressure
-Handling
TSV Contact
35 ~ 50 um
15 ~ 40 um5 ~ 20 um
TSV Contact
-Fine pitch
-Low height bump
1000 f TSV35 50 um
Application Main Memory Mobile Graphic
Number of Via and test frequency-1000s of TSV
Number of Vias < 1K > 1K > 7K
Number of IO Vias 0.25K 0.5K 2K ~ 4K
Test Frequency (Core) 200Mhz 200Mhz 200Mhz
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Test Frequency (Speed) 400Mhz ~ 800Mhz 200 ~ 400Mhz 800Mhz ~ 1Ghz
Post stack test
Die Sawing & Stack
Via fillingBonding
No Burn-In
TSV performance test & RepairCore test for TSV &
Repair 1) Continuity test?2) Resistance or delay?
MemoryFull cell test / RA & Repair
TSV performance test & Repair
Core test for Repair
Post repair core test
Memory
Memory
Memory
Full cell test / RA & Repair1) TSV direct contact?2) Interface for test only?
Memory
Memory
Memory
Post stack speed testSpeed performanceNeed or not?
Package Assembly
y
Memory
Processor
Substrate
Assemble Memory and Logic
Memory and Logic testFault isolation between logic and memory
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Package Test 1) Logic + Memory tester?2) DRAM access protocol?
Post stack test
B iBarriers
Making contact each TSV pad (Number of TSV, Fine pitch)
Handling bare dies without making damageHandling bare dies without making damage
Small parallelism due to limited ATE IO channels
Narrow Data Eye due to skew and jitter of IOs
To be considered
Need to avoid thermal stress during production testg p
To reduce the risk of crack, delamination, deformation, fatigue, etc..
Thermal stress : Burn-In / Bake / Thermal Cycle
T t ft TSV f iTest after TSV forming
Cell or performance degradation during thinning and TSV forming
All TSV parallel test and repair to reduce time
Package level redundancy analysis and repair
Simple failure information : Bit / Row / Column
Parallel DUT test / Parallel DUT RA / Parallel DUT repair
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Parallel DUT test / Parallel DUT RA / Parallel DUT repair
Summary
Cost is the 1st barrier for successful TSV memory stack business.
Cost adder : Dynamic Wafer Burn-In, Wafer level speed test,
Post stack TSV test, Post stack test for repair
Type Traditional DRAM
TSV Stacked DRAM
Cost Target
Key words in Wafer Burn-In
i f f ll C l i l f
Test Cost 1 1.3 ~ 1.6 Less than 115% of traditional stacked die test cost
Dynamic Wafer Burn-In, Wafer Full Contact, Multiple Wafer
Burn-In
K d i P b T tKey words in Probe Test
Contact fine pitch TSV
Key words in Post TestKey words in Post Test
Contact fine pitch TSV, Package level RA and Repair
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