Digital

Fundamentals Tenth Edition

Floyd

Chapter 15

2008 Pearson Education

DC Supply Voltage

Figure 15-1 Example of VCC and ground connection and distribution in an IC package.

Other pin connections are omitted for simplicity.

2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed

Agenda

Quiz #4:

Lecture: Chapter 15 (part 1); pp. 798-836

Lab 5; Exp 6: Interpreting Manufacturers

Data Sheets(Page 51).

Assignment: Questions 22, 24, 30, 32, 38, & 58, from the Problems section on pp. 831-835.

CMOS Logic Levels

Figure 15-2 Input and output logic

levels for CMOS.

Figure 15-3 Input and output logic levels for TTL.

TTL Logic Levels

Figure 15-4 Illustration of the effects of input noise on gate operation.

Figure 15-5 Illustration of noise margins.

Values are for 5 V CMOS, but the principle applies to any logic family.

Noise Margins VNH = VOH(min) VIH(min) VNL = VIL(max) VOL(max)

Figure 15-6 Currents from the dc supply.

Power Dissipation

For a gate in HIGH state: PD = VCCICCH

Average: PD = VCCICC

Figure 15-7 Power-versus-frequency curves for TTL and CMOS.

Power vs Frequency Curves

Note: Power of TTL is constant,

but power in CMOS increases as

frequency increases

Figure 15-8 A basic illustration of propagation delay.

Propagation Delay

Figure 15-9 Propagation delay times.

Propagation Delay

Figure 15-10 Loading a gate output with gate inputs.

Loading & Fan-out

Figure 15-11 Capacitive loading of a CMOS gate.

Loading & Fan-out

Figure 15-12 Basic illustration of current sourcing and current sinking in TTL logic gates.

Loading & Fan-out

Figure 15-13 HIGH-state TTL loading.

Loading & Fan-out

Figure 15-14 LOW-stage TTL loading.

Loading & Fan-out

Figure 15-15 Basic symbols and switching action of MOSFETs.

CMOS Circuits

Figure 15-16 Simplified MOSFET symbol.

CMOS Circuits

Figure 15-17 A CMOS inverter circuit.

CMOS Circuits

Figure 15-18 Operation of a CMOS inverter.

CMOS Circuits

Figure 15-19 A CMOS NAND gate circuit.

CMOS Circuits

Figure 15-20 A CMOS NOR gate circuit.

CMOS Circuits

Figure 15-21 Open-drain CMOS gates.

CMOS Circuits

Open-drain means that the drain terminal of the output transistor

is unconnected and must be connected externally to VDD through

a load.

Figure 15-22 The three states of a tristate circuit.

CMOS Circuits

Figure 15-23 A tristate CMOS inverter.

CMOS Circuits

Figure 15-24 Handling unused CMOS inputs.

CMOS Circuits

Handling CMOS:

1) All devices are shipped in an anti-static material

and should NOT be touched.

2) Place devices pins down on an antistatic mat.

3) All tools, test equipment, and metal benches

should be earth grounded.

4) Never insert CMOS devices into a circuit with

power on.

5) All unused pins should be connected to the

supply voltage or ground; never leave floating.

CMOS Circuits

2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed

Agenda

Quiz #4:

Lecture: Chapter 15 (part 1); pp. 798-836

Lab 5; Exp 6: Interpreting Manufacturers

Data Sheets(Page 51).

Assignment: Questions 22, 24, 30, 32, 38, & 58, from the Problems section on pp. 831-835.