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ed Neural Network Circuit Inside HighSpeed Camera

antyo Heruseto, amzah Afandi,Yulisdin Mukhlis,Eri Prasetyo WibowoGunadarma University

Jalan Margonda Raya 100Depok, Jawa Barat, Indonesia

Abstract- Analog VLSI on-chip learning Neural Networksrepresent a mature technology for a large number ofapplications involving industrial as well as consumerappliances. This is particularly the case when low powerconsumption, small size and/or very high speed are required.This approach exploits the computational features of NeuralNetworks, the implementation efficiency of analog VLSIcircuits and the adaptation capabilities of the on-chip learningfeedback schema. High-speed video cameras are powerful toolsfor investigating for instance the biomechanics analysis or themovements of mechanical parts in manufacturing processes. Inthe past years, the use of CMOS sensors instead of CCDs hasenabled the development of high-speed video cameras offeringdigital outputs, rcadout tlexibility, and lower manufacturingcosts. In this paper, we propose a high-speed smart camerabased on a CIVIOS sensor with embedded Analog NeuralNetwork

I. INTRODUCTION

The human vision presents high capacities In terms ofinformation acquisition (high image resolution) andinformation processing (high performance processing).Nevertheless, the human vision is limited because human'sreactions to a stimulus are not necessarily instantaneous.The human vision presents spatial and temporal resolutionlimitations. More precisely, the human vision temporalresolution is close to 100 milliseconds [I]. Moreover, thefast information storage capacity of the human system isdifficult to evaluate. On the other hand, the human visionsystem is very perforrnant in terms of image analysis whichextracts relevant information. In the last few years, technicalprogresses in signal acquisition [2, 3] and processing haveallowed the development of new artificial vision systemwhich equals or overpasses human capacities.

Therefore, the goal of our research is to implementembedded analog CMOS Neural Network for high speedsmart camera. High speed smart camera needs : : a fastimage acquisition, images with high resolution, and real-time image analysis which only keeps necessary information.Because of this, neural networks operating in a fewmilliseconds are required.

II. HIGH SPEED CAMERA DESCRIPTION

In order to design our high-speed smart camera, someconstraints had to be respected. The first one was of coursehigh frequency acquisition as well as embedded imageprocessing.

Nowadays, in the context of fast imaging, CMOS imagesensors present more and more advantages in comparisonwith CCD image sensors that we will summarize hereafter.(i) Random access to pixel regions: in CMOS image sensors,

both the detector and the readout amplifier are part ofeach pixel. This allows the integrated charge to beconverted into a voltage inside the pixel, which can thenbe read out over X- Y wires (instead of using a chargeshift register like in CCDs). This column and rowaddressability is similar to common RAM and allowsregion-of-interest (ROI) readout.

(ii) Intrapixel amplification and on-chip ADC (analog todigital converter) produce faster frame rates.

(iii) No smear and blooming effects: CCDs are limited bythe blooming effect because charge shift registers canleak charge to adjacent pixels when the CCD registeroverflows, causing bright lights. In CMOS imagesensors, the signal charge is converted to a voltage insidethe pixel and read out over the column bus, as in aDRAM (dynamic random access memory).With thisarchitecture, it is possible to add an antibloomingprotection in each pixel. Smear, caused by chargetransfer in a CCD under illumination, is also avoided.

(iv) Low power: CMOS pixel sensor architectures consumemuch less power-up to 100 x less power-than CCDs.This is a great advantage for portable high speedcameras.

A. High Speed Camera SystemsAs in a traditional image sensor, the core of the chip

presented ini this paper constructed of a two-dimensional (2-D) pixel array, here of 64 columns and 64 rows with randompixel ability, and some peripheral circuits. It contains about160 000 transistors on a 3.675 mm x 3.775 mm die. Themain chip characteristics are listed in Table I.

TABLE I . CHIP CHARACTERISTICSTechnology 0.35 pm 2-poly 4-metal CMOSArray size 64 x 64Chip size 11 mm"Number of transistors 160000Number of transistors 38/ nixelPixel size 35 urn x 35 urnSensor Fill Factor 25%Power consumption 110mWSuonlv voltaze 3.3 VFrame rate 10000 fps

Each individual pixel contains a photodiode for the lightto-voltagetransduction and 38 transistors integrating all theanalog circuitry dedicated to the image processingalgorithms, This amount of electronics includes a preloadingcircuit, two Analog Memory, Amplifier and Multiplexerstructures ([AMf) and an Analog Arithmetic Unit (A2U)based on a four-quadrant multiplier architecture. The fullpixel size is 35 um x 35~lm with a 25 % fill factor. Fig. 1shows a block diagram of the proposed chip. Thearchitectureof the chip is divided into three main blocks asin many circuits widely described in the literature. First, thearray of pixels (including photodiodes with their associatedcircuitryfor performing the analog computation) is placed atthe center. Second, placed below the chip core are thereadout circuits with the three asynchronous output buses:the first one is dedicated to the image processing resultswhereas the other two provide parallel outputs for full highrate acquisition of raw images. Finally, the left part of thesensor is dedicated to a row decoder for addressing thesuccessive rows of pixels. The pixel values are selected onerow at a time and read out to vertical column busesconnected to an output multiplexer. The chip also containstest structures used for cletailed characterization of thephotodiodes and processing units. These test structures canbe seen on the bottom left of the chip.

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Figure I. Block Diagram of the Chip

In Figure 1 shows of block diagram that have a speedcamera taking a picture of 10,000 frames / second. block thecamera has been designed is the matrix of 64x64 pixels or4096 pixels. The process of catching an object pixel byusing the decoder and then strengthened by columnmultiplexer. In this design, the image processing that useslow-level basic image processing such as edge detectionusing Sobel and Lappacian. [9]

Ill. EMBEDDED ANALOG CMOS EURALNETWORK

Conception of structures in CMOS technology thatdemand low power and low silicon area consumption havebeen widely investigated in the implementation of analog

neural networks in VLSI integrated circuits. FeedforwardMLP networks' building blocks require CMOS multipliersfor implementing the synapses, operational amplifier ascurrent voltage converter and sigmoid generator foractivation function circuits. A larger scale of integration ofsuch networks happens at the expense of simpler and, as aresult, nonlinear synaptical blocks. Regarding these aspectsit becomes advisable to derive suitable expressions to adjustthe back-propagation algorithm and deal with thesenonlinearities [5].

The synapses in a neural network can be realized byanalog multipliers if the inputs and the weights can berepresented by voltages. An illustrative synapse circuitwhich is a modified version of the well known Gilbertmultiplier is shown in Figure. 2. The inputs are in the formof voltage differences and are denoted by X, Y and bias.The output of the original Gilbert multiplier is a currentdifference and this difference is converted to a single endedcurrent (2) through current mirrors. This improves thelinearity of the multiplier as well as providing easyinterfacing to the following circuitry. Using voltage input-current output synapse for analog neural network is verysuitable for VLSI implementation since the actual signalsfrom outside are mostly in voltage form, and the summingoperation on synapse output can performed by connectingthe synapse output together.

''';;{foFigure 2. Analog CMOS Multiplier

The use of current-output synapses enables thesummation of those currents by simply connecting themtogether at the input of the neuron. This current sum can beconverted to voltage by using an opamp and a resistor as acurrent-to-voltage converter. The circuit diagram of theoparnp is given in figure 4.

Figure 3. Simulation of Multiplier with values linearity in range -I to I V

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Figure 4. Operational Amplifier

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Figure 5. Opamp simulation with input swing -3 to 3 V.

A sigmoid generator is used after the opamp to generatethe activation for the neuron and usually use inbackpropagation algorithm.

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Figure 6. Sigmoid Generator

Figure 7. Sigmoid simulation with values linearity in -1-1 V

For Simulation result using backpropagation algortihm foranalog and digital signal is given in picture 8 and 9

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Figure 8. Network Simulation using digital pattern.

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}~-h-~--~;<I:;};~T~j~L~;f=f-->~:. . . Targ'tG"omb",p" ! : ! : :

!~I,~~~~t~~F~f~• 5: ~1lJ J;J !l~ 5..: n, b: t:{; .1'lI; :tll

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Figure 9. Network Simulation Using Analog Pattern

The result of network simulation using analog and digitaltarget signal shows that close to the target to be recognize asa signal pattern.

IV. CONCLUSION

In this article we design analog neural network usinganalog CMOS 0.35 urn technolgy to recognize a signalpattern from high speed CM OS sensor. The simulationusing analog and digital simulation suitable for CM OSsensor with 80 MHz output signal frequency.

All designs and simulation of the analog neural networkcircuits described above are using mentor graphic withAMS technology 0.35 urn.

V. REFERENCES

[I] Annema, A.J, Hardware Realization of a NeuronTransfer Function and its Derivatives, Electronic letters,Vo!. 30, pp. 576-577,1994.

[2] Cardarili, G.c. and F. Sargeni,Very efficient VLSIImplementation of CNN with Discrete Templates,Electronic Letters, Vol. 29, pp. 1286-1287,1993.

[3] Fang, WJ, BJ. Sheu, O.T.c. Chen, A VLSr NeuralProcessor for Image Data Compression Using Self-Organization Networks, IEEE Transaction on NuralNetworks, Vo!. 3, pp. 506-518, 1992.

[4] Fausett, L., Fundamentals of Neural Network, PrenticeHall, Enlewood Cliffs, 1994

[5] Dillon,T., Arabshahi, P., Markus, RJ., Guest EditorialEveryday Application of Neural Networks, IEEETransaction on Volume 8, issue 4, July 1997.

[6] Hassoun, M.H., Fundamentals of Artificial NeuralNetwork, The MIT Press, Cambridge, 1995.

[7] Linares-Barranco, B., E. Sanchez-Sinencio, A.Rodriguez-Vazquez, and J.L. Huertas,J993, A CMOSAnalog Adaptive BAM with On-Chip Learning andWeight Refreshing, IEEE Transactions on Neuralnetworks, Vol.4, pp.445-455, 1993.

[8] R.Mosqueron, J .Dubois and M.Paindavoine, EmbeddedImage Processing/Compression for High-Speed CMOSSensor.

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