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Tunneling Transistors for Low Power Electronics James Teherani , Tao Yu, Dimitri Antoniadis, Judy Hoyt September 16, 2013 Support from NSF E3S Center

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Page 1: Tunneling Transistors for Low Power Electronics

Tunneling

Transistors for Low

Power Electronics

James Teherani, Tao Yu,

Dimitri Antoniadis, Judy Hoyt

September 16, 2013

Support from

NSF E3S Center

Page 2: Tunneling Transistors for Low Power Electronics

MOSFET TFET

September 16, 20132

(tunneling transistor)

Page 3: Tunneling Transistors for Low Power Electronics

MOSFET Scaling Crisis

September 16, 20133

Frequency scaling stalled

Power density of nuclear reactor

A. Danowitz, K. Kelley, J. Mao, J. P. Stevenson, and M. Horowitz, β€œCPU DB: Recording Microprocessor History,” Queue, vol. 10, no. 4, pp. 10:10–10:27, 4/2012.

1985 1990 1995 2000 2005 2010 2015

10 GHz

3 GHz

1 GHz

300 MHz

100 MHz

30 MHz

10 MHz

Pro

cesso

r C

lock S

pe

ed

Page 4: Tunneling Transistors for Low Power Electronics

September 16, 20134

Power & Voltage Scalingπ‘ƒπ‘Žπ‘π‘‘π‘–π‘£π‘’ = 𝛼𝐢𝑉𝑑𝑑

2 𝑓

π‘ƒπ‘π‘Žπ‘ π‘ π‘–π‘£π‘’ = πΌπ‘œπ‘“π‘“π‘‰π‘‘π‘‘ + 𝐼𝐺𝑉𝑑𝑑

0

1

2

3

4

5

1970 1980 1990 2000 2010

Vdd

(Vo

lts)

Voltage scaling stalled

π‘ƒπ‘‘π‘œπ‘‘π‘Žπ‘™ = π‘ƒπ‘Žπ‘π‘‘π‘–π‘£π‘’ + π‘ƒπ‘π‘Žπ‘ π‘ π‘–π‘£π‘’

A. Danowitz, K. Kelley, J. Mao, J. P. Stevenson, and M. Horowitz, β€œCPU DB: Recording Microprocessor History,” Queue, vol. 10, no. 4, pp. 10:10–10:27, 4/2012.

Page 5: Tunneling Transistors for Low Power Electronics

Transfer Characteristics

September 16, 20135

de

ca

de

mV

Dra

in C

urr

ent

(Ou

tpu

t)

Gate Voltage(Input)

πΌπ‘œπ‘“π‘“

𝑉𝑑𝑑2 𝑉𝑑𝑑1

πΌπ‘œπ‘›2πΌπ‘œπ‘›1

Transistor

log(𝐼)

SS–subthreshold swing (mV/decade)

Input

Output

p-type

DielectricGate

n-MOSFET

Input

Output

Sourcen-type

Drainn-type

Page 6: Tunneling Transistors for Low Power Electronics

Decrease SS

Transfer Characteristics

September 16, 20136

Dra

in C

urr

ent

(Ou

tpu

t)

Gate Voltage(Input)

πΌπ‘œπ‘“π‘“

𝑉𝑑𝑑2

πΌπ‘œπ‘›2

Transistor

log(𝐼)

SS–subthreshold swing (mV/decade)

Input

Output

Increased πΌπ‘œπ‘›for small 𝑉𝑑𝑑

p-type

DielectricGate

n-MOSFET

Input

Output

Sourcen-type

Drainn-type

Page 7: Tunneling Transistors for Low Power Electronics

September 16, 20137

If:

Reduce SS (subthreshold swing)

Then:

↓ 𝑉𝑑𝑑↓ π‘ƒπ‘‘π‘œπ‘‘π‘Žπ‘™

Page 8: Tunneling Transistors for Low Power Electronics

SS–Subthreshold Swing (MOSFET)

September 16, 20138

Ener

gy

n-MOSFET

x

Energy distribution of electrons

𝑛 𝐸 = 𝑓(𝐸) βˆ™ 𝑔𝐷𝑂𝑆(𝐸)thermal tail

CB

VB

Off-state current

𝑓 𝐸 β‰ˆ1

exp𝐸 βˆ’ πΈπ‘“π‘˜π‘‡

𝑓 𝐸 ⟹ 60 π‘šπ‘‰/π‘‘π‘’π‘π‘Žπ‘‘π‘’

Fermi-Dirac Distribution

Source Channel Drain

p-typeDielectric

n-type

Gate

n-typex

𝑓 𝐸1𝑓 𝐸2

β‰ˆ exp𝐸2 βˆ’ 𝐸1π‘˜π‘‡

Decreased off current

Distribution of Electrons

𝐸2

𝐸1

SS limited to 60 π‘šπ‘‰/π‘‘π‘’π‘π‘Žπ‘‘π‘’

Page 9: Tunneling Transistors for Low Power Electronics

MOSFET and TFET Structures

September 16, 20139

n-TFET

x

Energy distribution of holes

CB

VBOff-state currentX

Ener

gy

n-MOSFET

x

Energy distribution of electrons

thermal tail

CB

VB

Off-state current

Source Channel Drain Source Channel Drain

DielectricSource DrainGate

n-type n-typep-typex

DielectricSource DrainGate

p-type n-typeintrinsicx

Limited SS of πŸ”πŸŽπ’Žπ‘½/𝒅𝒆𝒄𝒂𝒅𝒆 No πŸ”πŸŽπ’Žπ‘½/𝒅𝒆𝒄𝒂𝒅𝒆 limit

Page 10: Tunneling Transistors for Low Power Electronics

Ener

gy

x

CB

VB

DielectricSource DrainGate

p-Si n-Sii-Sin-TFET

x

𝑇 ∝1

exp(π΄π‘Ÿπ‘’π‘Ž)

Homostructure

September 16, 201310

x

CB

VB

DielectricSource DrainGate

p-GaSb n-InAsi-InAsn-TFET

x

HeterostructureTunneling in

Page 11: Tunneling Transistors for Low Power Electronics

Experimental Results

September 16, 201311

Page 12: Tunneling Transistors for Low Power Electronics

Density of States Switch

September 16, 201312

CB

VB

CB

VB

OFF-State ON-State

Page 13: Tunneling Transistors for Low Power Electronics

Bilayer TFET Structure

September 16, 201313

+VD

p+ n+

Metal (+VG)Dielectric

(b)

MetalDielectric

(a)

iChannel

p+Source

n+Drain

Cut shown in (c)

DielectricMetal

BTBT

DielectricMetal (-VG)

Bottom

Gate

Top

Gate

(c)

𝐸1β„Ž

𝐸1𝑒

Page 14: Tunneling Transistors for Low Power Electronics

Challenges Limiting TFET

Performance

Fundamental

Phonon effects

Band edge abruptness

Technological

Interface states

Complex geometries, design

Junction abruptness

Thickness variation with thin body

structures

Work function engineering

September 16, 201314

Page 15: Tunneling Transistors for Low Power Electronics

Summary

Frequency and voltage scaling of MOSFETs have stalled due to power constraints

Substantial voltage scaling requires new switching physics

TFETs employ tunneling to overcome 60 π‘šπ‘‰/π‘‘π‘’π‘π‘Žπ‘‘π‘’ limit

Experimental results have shown 𝑺𝑺 < 60 π‘šπ‘‰/π‘‘π‘’π‘π‘Žπ‘‘π‘’, albeit at low currents

Much work is still needed in matching theory to experiment

Heterojunctions and density-of-states switching designs may lead to better TFET performance

We’re currently exploring the bilayer TFET, which utilizes an interesting device geometry to create electron and hole quantum wells

September 16, 201315


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