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Tutorials for Layout, DRC, and LVS
Sheng-Yu Peng10/27/2007
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Create New Library from Library ManagerFile New Library…
Attach the existing tech library --> TSMC 0.4u CMOS035 (4M, 2P, HV FET)
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Create Schematic Cell ViewFile New Cell View…
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Instantiate NMOS and PMOSAdd Instance i
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Change the Model name to be the EKV Models
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Add PinsAdd Pin …p
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Create Layout Cell View from Library ManagerFile New Cell View
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Set the X, Y snapping spacesOption Display …e
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Instance CellsCreate Instance …i
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Make connections with the appropriate layers
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Create ContactsCreate Contact … o
Via1 Poly Contact P-sub Contact N-well Contact
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Create PinsCreate Pin … P
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Place the Pins Properly and Save
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Run DRC Verify DRC…
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Check the DRC errors
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Check DRC errorsVerify Markers Find
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Correct the Layout error
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Extract the LayoutVerify Extract…
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Layout Verify with SchematicVerify LVS…
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Specify the schematic and extracted cell viewsRun
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Check the LVS ResultsOutput
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LVS Error DisplayShort the Vout and gnd! on purpose
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Extracted and Run LVS
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LVS not match from the Output file
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Open the Extracted Cell View
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Open the Error Display
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Open the Schematic Cell View
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Look at the error in Schematic Cell View
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Correct the Layout, DRC, Extract, and LVS
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DRC Free and LVS Matched