two zero two pole replaces cp - ieee entity web...

Mixed Signal Products

Wireless6/28/2008

Two Zero Two Pole Active Compensation Replaces a Charge Pump and Regulator

in PLLs 6-25-08

Stanley J. GoldmanTexas Instruments


Wireless6/28/2008

Agenda

• PLL Review• Various Loop Filters• 2 Zero 2 Pole Plots and Equations• 2 Zero 2 Pole Results


Wireless6/28/2008

PLL Basic Block DiagramInput Phase Transduced to Voltage and

Voltage Transduced to Output Phase


Wireless6/28/2008

Ideal VCO Transfer Function,Transduces Voltage to Frequency (Edges)

ωout=ωoff+Kv Vtune

ωout=∆θout/∆t

To = 2 M Td


Wireless6/28/2008

Digital Phase Detector Timing and Response to Ramped VCO Phase

V C O I N

R I N

V D D

V D D

U P

D O W N

QCCL

QCCL

D Q

D Q

Reset


Wireless6/28/2008

Ideal Phase Detector Transfer Function,Transduces Frequency (Edge) Differences to Voltage

Vpdavg=Kd θe (5MHz Ref. Freq.)


Wireless6/28/2008

Charge Pump Output Transduces Frequency (Edge) Differences to Current, Kp=I/(2 π)


Wireless6/28/2008

Example of Lock, Digital Loop(In Phase)

0 50000 100000 150000 200000 250000Time (ns)

0

1

2

3

Tune

Vol

tage

0

1

Up

0

1

Dow

n

0

1

VC

O O

utpu

t

0

1R

ef. I

n


Wireless6/28/2008

Loop Classifications


Wireless6/28/2008

Comparison of PLL Loop Filterswith Regulators driving VCO

• Charge pump PLL• Replica Bias PLL• Digital PLL• 1 Zero Active PLL


Wireless6/28/2008

Charge Pump PLL with Regulator

•Charge pump can not drive high current load•1 pin for external components


Wireless6/28/2008

Replica Biased Charge Pump PLL

Advantages/Disadvantages•Widely used for many years and many designs•High sensitivity to power supply at regulator output•Narrow frequency tuning range (~200mV for nano scaled devices)•Low output voltage swing to differential to single ended converter (50mVpp) •Narrow output voltage range for charge pump (~200mV for nano scaled devices)•Differential ring stops oscillating


Wireless6/28/2008

All Digital PLL with Regulator

•Sensitivity to power supply•Not state of the art performance in power, area, and noise? trade offs•Leakage does not change frequency


Wireless6/28/2008

1 Zero Active Compensation


Wireless6/28/2008

1 Zero, Type 2 Second Order Open Loop Gain Function (Active Filter)

Cascade of Transfer functions for Open Loop GainG(s)H(s)= (Phase Detector Gain)(Filter Transfer Function) (VCO Transfer Function)(Divider Transfer Function)

Substitute and Rearrange for Open Loop Gain Expression

Substitute and Rearrange for Closed Loop Gain Expression

= Capacitor in the operational amplifier'sfeedback path (F),

= Resistor in operational amplifier's feedback path (ohms) and,

= Resistor at the negative input terminalof the operational amplifier (ohms).

= Phase detector gain (volts/radian),= VCO transfer function gain

constant (radians/second/volt),= Integer divider value,= Loop Frequency Multiplication Factor,= Output frequency/ input frequency,

Kd

nmf

C

R1

R2

.G( )s H( )s ...Kd Kv

..nmf C R1

1

s2..s C R2 1


Wireless6/28/2008

Uncentered Type 2 1 Zero Open Loop Magnitude and Phase, 1MHz Bandwidth example


Wireless6/28/2008

Advantages of 2 Zero 2 Pole Compensation

• OPAMP Replacing a Charge Pump– Wider Supply Operating Range, Rail to Rail– Lower Voltage drop out– Linear Differential to Single Ended Conversion– Sources VCOs that draw current– No power down resets– Acts as voltage regulator to minimize sensitivity to power

supply– Flexibility in Compensation Polynomials

• 2 Zero 2 Pole Compensation– >90 deg. Added to Phase Margin – Wider Bandwidth– Wider and Optimum Stable Region for less process sensitivity


Wireless6/28/2008

100 1 103 1 104 1 105 1 10680

75

70

65

60

55

50

45

40

35

30

Mag.(dB)

Frequency (Hz)

fxfx/sqr(k)

fx sqr(k)

Gx

Desired high phase boost example of 2 zero 2 Pole magnitude response for compensation only and phase margin greater than 90 degrees, 10kHz BW Example


Wireless6/28/2008

Desired 2 Zero Phase Response for Compensation Only for Phase Margin Greater Than 90 degrees (120 deg), 10kHz BW

Example

100 1 103 1 104 1 105 1 106100

70

40

10

20

50

Phase (deg.)

Frequency (Hz)

PhaseBoost


Wireless6/28/2008

RC +90% and -50% process variation, shows PLL bandwidth insensitivity with 0.7 Damping factor and Symmetric centering of the poles

and zeroes

1 103× 1 104× 1 105×40−

32−

24−

16−

8−

0

8

16

24

32

40

Hrcmj

Hrc1mj

Hrc2mj

fj


Wireless6/28/2008

PLL connection for a type 2 and 2 zero loop compensation.


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VCO Description


Wireless6/28/2008

2 Zero 2 Pole Open Loop Transfer Function Equations

Vo

Vi

..1..s C1 C2 R1

..s C1 R2 1

1 ...s R2 C2

C1

C1 C2

..s R1 R3 C3 1

..s R3 C3 1

VoVi

.1s

.ω x

Gx

k

.1 sω x

k

1 sω x

k

.1 s

.ω x k1 s

.ω x k

k tanφ boost

445

2

Gx1.Kd Kv

.N ω x


Wireless6/28/2008

Magnitude response of 2 zero compensation solution to the design

1 . 10 4 1 .105

1 .106

1 .107

1 .108

60 55 50 45 40 35 30 25 20 15 10

5 0 5

10

Mag. (dB)

Frequency (Hz)

Gx

fx

fx/sqr(k)

fx sqr(k)


Wireless6/28/2008

Open loop phase response with type 2 and 2 zero compensation.

1 .104

1 .105

1 .106

1 .107

1 .108

100

95

90

85

80

75

70

65

60

55

50

45

40

Phase(deg.)

F requency (Hz)

Phase

Boost


Wireless6/28/2008

Open loop magnitude response with type 2 and 2 zero compensation

1 . 10 4 1.105 1.106 1. 10 7 1.108100

80

60

40

20

0

20

40

60

80

100

Mag. (dB)

Frequency (Hz)


Wireless6/28/2008

C021 Die photo of the PLL circuit, 300x200um=0.06mm2

PD

VCO

DIV

OPAMP BIAS

Filter

200µm

300µm


Wireless6/28/2008

Measured Data Spectrum, Reference Sidebands <-60dBc


Wireless6/28/2008

Measured Data Jitter <80ps peak to peak


Wireless6/28/2008

Measured Phase Noise,1MHz Bandwidth, -92dBc/Hz Phase Noise at 1MHz, High

Phase Margin, Low additive Noise

1E+4 1E+5 1E+6 1E+7 1E+8 1E+9Offset Frequency (Hz)

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

Sing

le S

ideb

and

Phas

e N

oise

(dBc

/Hz)

Leeson's model

MeasuredClosed loop PLL


Wireless6/28/2008

Comparison Table of Measured Data with Comparable PLL References

.02%/1%80ps p-p12-6000.061mW at 240MHz.065um 1.2V

This work APLL

All Digital PLL, diff. ring VCO130ps p-p30-160

3.12mW at 160MHz.25um 1.9V

Fahim TCAS '03

Differential ring VCO, VCR

155ps p-p360MHz10-3500.167mW at 200MHz.13um 1.5V

Hozer ISSCC '02

Differential ring VCO, self biased48ps p-p30-6500.187mW at 240MHz.13um 1.5V

ManeatisISSCC '03

Single ended ring CCO21ps p-p500-23500.1530mW at 2000MHz.1um 1.2V

K. Minami CICC '01

Supply ControledRing VCO, wide BW, 2.5MHZ BW.32%/1%[email protected] 1.9V

H. Ahn JSSC '00

Regulator included, single ended ring CCO.007%/1%

44ps p-p at 700MHz600- [email protected] 3.3V

J.M. InginoISSCC '01

Simulated, Supply Controled Ring VCO, wide BW.06%/1%[email protected] 3.3V

S. SidropoulosVLSI '00

Comments

power supply sensitivity, %-fvco/%-VddJitter

VCO Output Frequency (MHz)

Area (mm2) PowerProcessesDescription


Wireless6/28/2008

References, 1. Stanley Goldman, Phase Locked Loop Engineering

Handbook, Artech House, Boston, 2007.2. Roland Best, Phase Locked Loops Design

Simulation, & Applications, McGraw Hill, New York, 1997.

3. Behzad Razavi, Monolithic Phase-Locked Loops and Clock Recovery Circuits, IEEE Press, New York 1996.

4. William Egan, Frequency Synthesis by Phase-Lock, Wiley Interscience, New York, 1981.

5. Floyd Martin Gardner, Phaselock Techniques, Wiley Interscience, New York, 1979.


Wireless6/28/2008

Key Points• Voltage Regulator can be incorporated into loop

compensation (Dual Use)• Geometrically Centered Zeroes and Poles Reduces

sensitivity to R C process variations• Increasing Resistance can be used to reduce capacitor

size and overall loop size.• Wider loop bandwidths can be achieved with 2 zeros

because of the increase in phase margin.• Widest loops give lowest phase noise for references with

lower noise than the VCO• Further future improvements can be made to reduce

power, size, and area.• Active Compensation gives flexibility in compensation

two zero two pole replaces cp - ieee entity web...

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