ultra-low-voltage nanometer cmos circuits for smart energy...

1

Ultra-Low-Voltage

Nanometer CMOS Circuits

for Smart Energy-

Autonomous Systems

David Bol,

Cédric Hocquet, Dina Kamel, Julien De Vos,

Denis Flandre and Jean-Didier Legat

BWRC seminar, July 2nd, 2010Microelectronics Laboratory

2

UCL’s breath recording system

• Humidity sensor with capacitive I/F and wireless

transmission over IEEE802.15.4

• Diagnosis of sleep apnea-hypopnea syndrome

• Custom sensor with COTS µC and radio

• 2x AAA batteries

• Autonomy limited to 40hrs

D. Bol ULV Nanometer CMOS Circuits

[André, IEEE J.

Sensors, 2010]

2

3

IMEC’s EEG monitoring

• 1cm³ 8-channel ambulatory EEG system

• Custom readout with COTS µC and radio

• 120 mAh Li-ion battery 60hrs autonomy

• Power dominated by radio and µC


[Yazicioglu, Micro. J’08][Yazicioglu, IEEE JSSC’08]

4

40× power savings

Limited

programmability

MIT’s EEG monitoring

• 1-channel EEG seizure detection system

• 0.18µm CMOS 1V SoC with custom

readout + feature extraction processor


Dedicated on-chip

processing saves radio

bandwidth

[Verma, SVLSI’09] [Verma, JSSC’10]

3

5

TI’s EEG SoC


• 3mm² EEG seizure detection system

• Custom Cortex-M3 µC + dedicated HW

• 0.13µm CMOS, power @ 0.5V< 1µW

• Max. freq.: 7kHz @0.5V – 5MHz @1V

[Sridhara, SVLSI’10]

programmability

6

Energy-Autonomous Systems

• Radio bandwidth is limited by available energy

• On-chip processing costs less energy than

wireless communications

• Need smart EAS to transmit only useful data

• Constraint : currently low-volume market

� require low NRE and generic platformsD. Bol ULV Nanometer CMOS Circuits

Power

management

Energy generation

Harvesting

Storage

Energy conversion Functionality

Acquisition

Control

Communication

Signal

processing

4

7

HOW ?


Smart EAS

Power

management

Power

management

Energy generationEnergy generation

HarvestingHarvesting

StorageStorage

Energy conversionEnergy conversion FunctionalityFunctionality

AcquisitionAcquisition

ControlControl

Com.Com.

Signal

processing

Signal

processing

Power

management

Energy generation

Harvesting

Storage


Acquisition

Control

Com.

Signal

processing

Ultra-low-voltage (ULV) circuit operation

Nanometer CMOS technologies

8

Outline

• Motivation

• Why ULV in nanometer CMOS circuits ?

• ULV logic design challenges

• FD SOI technology

• ULV targets and roadmap

• Test case


5

9

0.2 0.4 0.6 0.8 1 1.210

3

104

105

106

107

108

Vdd

[V]

Fre

quen

cy [H

z]

MeasuredInverter ring osc.

251 stages - FO1LP SVT devices

Ultra-low-voltage nano-CMOS


– Speed penalty

– Sensitivity against variations

– Logic: low active energy Eop

– Memories: low static

power Pleak

Vdd ≤ 0.5V : MOSFETs in near/subthreshold regime

Nanometer CMOS : 65nm and smaller– Low area = low die cost

or high device count

– Low switched capacitances

– Speed boost

– High mask cost

– High variability

– High leakage

Motivations Limitations

0.2 0.4 0.6 0.8 1 1.20

0.2

0.4

0.6

0.8

Vdd

[V]

Eop

[pJ]

MeasuredInverter ring osc.251 stages - FO1LP SVT devices

Measurement

65nm LP

Measurement

65nm LP

10

Vdd scaling


Eop = ½ Nsw CL Vdd²

+ Vdd x Ileak x Top

Eleak• Scaling Vddbelow Vmin(R3/R2)is not useful

• Emin at one particular target frequency !

Eop = Ptot dt Top

[D. Bol, Analysis and minimization of practical energy in

45nm subthreshold logic circuits, 2008], Best Paper Award

104

105

106

107

108

109

0

0.5

1

1.5

Min

imu

m V

dd [V

]

8-bit RCA multiplier in 130nm technology

Speed limit

104

105

106

107

108

109

10-14

10-13

10-12

Throughput [Op/s]

Eop

[J]

Eleak

Esw

ftarget [Hz]

Functional limit

(fmin,Emin)

×

× (fmin,Vmin)

R3 R2 R1

R3 R2 R1

6

11

Vdd and technology scaling


104

105

106

107

108

109

0

0.5

1

1.5M

inim

um

Vdd

[V]

8-bit RCA multiplier in industrial technologies

Faster at

low VddLower

robustness

104

105

106

107

108

109

10-14

10-13

10-12

10-11

10-10

Throughput [Op/s]

Eop

[J]

Esw is reduced

Eleak is increased

ftarget [Hz]

× ×Low-performance Mid-perf.

• T=25°C

• MC Spice

simulations

• Foundry BSIM

compact models

• GP bulk

• Std-Vt devices

• Min. L

• Constant W/L

[D. Bol et al., Interests and limitations of technology

scaling for subthreshold logic, IEEE Trans. VLSI, 2009]

[D. Bol, Analysis and minimization

of practical energy in 45nm

subthreshold logic circuits, 2008],

Best Paper Award

ftarget [Hz]

12

Outline

• Motivation



– Energy efficiency

– Robustness

– Timing closure


• Test case


7

13

Energy efficiency


104

105

106

107

108

109

10-14

10-13

10-12

10-11

10-10

Throughput [Op/s]

Eop

[J]

Eleak is increased

ftarget [Hz]

× ×1

Esw is reduced

Esw is reduced

106

107

108

Eop

[J]

2

1

14

Theoretical Emin scaling trend


• T=25°C

• TCAD models

• LSTP bulk

• Min. L

• Constant W/L

• No variability

[Hanson, IEEE TED, 2008]

FO1 inverter

Vmin ~ S

Emin ~ CLS2

2

8

15

Practical Emin scaling trend

D. Bol

130nm 90nm 65nm 45nm0

10

20

30

40

50

60

Em

in [f

J]

CLS2

ULV Nanometer CMOS Circuits

Technology node

8-bit RCA multiplier simulations

0.2 0.3 0.4 0.520

30

40

50

60

70

80

90

100

Vdd

[V]

En

ergy

per

op

era

tion

[fJ]

130n

m

90nm

65nm

45nm

Eop

Estat

Emin× (Vmin, Emin)

• GP bulk std-Vt

• Foundry BSIM4 models

• Yield-aware simulation

2

• Subthreshold swing

• DIBL !

• Gate leakage

• Variability (RDF)Increase in:

leads to Emin penalty in nano-CMOS technologies[D. Bol, Nanometer MOSFET effects on the minimum-energy point of 45nm

subthreshold circuits, ACM/IEEE ISLPED, 2009] [D. Bol, ACM TODAES, 2010]

16

Optimum MOSFET selection

D. Bol

Lg [nm]

High-Vt

Std-Vt

Low-Vt

130 90 65 450

10

20

30

40

50

60

Em

in [f

J]

CLS2

8-bit RCA multiplier simulations

Optimum

MOSFET

selection

-35%

Baseline

devices

Technology node [nm]


2

[D. Bol, Nanometer MOSFET effects on the minimum-energy point of 45nm

subthreshold circuits, ACM/IEEE ISLPED, 2009] [D. Bol, ACM TODAES, 2010]

9

17

Energy efficiency


104

105

106

107

108

109

10-14

10-13

10-12

10-11

10-10

Throughput [Op/s]

Eop

[J]

Esw is reducedEleak is increased

ftarget [Hz]

× ×

106

107

108

Eop

[J]

2

1

1

18

Technology flavors

D. Bol

GP flavor

1V

1-3GHz

10-100W

LP flavor

1.2V

100-600MHz

0.5-5W


Commercial 65/45nm technology :

Power

management

Power

management



StorageStorage



ControlControl

Com.Com.

Signal

processing

Signal

processing

Power

management

Energy generation

Harvesting

Storage


Acquisition

Control

Com.

Signal

processing

For smart EAS, what to choose ?[D. Bol et al., Technology flavor selection and adaptive techniques for

timing-constrained 45nm subthreshold circuits, ACM/IEEE ISLPED, 2009]

1

10

19

Technology flavors for ULV CMOS

D. Bol

Commercial 65/45nm technology :

GP flavor

0.3-0.5V

1-50MHz

10-500µW

LP flavor

0.3-0.5V

10kHz-1MHz

0.1-10µW


Power

management

Power

management



StorageStorage



ControlControl

Com.Com.

Signal

processing

Signal

processing

Power

management

Energy generation

Harvesting

Storage


Acquisition

Control

Com.

Signal

processing

Smart EAS

1

[D. Bol et al., Technology flavor selection and adaptive techniques for


20

Minimum-energy @ target frequency


103

104

105

106

107

108

0

0.2

0.4

0.6

0.8

Min

imum

Vdd

[V]

103

104

105

106

107

10810

-14

10-13

10-12

ftarget

[Hz]

Eop

[J]

Std-Vt

High-Vt

LP

LP

GP

GP

Low-performance Mid-perf.

1High Ileak in GP

requires leakage

reduction technique

Active mode :

• Dual-Vt not feasible

< too large delay

difference at ULV

Sleep-mode :

• RBB not effective

< low body effect

• Power-gating harms

robustness

[D. Bol et al., Technology flavor selection and adaptive techniques for


8-bit RCA multiplier 45nm simulation

11

21

Variations of dynamic energy


[D. Kamel, D. Bol et al., Glitch-induced within-die variations of

dynamic energy in voltage-scaled nano-CMOS circuits, ESSCIRC, 2010]

Glitch-induced

Edyn variations

@1V @0.4V Glitches

induced by

path delay

variations65nm SBOX

65nm

SBOX

Monte-Carlo

simulations

65nm LP measurement

22

Outline

• Motivation




– Robustness

– Timing closure



• Test caseD. Bol ULV Nanometer CMOS Circuits

12

23

Logic noise margins


[D. Bol et al., Interests and limitations of technology

scaling for subthreshold logic, IEEE Trans. VLSI, 2009]

32 45 65 90 130 180 250

0

50

100

Technology node [nm]

SN

M [m

V]

Without DIBL

Nominal

µ-3σµ-4σ

Functionalfailure

DIBL

Variability

S degradation

@ 0.3V

Benchmark circuit

to estimate

probability of

functional faults

in logic[Kwong, ISLPED’06]

! DIBL !

24

ULV circuit robustness

D. Bol

• Logic gates with limited stacks

• Channel length upsize

• Library redesign

• Adaptive β ratio [Hwang,JSSC’10]

[D. Bol, IEEE Trans. VLSI, 2009]

Functional failure

3σ functional yield

Robust 0.3V operation

is no longer reachable

in 45/32nm technologies

Existing solutions:

Our solutions:


[Pu,JSSC’09][Kwong,JSSC’09]

[Abouzeid,ISLPED’09]

13

25

Power gating and robustness


[D. Bol et al., Robustness-aware sleep transistor engineering for

power-gated nanometer subthreshold circuits, IEEE ISCAS, 2010]

Sleep-transistor

series resistance

harms

robustness

std-Vt

high-Vt sleep

transistorsleep

Vdd

Vdd = 0.35V

45nm LP simulations

! DIBL !

26

101

102

0.2

0.4

0.6

0.8

1

high-Vt 40nm

std-Vt 40nm

std-Vt 80nm

std-Vt 80nm

101

102

0.2

0.4

0.6

0.8

1

NMOSS DIBL

[mV/dec] [mV/V]

high-Vt Lg=40nm 93.3 94.9std-Vt Lg=80nm 83.3 71.8

Sleep transistor engineering


Sleep-mode technique Min. Vdd for iso-robustness Emin penalty Esleep reduction

RBB @ Emin 0.35 0 % 9.6×

Conv. sleep transistor 0.42 19 % 105×

Opt. sleep transistor 0.37 8 % 108×

Opt. sleep transistor 0.41 18 % 168×

Ileak reductionIleak reduction

Re

lati

ve s

pe

ed

Re

lati

ve r

ob

ust

ne

ss

[D. Bol et al., Robustness-aware sleep transistor engineering for

power-gated nanometer subthreshold circuits, IEEE ISCAS, 2010]

45nm LP simulations

14

27

Outline

• Motivation




– Robustness

– Timing closure



• Test caseD. Bol ULV Nanometer CMOS Circuits

28

Timing closure


[D. Bol et al., The detrimental impact of negative Celsius

temperature on ultra-low-voltage CMOS logic, ESSCIRC, 2010]

65nm LP measurements

@[email protected]

@0.9V

At ULV: 1) temperature impact on delay stronger than global PV

2) low temperature = worst case

@[email protected]

@0.9V

15

29

PVT-induced Tcycle margins




Lower bound of industrial temperature range

(-40°C) degrades speed by a factor 5.3×

Tcycle margin 25°C -40°C

20mV Vdd drop 60% 95%

3σ die-to-die process variations 43% 75%

SS process corner 55% 96%

Combined PVT 2.3× 18.1×

65nm LP measurements @0.4V Room Industrial

Low temperature further increases the sensitivity

against process and voltage variations (deeper sub-Vt)

30

Impact of RDF on timing

D. Bol

[Kwong, IEEE J. Solid-State Circuits, 2009]

D Q

clk

D Q

Register A Register B

Combinatorial

logic

Launch

path

Capture path

Hold-time

constraint

TC-to-Q,min + Tpath,min

> Tskew + Thold

ULV circuits in nano-CMOS are prone

to hold time violations

Custom statistical

timing analysis[Kwong, JSSC’09]


16

31

Temperature and timing uncertainties

• Temperature magnifies path delay variations

• Low-temperature is a worst case for hold time


-25 0 25 50 750

200

400

600

I on v

aria

bilit

y

Temperature [°C]

-25 0 25 50 750

4

8

12

Pat

h de

lay

varia

bilit

y

Ion

DelayLD=5

LD=15

LD=40

@[email protected]



65nm LP simulations

32

Outline

• Motivation





• Test case


17

33

FD SOI technology

D. Bol

Mid-gap

metal gate

Substrate

Source Drain

Buried oxide (BOX)

Poly-Si

gate

Substrate

Source Drain

Buried oxide (BOX)

Doping similar to bulk

to control the SCE

Undoped channel

Partially-depleted (PD) SOI Fully-depleted (FD) SOI

TdepTSi

Tdep ~ 1/√Nch

[Weber, IEDM’08]

32nm FD SOI MOSFET

with high-κ/metal gate• No RDF � low variability

• No history effect

34

FD SOI for ULV circuits


Var.

Igate

DIBL S

short

Slong

0

5

10

15

20

25

30

Em

in [f

J]

[D. Bol, ACM TODAES, 2010]

[D. Bol et al., Sub-45nm fully-depleted SOI CMOS

subthreshold logic for ultra-low-power applications,

IEEE SOI Conference, 2008], Best Poster award

45nm technologiesS

[mV/dec]η

[mV/V]I0

[pA/µm]σVt

[mV]CL

[fF/µm]

Bulk 92.5 183 340 46 21.5

Undoped FD SOI 70.2 167 340 15.1 18.7

130nm 90nm 65nm 45nm0

10

20

30

40

50

60

Technology node

Trend in standard bulk technologies Optimum

MOSFET selection

FD SOI -35%

-60%

Em

in[fJ

]

Bulk FD SOI

• Energy: -60% Emin

• Speed: 10x boost @0.4V

• Robustness: minimum Vdd-90 mV

18

35

Outline

• Motivation





• Test case


36

ULV technology/circuit specifications


1 2Reducing Emin Reaching Emin

Technology level

Low CL, S, DIBL, variability (I0)

Igate, Ijunc < Isub @ 0.3-0.4V

Single device type for all logic gates I0 tuning

Relaxed constraints:

• Gate capacitance

• Gate/junction

leakages

• High leakage reduction

Sleep-mode technique

• Design-time device selection

• Run-time adaptive technique

• Multi-I0 devices

with coarse granularity

• On-chip I0 tuning

with fine granularity

• Mobility

• Access

resistances• Low impact on active-

mode operation

Circuit level

[D. Bol, “Pushing Ultra-Low-Power Digital Circuits into

the Nanometer Era”, Ph.D dissertation, UCL, 2008]

[D. Bol, “Roadmap for nanometer ultra-low-power

digital circuits based on sub/near-threshold CMOS

logic”, www.soiconsortium.org, 2009]

19

37

130 / 90 nm 65 / 45 nm 32 / 22 nm

EAS for basic

ULP applications

< 5µW

@0.01-1MIPS

Smart EAS for

new applications

5-100µW

@1-50MIPS

ULV technology/circuit roadmap


Node

Applications

Architectural techniques (//, pipe)

for meeting target frequency

[D. Bol, “Roadmap for nanometer ultra-low-power

digital circuits based on sub/near-threshold CMOS

logic”, www.soiconsortium.org, 2009]

Subthreshold logic

Bulk std devices

@ GP flavor

Subthreshold logic

Bulk opt. devices

@ LP flavor

+ ULV design flow

+ adaptive technique

Near-threshold logic

Bulk opt. devices

@ GP flavor

+ ULV design flow

+ power gating

+ arch. technique

Near-threshold logic

UTB FD SOI

@ dedicated flavor

+ ULV design flow

+ ???

Performance

issues @ULV

Economical

issues

38

Outline

• Motivation





• Test case


20

39

AES coprocessor for secure RFID tags

• ULV design flow - 65nm LP

• 8-bit architecture

• 3.5 kGE - 0.012 mm²

• Internal CLK generatorD. Bol ULV Nanometer CMOS Circuits

Power Budget for:

HF (13.56 MHz): 22.5 µW

UHF (900 MHz): 4 µW

40

103

104

105

106

0.6

0.8

1

1.2

1.4

1.6

1.8x 10

Max. throughput [bps]

CORE65LPSVTSUB65LPSVTSUB65LPSVTL80

Max. throughput [bps]

Eo

p[n

J] (

12

8-b

it e

ncr

yp

tio

n)

100 kbps

@0.4V

0.85µW

AES preliminary results

• ULV flow saves 5-10% energy

• Upsized Lg saves 10-15% energy

• Fits within passive RFID power budget


65nm LP measurement

[C. Hocquet et al., to

be published, 2010]

0.25V

0.5V

21

41

AES coprocessors comparison

Fast and low-cost ULV design flow in 65nm LP

� strong energy reduction without efforts devoted to

architecture/circuit optimizations


SourceComplexity

[Geq]

Tech.

[nm]

Area

[mm²]

Cycles

count

Vdd range

[V]

Eop @36kbps

[nJ]

Feldhofer,

Proc. IS’053400 350 0.25 1032 0.65-3.3 8.7† @0.65V

Good,

TVLSI’105500 130 0.021 356 0.75-1.3 2.5 @0.75V

Proposed 3500 65 0.012 1142 0.25-1.2 0.9 @0.35V

[C. Hocquet et al., to

be published, 2010]

Test chips with 8-bit architecture

† Eop extrapolated at minimum reported Vdd from 1.5V with Vdd² scaling law

42

Conclusions

• Autonomy/functionality

of EAS is limited

by radio power

• Need smart EAS

with processing

capability to limit radio usage

• ULV circuit operation + nanometer CMOS

technologies enables boosted processing capability

within µW power budget

• Proposed design techniques @65/45nm enable easy

and fast design (low NRE) for versatile smart EAS


Power

management

Power

management



StorageStorage


AcquisitionAcquisitionControlControl

Com.Com.

Signal

processing

Signal

processing

Power

management

Energy generation

Harvesting

Storage


AcquisitionControl

Com.

Signal

processing

22

43D. Bol

Acknowledgements:

• D. Bol’s work is funded by FNRS

and Walloon region of Belgium

• Ph.D students @ UCLouvain:

C. Hocquet, J. De Vos, D. Kamel,

F. Regazzoni (postdoc)

Any questions ?

Thank you!


44

References


[1] D. Bol et al.: “Interests and limitations of technology scaling for subthreshold logic”, in IEEE Trans. VLSI

Syst., vol. 17 (10), pp. 1508-1519, 2009.

[2] D. Bol et al.: “Analysis and minimization of practical energy in 45nm subthreshold logic circuits”, in Proc.

IEEE ICCD, 2008, pp. 294-300, Best Paper Award.

[3] D. Bol et al.: “The detrimental impact of negative operating temperature on ultra-low-voltage CMOS logic”,

accepted for IEEE ESSCIRC, 2010.

[4] D. Kamel et al.: “Glitch-induced within-die variations of dynamic energy in voltage-scaled nano-CMOS

circuits”, accepted for IEEE ESSCIRC, 2010.

[5] D. Bol et al.: “Technology flavor selection and adaptive techniques for timing-constrained 45nm

subthreshold circuits”, in Proc. ACM ISLPED, 2009, pp. 21-26.

[6] D. Bol et al.: “Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold circuits”, in

Proc. ACM ISLPED, 2009, pp. 3-8.

[7] D. Bol et al.: “Robustness-aware sleep transistor engineering for power-gated nanometer subthreshold

circuits”, in Proc. IEEE ISCAS, 2010, pp. 1484-1487.

[8] D. Bol et al.: “Channel length upsize for robust and compact subthreshold SRAM”, in Proc. FTFC, 2008, pp.

117-120.

[9] C. Hocquet et al.: “Assessment of 65nm subthreshold logic for smart RFID applications”, in Proc. FTFC, 2009.

[10] D. Bol et al.: “Sub-45nm fully-depleted SOI CMOS subthreshold logic for ultra-low-power applications”,

Proc. IEEC SOI Conf., 2008, pp. 57-58, Best Poster Award.

[11] D. Bol et al.: “Roadmap for nanometer ultra-low-power digital circuits”, available at

www.soiconsortium.org, 2009.

[12] D. Bol: “Pushing ultra-low-power digital circuits into the nanometer era”, Ph.D thesis, Université

catholique de Louvain, 2008.

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