ultra wide voltage range consideration of reliability-aware stt...
TRANSCRIPT
Microelectronics Reliability xxx (2015) xxx–xxx
MR-11572; No of Pages 5
Contents lists available at ScienceDirect
Microelectronics Reliability
j ourna l homepage: www.e lsev ie r .com/ locate /mr
Introductory invited paper
Ultra wide voltage range consideration of reliability-aware STT magnetic flip-flop in28 nm FDSOI technology
H. Cai a,⁎, Y. Wang a, L.A.B. Naviner a, W.S. Zhao b,c
a Institut Mines-Télécom, Télécom ParisTech, LTCI-CNRS-UMR 5141, 46 rue Barrault, 75013 Paris, Franceb IEF L'Institut d'Électronique Fondamentale, Univ Paris-Sud, CNRS 8622, 91405 Orsay, Francec School of Electronics and Information, Beihang University, Beijing, China
⁎ Corresponding author.E-mail address: [email protected] (H. Cai).
http://dx.doi.org/10.1016/j.microrel.2015.06.0230026-2714/© 2015 Elsevier Ltd. All rights reserved.
Please cite this article as: H. Cai, et al., Ultrtechnology, Microelectronics Reliability (201
a b s t r a c t
a r t i c l e i n f oArticle history:Received 25 May 2015Received in revised form 19 June 2015Accepted 20 June 2015Available online xxxx
Keywords:Magnetic tunnel junctionSTT-MFFReliabilityFDSOIUltra wide voltage range
We investigate stochastic and deterministic reliability problems in the hybrid magnetic tunnel junction (MTJ)/MOS circuit which is implemented with ultra thin body and buried oxide (UTBB) fully depleted silicon-on-insulator (FDSOI) technology. A spin torque transfer (STT) magnetic flip-flop (MFF) is designed with ultrawide voltage range,with 0.5 V to 1.2 V sense/read voltage, and 0.95V to 2Vwriting voltage, by using an industrial28 nm design kit and a physics-based STT-MTJ compact model. MFF performance can be improved with forwardbody bias (FBB) technology. The reliability-aware study shows that variability induced read/write failure ismoredominant comparedwith aging induced degradation. Reliability-aware design of STT-MFF is discussed by properselection of operation voltage.
© 2015 Elsevier Ltd. All rights reserved.
1. Introduction
Magneto-electronics or spintronics based non-volatile memorieshave been well-developed based on the spin-torque effect. Among thethree methods to switch magnetic tunnel junction (MTJ): field inducedmagnetization switching (FIMS), thermally assisted switching (TAS)and spin torque transfer (STT), STT-MTJ based circuit has low switchingcurrent and fast writing access, which features high power efficiency,speed and infinite endurance [1].
Non-volatile MRAM has been implemented with different supplyvoltages (Vdd is from 0.4 V to 2 V) [2–5]. Ultra thin body and buriedoxide (UTBB) fully depleted silicon-on-insulator (FDSOI) technologyhas been proposed and validated in low power circuit design [6]. Tran-sistors with flexible forward/reverse body bias (FBB/RBB) can bringpower–speed improvement. On the other hand, ultra wide operationvoltage range can be achieved to enhance overall performance.
Previous reliability studies of STT-MTJ circuits (mainly designedwith bulk-CMOS technology) focus on variability induced performancefluctuation or functional failure [7,8]. Aging mechanisms, such as hotcarrier injection (HCI), negative bias temperature instability (NBTI)and time dependent dielectric breakdown (TDDB) can significantly de-grade the performance parameters of integrated circuits [9,10]. Further-more, aging mechanisms remain and even become worse in high-kmetal-gate (HKMG) transistors in advanced nanometer CMOS nodes
a wide voltage range consid5), http://dx.doi.org/10.1016
[11]. Since the thin layer of SiO2 has been maintained in between thesubstrate and the high-k stack, whereas the substrate/dielectric inter-face did not change, NBTI and HCI are still the critical problems inHKMG technologies.
For STT-MTJ circuits implemented with FDSOI technology, neitherdeterministic reliability issues nor stochastic variability has beendiscussed before. The remainder of this paper is organized as follows.Section 2 describes different reliability issues. In Section 3, a 28 nmSTT-MFF (magnetic flip-flop)with ultrawide voltage range is proposed.Its nominal performances are simulated with full operation range (sup-ply voltage). Reliability-aware consideration of this circuit is presentedin Section 4. Finally, the conclusion is drawn in Section 5.
2. Reliability issues
Scaling-down of technology improves hybrid MTJ/CMOS circuit per-formance (e.g., area, speed and power consumption). However, the hy-brid circuits should meet reliability challenges including deterministicdegradations for active devices (transistors) and stochastic effects forboth passive and active devices. Reviewing the research of aging phe-nomena in CMOS technology, the main aging effects of deep submicronCMOS transistor include NBTI, HCI and TDDB [9,10]. NBTI and HCI cancause the generation of the interface traps which result in transistor pa-rameters shift over time (e.g., threshold voltage (Vth)). The time depen-dence of Vth degradation can be represented by thepower lawequation:ΔVth = Atn [12].
eration of reliability-aware STT magnetic flip-flop in 28 nm FDSOI/j.microrel.2015.06.023
Fig. 1. An equivalent transistor SPICE model for aging mechanisms (HCI, NBTI, TDDB).
2 H. Cai et al. / Microelectronics Reliability xxx (2015) xxx–xxx
An equivalent transistor SPICE model (see Fig. 1) for aging estima-tion is presented in [13]. For HCI and NBTI effects, parameter degrada-tion is modeled as Vth, mobility and output conductance degradation(ΔVth, ΔIu and ΔIg0 respectively). For TDDB phenomena, the traditionalOhmic model can build a current leakage path between transistor gateand source or drain diffusion. RGD and RGS are setup as variable resistorswhich can be used to represent soft-breakdown (SBD), which caninduce parametric variations but not functional failure [14].
When the dielectric breakdown (hard-breakdown) occurs at MTJoxide barrier, the lifetime for MTJ around 1 nm thick barrier can be es-timated to 10 years (at 400 mV operating voltage) [8]. For TDDB inFDSOI transistors, the breakdown voltage is as high as 2.4 V [15]. Thus,we focus on HCI and NBTI induced Vth degradation in this work.
Although the fabrication techniques have been greatly developed,parametric process variations can still shift circuit performance, whichmay cause functional failure. The variations mainly exist in lot-to-lot,wafer-to-wafer, die-to-die, as well as intra-die variation (within a die)[16]. From the view of IC designers, parametric process variations are in-duced by different physical independent phenomena. The variabilitysource in FDSOI transistor includes gate line-edge roughness (LER), ran-dom dopant fluctuations (RDFs) and metal gate granularity (MGG).These variations can be represented by a deviation in the parametermean of the designed circuit. Moreover, circuit functional failure canbe caused by stochastic process variations.
Fig. 2 shows the randomfluctuation of the relatively small number ofdopants and their discretemicroscopic arrangement in the channel. RDFleads to significant variations in the threshold voltage. Transistors canhave mutually independent Vth variation with respect to each other,regardless of their spatial location.
On the other hand, as an essential building block in STT-MFF, MTJsuffers intrinsically stochastic degradation due to the thermal fluctua-tions of magnetization. Due to the deviations of oxide barrier thickness(tox), free layer thickness (tsl) and tunnel magnetoresistance (TMR)ratio, MTJ switching errors occur with high probability. Indeed, writing
Fig. 2. A general view of line edge roughness and random dopant fluctuations.
Please cite this article as: H. Cai, et al., Ultra wide voltage range considtechnology, Microelectronics Reliability (2015), http://dx.doi.org/10.1016
operation fails to store data and sensing operation may erroneouslycause unexpected switching. This produces circuit functional failurewhich can influence negatively the reliability of CMOS/MTJ circuits.
3. STT-MFF with ultra wide voltage range — nominal simulation
Firstly we review the basic structure of STT-MTJ. It is an oxide barrier(MgO) sandwiched by two ferromagnetic layers (CoFeB) (see Fig. 3)[17]. Owing to the TMR effect, the MTJ resistance (Rp or Rap) is deter-mined by the corresponding magnetization orientation of the two FMlayers: parallel (P) or anti-parallel (AP). The state ofMTJ can be changedto opposite by using the Spin-Transfer Torque phenomenon. The highTMR ratio= (Rap-Rp)/Rp (e.g., N600% at room temperature [18]) allowsits easy integration into traditional MOS circuits [19].
Previous low power MFFs are designed by cascading two comple-mentary latches [2–5]. In order to enhance MFF latency and reliability,we propose a modified MFF architecture with sense amplifier basedflip-flop (SAFF) [20][21]. Fig. 4 illustrates the schematic view of the pro-posed STT-MFF. It consists of a differential write block, a sense amplifieras an input stage, a latch stage and the feedback circuit which is used tostore non-volatile data. The advantages of this architecture include:1) sensing amplifier strengthens weak input signals and latch them tosupply voltage. 2) The symmetrical structure provides equal out delayfor both true and complementary outputs. 3) Forward body biasFDSOI transistors can benefit both fast operations and low powerconsumption.
In normal flip-flopmode, signal FFen (flip-flop enable) is high.Whenclock makes a rising transition, the pre-charged sense-amplifier is usedto sample the complementary input data.
The operation principle of the STT-MFF non-volatilememory (NVM)mode contains non-volatile data writing, standby and data sensing. Thewriting mode is executed when clock signal is low, write enable wrenis high and FFen (Flip-flop enable) is low. In order to enhance write cur-rent to ensure data storing operation, the transistor W/L ratios (transis-tor M25–M28) are significantly increased, e.g., the W/L of M25 equals to500 nm/30 nm. Previous data stored in cross-coupled inverters can bestored into MTJs. In order to successfully save the data, a minimum of40 μA write current is required. The sensing mode executes after STT-MFF standby mode. The SA circuit is multiplexed to reload non-volatiledata in MTJs. SEen switches on M5 and M6 to read the data stored inMTJs.M3 and M4 are off to avoid sensing input data.
A SPICE compactmodel of STT-MTJ [7] is used,which integrates bothstatic and dynamic behaviors of STT-MTJ. The proposed circuit has beendesigned with a 28 nm UTBB FDSOI process. Functional simulations areperformed with Spectre simulator in Cadence analog design environ-ment (ADE), Fig. 5 shows thewaveform of simulated STT-MFF. The sim-ulated nominal performance parameters are presented in Table 1.
In order to minimize circuit area, minimum transistor length(30 nm) is used in this design.With 2 V forward body bias, MFF latencyis improved with 15.3%. A tradeoff exists at active power (12%). FBBbrings on extended operation range of FDSOI circuits. Furthermore, we
Fig. 3. The structure of STT-MTJ,MTJ is composed of three layers: two ferromagnetic layerssandwiched by a tunnel barrier layer [17].
eration of reliability-aware STT magnetic flip-flop in 28 nm FDSOI/j.microrel.2015.06.023
Fig. 4. The schematic view of STT-MFF. It is composed by a write block (transistor M25–M28), a sense amplifier as an input stage, a two-NAND based latch stage and the feedback circuit.
3H. Cai et al. / Microelectronics Reliability xxx (2015) xxx–xxx
study the full operation voltage range of designed STT-MFF. LowVt tran-sistors (LVT) using n-well below nMOSFET and p-well below pMOSFETdevices are used in this design, which significantly extend low voltagerange. Fig. 6 shows the simulation results: where write operation volt-age can be setup between 0.95 V and 2 V, and sensing circuit can be op-erated between0.45V and 1.2 V. An ultrawide voltage range is achievedin the designed STT-MFF.
From Fig. 6, we find that MTJ circuits' write energy (~pJ level) ishigher than read energy (~fJ level). Thus, low power design of STT-
Fig. 5. The nominal functional simulation of STT-MFF. D andQ stand for flip-flop input andoutput. The different operation modes are selected by control signals (FF_en, we_en andSE_en).
Please cite this article as: H. Cai, et al., Ultra wide voltage range considtechnology, Microelectronics Reliability (2015), http://dx.doi.org/10.1016
MTJ sensing circuits cannot significantly reduce the total powerconsumption.
4. Reliability analysis of STT-MFF
As illustrated in Section 3, the proposed ultra wide voltage rangeSTT-MFF achieves attractive performance. However, deterministic effectsand stochastic effects impact performance parameters, sometimes causecircuit functional failure. In this section, HCI, NBTI and parametric pro-cess variations in STT-MFF are studied.
4.1. Full range stochastic effect failure
The parametric process variations of transistors and MTJ devices, aswell as the stochastic behaviors of MTJ are evaluated by Cadence ADE-XL, with 500 runs Monte-Carlo methods. The simulation is performedwith 100 MHz clock (10 ns write duration). The stochastic effects oftransistors and MTJs are included.
Fig. 7 shows the failure probability for both writing and reading op-erations. Failure probability of MTJ writing error is high around thethreshold switching condition (minimum40 μAwrite current),whereasthe failure probability of read error is dominant at low supply voltage of
Table 1The simulated nominal performances of designed MFF, under 1 V supply voltage (bothsensing and write voltages are 1 V) and 100 MHz clock frequency. FBB technology canenhance MFF latency performance with power tradeoff.
No body bias Forward body bias
Output latency (ps) 53.4 45.2Clock-Q delay (ps) 59 50.1Active power (μW) 11.35 12.71
eration of reliability-aware STT magnetic flip-flop in 28 nm FDSOI/j.microrel.2015.06.023
0.5
1
1.5 0.8 1 1.2 1.4 1.6 1.8 2
0
100
200
300
400
500
600
MTJ Writing Voltage (V)Sensing Voltage (V)
Clo
ck−
Q L
atec
ncy
(ps)
50
100
150
200
250
300
350
400
450
500
550
0.4
0.6
0.8
1
1.2
1.4
0.81
1.21.4
1.61.8
2
0
0.5
1
1.5
MTJ Writing Voltage (V)Sensing Voltage (V)
Wri
te E
nerg
y (p
J)
0.4
0.6
0.8
1
1.2
1.4
0.4
0.6
0.8
1
1.2
1.4
0.81
1.21.4
1.61.8
2
0
1
2
3
MTJ Writing VoltageSensing Voltage (V)
Rea
d E
nerg
y (f
J)
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
a
b
c
Fig. 6.MFF performancewith full voltage range. a. Clock to output latency. b.Write energyconsumption. c. Read/sensing energy consumption.
0.40.6
0.81
1.21.4
0.81
1.21.4
1.61.8
2
−0.2
0
0.2
0.4
0.6
0.8
1
1.2
MTJ Writing Voltage (V)
Sensing failure probabiity
Sensing Voltage (V)
Failu
re P
roba
bilit
y
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0.40.6
0.81
1.21.4
0.81
1.21.4
1.61.8
2
−0.2
0
0.2
0.4
0.6
0.8
1
1.2
MTJ Writing Voltage (V)
Writing error probability
Sensing Voltage (V)
Failu
re P
roba
bilit
y
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
a
b
Fig. 7. The failure probability distributionwith different sensing andwriting voltages (MTJread/sensing failure and MTJ writing error). a. The sensing failure probability under fulloperation range investigation. A high writing voltage can ensure low failure probability.b. The writing error probability under full operation range investigation.
37.7
37.8
37.9
38
k−Q
late
ncy
(ps) NBTI
HCI
4 H. Cai et al. / Microelectronics Reliability xxx (2015) xxx–xxx
sensing circuits. The failure probability increases when sensing voltageis lower than 0.9 V and/or writing voltage is lower than 1.3 V. A reducedsensing voltage cannot save power, whereas leading to increased sens-ing failure probability. On the other hand, small writing voltage can de-crease the current flow throughMTJs. In this design, 40 μAwrite currentis required.
Thus, the functional failure of designed STT-MFF is highly dependentof operation voltage. Reliability should be highlighted when sensingvoltage is lower than 0.9 V and/or writing voltage is lower than 1.3 V.
104
105
106
107
108
37.5
37.6
Aging time (s)
Clo
c
Fig. 8. HCI and NBTI induced performance degradation. Tclk-q is slightly degraded by NBTIand HCI (Ideal Tclk-q = 37.63 ps).
4.2. Deterministic aging effects
Aging simulations are performed based on equivalent transistorSPICE model (see Fig. 1). It was experienced that both HCI and NBTIare strongly dependent on Vg.We choose theworst condition of transis-tor biasing,with Vdd-read=1.2 V andVdd-write=2V. Fig. 8 showsMRAMperformance clock-to-output delay (Tclk-q) due to Vth shift. Considering
Please cite this article as: H. Cai, et al., Ultra wide voltage range consideration of reliability-aware STT magnetic flip-flop in 28 nm FDSOItechnology, Microelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.06.023
5H. Cai et al. / Microelectronics Reliability xxx (2015) xxx–xxx
NBTI induced degradation,MRAM latency is not sensitive to NBTImech-anism due to the small Vth degradation (~10 mV@108 s aging node).
The worst case degradation of the HCI occurs when transistor drainand gate transistor voltages are identical Vg = Vd. Transistor M7 andM8 are in the worst case of HCI degradation. From Fig. 7, it can benoticed that HCI induced additional latency is obvious from 106 s. HCIinduced Tclk-q degradation is only 0.6% at 108 s aging node.
The degradations in other operation voltage are lower than thisworst case. In this design, aging induced degradation can be well allevi-ated by transistors with forward bias [9,10].
Thus, in the proposed STT-MFF circuits, deterministic aging effects(NBTI and HCI) only induce slight performance degradations, whichare not dominant compared to stochastic variability. Both deterministicaging effects and stochastic variability can be alleviated by carefuldesign of STT-MFF.
5. Conclusion
Variability-aware and aging-aware analysis of STT-MRAM has beenperformed in this paper. 28 nm FDSOI devices achieve speed boost inultra wide voltage range performance of STT-MFF. We find that lowpower design of STT-MTJ sensing circuits cannot significantly reducethe total power consumption where writing circuits are dominant. Var-iability induced failure problems aremore dominant compared to aginginduced degradation. The failure probability of STT-MFF is highlydependent of operation condition. Reliability-aware design of STT-MFFis discussed by proper selection of supply voltage.
Acknowledgments
This work is supported by a public grant overseen by the French Na-tional Research Agency (ANR) as part of the Investissement d'Avenirprogram, through the ANCD2, project funded by the IDEX Paris-Saclay,ANR-11-IDEX-0003-02.
References
[1] C. Chappert, A. Fert, F.N. Van Dau, The emergence of spin electronics in data storage,Nat. Mater. 6 (2007) 813–823.
Please cite this article as: H. Cai, et al., Ultra wide voltage range considtechnology, Microelectronics Reliability (2015), http://dx.doi.org/10.1016
[2] K. Ryu, et al., A magnetic tunnel junction based zero standby leakage current reten-tion flip-flop, IEEE Trans. VLSI 20 (11) (2012) 2044–2053.
[3] D. Chabi, et al., Ultra low power magnetic flip-flop based on checkpointing/powergating and self-enable mechanisms, IEEE Trans. CAS-I 60 (6) (2014) 1755–1765.
[4] W.S. Zhao, et al., Design considerations and strategies for high-reliable STT-MRAM,Microelectron. Reliab. 51 (2011) 1454–1458.
[5] Kazi, et al., A ReRAM-based non-volatile flip-flop with sub-VT read and CMOSvoltage-compatible write, Proc in IEEE NEWCAS 2013, pp. 1–4.
[6] T. Skotnicki, et al., Innovative materials, devices, and CMOS technologies for low-power mobile multimedia, IEEE Trans. Electron Devices 55 (1) (2008) 96–130.
[7] W.S. Zhao, et al., Failure and reliability analysis of STT-MRAM, Microelectron. Reliab.52 (2012) 1848–1852.
[8] Y. Wang, et al., Compact model of magnetic tunnel junction with stochastic spintransfer torque switching for reliability analyses, Microelectron. Reliab. 54 (2014)1774–1778.
[9] H. Cai, et al., Reliability aware design of low power continuous-time sigma-deltamodulator, Microelectron. Reliab. 51 (2011) 1449–1453.
[10] H. Cai, et al., Cross-layer investigation of continuous-time sigma-delta modulatorunder aging effects, Microelectron. Reliab. 55 (2015) 645–653.
[11] E. Maricau, et al., Analog circuit reliability in sub-32 nanometer CMOS: analysis andmitigation, Proc in DATE 2011, pp. 1–6.
[12] T. Ishigaki, et al., Effects of device structure and back biasing on HCI and NBTI insilicon-on-thin-BOX (SOTB) CMOSFET, IEEE Trans. Electron Devices 58 (4) (2011)1197–1204.
[13] E. Maricau, G. Gielen, Computer-aided analog circuit design for reliability in nano-meter CMOS, IEEE Trans. Emerg. Sel. Top. Circ. Syst. 1 (1) (2011) 50–58.
[14] H.Wang, et al., Impact of random soft oxide breakdown on SRAM energy/delay drift,IEEE Trans. Device Mater. Reliab. 7 (4) (2007) 581–591.
[15] X. Federspiel, et al., 28 nm node bulk vs FDSOI reliability comparison, Proc in IEEEIPRS, 2012 (3B.1.1–3B.1.4).
[16] H. Cai, et al., A hierarchical reliability simulation methodology for AMS integratedcircuits and systems, J. Low Power Electron. 8 (5) (2012) 697–705.
[17] M. Julliere, et al., Tunneling between ferromagnetic films, Phys. Lett. A 54 (3) (1975)225–226.
[18] S. Ikeda, et al., Tunnel magnetoresistance of 604% at 300 k by suppression of ta dif-fusion in CoFeBMgOCoFeB pseudospin-valves annealed at high temperature, Appl.Phys. Lett. 93 (8) (2008) (082508-082508-3).
[19] Y. Zhang, et al., Compact modeling of perpendicular-anisotropy CoFeB/MgO mag-netic tunnel junctions, IEEE Trans. Electron Devices 59 (3) (2012) 819–826.
[20] D. Markovic, et al., Analysis and design of low energy flip-flops, Proc in ISLPED 2001,pp. 52–55.
[21] H. Cai, et al., Multiplexing Sense Amplifier Based Magnetic Flip-Flop in 28nm FDSOITechnology, Nanotechnology, IEEE Transactions on 99 (2012)http://dx.doi.org/10.1109/TNANO.2015.2438017 vol.PP, no.99, pp.1.
eration of reliability-aware STT magnetic flip-flop in 28 nm FDSOI/j.microrel.2015.06.023