Microelectronics Reliability xxx (2015) xxx–xxx

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Microelectronics Reliability

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Introductory invited paper

Impact of PVT variability on 20 nm FinFET standard cells

A.L. Zimpeck a,⁎, C. Meinhardt b, R.A.L. Reis a

a Instituto de Informática, Graduate Program in Computer Science (PPGC), Federal University of Rio Grande do Sul, Bento Gonçalves Av. 9500, Porto Alegre, RS, 91501970, Brazilb Center for Computational Science (C3), Group of Digital Systems and Embedded (GSDE), Federal University of Rio Grande, Av. Itália km8, Rio Grande, RS, 96203900, Brazil

⁎ Corresponding author.E-mail address: alzimpeck@inf.ufrgs.br (A.L. Zimpeck)

http://dx.doi.org/10.1016/j.microrel.2015.06.0390026-2714/© 2015 Elsevier Ltd. All rights reserved.

Please cite this article as: A.L. Zimpeck, et ahttp://dx.doi.org/10.1016/j.microrel.2015.

a b s t r a c t

a r t i c l e i n f o

Article history:Received 25 May 2015Received in revised form 20 June 2015Accepted 21 June 2015Available online xxxx

Keywords:Standard cellFinFET devicesProcess variabilityPVT analysisMicroelectronics

FinFET technology is pointed as the main candidate to replace CMOS bulk process in sub-22 nm circuits. Predic-tive technology and design exploration help to understand significant effects of variability sources and theirimpact on circuit performance and power consumption. This paper evaluates the impact of process, voltageand temperature (PVT) variations on timing and total power of predictive standard cells in 20 nm FinFETstechnology node. Results emphasize that standard cell designs in future technologies have to take into accountPVT variability in the early steps of the design.

© 2015 Elsevier Ltd. All rights reserved.

1. Introduction

The scaling down of new nanotechnologies adopted in the integrat-ed circuits design brought new challenges, as aging effects, increase inleakage currents and soft errors [1]. Multi-gate devices are pointed asthe main candidate to replace CMOS bulk process in sub-22 nm circuits[2], since these devices provide better short-channel effects (SCE)control, lower leakage and better yield [3].

Among different multi-gate device structures, FinFET (Fin-ShapedField Effect Transistor) technology stands out because of the perfectisolation and high driving capability both for high-speed and lowpower applications. However, there is a number of scaling challengesto FinFET technology [3], as process, voltage and temperature (PVT)variations. Due to PVT variability, each circuit may present a differentbehaviour, as high deviation on performance and abnormal powerconsumption. Also, it can accelerate circuit degradation and make thecircuit inappropriate for its initial purpose [4].

The main objective of this work is to provide a predictive evaluationof PVT variation impact on a subset of circuits using a commercial stan-dard cell at 20 nm FinFET technology. These evaluations help to predictthe influence of PVT variations in future technology nodes and identify-ing relevant behavioural standards with respect to the use of FinFETtechnology in digital designs, highlighting the need to consider allelectrical characteristics in the development of IC Designs and EDAtools for FinFET technology.

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l., Impact of PVT variability o06.039

The paper is organized as follows. Section 2 introduces the conceptsof process, voltage and temperature variability. Section 3 resumes someFinFET properties. The experimental setup is discussed in Section 4.Section 5 presents a description of PVT analysis results and discussions.Finally, conclusions are presented in Section 6.

2. PVT variability

Process variations are caused, in the majority of the cases, duringthe lithography step of the fabrication process. The variability can bedivided into three factors: environment factors, reliability factors andphysical factors [5].

Environment factors appear during the operation of a circuit. Powersupply and temperature oscillations are examples of environmentfactors. Reliability factors are related to aging of the transistor, due thehigh electrical fields presented in modern circuits. NBTI (Negative BiasTemperature Instability) and Electromigration are classical problemsin the reliability area [6–8]. Finally, the physical factors are associatedto variations in geometrical and electrical parameters, which induce alag in transistor performance.

Voltage is usually associated with the system power consumption.However, the system performance is also affected by the supply voltagedeviations. It occurs because transistor saturation current depends onthe power supply and the gate delay is dependent on the saturationcurrent. This relation is exponential for a wide voltage range. Moreover,devices and interconnections may have performance and power con-sumption affected due to temperature dependence [9]. Temperature

n 20 nm FinFET standard cells, Microelectronics Reliability (2015),

Fig. 2.Metal gate fabrication ideal and real aspects [16].

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variations across communicating blocks on a same chip may causeperformance mismatches, logic or functional failures [10].

3. FinFET background

FinFET is a double-gate device in which the technology consists ofvertical silicon fins to form the channel region and to connect the sourceand drain regions at each end [1]. The gate region is wrapped aroundthis vertical fin. MOS channels are formed at the two sidewalls plustopside of the fin. This fin-like geometry, where the depletion regionsreach from the gates entirely into the body region, implies that no freecharge carriers are available, making the suppression of SCE possiblein FinFETs [2].

Fig. 1 presents FinFET key geometric parameters [11]: gate length(LG), fin height (HFIN) and fin thickness (TSI). Fin engineering (balancingheight, fin thickness, oxide thickness and channel length) is essential tominimize the leakage current (IOFF) and maximize the “on” current(ION) [1].

There is a number of scaling challenges to FinFET technology, such asgeometric variability, mitigation of random dopant fluctuation (RDF),fringe capacitance to contact/facet, low-k spacer, fin and gate fidelity(patterning and etch), conformal coverage in gate wrap-around devices(Vt tuning), chemical–mechanical planarization (CMP) polish chal-lenges and contact resistances [3]. Themain expected sources of processvariability for sub-22 nm FinFETs are the gate length (LG), fin height(HFIN), fin thickness (TSI) and metal gate workfunction fluctuation(WFF) [3–5]. A previous study highlights the WFF as the main factorto impact the FinFET device currents on sub-20 nm devices [13].

Wang [14] highlights the high correlation between the variability inION and IOFF currents and threshold voltagefluctuation in the presence ofgranularity of the metal gate (MGG). WFF is caused by the dependencyof metal workfunction on the orientation of its grains, as depicted inFig. 2. In the ideal fabrication process, metal gate devices have thegates producedwithmetal uniformly aligned and very lowerWFF devi-ation. Nevertheless, in real manufacturing process, metal gate devicesare generally produced with metals with different workfunctions(Φm) randomly aligned which causes higher WF variation.

Among the main works in the recent years regarding FinFET stan-dard cells, due to the relevance of the contribution, it is important toemphasize the following works: an analysis of the layout presented in[1], a methodology to estimate the leakage proposed in [11], an investi-gation about optimization for performance and manufacturability from[17] and one methodology proposed to find optimal sizing of basiccircuit blocks considering process variation [15]. However, in [15],workfunction fluctuation (WFF) impact is not considered as one process

Fig. 1. Structure and geometric parameters of FinFETs [12].

Please cite this article as: A.L. Zimpeck, et al., Impact of PVT variability ohttp://dx.doi.org/10.1016/j.microrel.2015.06.039

variation source. At themoment, to the best of our knowledge, no inves-tigation covers the impact of WFF in process, voltage and temperature(PVT) evaluation of standard cells.

4. PVT variability investigation

In order to analyse the impact of PVT variability this work considersa subset of circuits that represents the 1-to-4-input combinational cellsmost frequently available in traditional commercial standard celllibraries in NanoCMOS. As vendor tools for standard cells using FinFETare not yet available, this experiment generates a predictive librarywhere all cells were adapted to the 20 nm FinFET technology node,respecting the aspects ratio of the commercial library in 45 nm.

The predictive evaluation adopts the 20 nm high performance (HP)application version from PTM–MG [18,20]. This model allows us to con-sider predictive models for fully depleted SOI FinFETs. The nominalvalues of the main parameter devices for 20 nm-HP are presented inTable 1.

This work considers four main sources of variability in FinFET de-vices: gate length (LG), fin height (HFIN), fin width (WFIN) and gateworkfunction fluctuation (WFF). Analyses considering geometric andelectrical variability in these parameters were made in [13] for NFETand PFET devices. Results show that gate length and fin width have animportant deviation impact on ION and IOFF, respectively. However, thelargest deviation impact in both currents is given by WFF, which pro-vokes a considerable deviation in total power that has to be consideredin VLSI designs.

A previous study highlights the impact of process variation in thetiming and power of standard cells [19]. It was proved that WFF hasmore impact on the total power consumption (24% on average) thantiming results (8% on average). It stresses the importance of consideringWFF on current and threshold voltage in the early design steps, mainlyin the EDA tools for automatic layout generation.

Table 120 nm FinFET Device Parameters [20].

Parameter Nominal value

Supply voltage 0.9 VChannel length (LFIN) 24 nmFin height (HFIN) 28 nmFin thickness (TSI) 15 nmOxide thickness (TOX) 1.40 nmChannel doping 5e23 m−3

Source/drain doping 3e26 m−3

Work function of gate (HP NFET) 4.38 eVWork function of gate (HP PFET) 4.80 eVWork function of gate (LSTP NFET) 4.56 eVWork function of gate (LSTP PFET) 4.62 eV

n 20 nm FinFET standard cells, Microelectronics Reliability (2015),

Fig. 3. Nominal PDP results compared with mean values results for the standard cell gates under WFF.

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Metal gate workfunction exhibit a multi-nominal distribution,which can be approximated by a Gaussian distribution if the numberof grains on the surface of metal-gate is high enough (N10). Thus, pro-cess variability was taken through 10,000 Monte Carlo simulationswith workfunction parameter modelled as a Gaussian function with3σ deviation of 5% from nominal values. Supply voltage was variedfrom 0.3 V to 0.9 V and propagation delay for all timing arcs was takenfor each supply value. The temperature was changed from 25 °C to250 °C in intervals of 25 °C for all timing arcs too.

All simulations were carried out using HSPICE. Timing measure-ments consider the average propagation time and total power is thepower consumed during the execution of the timing arcs simulation.The comparison in these experiments was made regarding the PowerDelay Product (PDP).

5. Results

This section presents the results of predictive evaluation of process,voltage and temperature (PVT) variation impact on timing and totalpower that a FinFET device may be subject in their lifetime.

5.1. Process variation

Process variation assumes greater importance with technology scal-ing because integrated circuits become more sensitive to parametricvariations and even small differences introduced in fabrication process,may already be sufficient for change the circuit behaviour [12]. Fig. 3shows a comparison between PDP nominal values and under WFFvariations. Nominal values are used as a form of reference values to

Fig. 4. Voltage variability results for th

Please cite this article as: A.L. Zimpeck, et al., Impact of PVT variability ohttp://dx.doi.org/10.1016/j.microrel.2015.06.039

the variability analysis and PDP under variations refers a mean fromresults of Monte Carlo simulations considering the standard cellsunder workfunction fluctuation (WFF).

The results of the comparison highlights that Full-Adder (FA), AND4and Half-Adder (HA) aremore sensible to variations ofWFF. These cellspresent deviations of 10.33%, 19.76% and 35.36% above the PDP nominalvalues, respectively. On the other hand, the cells less sensible to varia-tions of WFF are INV, NAND2 and AOI21 with deviations of 11.11%,18.57% and 22.44% more than the PDP nominal values, respectively.

5.2. Supply voltage variation

The supply voltage can also vary along lifetime of a circuit due tounbalanced power distribution network, for example. Thereby, thesecond part of this work focus evaluates the impacts that supply voltageoscillation causes in the cells.

For the cells AND3, NOR4, OR4 and FA, the frequency of activitywas reduced to allow the near-threshold operation in the voltageexperiments. Thus, these circuits consume less power at nominal valuesof temperature and voltage, because these cells will remain more timein the static behaviour at high voltages than in the temperatureexperiment.

Fig. 4 shows that timing percentage increase reaches at 0.3 Vcompared to the nominal voltage for all timing arcs of each cell fromthe library. Analysing the results, the cells that present more sensitiveto variations are FA, NOR3 and NAND4 with deviations of 60.79%,26.86% and 25.84%, respectively.

Fig. 5 presents the improvement in timing, total power and PDPmedium values normalized to the nominal values of all cells evaluated

e standard cell gates under WFF.

n 20 nm FinFET standard cells, Microelectronics Reliability (2015),

Fig. 5. Timing, total power and PDP results with voltage variation.

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for a voltage range from 0.9 V to 0.3 V. Standard cells operating at near-threshold voltages presentmore than 60%of PDP reduction, consideringthe voltage range from 0.4 V to 0.3 V. Cells AND4, NAND4 and NOR3can present up to 70% of PDP reduction when operating at 0.3 V. Thereduction of the circuit voltage to 0.3 V implies in a total power decreaseof round of 90%. It also causes a propagation time increase of more thanthree times (334%) considering the mean propagation time.

5.3. Temperature variation

Table 2 shows the PDP temperature impact for all timing arcs of eachcell from the library. For the temperature results, columnΔPDP resumeshow many times (x) the PDP increases when operating at 250 °C com-pared to the nominal temperature operation. The PDP results allow usto see that HA, XOR2, XNOR2, AND4 and MUX2 are more sensitive tothe effects of temperature oscillation. Fig. 6 highlights the cells thatconsumemore power in this set. The Full Adder is the cell that presentsthe largest power consumption at room temperature and the tempera-ture increase makes this cell reaching even higher energy values. It isimportant to note that these cells reach power results in the order ofdozens of μW. AND4 cell shows the larger sensibility to temperatureoscillation, with an increase of 4% for each temperature degree increase.

Table 220 nm FinFET standard cell PDP results under temperature variability. The bold data high-light the cells more sensitive to the effects of temperature oscillation in relation to PDP.

Circuit PDP (aJ)

50 °C 100 °C 150 °C 200 °C 250 °C ΔPDP (x)

AND2 11.6 14.1 24.3 51.1 111 9.5AND3 21.4 25.4 40.1 81.4 183 8.5AND4 26.6 32.4 54.5 123 311 11.7AOI21 6.4 7.6 12 22.4 43.6 6.8AOI211 8.4 10.5 17.5 34 67.5 8AOI22 5.9 7.6 13.2 26.7 53.1 9BUFFER 12.2 13.7 19.5 34 46 3.7INV 6.3 6.7 8.7 14.1 24.8 3.9MUX2 15.8 20.1 35.3 73.2 155 9.8NAND2 7.26 8.47 13.1 24.2 46 6.3NAND3 14.8 17.4 25.3 45.4 85 5.7NAND4 21.6 25.3 38.8 70 137 6.3NOR2 10.8 12.2 17.3 29.5 53.9 4.9NOR3 13.1 15 21 35.5 65.5 5NOR4 23 25.4 33.6 52.2 90.9 3.9OAI21 5 6.2 10.4 21.1 41.3 8.2OAI211 6.6 8.3 15.2 31.6 63.2 9.5OAI22 7 8.8 14.7 29.2 56.9 8.1OR2 12 14.4 23 45.9 96.8 8.1OR3 17.6 21.6 34.3 71.8 161 9.1OR4 29.5 35.5 53.9 107 239 8.1XNOR2 9.2 12.2 22.8 50.2 106 11.5XOR2 8.7 11.8 22.4 48.4 102 11.7FA 42.1 50.9 71.6 118 202 4.8HA 13.1 18.8 39.2 90.1 193 14.7

Please cite this article as: A.L. Zimpeck, et al., Impact of PVT variability ohttp://dx.doi.org/10.1016/j.microrel.2015.06.039

As the temperature was varied, results show that the average timingremains practically constant, with a slight increase when the tempera-ture rises. However, total power consumption is impacted by the tem-perature increase. Variations of temperature between 25 °C and125 °C indicate a small increase in the total power, but at higher temper-atures, the power can increase by around five times the nominal values.

Results show that small variations in the nominal voltages, consider-ing a noisemargin of 0.3V, can cause oscillations of up to 30% increase inthe average propagation time. Regarding the impact on the PDP, thesefluctuations can cause reductions of up to 50% in the PDP. Thus, it ispossible to obtain an intermediate point of operation without reducingperformance and with good outcomes in total power reduction andPDP.

However, it is important to highlight that the temperature of oneblock in an integrated circuit does not depend only on the power con-sumption of the block itself, but also on the temperature of adjacentblocks because of lateral heat transfer [12].

6. Conclusions

This work evaluates the total power and timing impact due to PVTvariations. The analysis of process variation shows that Full-Adders(FA) and Half-Adders (HA) aremore sensitive toWFF variations, havinga bigger PDP deviation from nominal values.

When analysing the voltage variation, AND4, NAND4 andNOR3 cellscan present up to 70% of PDP reduction when operating with a 0.3 volt-age. However, the disadvantage of voltage reduction is the impact ontiming. In these experiments, the voltage reduction provokes a timingincrease of more than three times.

HA, FA, OR3, OR4 and AND4 cells are more sensitive to the effects oftemperature oscillation. Total power consumption is the principal pa-rameter impacted by the temperature increase. In higher temperatures,the power increase can reach results of around five times the nominalvalues.

It is important to highlight that WFF has an enormous impact onIOFF [4,13]. This effect provokes significant deviations on static powerof standard cells. Static power impact is covered in a previous workthat emphasizes that, due to the simple structure, Inverter, NAND2and NOR2 indicate a high sensibility to WFF in relation to staticpower. For cells with similar function, but different number of inputs,it is possible to note a decreasing WFF sensibility as the number ofinputs rise.

Acknowledgments

The authors would like to acknowledge the financial support fromthe CNPq (National Council for Scientific and Technological Develop-ment — Brazil) which provided scholarship for the development ofthis work. We would also acknowledge the support from the PPGC(Programa de Pós Graduação em Computação) and the Instituto deInformática da UFRGS which support the development of this work

n 20 nm FinFET standard cells, Microelectronics Reliability (2015),

Fig. 6. Top 5 cells more sensible to temperature variation.

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and provided the necessary infrastructure, including auxiliary financialsupport.

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