Shunpei YamazakiPresidentSemiconductor Energy Laboratory Co Ltd

May 27 2015

Unique Technology from Japan to the World

mdashSuper Low Power LSI using CAAC-OSmdash

2

Contents

1) What is CAAC-IGZO

2) Can we make FETs by using it (oxide semiconductor)

3) Can we really make FETs as good as Si nMOS FETs by using CAAC-IGZO

4) Can we really make CMOS LSI by using a stacked structure with Si pMOS

5) What is 30-nm (channel length) FETLSI like

6) Do you really think you can catch up with Si VLSI

1 IntroductionndashHistory

3

1-1 History of CAAC-IGZO

1985 N Kimizuka synthesized IGZO for the first time in the world andrevealed its crystal structure1)

1987 Kimizuka proposed the use of IGZO as a semiconductor element2)

1995 J F M Cillessen at Philips proposed an oxide semiconductor (OS) FETincluding IGZO3)

20099 Yamazaki (SEL) discovered CAAC (Jpn Pat No 5211261)20115 SELrsquos NOSRAM4)

20116 SELrsquos image sensor5)

20137 SELrsquos FPGA6)

20139 A paper on 8-bit CPU by SEL7) was selected for SSDM Paper Award from more than 700 papers

20146 A paper on an 8K organic EL display by SEL8) received Distinguished Paper Award at SID Display Week 2014

1) N Kimizuka and T Mohri J Solid State Chem 60 382 (1985)2) Jpn Pat No 16393983) J F M Cillessen et al US Pat No 5744864 (1995)4) T Matsuzaki et al 3rd IEEE Int Memory Workshop pp185‐188 (2011)5) T Aoki et al Symp VLSI Technology Tech pp174‐175 (2011)

6) Y Okamoto et al ECS Trans 54(1) pp 141-149 (2013)7) T Ohmaru et al Ext Abstr Solid States Device and Materials

pp 1144-1145 (2012)8) S Kawashima et al SID Symp Digest 45 pp627-630 (2014)

4

5

1) Single-crystal IGZO was first synthesized in 1985 by Kimizuka (at National Institute for Research in Inorganic Materials) ITO ZnO and other oxide semiconductors have been widely used as conductive transparent oxides (CTOs) They have been studied since the 1980s for use in FETs especially thin-film transistors (TFTs)

2) SEL discovered a new crystal structure (CAAC-IGZO) in 2009 It is neither single-crystal nor amorphous CAAC-IGZO is characterized by no clear grain boundary being observedWe succeeded in paving the way for its first VLSI applicationby thoroughly seeking details as done for semiconductors We consider a c-axis-aligned a-b-plane-anchored crystal (CAAC)structure as a new crystal structure

1-2 Materials and Application (Device LSI System)

CAAC-IGZO has been comprehensively examined from the aspects of devices and application as well as materials

Device Process PropertiesFeatures

Material Defect control Thin-film formation Structure Film quality evaluation

Device Element structure examination

Process developmentCompatibility with existing Si LSI Device properties

Application

LSI

Combination of OSpassive element

Smaller F2

Challenge to scaling

OSSi hybrid3D structure

Development of process at le500C (400C)

Solution for scaling-related problems

System

IoT8K TV

Cell phone

Compatibility with interfaces of other systems by communication

means etc

Larger sizeShorter process

Logic circuit Super low power

6

2 What kind of crystal morphology does CAAC have

7

Discovered by SEL mass produced by Sharp

3 nm 3 nm

single crystalsingle crystal nano-crystalCAAC amorphous-like amorphous

Thickness 50 nm

CAAC nanocrystal

Classification of Oxide Semiconductor Materials

Thickness 50 nm

c-ax

is

Crystal structure of IGZO

88

2)

1) K Nomura T Kamiya H Ohta T Uruga M Hirano and H Hosono

Phys Rev B 75 035212 (2007) 2) Y Kurosawa et al

JSAP Autumn Meeting 2014 18p-A12-2

The simulation model of ldquoamorphous IGZO1)rdquo by Melt quench method

copyThe Japan Society of Applied Physics 2014

amorphous structure

Characteristics of CAAC-IGZO Film

Derived from quartz substrate

E-beam is incident parallel to the substrate surface

E-beam is incident perpendicularto the substrate surface

Rotation within (110) plane

Sample structure

electron diffraction (a-b plane)

X-ray diffraction (c-axis)

electron diffraction (c-axis)c-axis

a

b

Clear orientationNo orientation

Clearorientation

No orientation

CAAC c-axis-aligned a-b-plane-anchored crystalCAAC c-axis-aligned a-b-plane-anchored crystal

X-ray diffraction (a-b plane)

9

(d) CAAC crystal pellet (e) Cross-sectional image of unit pelletIn Ga or Zn O

(Chip)

Substrate

Cross-sectional TEM of CAAC-IGZO Film

08 nm

3 nm

(a) (b)TEM imageHR-TEM imageDetail of area in (a)

IGZO Film

Substrate

50 nm

10

平面TEM高分解能像FFT image processing-Extract data on a certain wavenumber range

Processing using an original program

Plan‐view TEM Crystal Lattice Image

FFT Filtered Image(FFTFast FourierTransform)

Lattice Extraction Image

Hexagonal Lattice Orientation Analysis amp

Color Mapping

Perfect regular hexagon

Neighboring lattice points(6 points)

Reference lattice point

1) Determine the orientation of a perfect regular hexagon so as to minimize the sum of the distances from the vertices of the perfect regular hexagon to six points neighboring a reference lattice point

Average distance a the average of distances from the reference lattice point to its neighboring six lattice points

2) Color each lattice point after the step 1) according to the difference from a reference angle In this study the modal angle was set to 30

6050403020100

ex

θ x

Average distance a

0 le θ lt 60

orientations of hexagons [degree]

Analysis Procedure Hexagonal LatticeOrientation Analysis amp Color Mapping

Processing using an original program

11

(a) A plan-view TEM image (b) A color mapping image obtained from an FFT filtered image of (a) The orientations of the hexagons are sorted by the angle (0minus60) and shown in different colors The colors of the adjoining grains are adjacent colors on the color scale

10 nm

(3)

(4)

(1)(2)

(a)

Plan-view Observations of CAAC-IGZO Film

(b)orientations of hexagons [degree]

60

50

40

30

20

10

0

12

(d)(a) (b) (c)

(d)(a) (c)(b)

(1)

(2)

Observations in Grain

Magnifying observations in a grain with a size of several tens of nanometers at the atomic level(a) Plan-view TEM images (b)(c) FFT filtered images (d) Color mapping imagesDotted lines denote boundaries between pellets Solid lines show a hexagon formed with lattice points

plan-view FFT filtered images color mapping

60

50

40

30

20

10

0

orientations of hexagons [degree]

Pellet

Hexagon formed with lattice points

Reg

ions

cor

resp

ondi

ng to

thos

e in

the

plan

-vie

w T

EM

imag

e of

the

wid

e ar

ea

13

In Ga or Zn O

066 nm

038 nm

ｚｚ

Side view of a unit cell

198 nm

181 nm

Surface of a unit cellHexagon formed with lattice points

07 nm

(Ga Zn)O

(Ga Zn)O

InO2

Homologous crystal structure

CAAC-OS pellet unit cellSemi hard material (a flexible crystal structure) by oxygen as a cushion between In Ga and Zn

Oxygen

Oxygen

14

Magnifying observations in a boundary portion between grains with a size of several tens of nanometers at the atomic level(a) Plan-view TEM images (b)(c) FFT filtered images (d) Color mapping imagesDeformed hexagons pentagons and heptagons are formed with lattice points at the boundary denoted by a dotted line and they are anchored to each other

Observations in Boundary Portion between Grains

60

50

40

30

20

10

0

orientations of hexagons [degree]

Boundary(3

)(4

)

plan-view FFT filtered images color mapping

(d)

(d)

(a)

(a) (c)

(b)

(b)

(c)R

egio

ns c

orre

spon

ding

to th

ose

in th

e pl

an-v

iew

TE

M im

age

of th

e w

ide

area

15

(a) and (c) Distribution of number of Voronoi polygons in single crystal IGZO and CAAC-IGZO (b) and (d) Distribution of Voronoi hexagons (yellow regions) and other polygons (blue regions) in the single crystal IGZO and the CAAC-IGZO

Distribution of Number of Voronoi Polygons

In the single crystal IGZO hexagonal Voronoi regions occupy almost the entire field of view In the CAAC-IGZO hexagons are the majority but pentagons and heptagons also appear

Single crystal IGZO CAAC-IGZOSingle crystal IGZO film [] CAAC-IGZO film []

Tetragon 01 07

Pentagon 12 155

Hexagon 982 683

Heptagon 04 145

Octagon 02 09

Nonagon 00 00

16

2 3 4 51

5 nmminus1

5 nmminus1

minus231degminus84degminus75 deg minus310degminus246deg

+118deg +15deg +135deg +04deg minus55deg2 3 4 51

(a)1 2 34 5

20 nm

(b) 12

3

4

5 20 nm

Panel (a) shows the points along the surface of the CAAC-IGZO film that were probed by NBED and the five remaining panels in the top row show the corresponding NBED patterns Panel (b) shows the points probed by NBED in the thickness of the film and the five remaining panels in the lower row show the corresponding NBED patterns The angle of the crystal axis is slightly shifted in both the surface and thickness directions

Nanobeam Electron Diffraction (NBED 1 nmɸ) Patterns of CAAC-IGZO Film

17

Nanobeam Electron Diffraction (NBED 1 nmɸ) Patterns of CAAC-IGZO Film

Broadanisotropic diffraction spots

Sharpcircular diffraction spots

The electron diffraction pattern of single-crystal IGZO has circular spots as shown in (b) Diffraction spots of CAAC-IGZO are not circular but anisotropic and broad

18

Schematic Band Diagram of IGZOSimple schematic diagram of defect levels in IGZO film

elec

tron

ener

gy [e

V]

surface shallow DOS(sDOS)

bulk shallow DOS(sDOS)

bulk deep DOS(dDOS)

Density of States (DOS) of IGZO

19

28-32 eV

Silicon oxide IGZO

CAAC-IGZO63 (gcm3)

nc-IGZO61 (gcm3)

a-like IGZO59 (gcm3)

αCPM Absorption coefficient estimated by a constant photocurrent method (CPM)

N Ishihara et al Proc AM-FPD12 143 (2012)J Koezuka et al SID2013 Symposium Digest 723 (2013)

A high density of deep-level states (dDOS) exists in the low-density IGZO filmThe higher the film density is (like CAAC) the lower the dDOS is

Light absorptions by IGZO films with different crystal structureswere measured to quantify the densities of deep energy trapstates (dDOS)

Density of States (DOS) of IGZO

a-like IGZO 53 times 100

20

Formation of Oxygen Vacancies (VO) in IGZO

software VASP

exchange correlation function

GGA

pseudo potential PAW

cut-off energy 800 eV

k-point 1times1times1VO are

likely to be formed

Crystal Amorphous

In Ga Zn O

-1180

-1178

-1176

-1174

-1172

-15 -10 -5 0 5 10 15

Tota

l Ene

rgy

[eV]

Distance from Interface [Aring]

InterfaceInterface

VO are highly likely to be formed

A comparison of formation of oxygen vacancies (VO) between amorphous and crystal structures was made by first-principles calculation The results indicate that VO are easily formed in the amorphous structure

21

Features of CAAC-IGZO as MaterialCAAC-IGZO c-Si

1)CAAC structure (not single-crystal nano-crystalline or amorphous)rarr No clear grain boundary is observed

lattice points to form a pentagon and heptagon

Single crystal is preferable because polycrystal has a high concentration of defects at grain boundaries2)

Crystal grains (pellets) are anchored to each other to form one big crystalrarr It can be used in VLSI devices on the scale of 5ndash60 nm

3) Not a close-packed structure rather has cushion propertiesA cubic dense structure Doped with B or P Formed by crystal pulling at approx 1420C4)

Although single-crystal IGZO is formed at very high temperatures of 1200ndash1500C CAAC-IGZO can be formed at 100ndash500C by sputteringrarr It can be placed between Si LSI and metal wire layers

5) Homologous layered structure (Semi hard structure) Diamond structure(hard)

6) Composed of four elements (In Ga Zn and O) Si alone

22

3 Performance of CAAC-IGZO FET

23

IdndashVg characteristics and mobilities of CAAC-IGZO FETs with channel lengths of (a) 2 μm and (b) 6 μm The channel widths are 50 μm

It may be possible to apply all kinds of displays (TV smartphone PC by using OEL LCD)

L = 2 μm (W = 50 μm) L = 6 μm (W = 50 μm)

High-mobility CAAC-IGZO FETs

24

(a) (b)

CAAC-IGZO TrIoff = 1times10minus22 Aμm

(100 yAμm)IonIoff = 1018

IndashV characteristics of CAAC-IGZO and Si transistors

Si TrIoff = 1times10minus12 Aμm

(1 pAμm)IonIoff = 109

Off-state Current of CAAC-IGZO and Si FETsUnit

zA (10minus21)

yA (10minus24)

aA (10minus18)

fA (10minus15)

pA (10minus12)

nA (10minus9)

μA (10minus6)

mA (10minus3)

25

How to Measure Off-state Current60

0 μm

360 μm L = 044 μmW = 10 mm(50 μmtimes200)Tox = 20 nm

A huge transistor with a channel width of 10 mm for off-state leakage current measurement (optical micrograph)

Concept of measurement

Node FN(Vout)

Behavior of potential at node FN (Vout) over time

Measuredtransistor

26

Arrhenius plot of off-state leakage current1)Change of Vout measured over time

1) S Yamazaki et al Jpn J Appl Phys vol 53 pp 04ED18 (2014)

At a gate voltage of minus3 V and 85Cthe off-state leakage current was 6 yAm (1 yA = 10minus24 A)Nonvolatility for 10 years at 85C is ensured

Off-state CurrentUnitAμm

mA (10minus3)μA (10minus6)nA (10minus9)pA (10minus12)fA (10minus15)aA (10minus18)zA (10minus21)yA (10minus24)Le

akag

e cu

rrent

[Aμ

m]

27

-5

0

5

10

15

20

25

30

RF

Gai

n [d

B]

周波数[Hz]109 1010 101130 GHz

Vd = 20 VVg = 20 V( gm max )

WL = 18 μm30 nm

Operation with a cutoff frequency of about 30 GHz is demonstratedThe off-state leakage current of an OS FET (W = 60 nm) is expected at 100 zA or less at 85C even for a 30-nm-node FET

Lower measurement limit

High Cutoff Frequency and Low Off-state Current (30 nm)

28

Frequency [Hz]30 GHz

LW = 30 18000 (60 nmtimes300 Parallel) nm

Short-channel Characteristics of OS FETs

Favorable FET characteristics were obtained with a 11-nm-thick gate insulating film when L = 32 nm

The graphs show that OS FETs are resistant to short-channel effects This is probably because they have a ldquosurrounded-channel (S-ch) structure with a thin active layerrdquo and

are ldquoaccumulation-mode devicesrdquo and ldquoCAAC-IGZO has dielectric anisotropyrdquo(S-ch structure an FET structure where the active layer is electrically surrounded by the gate electrode)

GI = 11 nm

29

0

5

10

15

20

001 01 1 10 100

μ FE

[cm

2middotV-1

middot s-1]

チャネル長 [μm]

理論

Planar TypeS‐ch Type

0

200

400

600

001 01 1 10 100

μ FE

[cm

2 middotV-1

middots-1

]チャネル長 [μm]

理論

Planar Type

Short-channel Characteristics of OS FETs

Channel length dependence of field-effect mobility

(single-crystal Si FET)

Channel length dependence of field-effect mobility

（CAAC‐IGZO FET)

The field-effect mobility (μFE) of a CAAC-IGZO FET with a reduced channel length is close to that of a single-crystal Si FET with the same size

μ FE[

cm2 V

-1s

-1]

Channel length

0

20

5

10

15

10 nm 100 nm 1 μm 100 μm10 μm 10 nm 100 nm 1 μm 100 μm10 μm

Channel length

0

600

200

400

μ FE[

cm2 V

-1s

-1]

Theoretical Theoretical

30

Temperature Dependence of CAAC-IGZO FET

OS-FET

編集中編集中

L=048um GI=20nm

Vth

S値

ID_VG特性

単結晶 p-ch Si Tr （SOI）

L=035um GI=20nm L=035um GI=20nm

編集中 編集中

単結晶 n-ch Si Tr （SOI）

‐05

00

05

10

15

0 50 100 150 200 250

Vth[V]

基板温度 []

0

50

100

150

200

250

300

0 50 100 150 200 250

S‐Value[mVdec]

基板温度 []

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

Vg [V]

250

‐05

0

05

1

15

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

‐15

‐1

‐05

0

05

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

T = minus40C minus 25C 0C 25C 50C 100C 150C 200C 250C

CAAC-OS FETs have a sufficient onoff ratio even at 200C or higherThe S-value shows little change (or is constant) compared with Si FETs

Single‐crystal n‐ch Tr (SOI) Single‐crystal p‐ch Tr (SOI)OS FET

ID‐VGCharac‐teristics

Vth

S‐value

Substrate temperature [C] Substrate temperature [C] Substrate temperature [C]

Substrate temperature [C]Substrate temperature [C]Substrate temperature [C]

31

1E-07

1E-06

1E-05

1E-04

1E-03

1E-02

0 5 10 15 20 25 30V D [V]

ID [A

]Si transistorL =09um T ox=20nm

IGZO transistorL =09um T ox=20nm

4V 26V

L ＝ 09 μm W ＝ 10 μm TOX = 20 nm VG ＝ 2 V

n = 2

CAAC-IGZO transistors have a higher breakdown voltage than Si transistorsNo hot carrier degradation and avalanche breakdown are observed

Breakdown Voltage of CAAC-IGZO and Si FETs

32

Schematic Band Diagram of Channel Regionmdash OS FET vs n-ch Si FET

Inversion Depletion Accumulation

Vg gt 0 V (ON State) Vg lt 0 V (OFF State)Vg = 0V

CAAC-IGZO(S-channel)

n-ch Si

OS2CAAC-IGZO

OS3Gate E

GI GI

Gate E

Gate E

GI

Si

EC

EV

Ef

EfEC

EV

Eg=32eV

Eg=12eV

ElectronsA Arsquo

OS3

Holes

A ArsquoA Arsquo

33

M Murakami et al Proc AM-FPDrsquo12 Digest p 174 (2012)

CAAC-IGZO c-Si

1) Bandgap (Eg) 28ndash32 eV 112 eV

2) Intrinsic carrierconcentration 10minus9 cm3 10+11 cm3

3) Depletion layer km order μm order

4) Electron effective mass (meme)

023ndash025 019 (transverse)098 (longitudinal)

5) Hole effective mass (mhme)

11ndash40 016 (light)049 (heavy)

6) Structure Layered structure(Homologous) Diamond cubic

7) Conductivity i-type n-type n-type p-type

Comparison of Physical Properties between CAAC-IGZO and c-Si

34

Features of CAAC-IGZO as Device

CAAC‐IGZO c‐Si

1) Four-terminal circuitFour-terminal circuit MRAM and FeRAM are two-terminal circuits

2) Almost no short-channel effects Short-channel effects are most troublesome

3) Normally off Uncontrollable Vth high purity and intrinsic

Vth is controllable by channel doping with B

4) IonIoff ratio of 1020 IonIoff le 1010

5) nMOS onlyCMOS feasible with Si pMOS

CMOS Si nMOSSi pMOS

6) Bulk channel buried channel Shifting from surface-channel (planar) to bulk-channel (Fin)

35

4 30-nm Scaling of CAAC-IGZO FET

36

Trench Gate Self-aligned FET

L-direction W-direction

L-direction W-direction

CAAC-OS

Gate Electrode Gate Insulating Film

CAAC-OSDrain

ElectrodeSource

Electrode

Gate Electrode

Gate Insulating Film

48 nm

Gate Electrode

Gate Insulating Film

CAAC-OS34 nm

Source Electrode

Drain Electrode

CAAC-OS

Gate Insulating FilmGate Electrode

19 nm

50 nm

S-ch structure

FETrsquos active layer (CAAC-IGZO OS2 layer) is electrically surrounded by the gate electrodeWe call this FET structure a

surrounded-channel (S-ch) structure

37

Stacked Structure of OS FET and Si FET

pMOSSi

nMOSOS

GND

VDD

A Arsquo

B

Brsquo gate metal

source drain

gate insulator

CAAC-IGZO

electrode

gate

source drain

Si

SiO2

A Arsquo

B

Brsquo

OS FET

Si FET

High integration by stacking the CAAC-OS FET over the Si-FET

Si Substrate Si Substrate

W-directionL-direction

38

Comparison between CAAC-OS FET and Si nMOS FETItem CAAC-OS FET Si nMOS FET

1 Short-channel effect Small or none timesLarge (largest issue in Si NMOS FET)

2 Scaling le 30 nm (Possibility of 5 nm) Possible to ge 5 nm

3 Off-state current yAμm (10minus24 Aμm) times fAμm (10minus15 Aμm)

4 Mobility

Long channel Low High

Short channel Slightly decrease

Decrease (110 in 30-nm device)

5 Temperature characteristics

On-state current

Increase at high temperature

Decrease at high temperature

Off-state current Sufficiently low times

Drastically increase at high temperature

6 Drain breakdown voltage High Low7 Impact ionization Not observed Observed+2 +1 minus1 times minus2

39

Item CAAC-OS FET Si nMOS FET

8 Hot carrier degradation Not observed Large

9 Punch-through Not observed Strongly need balance with scaling

10 Frequency characteristics gt 30 GHz gt 300 GHz

11 Drift velocity Close to Si with channel length about 10 nm

Saturates with channel length about 100 nm

12 Sub-threshold value Small even with thick GI

Need thinner GI by miniaturizing

13 Dielectric anisotropy Observed Not observed

14 S-channel structure(Fin tri-gate type)

Extremely important and effective

Extremely important in shorter channel and effective

+25 minus1+2 +1 minus1 times minus2

Comparison between CAAC-OS FET and Si nMOS FET

40

5 CAAC-IGZO FET for LSI Application

41

Two-terminal circuit(diode)

Potential as Logic Circuit

Dependent control of input and output Need a transistor for four-terminal control Increased F2

Independently controllable inputs and outputs Desirable logic design Sufficiently low Ioff Practically an insulator

Four-terminal circuit

A B

C D

Input Output

42

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

2

Contents

1) What is CAAC-IGZO

2) Can we make FETs by using it (oxide semiconductor)

3) Can we really make FETs as good as Si nMOS FETs by using CAAC-IGZO

4) Can we really make CMOS LSI by using a stacked structure with Si pMOS

5) What is 30-nm (channel length) FETLSI like

6) Do you really think you can catch up with Si VLSI

1 IntroductionndashHistory

3

1-1 History of CAAC-IGZO

1985 N Kimizuka synthesized IGZO for the first time in the world andrevealed its crystal structure1)

1987 Kimizuka proposed the use of IGZO as a semiconductor element2)

1995 J F M Cillessen at Philips proposed an oxide semiconductor (OS) FETincluding IGZO3)

20099 Yamazaki (SEL) discovered CAAC (Jpn Pat No 5211261)20115 SELrsquos NOSRAM4)

20116 SELrsquos image sensor5)

20137 SELrsquos FPGA6)

20139 A paper on 8-bit CPU by SEL7) was selected for SSDM Paper Award from more than 700 papers

20146 A paper on an 8K organic EL display by SEL8) received Distinguished Paper Award at SID Display Week 2014

1) N Kimizuka and T Mohri J Solid State Chem 60 382 (1985)2) Jpn Pat No 16393983) J F M Cillessen et al US Pat No 5744864 (1995)4) T Matsuzaki et al 3rd IEEE Int Memory Workshop pp185‐188 (2011)5) T Aoki et al Symp VLSI Technology Tech pp174‐175 (2011)

6) Y Okamoto et al ECS Trans 54(1) pp 141-149 (2013)7) T Ohmaru et al Ext Abstr Solid States Device and Materials

pp 1144-1145 (2012)8) S Kawashima et al SID Symp Digest 45 pp627-630 (2014)

4

5

1) Single-crystal IGZO was first synthesized in 1985 by Kimizuka (at National Institute for Research in Inorganic Materials) ITO ZnO and other oxide semiconductors have been widely used as conductive transparent oxides (CTOs) They have been studied since the 1980s for use in FETs especially thin-film transistors (TFTs)

2) SEL discovered a new crystal structure (CAAC-IGZO) in 2009 It is neither single-crystal nor amorphous CAAC-IGZO is characterized by no clear grain boundary being observedWe succeeded in paving the way for its first VLSI applicationby thoroughly seeking details as done for semiconductors We consider a c-axis-aligned a-b-plane-anchored crystal (CAAC)structure as a new crystal structure

1-2 Materials and Application (Device LSI System)

CAAC-IGZO has been comprehensively examined from the aspects of devices and application as well as materials

Device Process PropertiesFeatures

Material Defect control Thin-film formation Structure Film quality evaluation

Device Element structure examination

Process developmentCompatibility with existing Si LSI Device properties

Application

LSI

Combination of OSpassive element

Smaller F2

Challenge to scaling

OSSi hybrid3D structure

Development of process at le500C (400C)

Solution for scaling-related problems

System

IoT8K TV

Cell phone

Compatibility with interfaces of other systems by communication

means etc

Larger sizeShorter process

Logic circuit Super low power

6

2 What kind of crystal morphology does CAAC have

7

Discovered by SEL mass produced by Sharp

3 nm 3 nm

single crystalsingle crystal nano-crystalCAAC amorphous-like amorphous

Thickness 50 nm

CAAC nanocrystal

Classification of Oxide Semiconductor Materials

Thickness 50 nm

c-ax

is

Crystal structure of IGZO

88

2)

1) K Nomura T Kamiya H Ohta T Uruga M Hirano and H Hosono

Phys Rev B 75 035212 (2007) 2) Y Kurosawa et al

JSAP Autumn Meeting 2014 18p-A12-2

The simulation model of ldquoamorphous IGZO1)rdquo by Melt quench method

copyThe Japan Society of Applied Physics 2014

amorphous structure

Characteristics of CAAC-IGZO Film

Derived from quartz substrate

E-beam is incident parallel to the substrate surface

E-beam is incident perpendicularto the substrate surface

Rotation within (110) plane

Sample structure

electron diffraction (a-b plane)

X-ray diffraction (c-axis)

electron diffraction (c-axis)c-axis

a

b

Clear orientationNo orientation

Clearorientation

No orientation

CAAC c-axis-aligned a-b-plane-anchored crystalCAAC c-axis-aligned a-b-plane-anchored crystal

X-ray diffraction (a-b plane)

9

(d) CAAC crystal pellet (e) Cross-sectional image of unit pelletIn Ga or Zn O

(Chip)

Substrate

Cross-sectional TEM of CAAC-IGZO Film

08 nm

3 nm

(a) (b)TEM imageHR-TEM imageDetail of area in (a)

IGZO Film

Substrate

50 nm

10

平面TEM高分解能像FFT image processing-Extract data on a certain wavenumber range

Processing using an original program

Plan‐view TEM Crystal Lattice Image

FFT Filtered Image(FFTFast FourierTransform)

Lattice Extraction Image

Hexagonal Lattice Orientation Analysis amp

Color Mapping

Perfect regular hexagon

Neighboring lattice points(6 points)

Reference lattice point

1) Determine the orientation of a perfect regular hexagon so as to minimize the sum of the distances from the vertices of the perfect regular hexagon to six points neighboring a reference lattice point

Average distance a the average of distances from the reference lattice point to its neighboring six lattice points

2) Color each lattice point after the step 1) according to the difference from a reference angle In this study the modal angle was set to 30

6050403020100

ex

θ x

Average distance a

0 le θ lt 60

orientations of hexagons [degree]

Analysis Procedure Hexagonal LatticeOrientation Analysis amp Color Mapping

Processing using an original program

11

(a) A plan-view TEM image (b) A color mapping image obtained from an FFT filtered image of (a) The orientations of the hexagons are sorted by the angle (0minus60) and shown in different colors The colors of the adjoining grains are adjacent colors on the color scale

10 nm

(3)

(4)

(1)(2)

(a)

Plan-view Observations of CAAC-IGZO Film

(b)orientations of hexagons [degree]

60

50

40

30

20

10

0

12

(d)(a) (b) (c)

(d)(a) (c)(b)

(1)

(2)

Observations in Grain

Magnifying observations in a grain with a size of several tens of nanometers at the atomic level(a) Plan-view TEM images (b)(c) FFT filtered images (d) Color mapping imagesDotted lines denote boundaries between pellets Solid lines show a hexagon formed with lattice points

plan-view FFT filtered images color mapping

60

50

40

30

20

10

0

orientations of hexagons [degree]

Pellet

Hexagon formed with lattice points

Reg

ions

cor

resp

ondi

ng to

thos

e in

the

plan

-vie

w T

EM

imag

e of

the

wid

e ar

ea

13

In Ga or Zn O

066 nm

038 nm

ｚｚ

Side view of a unit cell

198 nm

181 nm

Surface of a unit cellHexagon formed with lattice points

07 nm

(Ga Zn)O

(Ga Zn)O

InO2

Homologous crystal structure

CAAC-OS pellet unit cellSemi hard material (a flexible crystal structure) by oxygen as a cushion between In Ga and Zn

Oxygen

Oxygen

14

Magnifying observations in a boundary portion between grains with a size of several tens of nanometers at the atomic level(a) Plan-view TEM images (b)(c) FFT filtered images (d) Color mapping imagesDeformed hexagons pentagons and heptagons are formed with lattice points at the boundary denoted by a dotted line and they are anchored to each other

Observations in Boundary Portion between Grains

60

50

40

30

20

10

0

orientations of hexagons [degree]

Boundary(3

)(4

)

plan-view FFT filtered images color mapping

(d)

(d)

(a)

(a) (c)

(b)

(b)

(c)R

egio

ns c

orre

spon

ding

to th

ose

in th

e pl

an-v

iew

TE

M im

age

of th

e w

ide

area

15

(a) and (c) Distribution of number of Voronoi polygons in single crystal IGZO and CAAC-IGZO (b) and (d) Distribution of Voronoi hexagons (yellow regions) and other polygons (blue regions) in the single crystal IGZO and the CAAC-IGZO

Distribution of Number of Voronoi Polygons

In the single crystal IGZO hexagonal Voronoi regions occupy almost the entire field of view In the CAAC-IGZO hexagons are the majority but pentagons and heptagons also appear

Single crystal IGZO CAAC-IGZOSingle crystal IGZO film [] CAAC-IGZO film []

Tetragon 01 07

Pentagon 12 155

Hexagon 982 683

Heptagon 04 145

Octagon 02 09

Nonagon 00 00

16

2 3 4 51

5 nmminus1

5 nmminus1

minus231degminus84degminus75 deg minus310degminus246deg

+118deg +15deg +135deg +04deg minus55deg2 3 4 51

(a)1 2 34 5

20 nm

(b) 12

3

4

5 20 nm

Panel (a) shows the points along the surface of the CAAC-IGZO film that were probed by NBED and the five remaining panels in the top row show the corresponding NBED patterns Panel (b) shows the points probed by NBED in the thickness of the film and the five remaining panels in the lower row show the corresponding NBED patterns The angle of the crystal axis is slightly shifted in both the surface and thickness directions

Nanobeam Electron Diffraction (NBED 1 nmɸ) Patterns of CAAC-IGZO Film

17

Nanobeam Electron Diffraction (NBED 1 nmɸ) Patterns of CAAC-IGZO Film

Broadanisotropic diffraction spots

Sharpcircular diffraction spots

The electron diffraction pattern of single-crystal IGZO has circular spots as shown in (b) Diffraction spots of CAAC-IGZO are not circular but anisotropic and broad

18

Schematic Band Diagram of IGZOSimple schematic diagram of defect levels in IGZO film

elec

tron

ener

gy [e

V]

surface shallow DOS(sDOS)

bulk shallow DOS(sDOS)

bulk deep DOS(dDOS)

Density of States (DOS) of IGZO

19

28-32 eV

Silicon oxide IGZO

CAAC-IGZO63 (gcm3)

nc-IGZO61 (gcm3)

a-like IGZO59 (gcm3)

αCPM Absorption coefficient estimated by a constant photocurrent method (CPM)

N Ishihara et al Proc AM-FPD12 143 (2012)J Koezuka et al SID2013 Symposium Digest 723 (2013)

A high density of deep-level states (dDOS) exists in the low-density IGZO filmThe higher the film density is (like CAAC) the lower the dDOS is

Light absorptions by IGZO films with different crystal structureswere measured to quantify the densities of deep energy trapstates (dDOS)

Density of States (DOS) of IGZO

a-like IGZO 53 times 100

20

Formation of Oxygen Vacancies (VO) in IGZO

software VASP

exchange correlation function

GGA

pseudo potential PAW

cut-off energy 800 eV

k-point 1times1times1VO are

likely to be formed

Crystal Amorphous

In Ga Zn O

-1180

-1178

-1176

-1174

-1172

-15 -10 -5 0 5 10 15

Tota

l Ene

rgy

[eV]

Distance from Interface [Aring]

InterfaceInterface

VO are highly likely to be formed

A comparison of formation of oxygen vacancies (VO) between amorphous and crystal structures was made by first-principles calculation The results indicate that VO are easily formed in the amorphous structure

21

Features of CAAC-IGZO as MaterialCAAC-IGZO c-Si

1)CAAC structure (not single-crystal nano-crystalline or amorphous)rarr No clear grain boundary is observed

lattice points to form a pentagon and heptagon

Single crystal is preferable because polycrystal has a high concentration of defects at grain boundaries2)

Crystal grains (pellets) are anchored to each other to form one big crystalrarr It can be used in VLSI devices on the scale of 5ndash60 nm

3) Not a close-packed structure rather has cushion propertiesA cubic dense structure Doped with B or P Formed by crystal pulling at approx 1420C4)

Although single-crystal IGZO is formed at very high temperatures of 1200ndash1500C CAAC-IGZO can be formed at 100ndash500C by sputteringrarr It can be placed between Si LSI and metal wire layers

5) Homologous layered structure (Semi hard structure) Diamond structure(hard)

6) Composed of four elements (In Ga Zn and O) Si alone

22

3 Performance of CAAC-IGZO FET

23

IdndashVg characteristics and mobilities of CAAC-IGZO FETs with channel lengths of (a) 2 μm and (b) 6 μm The channel widths are 50 μm

It may be possible to apply all kinds of displays (TV smartphone PC by using OEL LCD)

L = 2 μm (W = 50 μm) L = 6 μm (W = 50 μm)

High-mobility CAAC-IGZO FETs

24

(a) (b)

CAAC-IGZO TrIoff = 1times10minus22 Aμm

(100 yAμm)IonIoff = 1018

IndashV characteristics of CAAC-IGZO and Si transistors

Si TrIoff = 1times10minus12 Aμm

(1 pAμm)IonIoff = 109

Off-state Current of CAAC-IGZO and Si FETsUnit

zA (10minus21)

yA (10minus24)

aA (10minus18)

fA (10minus15)

pA (10minus12)

nA (10minus9)

μA (10minus6)

mA (10minus3)

25

How to Measure Off-state Current60

0 μm

360 μm L = 044 μmW = 10 mm(50 μmtimes200)Tox = 20 nm

A huge transistor with a channel width of 10 mm for off-state leakage current measurement (optical micrograph)

Concept of measurement

Node FN(Vout)

Behavior of potential at node FN (Vout) over time

Measuredtransistor

26

Arrhenius plot of off-state leakage current1)Change of Vout measured over time

1) S Yamazaki et al Jpn J Appl Phys vol 53 pp 04ED18 (2014)

At a gate voltage of minus3 V and 85Cthe off-state leakage current was 6 yAm (1 yA = 10minus24 A)Nonvolatility for 10 years at 85C is ensured

Off-state CurrentUnitAμm

mA (10minus3)μA (10minus6)nA (10minus9)pA (10minus12)fA (10minus15)aA (10minus18)zA (10minus21)yA (10minus24)Le

akag

e cu

rrent

[Aμ

m]

27

-5

0

5

10

15

20

25

30

RF

Gai

n [d

B]

周波数[Hz]109 1010 101130 GHz

Vd = 20 VVg = 20 V( gm max )

WL = 18 μm30 nm

Operation with a cutoff frequency of about 30 GHz is demonstratedThe off-state leakage current of an OS FET (W = 60 nm) is expected at 100 zA or less at 85C even for a 30-nm-node FET

Lower measurement limit

High Cutoff Frequency and Low Off-state Current (30 nm)

28

Frequency [Hz]30 GHz

LW = 30 18000 (60 nmtimes300 Parallel) nm

Short-channel Characteristics of OS FETs

Favorable FET characteristics were obtained with a 11-nm-thick gate insulating film when L = 32 nm

The graphs show that OS FETs are resistant to short-channel effects This is probably because they have a ldquosurrounded-channel (S-ch) structure with a thin active layerrdquo and

are ldquoaccumulation-mode devicesrdquo and ldquoCAAC-IGZO has dielectric anisotropyrdquo(S-ch structure an FET structure where the active layer is electrically surrounded by the gate electrode)

GI = 11 nm

29

0

5

10

15

20

001 01 1 10 100

μ FE

[cm

2middotV-1

middot s-1]

チャネル長 [μm]

理論

Planar TypeS‐ch Type

0

200

400

600

001 01 1 10 100

μ FE

[cm

2 middotV-1

middots-1

]チャネル長 [μm]

理論

Planar Type

Short-channel Characteristics of OS FETs

Channel length dependence of field-effect mobility

(single-crystal Si FET)

Channel length dependence of field-effect mobility

（CAAC‐IGZO FET)

The field-effect mobility (μFE) of a CAAC-IGZO FET with a reduced channel length is close to that of a single-crystal Si FET with the same size

μ FE[

cm2 V

-1s

-1]

Channel length

0

20

5

10

15

10 nm 100 nm 1 μm 100 μm10 μm 10 nm 100 nm 1 μm 100 μm10 μm

Channel length

0

600

200

400

μ FE[

cm2 V

-1s

-1]

Theoretical Theoretical

30

Temperature Dependence of CAAC-IGZO FET

OS-FET

編集中編集中

L=048um GI=20nm

Vth

S値

ID_VG特性

単結晶 p-ch Si Tr （SOI）

L=035um GI=20nm L=035um GI=20nm

編集中 編集中

単結晶 n-ch Si Tr （SOI）

‐05

00

05

10

15

0 50 100 150 200 250

Vth[V]

基板温度 []

0

50

100

150

200

250

300

0 50 100 150 200 250

S‐Value[mVdec]

基板温度 []

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

Vg [V]

250

‐05

0

05

1

15

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

‐15

‐1

‐05

0

05

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

T = minus40C minus 25C 0C 25C 50C 100C 150C 200C 250C

CAAC-OS FETs have a sufficient onoff ratio even at 200C or higherThe S-value shows little change (or is constant) compared with Si FETs

Single‐crystal n‐ch Tr (SOI) Single‐crystal p‐ch Tr (SOI)OS FET

ID‐VGCharac‐teristics

Vth

S‐value

Substrate temperature [C] Substrate temperature [C] Substrate temperature [C]

Substrate temperature [C]Substrate temperature [C]Substrate temperature [C]

31

1E-07

1E-06

1E-05

1E-04

1E-03

1E-02

0 5 10 15 20 25 30V D [V]

ID [A

]Si transistorL =09um T ox=20nm

IGZO transistorL =09um T ox=20nm

4V 26V

L ＝ 09 μm W ＝ 10 μm TOX = 20 nm VG ＝ 2 V

n = 2

CAAC-IGZO transistors have a higher breakdown voltage than Si transistorsNo hot carrier degradation and avalanche breakdown are observed

Breakdown Voltage of CAAC-IGZO and Si FETs

32

Schematic Band Diagram of Channel Regionmdash OS FET vs n-ch Si FET

Inversion Depletion Accumulation

Vg gt 0 V (ON State) Vg lt 0 V (OFF State)Vg = 0V

CAAC-IGZO(S-channel)

n-ch Si

OS2CAAC-IGZO

OS3Gate E

GI GI

Gate E

Gate E

GI

Si

EC

EV

Ef

EfEC

EV

Eg=32eV

Eg=12eV

ElectronsA Arsquo

OS3

Holes

A ArsquoA Arsquo

33

M Murakami et al Proc AM-FPDrsquo12 Digest p 174 (2012)

CAAC-IGZO c-Si

1) Bandgap (Eg) 28ndash32 eV 112 eV

2) Intrinsic carrierconcentration 10minus9 cm3 10+11 cm3

3) Depletion layer km order μm order

4) Electron effective mass (meme)

023ndash025 019 (transverse)098 (longitudinal)

5) Hole effective mass (mhme)

11ndash40 016 (light)049 (heavy)

6) Structure Layered structure(Homologous) Diamond cubic

7) Conductivity i-type n-type n-type p-type

Comparison of Physical Properties between CAAC-IGZO and c-Si

34

Features of CAAC-IGZO as Device

CAAC‐IGZO c‐Si

1) Four-terminal circuitFour-terminal circuit MRAM and FeRAM are two-terminal circuits

2) Almost no short-channel effects Short-channel effects are most troublesome

3) Normally off Uncontrollable Vth high purity and intrinsic

Vth is controllable by channel doping with B

4) IonIoff ratio of 1020 IonIoff le 1010

5) nMOS onlyCMOS feasible with Si pMOS

CMOS Si nMOSSi pMOS

6) Bulk channel buried channel Shifting from surface-channel (planar) to bulk-channel (Fin)

35

4 30-nm Scaling of CAAC-IGZO FET

36

Trench Gate Self-aligned FET

L-direction W-direction

L-direction W-direction

CAAC-OS

Gate Electrode Gate Insulating Film

CAAC-OSDrain

ElectrodeSource

Electrode

Gate Electrode

Gate Insulating Film

48 nm

Gate Electrode

Gate Insulating Film

CAAC-OS34 nm

Source Electrode

Drain Electrode

CAAC-OS

Gate Insulating FilmGate Electrode

19 nm

50 nm

S-ch structure

FETrsquos active layer (CAAC-IGZO OS2 layer) is electrically surrounded by the gate electrodeWe call this FET structure a

surrounded-channel (S-ch) structure

37

Stacked Structure of OS FET and Si FET

pMOSSi

nMOSOS

GND

VDD

A Arsquo

B

Brsquo gate metal

source drain

gate insulator

CAAC-IGZO

electrode

gate

source drain

Si

SiO2

A Arsquo

B

Brsquo

OS FET

Si FET

High integration by stacking the CAAC-OS FET over the Si-FET

Si Substrate Si Substrate

W-directionL-direction

38

Comparison between CAAC-OS FET and Si nMOS FETItem CAAC-OS FET Si nMOS FET

1 Short-channel effect Small or none timesLarge (largest issue in Si NMOS FET)

2 Scaling le 30 nm (Possibility of 5 nm) Possible to ge 5 nm

3 Off-state current yAμm (10minus24 Aμm) times fAμm (10minus15 Aμm)

4 Mobility

Long channel Low High

Short channel Slightly decrease

Decrease (110 in 30-nm device)

5 Temperature characteristics

On-state current

Increase at high temperature

Decrease at high temperature

Off-state current Sufficiently low times

Drastically increase at high temperature

6 Drain breakdown voltage High Low7 Impact ionization Not observed Observed+2 +1 minus1 times minus2

39

Item CAAC-OS FET Si nMOS FET

8 Hot carrier degradation Not observed Large

9 Punch-through Not observed Strongly need balance with scaling

10 Frequency characteristics gt 30 GHz gt 300 GHz

11 Drift velocity Close to Si with channel length about 10 nm

Saturates with channel length about 100 nm

12 Sub-threshold value Small even with thick GI

Need thinner GI by miniaturizing

13 Dielectric anisotropy Observed Not observed

14 S-channel structure(Fin tri-gate type)

Extremely important and effective

Extremely important in shorter channel and effective

+25 minus1+2 +1 minus1 times minus2

Comparison between CAAC-OS FET and Si nMOS FET

40

5 CAAC-IGZO FET for LSI Application

41

Two-terminal circuit(diode)

Potential as Logic Circuit

Dependent control of input and output Need a transistor for four-terminal control Increased F2

Independently controllable inputs and outputs Desirable logic design Sufficiently low Ioff Practically an insulator

Four-terminal circuit

A B

C D

Input Output

42

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

1 IntroductionndashHistory

3

1-1 History of CAAC-IGZO

1985 N Kimizuka synthesized IGZO for the first time in the world andrevealed its crystal structure1)

1987 Kimizuka proposed the use of IGZO as a semiconductor element2)

1995 J F M Cillessen at Philips proposed an oxide semiconductor (OS) FETincluding IGZO3)

20099 Yamazaki (SEL) discovered CAAC (Jpn Pat No 5211261)20115 SELrsquos NOSRAM4)

20116 SELrsquos image sensor5)

20137 SELrsquos FPGA6)

20139 A paper on 8-bit CPU by SEL7) was selected for SSDM Paper Award from more than 700 papers

20146 A paper on an 8K organic EL display by SEL8) received Distinguished Paper Award at SID Display Week 2014

1) N Kimizuka and T Mohri J Solid State Chem 60 382 (1985)2) Jpn Pat No 16393983) J F M Cillessen et al US Pat No 5744864 (1995)4) T Matsuzaki et al 3rd IEEE Int Memory Workshop pp185‐188 (2011)5) T Aoki et al Symp VLSI Technology Tech pp174‐175 (2011)

6) Y Okamoto et al ECS Trans 54(1) pp 141-149 (2013)7) T Ohmaru et al Ext Abstr Solid States Device and Materials

pp 1144-1145 (2012)8) S Kawashima et al SID Symp Digest 45 pp627-630 (2014)

4

5

1) Single-crystal IGZO was first synthesized in 1985 by Kimizuka (at National Institute for Research in Inorganic Materials) ITO ZnO and other oxide semiconductors have been widely used as conductive transparent oxides (CTOs) They have been studied since the 1980s for use in FETs especially thin-film transistors (TFTs)

2) SEL discovered a new crystal structure (CAAC-IGZO) in 2009 It is neither single-crystal nor amorphous CAAC-IGZO is characterized by no clear grain boundary being observedWe succeeded in paving the way for its first VLSI applicationby thoroughly seeking details as done for semiconductors We consider a c-axis-aligned a-b-plane-anchored crystal (CAAC)structure as a new crystal structure

1-2 Materials and Application (Device LSI System)

CAAC-IGZO has been comprehensively examined from the aspects of devices and application as well as materials

Device Process PropertiesFeatures

Material Defect control Thin-film formation Structure Film quality evaluation

Device Element structure examination

Process developmentCompatibility with existing Si LSI Device properties

Application

LSI

Combination of OSpassive element

Smaller F2

Challenge to scaling

OSSi hybrid3D structure

Development of process at le500C (400C)

Solution for scaling-related problems

System

IoT8K TV

Cell phone

Compatibility with interfaces of other systems by communication

means etc

Larger sizeShorter process

Logic circuit Super low power

6

2 What kind of crystal morphology does CAAC have

7

Discovered by SEL mass produced by Sharp

3 nm 3 nm

single crystalsingle crystal nano-crystalCAAC amorphous-like amorphous

Thickness 50 nm

CAAC nanocrystal

Classification of Oxide Semiconductor Materials

Thickness 50 nm

c-ax

is

Crystal structure of IGZO

88

2)

1) K Nomura T Kamiya H Ohta T Uruga M Hirano and H Hosono

Phys Rev B 75 035212 (2007) 2) Y Kurosawa et al

JSAP Autumn Meeting 2014 18p-A12-2

The simulation model of ldquoamorphous IGZO1)rdquo by Melt quench method

copyThe Japan Society of Applied Physics 2014

amorphous structure

Characteristics of CAAC-IGZO Film

Derived from quartz substrate

E-beam is incident parallel to the substrate surface

E-beam is incident perpendicularto the substrate surface

Rotation within (110) plane

Sample structure

electron diffraction (a-b plane)

X-ray diffraction (c-axis)

electron diffraction (c-axis)c-axis

a

b

Clear orientationNo orientation

Clearorientation

No orientation

CAAC c-axis-aligned a-b-plane-anchored crystalCAAC c-axis-aligned a-b-plane-anchored crystal

X-ray diffraction (a-b plane)

9

(d) CAAC crystal pellet (e) Cross-sectional image of unit pelletIn Ga or Zn O

(Chip)

Substrate

Cross-sectional TEM of CAAC-IGZO Film

08 nm

3 nm

(a) (b)TEM imageHR-TEM imageDetail of area in (a)

IGZO Film

Substrate

50 nm

10

平面TEM高分解能像FFT image processing-Extract data on a certain wavenumber range

Processing using an original program

Plan‐view TEM Crystal Lattice Image

FFT Filtered Image(FFTFast FourierTransform)

Lattice Extraction Image

Hexagonal Lattice Orientation Analysis amp

Color Mapping

Perfect regular hexagon

Neighboring lattice points(6 points)

Reference lattice point

1) Determine the orientation of a perfect regular hexagon so as to minimize the sum of the distances from the vertices of the perfect regular hexagon to six points neighboring a reference lattice point

Average distance a the average of distances from the reference lattice point to its neighboring six lattice points

2) Color each lattice point after the step 1) according to the difference from a reference angle In this study the modal angle was set to 30

6050403020100

ex

θ x

Average distance a

0 le θ lt 60

orientations of hexagons [degree]

Analysis Procedure Hexagonal LatticeOrientation Analysis amp Color Mapping

Processing using an original program

11

(a) A plan-view TEM image (b) A color mapping image obtained from an FFT filtered image of (a) The orientations of the hexagons are sorted by the angle (0minus60) and shown in different colors The colors of the adjoining grains are adjacent colors on the color scale

10 nm

(3)

(4)

(1)(2)

(a)

Plan-view Observations of CAAC-IGZO Film

(b)orientations of hexagons [degree]

60

50

40

30

20

10

0

12

(d)(a) (b) (c)

(d)(a) (c)(b)

(1)

(2)

Observations in Grain

Magnifying observations in a grain with a size of several tens of nanometers at the atomic level(a) Plan-view TEM images (b)(c) FFT filtered images (d) Color mapping imagesDotted lines denote boundaries between pellets Solid lines show a hexagon formed with lattice points

plan-view FFT filtered images color mapping

60

50

40

30

20

10

0

orientations of hexagons [degree]

Pellet

Hexagon formed with lattice points

Reg

ions

cor

resp

ondi

ng to

thos

e in

the

plan

-vie

w T

EM

imag

e of

the

wid

e ar

ea

13

In Ga or Zn O

066 nm

038 nm

ｚｚ

Side view of a unit cell

198 nm

181 nm

Surface of a unit cellHexagon formed with lattice points

07 nm

(Ga Zn)O

(Ga Zn)O

InO2

Homologous crystal structure

CAAC-OS pellet unit cellSemi hard material (a flexible crystal structure) by oxygen as a cushion between In Ga and Zn

Oxygen

Oxygen

14

Magnifying observations in a boundary portion between grains with a size of several tens of nanometers at the atomic level(a) Plan-view TEM images (b)(c) FFT filtered images (d) Color mapping imagesDeformed hexagons pentagons and heptagons are formed with lattice points at the boundary denoted by a dotted line and they are anchored to each other

Observations in Boundary Portion between Grains

60

50

40

30

20

10

0

orientations of hexagons [degree]

Boundary(3

)(4

)

plan-view FFT filtered images color mapping

(d)

(d)

(a)

(a) (c)

(b)

(b)

(c)R

egio

ns c

orre

spon

ding

to th

ose

in th

e pl

an-v

iew

TE

M im

age

of th

e w

ide

area

15

(a) and (c) Distribution of number of Voronoi polygons in single crystal IGZO and CAAC-IGZO (b) and (d) Distribution of Voronoi hexagons (yellow regions) and other polygons (blue regions) in the single crystal IGZO and the CAAC-IGZO

Distribution of Number of Voronoi Polygons

In the single crystal IGZO hexagonal Voronoi regions occupy almost the entire field of view In the CAAC-IGZO hexagons are the majority but pentagons and heptagons also appear

Single crystal IGZO CAAC-IGZOSingle crystal IGZO film [] CAAC-IGZO film []

Tetragon 01 07

Pentagon 12 155

Hexagon 982 683

Heptagon 04 145

Octagon 02 09

Nonagon 00 00

16

2 3 4 51

5 nmminus1

5 nmminus1

minus231degminus84degminus75 deg minus310degminus246deg

+118deg +15deg +135deg +04deg minus55deg2 3 4 51

(a)1 2 34 5

20 nm

(b) 12

3

4

5 20 nm

Panel (a) shows the points along the surface of the CAAC-IGZO film that were probed by NBED and the five remaining panels in the top row show the corresponding NBED patterns Panel (b) shows the points probed by NBED in the thickness of the film and the five remaining panels in the lower row show the corresponding NBED patterns The angle of the crystal axis is slightly shifted in both the surface and thickness directions

Nanobeam Electron Diffraction (NBED 1 nmɸ) Patterns of CAAC-IGZO Film

17

Nanobeam Electron Diffraction (NBED 1 nmɸ) Patterns of CAAC-IGZO Film

Broadanisotropic diffraction spots

Sharpcircular diffraction spots

The electron diffraction pattern of single-crystal IGZO has circular spots as shown in (b) Diffraction spots of CAAC-IGZO are not circular but anisotropic and broad

18

Schematic Band Diagram of IGZOSimple schematic diagram of defect levels in IGZO film

elec

tron

ener

gy [e

V]

surface shallow DOS(sDOS)

bulk shallow DOS(sDOS)

bulk deep DOS(dDOS)

Density of States (DOS) of IGZO

19

28-32 eV

Silicon oxide IGZO

CAAC-IGZO63 (gcm3)

nc-IGZO61 (gcm3)

a-like IGZO59 (gcm3)

αCPM Absorption coefficient estimated by a constant photocurrent method (CPM)

N Ishihara et al Proc AM-FPD12 143 (2012)J Koezuka et al SID2013 Symposium Digest 723 (2013)

A high density of deep-level states (dDOS) exists in the low-density IGZO filmThe higher the film density is (like CAAC) the lower the dDOS is

Light absorptions by IGZO films with different crystal structureswere measured to quantify the densities of deep energy trapstates (dDOS)

Density of States (DOS) of IGZO

a-like IGZO 53 times 100

20

Formation of Oxygen Vacancies (VO) in IGZO

software VASP

exchange correlation function

GGA

pseudo potential PAW

cut-off energy 800 eV

k-point 1times1times1VO are

likely to be formed

Crystal Amorphous

In Ga Zn O

-1180

-1178

-1176

-1174

-1172

-15 -10 -5 0 5 10 15

Tota

l Ene

rgy

[eV]

Distance from Interface [Aring]

InterfaceInterface

VO are highly likely to be formed

A comparison of formation of oxygen vacancies (VO) between amorphous and crystal structures was made by first-principles calculation The results indicate that VO are easily formed in the amorphous structure

21

Features of CAAC-IGZO as MaterialCAAC-IGZO c-Si

1)CAAC structure (not single-crystal nano-crystalline or amorphous)rarr No clear grain boundary is observed

lattice points to form a pentagon and heptagon

Single crystal is preferable because polycrystal has a high concentration of defects at grain boundaries2)

Crystal grains (pellets) are anchored to each other to form one big crystalrarr It can be used in VLSI devices on the scale of 5ndash60 nm

3) Not a close-packed structure rather has cushion propertiesA cubic dense structure Doped with B or P Formed by crystal pulling at approx 1420C4)

Although single-crystal IGZO is formed at very high temperatures of 1200ndash1500C CAAC-IGZO can be formed at 100ndash500C by sputteringrarr It can be placed between Si LSI and metal wire layers

5) Homologous layered structure (Semi hard structure) Diamond structure(hard)

6) Composed of four elements (In Ga Zn and O) Si alone

22

3 Performance of CAAC-IGZO FET

23

IdndashVg characteristics and mobilities of CAAC-IGZO FETs with channel lengths of (a) 2 μm and (b) 6 μm The channel widths are 50 μm

It may be possible to apply all kinds of displays (TV smartphone PC by using OEL LCD)

L = 2 μm (W = 50 μm) L = 6 μm (W = 50 μm)

High-mobility CAAC-IGZO FETs

24

(a) (b)

CAAC-IGZO TrIoff = 1times10minus22 Aμm

(100 yAμm)IonIoff = 1018

IndashV characteristics of CAAC-IGZO and Si transistors

Si TrIoff = 1times10minus12 Aμm

(1 pAμm)IonIoff = 109

Off-state Current of CAAC-IGZO and Si FETsUnit

zA (10minus21)

yA (10minus24)

aA (10minus18)

fA (10minus15)

pA (10minus12)

nA (10minus9)

μA (10minus6)

mA (10minus3)

25

How to Measure Off-state Current60

0 μm

360 μm L = 044 μmW = 10 mm(50 μmtimes200)Tox = 20 nm

A huge transistor with a channel width of 10 mm for off-state leakage current measurement (optical micrograph)

Concept of measurement

Node FN(Vout)

Behavior of potential at node FN (Vout) over time

Measuredtransistor

26

Arrhenius plot of off-state leakage current1)Change of Vout measured over time

1) S Yamazaki et al Jpn J Appl Phys vol 53 pp 04ED18 (2014)

At a gate voltage of minus3 V and 85Cthe off-state leakage current was 6 yAm (1 yA = 10minus24 A)Nonvolatility for 10 years at 85C is ensured

Off-state CurrentUnitAμm

mA (10minus3)μA (10minus6)nA (10minus9)pA (10minus12)fA (10minus15)aA (10minus18)zA (10minus21)yA (10minus24)Le

akag

e cu

rrent

[Aμ

m]

27

-5

0

5

10

15

20

25

30

RF

Gai

n [d

B]

周波数[Hz]109 1010 101130 GHz

Vd = 20 VVg = 20 V( gm max )

WL = 18 μm30 nm

Operation with a cutoff frequency of about 30 GHz is demonstratedThe off-state leakage current of an OS FET (W = 60 nm) is expected at 100 zA or less at 85C even for a 30-nm-node FET

Lower measurement limit

High Cutoff Frequency and Low Off-state Current (30 nm)

28

Frequency [Hz]30 GHz

LW = 30 18000 (60 nmtimes300 Parallel) nm

Short-channel Characteristics of OS FETs

Favorable FET characteristics were obtained with a 11-nm-thick gate insulating film when L = 32 nm

The graphs show that OS FETs are resistant to short-channel effects This is probably because they have a ldquosurrounded-channel (S-ch) structure with a thin active layerrdquo and

are ldquoaccumulation-mode devicesrdquo and ldquoCAAC-IGZO has dielectric anisotropyrdquo(S-ch structure an FET structure where the active layer is electrically surrounded by the gate electrode)

GI = 11 nm

29

0

5

10

15

20

001 01 1 10 100

μ FE

[cm

2middotV-1

middot s-1]

チャネル長 [μm]

理論

Planar TypeS‐ch Type

0

200

400

600

001 01 1 10 100

μ FE

[cm

2 middotV-1

middots-1

]チャネル長 [μm]

理論

Planar Type

Short-channel Characteristics of OS FETs

Channel length dependence of field-effect mobility

(single-crystal Si FET)

Channel length dependence of field-effect mobility

（CAAC‐IGZO FET)

The field-effect mobility (μFE) of a CAAC-IGZO FET with a reduced channel length is close to that of a single-crystal Si FET with the same size

μ FE[

cm2 V

-1s

-1]

Channel length

0

20

5

10

15

10 nm 100 nm 1 μm 100 μm10 μm 10 nm 100 nm 1 μm 100 μm10 μm

Channel length

0

600

200

400

μ FE[

cm2 V

-1s

-1]

Theoretical Theoretical

30

Temperature Dependence of CAAC-IGZO FET

OS-FET

編集中編集中

L=048um GI=20nm

Vth

S値

ID_VG特性

単結晶 p-ch Si Tr （SOI）

L=035um GI=20nm L=035um GI=20nm

編集中 編集中

単結晶 n-ch Si Tr （SOI）

‐05

00

05

10

15

0 50 100 150 200 250

Vth[V]

基板温度 []

0

50

100

150

200

250

300

0 50 100 150 200 250

S‐Value[mVdec]

基板温度 []

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

Vg [V]

250

‐05

0

05

1

15

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

‐15

‐1

‐05

0

05

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

T = minus40C minus 25C 0C 25C 50C 100C 150C 200C 250C

CAAC-OS FETs have a sufficient onoff ratio even at 200C or higherThe S-value shows little change (or is constant) compared with Si FETs

Single‐crystal n‐ch Tr (SOI) Single‐crystal p‐ch Tr (SOI)OS FET

ID‐VGCharac‐teristics

Vth

S‐value

Substrate temperature [C] Substrate temperature [C] Substrate temperature [C]

Substrate temperature [C]Substrate temperature [C]Substrate temperature [C]

31

1E-07

1E-06

1E-05

1E-04

1E-03

1E-02

0 5 10 15 20 25 30V D [V]

ID [A

]Si transistorL =09um T ox=20nm

IGZO transistorL =09um T ox=20nm

4V 26V

L ＝ 09 μm W ＝ 10 μm TOX = 20 nm VG ＝ 2 V

n = 2

CAAC-IGZO transistors have a higher breakdown voltage than Si transistorsNo hot carrier degradation and avalanche breakdown are observed

Breakdown Voltage of CAAC-IGZO and Si FETs

32

Schematic Band Diagram of Channel Regionmdash OS FET vs n-ch Si FET

Inversion Depletion Accumulation

Vg gt 0 V (ON State) Vg lt 0 V (OFF State)Vg = 0V

CAAC-IGZO(S-channel)

n-ch Si

OS2CAAC-IGZO

OS3Gate E

GI GI

Gate E

Gate E

GI

Si

EC

EV

Ef

EfEC

EV

Eg=32eV

Eg=12eV

ElectronsA Arsquo

OS3

Holes

A ArsquoA Arsquo

33

M Murakami et al Proc AM-FPDrsquo12 Digest p 174 (2012)

CAAC-IGZO c-Si

1) Bandgap (Eg) 28ndash32 eV 112 eV

2) Intrinsic carrierconcentration 10minus9 cm3 10+11 cm3

3) Depletion layer km order μm order

4) Electron effective mass (meme)

023ndash025 019 (transverse)098 (longitudinal)

5) Hole effective mass (mhme)

11ndash40 016 (light)049 (heavy)

6) Structure Layered structure(Homologous) Diamond cubic

7) Conductivity i-type n-type n-type p-type

Comparison of Physical Properties between CAAC-IGZO and c-Si

34

Features of CAAC-IGZO as Device

CAAC‐IGZO c‐Si

1) Four-terminal circuitFour-terminal circuit MRAM and FeRAM are two-terminal circuits

2) Almost no short-channel effects Short-channel effects are most troublesome

3) Normally off Uncontrollable Vth high purity and intrinsic

Vth is controllable by channel doping with B

4) IonIoff ratio of 1020 IonIoff le 1010

5) nMOS onlyCMOS feasible with Si pMOS

CMOS Si nMOSSi pMOS

6) Bulk channel buried channel Shifting from surface-channel (planar) to bulk-channel (Fin)

35

4 30-nm Scaling of CAAC-IGZO FET

36

Trench Gate Self-aligned FET

L-direction W-direction

L-direction W-direction

CAAC-OS

Gate Electrode Gate Insulating Film

CAAC-OSDrain

ElectrodeSource

Electrode

Gate Electrode

Gate Insulating Film

48 nm

Gate Electrode

Gate Insulating Film

CAAC-OS34 nm

Source Electrode

Drain Electrode

CAAC-OS

Gate Insulating FilmGate Electrode

19 nm

50 nm

S-ch structure

FETrsquos active layer (CAAC-IGZO OS2 layer) is electrically surrounded by the gate electrodeWe call this FET structure a

surrounded-channel (S-ch) structure

37

Stacked Structure of OS FET and Si FET

pMOSSi

nMOSOS

GND

VDD

A Arsquo

B

Brsquo gate metal

source drain

gate insulator

CAAC-IGZO

electrode

gate

source drain

Si

SiO2

A Arsquo

B

Brsquo

OS FET

Si FET

High integration by stacking the CAAC-OS FET over the Si-FET

Si Substrate Si Substrate

W-directionL-direction

38

Comparison between CAAC-OS FET and Si nMOS FETItem CAAC-OS FET Si nMOS FET

1 Short-channel effect Small or none timesLarge (largest issue in Si NMOS FET)

2 Scaling le 30 nm (Possibility of 5 nm) Possible to ge 5 nm

3 Off-state current yAμm (10minus24 Aμm) times fAμm (10minus15 Aμm)

4 Mobility

Long channel Low High

Short channel Slightly decrease

Decrease (110 in 30-nm device)

5 Temperature characteristics

On-state current

Increase at high temperature

Decrease at high temperature

Off-state current Sufficiently low times

Drastically increase at high temperature

6 Drain breakdown voltage High Low7 Impact ionization Not observed Observed+2 +1 minus1 times minus2

39

Item CAAC-OS FET Si nMOS FET

8 Hot carrier degradation Not observed Large

9 Punch-through Not observed Strongly need balance with scaling

10 Frequency characteristics gt 30 GHz gt 300 GHz

11 Drift velocity Close to Si with channel length about 10 nm

Saturates with channel length about 100 nm

12 Sub-threshold value Small even with thick GI

Need thinner GI by miniaturizing

13 Dielectric anisotropy Observed Not observed

14 S-channel structure(Fin tri-gate type)

Extremely important and effective

Extremely important in shorter channel and effective

+25 minus1+2 +1 minus1 times minus2

Comparison between CAAC-OS FET and Si nMOS FET

40

5 CAAC-IGZO FET for LSI Application

41

Two-terminal circuit(diode)

Potential as Logic Circuit

Dependent control of input and output Need a transistor for four-terminal control Increased F2

Independently controllable inputs and outputs Desirable logic design Sufficiently low Ioff Practically an insulator

Four-terminal circuit

A B

C D

Input Output

42

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

1-1 History of CAAC-IGZO

1985 N Kimizuka synthesized IGZO for the first time in the world andrevealed its crystal structure1)

1987 Kimizuka proposed the use of IGZO as a semiconductor element2)

1995 J F M Cillessen at Philips proposed an oxide semiconductor (OS) FETincluding IGZO3)

20099 Yamazaki (SEL) discovered CAAC (Jpn Pat No 5211261)20115 SELrsquos NOSRAM4)

20116 SELrsquos image sensor5)

20137 SELrsquos FPGA6)

20139 A paper on 8-bit CPU by SEL7) was selected for SSDM Paper Award from more than 700 papers

20146 A paper on an 8K organic EL display by SEL8) received Distinguished Paper Award at SID Display Week 2014

1) N Kimizuka and T Mohri J Solid State Chem 60 382 (1985)2) Jpn Pat No 16393983) J F M Cillessen et al US Pat No 5744864 (1995)4) T Matsuzaki et al 3rd IEEE Int Memory Workshop pp185‐188 (2011)5) T Aoki et al Symp VLSI Technology Tech pp174‐175 (2011)

6) Y Okamoto et al ECS Trans 54(1) pp 141-149 (2013)7) T Ohmaru et al Ext Abstr Solid States Device and Materials

pp 1144-1145 (2012)8) S Kawashima et al SID Symp Digest 45 pp627-630 (2014)

4

5

1) Single-crystal IGZO was first synthesized in 1985 by Kimizuka (at National Institute for Research in Inorganic Materials) ITO ZnO and other oxide semiconductors have been widely used as conductive transparent oxides (CTOs) They have been studied since the 1980s for use in FETs especially thin-film transistors (TFTs)

2) SEL discovered a new crystal structure (CAAC-IGZO) in 2009 It is neither single-crystal nor amorphous CAAC-IGZO is characterized by no clear grain boundary being observedWe succeeded in paving the way for its first VLSI applicationby thoroughly seeking details as done for semiconductors We consider a c-axis-aligned a-b-plane-anchored crystal (CAAC)structure as a new crystal structure

1-2 Materials and Application (Device LSI System)

CAAC-IGZO has been comprehensively examined from the aspects of devices and application as well as materials

Device Process PropertiesFeatures

Material Defect control Thin-film formation Structure Film quality evaluation

Device Element structure examination

Process developmentCompatibility with existing Si LSI Device properties

Application

LSI

Combination of OSpassive element

Smaller F2

Challenge to scaling

OSSi hybrid3D structure

Development of process at le500C (400C)

Solution for scaling-related problems

System

IoT8K TV

Cell phone

Compatibility with interfaces of other systems by communication

means etc

Larger sizeShorter process

Logic circuit Super low power

6

2 What kind of crystal morphology does CAAC have

7

Discovered by SEL mass produced by Sharp

3 nm 3 nm

single crystalsingle crystal nano-crystalCAAC amorphous-like amorphous

Thickness 50 nm

CAAC nanocrystal

Classification of Oxide Semiconductor Materials

Thickness 50 nm

c-ax

is

Crystal structure of IGZO

88

2)

1) K Nomura T Kamiya H Ohta T Uruga M Hirano and H Hosono

Phys Rev B 75 035212 (2007) 2) Y Kurosawa et al

JSAP Autumn Meeting 2014 18p-A12-2

The simulation model of ldquoamorphous IGZO1)rdquo by Melt quench method

copyThe Japan Society of Applied Physics 2014

amorphous structure

Characteristics of CAAC-IGZO Film

Derived from quartz substrate

E-beam is incident parallel to the substrate surface

E-beam is incident perpendicularto the substrate surface

Rotation within (110) plane

Sample structure

electron diffraction (a-b plane)

X-ray diffraction (c-axis)

electron diffraction (c-axis)c-axis

a

b

Clear orientationNo orientation

Clearorientation

No orientation

CAAC c-axis-aligned a-b-plane-anchored crystalCAAC c-axis-aligned a-b-plane-anchored crystal

X-ray diffraction (a-b plane)

9

(d) CAAC crystal pellet (e) Cross-sectional image of unit pelletIn Ga or Zn O

(Chip)

Substrate

Cross-sectional TEM of CAAC-IGZO Film

08 nm

3 nm

(a) (b)TEM imageHR-TEM imageDetail of area in (a)

IGZO Film

Substrate

50 nm

10

平面TEM高分解能像FFT image processing-Extract data on a certain wavenumber range

Processing using an original program

Plan‐view TEM Crystal Lattice Image

FFT Filtered Image(FFTFast FourierTransform)

Lattice Extraction Image

Hexagonal Lattice Orientation Analysis amp

Color Mapping

Perfect regular hexagon

Neighboring lattice points(6 points)

Reference lattice point

1) Determine the orientation of a perfect regular hexagon so as to minimize the sum of the distances from the vertices of the perfect regular hexagon to six points neighboring a reference lattice point

Average distance a the average of distances from the reference lattice point to its neighboring six lattice points

2) Color each lattice point after the step 1) according to the difference from a reference angle In this study the modal angle was set to 30

6050403020100

ex

θ x

Average distance a

0 le θ lt 60

orientations of hexagons [degree]

Analysis Procedure Hexagonal LatticeOrientation Analysis amp Color Mapping

Processing using an original program

11

(a) A plan-view TEM image (b) A color mapping image obtained from an FFT filtered image of (a) The orientations of the hexagons are sorted by the angle (0minus60) and shown in different colors The colors of the adjoining grains are adjacent colors on the color scale

10 nm

(3)

(4)

(1)(2)

(a)

Plan-view Observations of CAAC-IGZO Film

(b)orientations of hexagons [degree]

60

50

40

30

20

10

0

12

(d)(a) (b) (c)

(d)(a) (c)(b)

(1)

(2)

Observations in Grain

Magnifying observations in a grain with a size of several tens of nanometers at the atomic level(a) Plan-view TEM images (b)(c) FFT filtered images (d) Color mapping imagesDotted lines denote boundaries between pellets Solid lines show a hexagon formed with lattice points

plan-view FFT filtered images color mapping

60

50

40

30

20

10

0

orientations of hexagons [degree]

Pellet

Hexagon formed with lattice points

Reg

ions

cor

resp

ondi

ng to

thos

e in

the

plan

-vie

w T

EM

imag

e of

the

wid

e ar

ea

13

In Ga or Zn O

066 nm

038 nm

ｚｚ

Side view of a unit cell

198 nm

181 nm

Surface of a unit cellHexagon formed with lattice points

07 nm

(Ga Zn)O

(Ga Zn)O

InO2

Homologous crystal structure

CAAC-OS pellet unit cellSemi hard material (a flexible crystal structure) by oxygen as a cushion between In Ga and Zn

Oxygen

Oxygen

14

Magnifying observations in a boundary portion between grains with a size of several tens of nanometers at the atomic level(a) Plan-view TEM images (b)(c) FFT filtered images (d) Color mapping imagesDeformed hexagons pentagons and heptagons are formed with lattice points at the boundary denoted by a dotted line and they are anchored to each other

Observations in Boundary Portion between Grains

60

50

40

30

20

10

0

orientations of hexagons [degree]

Boundary(3

)(4

)

plan-view FFT filtered images color mapping

(d)

(d)

(a)

(a) (c)

(b)

(b)

(c)R

egio

ns c

orre

spon

ding

to th

ose

in th

e pl

an-v

iew

TE

M im

age

of th

e w

ide

area

15

(a) and (c) Distribution of number of Voronoi polygons in single crystal IGZO and CAAC-IGZO (b) and (d) Distribution of Voronoi hexagons (yellow regions) and other polygons (blue regions) in the single crystal IGZO and the CAAC-IGZO

Distribution of Number of Voronoi Polygons

In the single crystal IGZO hexagonal Voronoi regions occupy almost the entire field of view In the CAAC-IGZO hexagons are the majority but pentagons and heptagons also appear

Single crystal IGZO CAAC-IGZOSingle crystal IGZO film [] CAAC-IGZO film []

Tetragon 01 07

Pentagon 12 155

Hexagon 982 683

Heptagon 04 145

Octagon 02 09

Nonagon 00 00

16

2 3 4 51

5 nmminus1

5 nmminus1

minus231degminus84degminus75 deg minus310degminus246deg

+118deg +15deg +135deg +04deg minus55deg2 3 4 51

(a)1 2 34 5

20 nm

(b) 12

3

4

5 20 nm

Panel (a) shows the points along the surface of the CAAC-IGZO film that were probed by NBED and the five remaining panels in the top row show the corresponding NBED patterns Panel (b) shows the points probed by NBED in the thickness of the film and the five remaining panels in the lower row show the corresponding NBED patterns The angle of the crystal axis is slightly shifted in both the surface and thickness directions

Nanobeam Electron Diffraction (NBED 1 nmɸ) Patterns of CAAC-IGZO Film

17

Nanobeam Electron Diffraction (NBED 1 nmɸ) Patterns of CAAC-IGZO Film

Broadanisotropic diffraction spots

Sharpcircular diffraction spots

The electron diffraction pattern of single-crystal IGZO has circular spots as shown in (b) Diffraction spots of CAAC-IGZO are not circular but anisotropic and broad

18

Schematic Band Diagram of IGZOSimple schematic diagram of defect levels in IGZO film

elec

tron

ener

gy [e

V]

surface shallow DOS(sDOS)

bulk shallow DOS(sDOS)

bulk deep DOS(dDOS)

Density of States (DOS) of IGZO

19

28-32 eV

Silicon oxide IGZO

CAAC-IGZO63 (gcm3)

nc-IGZO61 (gcm3)

a-like IGZO59 (gcm3)

αCPM Absorption coefficient estimated by a constant photocurrent method (CPM)

N Ishihara et al Proc AM-FPD12 143 (2012)J Koezuka et al SID2013 Symposium Digest 723 (2013)

A high density of deep-level states (dDOS) exists in the low-density IGZO filmThe higher the film density is (like CAAC) the lower the dDOS is

Light absorptions by IGZO films with different crystal structureswere measured to quantify the densities of deep energy trapstates (dDOS)

Density of States (DOS) of IGZO

a-like IGZO 53 times 100

20

Formation of Oxygen Vacancies (VO) in IGZO

software VASP

exchange correlation function

GGA

pseudo potential PAW

cut-off energy 800 eV

k-point 1times1times1VO are

likely to be formed

Crystal Amorphous

In Ga Zn O

-1180

-1178

-1176

-1174

-1172

-15 -10 -5 0 5 10 15

Tota

l Ene

rgy

[eV]

Distance from Interface [Aring]

InterfaceInterface

VO are highly likely to be formed

A comparison of formation of oxygen vacancies (VO) between amorphous and crystal structures was made by first-principles calculation The results indicate that VO are easily formed in the amorphous structure

21

Features of CAAC-IGZO as MaterialCAAC-IGZO c-Si

1)CAAC structure (not single-crystal nano-crystalline or amorphous)rarr No clear grain boundary is observed

lattice points to form a pentagon and heptagon

Single crystal is preferable because polycrystal has a high concentration of defects at grain boundaries2)

Crystal grains (pellets) are anchored to each other to form one big crystalrarr It can be used in VLSI devices on the scale of 5ndash60 nm

3) Not a close-packed structure rather has cushion propertiesA cubic dense structure Doped with B or P Formed by crystal pulling at approx 1420C4)

Although single-crystal IGZO is formed at very high temperatures of 1200ndash1500C CAAC-IGZO can be formed at 100ndash500C by sputteringrarr It can be placed between Si LSI and metal wire layers

5) Homologous layered structure (Semi hard structure) Diamond structure(hard)

6) Composed of four elements (In Ga Zn and O) Si alone

22

3 Performance of CAAC-IGZO FET

23

IdndashVg characteristics and mobilities of CAAC-IGZO FETs with channel lengths of (a) 2 μm and (b) 6 μm The channel widths are 50 μm

It may be possible to apply all kinds of displays (TV smartphone PC by using OEL LCD)

L = 2 μm (W = 50 μm) L = 6 μm (W = 50 μm)

High-mobility CAAC-IGZO FETs

24

(a) (b)

CAAC-IGZO TrIoff = 1times10minus22 Aμm

(100 yAμm)IonIoff = 1018

IndashV characteristics of CAAC-IGZO and Si transistors

Si TrIoff = 1times10minus12 Aμm

(1 pAμm)IonIoff = 109

Off-state Current of CAAC-IGZO and Si FETsUnit

zA (10minus21)

yA (10minus24)

aA (10minus18)

fA (10minus15)

pA (10minus12)

nA (10minus9)

μA (10minus6)

mA (10minus3)

25

How to Measure Off-state Current60

0 μm

360 μm L = 044 μmW = 10 mm(50 μmtimes200)Tox = 20 nm

A huge transistor with a channel width of 10 mm for off-state leakage current measurement (optical micrograph)

Concept of measurement

Node FN(Vout)

Behavior of potential at node FN (Vout) over time

Measuredtransistor

26

Arrhenius plot of off-state leakage current1)Change of Vout measured over time

1) S Yamazaki et al Jpn J Appl Phys vol 53 pp 04ED18 (2014)

At a gate voltage of minus3 V and 85Cthe off-state leakage current was 6 yAm (1 yA = 10minus24 A)Nonvolatility for 10 years at 85C is ensured

Off-state CurrentUnitAμm

mA (10minus3)μA (10minus6)nA (10minus9)pA (10minus12)fA (10minus15)aA (10minus18)zA (10minus21)yA (10minus24)Le

akag

e cu

rrent

[Aμ

m]

27

-5

0

5

10

15

20

25

30

RF

Gai

n [d

B]

周波数[Hz]109 1010 101130 GHz

Vd = 20 VVg = 20 V( gm max )

WL = 18 μm30 nm

Operation with a cutoff frequency of about 30 GHz is demonstratedThe off-state leakage current of an OS FET (W = 60 nm) is expected at 100 zA or less at 85C even for a 30-nm-node FET

Lower measurement limit

High Cutoff Frequency and Low Off-state Current (30 nm)

28

Frequency [Hz]30 GHz

LW = 30 18000 (60 nmtimes300 Parallel) nm

Short-channel Characteristics of OS FETs

Favorable FET characteristics were obtained with a 11-nm-thick gate insulating film when L = 32 nm

The graphs show that OS FETs are resistant to short-channel effects This is probably because they have a ldquosurrounded-channel (S-ch) structure with a thin active layerrdquo and

are ldquoaccumulation-mode devicesrdquo and ldquoCAAC-IGZO has dielectric anisotropyrdquo(S-ch structure an FET structure where the active layer is electrically surrounded by the gate electrode)

GI = 11 nm

29

0

5

10

15

20

001 01 1 10 100

μ FE

[cm

2middotV-1

middot s-1]

チャネル長 [μm]

理論

Planar TypeS‐ch Type

0

200

400

600

001 01 1 10 100

μ FE

[cm

2 middotV-1

middots-1

]チャネル長 [μm]

理論

Planar Type

Short-channel Characteristics of OS FETs

Channel length dependence of field-effect mobility

(single-crystal Si FET)

Channel length dependence of field-effect mobility

（CAAC‐IGZO FET)

The field-effect mobility (μFE) of a CAAC-IGZO FET with a reduced channel length is close to that of a single-crystal Si FET with the same size

μ FE[

cm2 V

-1s

-1]

Channel length

0

20

5

10

15

10 nm 100 nm 1 μm 100 μm10 μm 10 nm 100 nm 1 μm 100 μm10 μm

Channel length

0

600

200

400

μ FE[

cm2 V

-1s

-1]

Theoretical Theoretical

30

Temperature Dependence of CAAC-IGZO FET

OS-FET

編集中編集中

L=048um GI=20nm

Vth

S値

ID_VG特性

単結晶 p-ch Si Tr （SOI）

L=035um GI=20nm L=035um GI=20nm

編集中 編集中

単結晶 n-ch Si Tr （SOI）

‐05

00

05

10

15

0 50 100 150 200 250

Vth[V]

基板温度 []

0

50

100

150

200

250

300

0 50 100 150 200 250

S‐Value[mVdec]

基板温度 []

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

Vg [V]

250

‐05

0

05

1

15

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

‐15

‐1

‐05

0

05

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

T = minus40C minus 25C 0C 25C 50C 100C 150C 200C 250C

CAAC-OS FETs have a sufficient onoff ratio even at 200C or higherThe S-value shows little change (or is constant) compared with Si FETs

Single‐crystal n‐ch Tr (SOI) Single‐crystal p‐ch Tr (SOI)OS FET

ID‐VGCharac‐teristics

Vth

S‐value

Substrate temperature [C] Substrate temperature [C] Substrate temperature [C]

Substrate temperature [C]Substrate temperature [C]Substrate temperature [C]

31

1E-07

1E-06

1E-05

1E-04

1E-03

1E-02

0 5 10 15 20 25 30V D [V]

ID [A

]Si transistorL =09um T ox=20nm

IGZO transistorL =09um T ox=20nm

4V 26V

L ＝ 09 μm W ＝ 10 μm TOX = 20 nm VG ＝ 2 V

n = 2

CAAC-IGZO transistors have a higher breakdown voltage than Si transistorsNo hot carrier degradation and avalanche breakdown are observed

Breakdown Voltage of CAAC-IGZO and Si FETs

32

Schematic Band Diagram of Channel Regionmdash OS FET vs n-ch Si FET

Inversion Depletion Accumulation

Vg gt 0 V (ON State) Vg lt 0 V (OFF State)Vg = 0V

CAAC-IGZO(S-channel)

n-ch Si

OS2CAAC-IGZO

OS3Gate E

GI GI

Gate E

Gate E

GI

Si

EC

EV

Ef

EfEC

EV

Eg=32eV

Eg=12eV

ElectronsA Arsquo

OS3

Holes

A ArsquoA Arsquo

33

M Murakami et al Proc AM-FPDrsquo12 Digest p 174 (2012)

CAAC-IGZO c-Si

1) Bandgap (Eg) 28ndash32 eV 112 eV

2) Intrinsic carrierconcentration 10minus9 cm3 10+11 cm3

3) Depletion layer km order μm order

4) Electron effective mass (meme)

023ndash025 019 (transverse)098 (longitudinal)

5) Hole effective mass (mhme)

11ndash40 016 (light)049 (heavy)

6) Structure Layered structure(Homologous) Diamond cubic

7) Conductivity i-type n-type n-type p-type

Comparison of Physical Properties between CAAC-IGZO and c-Si

34

Features of CAAC-IGZO as Device

CAAC‐IGZO c‐Si

1) Four-terminal circuitFour-terminal circuit MRAM and FeRAM are two-terminal circuits

2) Almost no short-channel effects Short-channel effects are most troublesome

3) Normally off Uncontrollable Vth high purity and intrinsic

Vth is controllable by channel doping with B

4) IonIoff ratio of 1020 IonIoff le 1010

5) nMOS onlyCMOS feasible with Si pMOS

CMOS Si nMOSSi pMOS

6) Bulk channel buried channel Shifting from surface-channel (planar) to bulk-channel (Fin)

35

4 30-nm Scaling of CAAC-IGZO FET

36

Trench Gate Self-aligned FET

L-direction W-direction

L-direction W-direction

CAAC-OS

Gate Electrode Gate Insulating Film

CAAC-OSDrain

ElectrodeSource

Electrode

Gate Electrode

Gate Insulating Film

48 nm

Gate Electrode

Gate Insulating Film

CAAC-OS34 nm

Source Electrode

Drain Electrode

CAAC-OS

Gate Insulating FilmGate Electrode

19 nm

50 nm

S-ch structure

FETrsquos active layer (CAAC-IGZO OS2 layer) is electrically surrounded by the gate electrodeWe call this FET structure a

surrounded-channel (S-ch) structure

37

Stacked Structure of OS FET and Si FET

pMOSSi

nMOSOS

GND

VDD

A Arsquo

B

Brsquo gate metal

source drain

gate insulator

CAAC-IGZO

electrode

gate

source drain

Si

SiO2

A Arsquo

B

Brsquo

OS FET

Si FET

High integration by stacking the CAAC-OS FET over the Si-FET

Si Substrate Si Substrate

W-directionL-direction

38

Comparison between CAAC-OS FET and Si nMOS FETItem CAAC-OS FET Si nMOS FET

1 Short-channel effect Small or none timesLarge (largest issue in Si NMOS FET)

2 Scaling le 30 nm (Possibility of 5 nm) Possible to ge 5 nm

3 Off-state current yAμm (10minus24 Aμm) times fAμm (10minus15 Aμm)

4 Mobility

Long channel Low High

Short channel Slightly decrease

Decrease (110 in 30-nm device)

5 Temperature characteristics

On-state current

Increase at high temperature

Decrease at high temperature

Off-state current Sufficiently low times

Drastically increase at high temperature

6 Drain breakdown voltage High Low7 Impact ionization Not observed Observed+2 +1 minus1 times minus2

39

Item CAAC-OS FET Si nMOS FET

8 Hot carrier degradation Not observed Large

9 Punch-through Not observed Strongly need balance with scaling

10 Frequency characteristics gt 30 GHz gt 300 GHz

11 Drift velocity Close to Si with channel length about 10 nm

Saturates with channel length about 100 nm

12 Sub-threshold value Small even with thick GI

Need thinner GI by miniaturizing

13 Dielectric anisotropy Observed Not observed

14 S-channel structure(Fin tri-gate type)

Extremely important and effective

Extremely important in shorter channel and effective

+25 minus1+2 +1 minus1 times minus2

Comparison between CAAC-OS FET and Si nMOS FET

40

5 CAAC-IGZO FET for LSI Application

41

Two-terminal circuit(diode)

Potential as Logic Circuit

Dependent control of input and output Need a transistor for four-terminal control Increased F2

Independently controllable inputs and outputs Desirable logic design Sufficiently low Ioff Practically an insulator

Four-terminal circuit

A B

C D

Input Output

42

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

5

1) Single-crystal IGZO was first synthesized in 1985 by Kimizuka (at National Institute for Research in Inorganic Materials) ITO ZnO and other oxide semiconductors have been widely used as conductive transparent oxides (CTOs) They have been studied since the 1980s for use in FETs especially thin-film transistors (TFTs)

2) SEL discovered a new crystal structure (CAAC-IGZO) in 2009 It is neither single-crystal nor amorphous CAAC-IGZO is characterized by no clear grain boundary being observedWe succeeded in paving the way for its first VLSI applicationby thoroughly seeking details as done for semiconductors We consider a c-axis-aligned a-b-plane-anchored crystal (CAAC)structure as a new crystal structure

1-2 Materials and Application (Device LSI System)

CAAC-IGZO has been comprehensively examined from the aspects of devices and application as well as materials

Device Process PropertiesFeatures

Material Defect control Thin-film formation Structure Film quality evaluation

Device Element structure examination

Process developmentCompatibility with existing Si LSI Device properties

Application

LSI

Combination of OSpassive element

Smaller F2

Challenge to scaling

OSSi hybrid3D structure

Development of process at le500C (400C)

Solution for scaling-related problems

System

IoT8K TV

Cell phone

Compatibility with interfaces of other systems by communication

means etc

Larger sizeShorter process

Logic circuit Super low power

6

2 What kind of crystal morphology does CAAC have

7

Discovered by SEL mass produced by Sharp

3 nm 3 nm

single crystalsingle crystal nano-crystalCAAC amorphous-like amorphous

Thickness 50 nm

CAAC nanocrystal

Classification of Oxide Semiconductor Materials

Thickness 50 nm

c-ax

is

Crystal structure of IGZO

88

2)

1) K Nomura T Kamiya H Ohta T Uruga M Hirano and H Hosono

Phys Rev B 75 035212 (2007) 2) Y Kurosawa et al

JSAP Autumn Meeting 2014 18p-A12-2

The simulation model of ldquoamorphous IGZO1)rdquo by Melt quench method

copyThe Japan Society of Applied Physics 2014

amorphous structure

Characteristics of CAAC-IGZO Film

Derived from quartz substrate

E-beam is incident parallel to the substrate surface

E-beam is incident perpendicularto the substrate surface

Rotation within (110) plane

Sample structure

electron diffraction (a-b plane)

X-ray diffraction (c-axis)

electron diffraction (c-axis)c-axis

a

b

Clear orientationNo orientation

Clearorientation

No orientation

CAAC c-axis-aligned a-b-plane-anchored crystalCAAC c-axis-aligned a-b-plane-anchored crystal

X-ray diffraction (a-b plane)

9

(d) CAAC crystal pellet (e) Cross-sectional image of unit pelletIn Ga or Zn O

(Chip)

Substrate

Cross-sectional TEM of CAAC-IGZO Film

08 nm

3 nm

(a) (b)TEM imageHR-TEM imageDetail of area in (a)

IGZO Film

Substrate

50 nm

10

平面TEM高分解能像FFT image processing-Extract data on a certain wavenumber range

Processing using an original program

Plan‐view TEM Crystal Lattice Image

FFT Filtered Image(FFTFast FourierTransform)

Lattice Extraction Image

Hexagonal Lattice Orientation Analysis amp

Color Mapping

Perfect regular hexagon

Neighboring lattice points(6 points)

Reference lattice point

1) Determine the orientation of a perfect regular hexagon so as to minimize the sum of the distances from the vertices of the perfect regular hexagon to six points neighboring a reference lattice point

Average distance a the average of distances from the reference lattice point to its neighboring six lattice points

2) Color each lattice point after the step 1) according to the difference from a reference angle In this study the modal angle was set to 30

6050403020100

ex

θ x

Average distance a

0 le θ lt 60

orientations of hexagons [degree]

Analysis Procedure Hexagonal LatticeOrientation Analysis amp Color Mapping

Processing using an original program

11

(a) A plan-view TEM image (b) A color mapping image obtained from an FFT filtered image of (a) The orientations of the hexagons are sorted by the angle (0minus60) and shown in different colors The colors of the adjoining grains are adjacent colors on the color scale

10 nm

(3)

(4)

(1)(2)

(a)

Plan-view Observations of CAAC-IGZO Film

(b)orientations of hexagons [degree]

60

50

40

30

20

10

0

12

(d)(a) (b) (c)

(d)(a) (c)(b)

(1)

(2)

Observations in Grain

Magnifying observations in a grain with a size of several tens of nanometers at the atomic level(a) Plan-view TEM images (b)(c) FFT filtered images (d) Color mapping imagesDotted lines denote boundaries between pellets Solid lines show a hexagon formed with lattice points

plan-view FFT filtered images color mapping

60

50

40

30

20

10

0

orientations of hexagons [degree]

Pellet

Hexagon formed with lattice points

Reg

ions

cor

resp

ondi

ng to

thos

e in

the

plan

-vie

w T

EM

imag

e of

the

wid

e ar

ea

13

In Ga or Zn O

066 nm

038 nm

ｚｚ

Side view of a unit cell

198 nm

181 nm

Surface of a unit cellHexagon formed with lattice points

07 nm

(Ga Zn)O

(Ga Zn)O

InO2

Homologous crystal structure

CAAC-OS pellet unit cellSemi hard material (a flexible crystal structure) by oxygen as a cushion between In Ga and Zn

Oxygen

Oxygen

14

Magnifying observations in a boundary portion between grains with a size of several tens of nanometers at the atomic level(a) Plan-view TEM images (b)(c) FFT filtered images (d) Color mapping imagesDeformed hexagons pentagons and heptagons are formed with lattice points at the boundary denoted by a dotted line and they are anchored to each other

Observations in Boundary Portion between Grains

60

50

40

30

20

10

0

orientations of hexagons [degree]

Boundary(3

)(4

)

plan-view FFT filtered images color mapping

(d)

(d)

(a)

(a) (c)

(b)

(b)

(c)R

egio

ns c

orre

spon

ding

to th

ose

in th

e pl

an-v

iew

TE

M im

age

of th

e w

ide

area

15

(a) and (c) Distribution of number of Voronoi polygons in single crystal IGZO and CAAC-IGZO (b) and (d) Distribution of Voronoi hexagons (yellow regions) and other polygons (blue regions) in the single crystal IGZO and the CAAC-IGZO

Distribution of Number of Voronoi Polygons

In the single crystal IGZO hexagonal Voronoi regions occupy almost the entire field of view In the CAAC-IGZO hexagons are the majority but pentagons and heptagons also appear

Single crystal IGZO CAAC-IGZOSingle crystal IGZO film [] CAAC-IGZO film []

Tetragon 01 07

Pentagon 12 155

Hexagon 982 683

Heptagon 04 145

Octagon 02 09

Nonagon 00 00

16

2 3 4 51

5 nmminus1

5 nmminus1

minus231degminus84degminus75 deg minus310degminus246deg

+118deg +15deg +135deg +04deg minus55deg2 3 4 51

(a)1 2 34 5

20 nm

(b) 12

3

4

5 20 nm

Panel (a) shows the points along the surface of the CAAC-IGZO film that were probed by NBED and the five remaining panels in the top row show the corresponding NBED patterns Panel (b) shows the points probed by NBED in the thickness of the film and the five remaining panels in the lower row show the corresponding NBED patterns The angle of the crystal axis is slightly shifted in both the surface and thickness directions

Nanobeam Electron Diffraction (NBED 1 nmɸ) Patterns of CAAC-IGZO Film

17

Nanobeam Electron Diffraction (NBED 1 nmɸ) Patterns of CAAC-IGZO Film

Broadanisotropic diffraction spots

Sharpcircular diffraction spots

The electron diffraction pattern of single-crystal IGZO has circular spots as shown in (b) Diffraction spots of CAAC-IGZO are not circular but anisotropic and broad

18

Schematic Band Diagram of IGZOSimple schematic diagram of defect levels in IGZO film

elec

tron

ener

gy [e

V]

surface shallow DOS(sDOS)

bulk shallow DOS(sDOS)

bulk deep DOS(dDOS)

Density of States (DOS) of IGZO

19

28-32 eV

Silicon oxide IGZO

CAAC-IGZO63 (gcm3)

nc-IGZO61 (gcm3)

a-like IGZO59 (gcm3)

αCPM Absorption coefficient estimated by a constant photocurrent method (CPM)

N Ishihara et al Proc AM-FPD12 143 (2012)J Koezuka et al SID2013 Symposium Digest 723 (2013)

A high density of deep-level states (dDOS) exists in the low-density IGZO filmThe higher the film density is (like CAAC) the lower the dDOS is

Light absorptions by IGZO films with different crystal structureswere measured to quantify the densities of deep energy trapstates (dDOS)

Density of States (DOS) of IGZO

a-like IGZO 53 times 100

20

Formation of Oxygen Vacancies (VO) in IGZO

software VASP

exchange correlation function

GGA

pseudo potential PAW

cut-off energy 800 eV

k-point 1times1times1VO are

likely to be formed

Crystal Amorphous

In Ga Zn O

-1180

-1178

-1176

-1174

-1172

-15 -10 -5 0 5 10 15

Tota

l Ene

rgy

[eV]

Distance from Interface [Aring]

InterfaceInterface

VO are highly likely to be formed

A comparison of formation of oxygen vacancies (VO) between amorphous and crystal structures was made by first-principles calculation The results indicate that VO are easily formed in the amorphous structure

21

Features of CAAC-IGZO as MaterialCAAC-IGZO c-Si

1)CAAC structure (not single-crystal nano-crystalline or amorphous)rarr No clear grain boundary is observed

lattice points to form a pentagon and heptagon

Single crystal is preferable because polycrystal has a high concentration of defects at grain boundaries2)

Crystal grains (pellets) are anchored to each other to form one big crystalrarr It can be used in VLSI devices on the scale of 5ndash60 nm

3) Not a close-packed structure rather has cushion propertiesA cubic dense structure Doped with B or P Formed by crystal pulling at approx 1420C4)

Although single-crystal IGZO is formed at very high temperatures of 1200ndash1500C CAAC-IGZO can be formed at 100ndash500C by sputteringrarr It can be placed between Si LSI and metal wire layers

5) Homologous layered structure (Semi hard structure) Diamond structure(hard)

6) Composed of four elements (In Ga Zn and O) Si alone

22

3 Performance of CAAC-IGZO FET

23

IdndashVg characteristics and mobilities of CAAC-IGZO FETs with channel lengths of (a) 2 μm and (b) 6 μm The channel widths are 50 μm

It may be possible to apply all kinds of displays (TV smartphone PC by using OEL LCD)

L = 2 μm (W = 50 μm) L = 6 μm (W = 50 μm)

High-mobility CAAC-IGZO FETs

24

(a) (b)

CAAC-IGZO TrIoff = 1times10minus22 Aμm

(100 yAμm)IonIoff = 1018

IndashV characteristics of CAAC-IGZO and Si transistors

Si TrIoff = 1times10minus12 Aμm

(1 pAμm)IonIoff = 109

Off-state Current of CAAC-IGZO and Si FETsUnit

zA (10minus21)

yA (10minus24)

aA (10minus18)

fA (10minus15)

pA (10minus12)

nA (10minus9)

μA (10minus6)

mA (10minus3)

25

How to Measure Off-state Current60

0 μm

360 μm L = 044 μmW = 10 mm(50 μmtimes200)Tox = 20 nm

A huge transistor with a channel width of 10 mm for off-state leakage current measurement (optical micrograph)

Concept of measurement

Node FN(Vout)

Behavior of potential at node FN (Vout) over time

Measuredtransistor

26

Arrhenius plot of off-state leakage current1)Change of Vout measured over time

1) S Yamazaki et al Jpn J Appl Phys vol 53 pp 04ED18 (2014)

At a gate voltage of minus3 V and 85Cthe off-state leakage current was 6 yAm (1 yA = 10minus24 A)Nonvolatility for 10 years at 85C is ensured

Off-state CurrentUnitAμm

mA (10minus3)μA (10minus6)nA (10minus9)pA (10minus12)fA (10minus15)aA (10minus18)zA (10minus21)yA (10minus24)Le

akag

e cu

rrent

[Aμ

m]

27

-5

0

5

10

15

20

25

30

RF

Gai

n [d

B]

周波数[Hz]109 1010 101130 GHz

Vd = 20 VVg = 20 V( gm max )

WL = 18 μm30 nm

Operation with a cutoff frequency of about 30 GHz is demonstratedThe off-state leakage current of an OS FET (W = 60 nm) is expected at 100 zA or less at 85C even for a 30-nm-node FET

Lower measurement limit

High Cutoff Frequency and Low Off-state Current (30 nm)

28

Frequency [Hz]30 GHz

LW = 30 18000 (60 nmtimes300 Parallel) nm

Short-channel Characteristics of OS FETs

Favorable FET characteristics were obtained with a 11-nm-thick gate insulating film when L = 32 nm

The graphs show that OS FETs are resistant to short-channel effects This is probably because they have a ldquosurrounded-channel (S-ch) structure with a thin active layerrdquo and

are ldquoaccumulation-mode devicesrdquo and ldquoCAAC-IGZO has dielectric anisotropyrdquo(S-ch structure an FET structure where the active layer is electrically surrounded by the gate electrode)

GI = 11 nm

29

0

5

10

15

20

001 01 1 10 100

μ FE

[cm

2middotV-1

middot s-1]

チャネル長 [μm]

理論

Planar TypeS‐ch Type

0

200

400

600

001 01 1 10 100

μ FE

[cm

2 middotV-1

middots-1

]チャネル長 [μm]

理論

Planar Type

Short-channel Characteristics of OS FETs

Channel length dependence of field-effect mobility

(single-crystal Si FET)

Channel length dependence of field-effect mobility

（CAAC‐IGZO FET)

The field-effect mobility (μFE) of a CAAC-IGZO FET with a reduced channel length is close to that of a single-crystal Si FET with the same size

μ FE[

cm2 V

-1s

-1]

Channel length

0

20

5

10

15

10 nm 100 nm 1 μm 100 μm10 μm 10 nm 100 nm 1 μm 100 μm10 μm

Channel length

0

600

200

400

μ FE[

cm2 V

-1s

-1]

Theoretical Theoretical

30

Temperature Dependence of CAAC-IGZO FET

OS-FET

編集中編集中

L=048um GI=20nm

Vth

S値

ID_VG特性

単結晶 p-ch Si Tr （SOI）

L=035um GI=20nm L=035um GI=20nm

編集中 編集中

単結晶 n-ch Si Tr （SOI）

‐05

00

05

10

15

0 50 100 150 200 250

Vth[V]

基板温度 []

0

50

100

150

200

250

300

0 50 100 150 200 250

S‐Value[mVdec]

基板温度 []

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

Vg [V]

250

‐05

0

05

1

15

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

‐15

‐1

‐05

0

05

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

T = minus40C minus 25C 0C 25C 50C 100C 150C 200C 250C

CAAC-OS FETs have a sufficient onoff ratio even at 200C or higherThe S-value shows little change (or is constant) compared with Si FETs

Single‐crystal n‐ch Tr (SOI) Single‐crystal p‐ch Tr (SOI)OS FET

ID‐VGCharac‐teristics

Vth

S‐value

Substrate temperature [C] Substrate temperature [C] Substrate temperature [C]

Substrate temperature [C]Substrate temperature [C]Substrate temperature [C]

31

1E-07

1E-06

1E-05

1E-04

1E-03

1E-02

0 5 10 15 20 25 30V D [V]

ID [A

]Si transistorL =09um T ox=20nm

IGZO transistorL =09um T ox=20nm

4V 26V

L ＝ 09 μm W ＝ 10 μm TOX = 20 nm VG ＝ 2 V

n = 2

CAAC-IGZO transistors have a higher breakdown voltage than Si transistorsNo hot carrier degradation and avalanche breakdown are observed

Breakdown Voltage of CAAC-IGZO and Si FETs

32

Schematic Band Diagram of Channel Regionmdash OS FET vs n-ch Si FET

Inversion Depletion Accumulation

Vg gt 0 V (ON State) Vg lt 0 V (OFF State)Vg = 0V

CAAC-IGZO(S-channel)

n-ch Si

OS2CAAC-IGZO

OS3Gate E

GI GI

Gate E

Gate E

GI

Si

EC

EV

Ef

EfEC

EV

Eg=32eV

Eg=12eV

ElectronsA Arsquo

OS3

Holes

A ArsquoA Arsquo

33

M Murakami et al Proc AM-FPDrsquo12 Digest p 174 (2012)

CAAC-IGZO c-Si

1) Bandgap (Eg) 28ndash32 eV 112 eV

2) Intrinsic carrierconcentration 10minus9 cm3 10+11 cm3

3) Depletion layer km order μm order

4) Electron effective mass (meme)

023ndash025 019 (transverse)098 (longitudinal)

5) Hole effective mass (mhme)

11ndash40 016 (light)049 (heavy)

6) Structure Layered structure(Homologous) Diamond cubic

7) Conductivity i-type n-type n-type p-type

Comparison of Physical Properties between CAAC-IGZO and c-Si

34

Features of CAAC-IGZO as Device

CAAC‐IGZO c‐Si

1) Four-terminal circuitFour-terminal circuit MRAM and FeRAM are two-terminal circuits

2) Almost no short-channel effects Short-channel effects are most troublesome

3) Normally off Uncontrollable Vth high purity and intrinsic

Vth is controllable by channel doping with B

4) IonIoff ratio of 1020 IonIoff le 1010

5) nMOS onlyCMOS feasible with Si pMOS

CMOS Si nMOSSi pMOS

6) Bulk channel buried channel Shifting from surface-channel (planar) to bulk-channel (Fin)

35

4 30-nm Scaling of CAAC-IGZO FET

36

Trench Gate Self-aligned FET

L-direction W-direction

L-direction W-direction

CAAC-OS

Gate Electrode Gate Insulating Film

CAAC-OSDrain

ElectrodeSource

Electrode

Gate Electrode

Gate Insulating Film

48 nm

Gate Electrode

Gate Insulating Film

CAAC-OS34 nm

Source Electrode

Drain Electrode

CAAC-OS

Gate Insulating FilmGate Electrode

19 nm

50 nm

S-ch structure

FETrsquos active layer (CAAC-IGZO OS2 layer) is electrically surrounded by the gate electrodeWe call this FET structure a

surrounded-channel (S-ch) structure

37

Stacked Structure of OS FET and Si FET

pMOSSi

nMOSOS

GND

VDD

A Arsquo

B

Brsquo gate metal

source drain

gate insulator

CAAC-IGZO

electrode

gate

source drain

Si

SiO2

A Arsquo

B

Brsquo

OS FET

Si FET

High integration by stacking the CAAC-OS FET over the Si-FET

Si Substrate Si Substrate

W-directionL-direction

38

Comparison between CAAC-OS FET and Si nMOS FETItem CAAC-OS FET Si nMOS FET

1 Short-channel effect Small or none timesLarge (largest issue in Si NMOS FET)

2 Scaling le 30 nm (Possibility of 5 nm) Possible to ge 5 nm

3 Off-state current yAμm (10minus24 Aμm) times fAμm (10minus15 Aμm)

4 Mobility

Long channel Low High

Short channel Slightly decrease

Decrease (110 in 30-nm device)

5 Temperature characteristics

On-state current

Increase at high temperature

Decrease at high temperature

Off-state current Sufficiently low times

Drastically increase at high temperature

6 Drain breakdown voltage High Low7 Impact ionization Not observed Observed+2 +1 minus1 times minus2

39

Item CAAC-OS FET Si nMOS FET

8 Hot carrier degradation Not observed Large

9 Punch-through Not observed Strongly need balance with scaling

10 Frequency characteristics gt 30 GHz gt 300 GHz

11 Drift velocity Close to Si with channel length about 10 nm

Saturates with channel length about 100 nm

12 Sub-threshold value Small even with thick GI

Need thinner GI by miniaturizing

13 Dielectric anisotropy Observed Not observed

14 S-channel structure(Fin tri-gate type)

Extremely important and effective

Extremely important in shorter channel and effective

+25 minus1+2 +1 minus1 times minus2

Comparison between CAAC-OS FET and Si nMOS FET

40

5 CAAC-IGZO FET for LSI Application

41

Two-terminal circuit(diode)

Potential as Logic Circuit

Dependent control of input and output Need a transistor for four-terminal control Increased F2

Independently controllable inputs and outputs Desirable logic design Sufficiently low Ioff Practically an insulator

Four-terminal circuit

A B

C D

Input Output

42

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

1-2 Materials and Application (Device LSI System)

CAAC-IGZO has been comprehensively examined from the aspects of devices and application as well as materials

Device Process PropertiesFeatures

Material Defect control Thin-film formation Structure Film quality evaluation

Device Element structure examination

Process developmentCompatibility with existing Si LSI Device properties

Application

LSI

Combination of OSpassive element

Smaller F2

Challenge to scaling

OSSi hybrid3D structure

Development of process at le500C (400C)

Solution for scaling-related problems

System

IoT8K TV

Cell phone

Compatibility with interfaces of other systems by communication

means etc

Larger sizeShorter process

Logic circuit Super low power

6

2 What kind of crystal morphology does CAAC have

7

Discovered by SEL mass produced by Sharp

3 nm 3 nm

single crystalsingle crystal nano-crystalCAAC amorphous-like amorphous

Thickness 50 nm

CAAC nanocrystal

Classification of Oxide Semiconductor Materials

Thickness 50 nm

c-ax

is

Crystal structure of IGZO

88

2)

1) K Nomura T Kamiya H Ohta T Uruga M Hirano and H Hosono

Phys Rev B 75 035212 (2007) 2) Y Kurosawa et al

JSAP Autumn Meeting 2014 18p-A12-2

The simulation model of ldquoamorphous IGZO1)rdquo by Melt quench method

copyThe Japan Society of Applied Physics 2014

amorphous structure

Characteristics of CAAC-IGZO Film

Derived from quartz substrate

E-beam is incident parallel to the substrate surface

E-beam is incident perpendicularto the substrate surface

Rotation within (110) plane

Sample structure

electron diffraction (a-b plane)

X-ray diffraction (c-axis)

electron diffraction (c-axis)c-axis

a

b

Clear orientationNo orientation

Clearorientation

No orientation

CAAC c-axis-aligned a-b-plane-anchored crystalCAAC c-axis-aligned a-b-plane-anchored crystal

X-ray diffraction (a-b plane)

9

(d) CAAC crystal pellet (e) Cross-sectional image of unit pelletIn Ga or Zn O

(Chip)

Substrate

Cross-sectional TEM of CAAC-IGZO Film

08 nm

3 nm

(a) (b)TEM imageHR-TEM imageDetail of area in (a)

IGZO Film

Substrate

50 nm

10

平面TEM高分解能像FFT image processing-Extract data on a certain wavenumber range

Processing using an original program

Plan‐view TEM Crystal Lattice Image

FFT Filtered Image(FFTFast FourierTransform)

Lattice Extraction Image

Hexagonal Lattice Orientation Analysis amp

Color Mapping

Perfect regular hexagon

Neighboring lattice points(6 points)

Reference lattice point

1) Determine the orientation of a perfect regular hexagon so as to minimize the sum of the distances from the vertices of the perfect regular hexagon to six points neighboring a reference lattice point

Average distance a the average of distances from the reference lattice point to its neighboring six lattice points

2) Color each lattice point after the step 1) according to the difference from a reference angle In this study the modal angle was set to 30

6050403020100

ex

θ x

Average distance a

0 le θ lt 60

orientations of hexagons [degree]

Analysis Procedure Hexagonal LatticeOrientation Analysis amp Color Mapping

Processing using an original program

11

(a) A plan-view TEM image (b) A color mapping image obtained from an FFT filtered image of (a) The orientations of the hexagons are sorted by the angle (0minus60) and shown in different colors The colors of the adjoining grains are adjacent colors on the color scale

10 nm

(3)

(4)

(1)(2)

(a)

Plan-view Observations of CAAC-IGZO Film

(b)orientations of hexagons [degree]

60

50

40

30

20

10

0

12

(d)(a) (b) (c)

(d)(a) (c)(b)

(1)

(2)

Observations in Grain

Magnifying observations in a grain with a size of several tens of nanometers at the atomic level(a) Plan-view TEM images (b)(c) FFT filtered images (d) Color mapping imagesDotted lines denote boundaries between pellets Solid lines show a hexagon formed with lattice points

plan-view FFT filtered images color mapping

60

50

40

30

20

10

0

orientations of hexagons [degree]

Pellet

Hexagon formed with lattice points

Reg

ions

cor

resp

ondi

ng to

thos

e in

the

plan

-vie

w T

EM

imag

e of

the

wid

e ar

ea

13

In Ga or Zn O

066 nm

038 nm

ｚｚ

Side view of a unit cell

198 nm

181 nm

Surface of a unit cellHexagon formed with lattice points

07 nm

(Ga Zn)O

(Ga Zn)O

InO2

Homologous crystal structure

CAAC-OS pellet unit cellSemi hard material (a flexible crystal structure) by oxygen as a cushion between In Ga and Zn

Oxygen

Oxygen

14

Magnifying observations in a boundary portion between grains with a size of several tens of nanometers at the atomic level(a) Plan-view TEM images (b)(c) FFT filtered images (d) Color mapping imagesDeformed hexagons pentagons and heptagons are formed with lattice points at the boundary denoted by a dotted line and they are anchored to each other

Observations in Boundary Portion between Grains

60

50

40

30

20

10

0

orientations of hexagons [degree]

Boundary(3

)(4

)

plan-view FFT filtered images color mapping

(d)

(d)

(a)

(a) (c)

(b)

(b)

(c)R

egio

ns c

orre

spon

ding

to th

ose

in th

e pl

an-v

iew

TE

M im

age

of th

e w

ide

area

15

(a) and (c) Distribution of number of Voronoi polygons in single crystal IGZO and CAAC-IGZO (b) and (d) Distribution of Voronoi hexagons (yellow regions) and other polygons (blue regions) in the single crystal IGZO and the CAAC-IGZO

Distribution of Number of Voronoi Polygons

In the single crystal IGZO hexagonal Voronoi regions occupy almost the entire field of view In the CAAC-IGZO hexagons are the majority but pentagons and heptagons also appear

Single crystal IGZO CAAC-IGZOSingle crystal IGZO film [] CAAC-IGZO film []

Tetragon 01 07

Pentagon 12 155

Hexagon 982 683

Heptagon 04 145

Octagon 02 09

Nonagon 00 00

16

2 3 4 51

5 nmminus1

5 nmminus1

minus231degminus84degminus75 deg minus310degminus246deg

+118deg +15deg +135deg +04deg minus55deg2 3 4 51

(a)1 2 34 5

20 nm

(b) 12

3

4

5 20 nm

Panel (a) shows the points along the surface of the CAAC-IGZO film that were probed by NBED and the five remaining panels in the top row show the corresponding NBED patterns Panel (b) shows the points probed by NBED in the thickness of the film and the five remaining panels in the lower row show the corresponding NBED patterns The angle of the crystal axis is slightly shifted in both the surface and thickness directions

Nanobeam Electron Diffraction (NBED 1 nmɸ) Patterns of CAAC-IGZO Film

17

Nanobeam Electron Diffraction (NBED 1 nmɸ) Patterns of CAAC-IGZO Film

Broadanisotropic diffraction spots

Sharpcircular diffraction spots

The electron diffraction pattern of single-crystal IGZO has circular spots as shown in (b) Diffraction spots of CAAC-IGZO are not circular but anisotropic and broad

18

Schematic Band Diagram of IGZOSimple schematic diagram of defect levels in IGZO film

elec

tron

ener

gy [e

V]

surface shallow DOS(sDOS)

bulk shallow DOS(sDOS)

bulk deep DOS(dDOS)

Density of States (DOS) of IGZO

19

28-32 eV

Silicon oxide IGZO

CAAC-IGZO63 (gcm3)

nc-IGZO61 (gcm3)

a-like IGZO59 (gcm3)

αCPM Absorption coefficient estimated by a constant photocurrent method (CPM)

N Ishihara et al Proc AM-FPD12 143 (2012)J Koezuka et al SID2013 Symposium Digest 723 (2013)

A high density of deep-level states (dDOS) exists in the low-density IGZO filmThe higher the film density is (like CAAC) the lower the dDOS is

Light absorptions by IGZO films with different crystal structureswere measured to quantify the densities of deep energy trapstates (dDOS)

Density of States (DOS) of IGZO

a-like IGZO 53 times 100

20

Formation of Oxygen Vacancies (VO) in IGZO

software VASP

exchange correlation function

GGA

pseudo potential PAW

cut-off energy 800 eV

k-point 1times1times1VO are

likely to be formed

Crystal Amorphous

In Ga Zn O

-1180

-1178

-1176

-1174

-1172

-15 -10 -5 0 5 10 15

Tota

l Ene

rgy

[eV]

Distance from Interface [Aring]

InterfaceInterface

VO are highly likely to be formed

A comparison of formation of oxygen vacancies (VO) between amorphous and crystal structures was made by first-principles calculation The results indicate that VO are easily formed in the amorphous structure

21

Features of CAAC-IGZO as MaterialCAAC-IGZO c-Si

1)CAAC structure (not single-crystal nano-crystalline or amorphous)rarr No clear grain boundary is observed

lattice points to form a pentagon and heptagon

Single crystal is preferable because polycrystal has a high concentration of defects at grain boundaries2)

Crystal grains (pellets) are anchored to each other to form one big crystalrarr It can be used in VLSI devices on the scale of 5ndash60 nm

3) Not a close-packed structure rather has cushion propertiesA cubic dense structure Doped with B or P Formed by crystal pulling at approx 1420C4)

Although single-crystal IGZO is formed at very high temperatures of 1200ndash1500C CAAC-IGZO can be formed at 100ndash500C by sputteringrarr It can be placed between Si LSI and metal wire layers

5) Homologous layered structure (Semi hard structure) Diamond structure(hard)

6) Composed of four elements (In Ga Zn and O) Si alone

22

3 Performance of CAAC-IGZO FET

23

IdndashVg characteristics and mobilities of CAAC-IGZO FETs with channel lengths of (a) 2 μm and (b) 6 μm The channel widths are 50 μm

It may be possible to apply all kinds of displays (TV smartphone PC by using OEL LCD)

L = 2 μm (W = 50 μm) L = 6 μm (W = 50 μm)

High-mobility CAAC-IGZO FETs

24

(a) (b)

CAAC-IGZO TrIoff = 1times10minus22 Aμm

(100 yAμm)IonIoff = 1018

IndashV characteristics of CAAC-IGZO and Si transistors

Si TrIoff = 1times10minus12 Aμm

(1 pAμm)IonIoff = 109

Off-state Current of CAAC-IGZO and Si FETsUnit

zA (10minus21)

yA (10minus24)

aA (10minus18)

fA (10minus15)

pA (10minus12)

nA (10minus9)

μA (10minus6)

mA (10minus3)

25

How to Measure Off-state Current60

0 μm

360 μm L = 044 μmW = 10 mm(50 μmtimes200)Tox = 20 nm

A huge transistor with a channel width of 10 mm for off-state leakage current measurement (optical micrograph)

Concept of measurement

Node FN(Vout)

Behavior of potential at node FN (Vout) over time

Measuredtransistor

26

Arrhenius plot of off-state leakage current1)Change of Vout measured over time

1) S Yamazaki et al Jpn J Appl Phys vol 53 pp 04ED18 (2014)

At a gate voltage of minus3 V and 85Cthe off-state leakage current was 6 yAm (1 yA = 10minus24 A)Nonvolatility for 10 years at 85C is ensured

Off-state CurrentUnitAμm

mA (10minus3)μA (10minus6)nA (10minus9)pA (10minus12)fA (10minus15)aA (10minus18)zA (10minus21)yA (10minus24)Le

akag

e cu

rrent

[Aμ

m]

27

-5

0

5

10

15

20

25

30

RF

Gai

n [d

B]

周波数[Hz]109 1010 101130 GHz

Vd = 20 VVg = 20 V( gm max )

WL = 18 μm30 nm

Operation with a cutoff frequency of about 30 GHz is demonstratedThe off-state leakage current of an OS FET (W = 60 nm) is expected at 100 zA or less at 85C even for a 30-nm-node FET

Lower measurement limit

High Cutoff Frequency and Low Off-state Current (30 nm)

28

Frequency [Hz]30 GHz

LW = 30 18000 (60 nmtimes300 Parallel) nm

Short-channel Characteristics of OS FETs

Favorable FET characteristics were obtained with a 11-nm-thick gate insulating film when L = 32 nm

The graphs show that OS FETs are resistant to short-channel effects This is probably because they have a ldquosurrounded-channel (S-ch) structure with a thin active layerrdquo and

are ldquoaccumulation-mode devicesrdquo and ldquoCAAC-IGZO has dielectric anisotropyrdquo(S-ch structure an FET structure where the active layer is electrically surrounded by the gate electrode)

GI = 11 nm

29

0

5

10

15

20

001 01 1 10 100

μ FE

[cm

2middotV-1

middot s-1]

チャネル長 [μm]

理論

Planar TypeS‐ch Type

0

200

400

600

001 01 1 10 100

μ FE

[cm

2 middotV-1

middots-1

]チャネル長 [μm]

理論

Planar Type

Short-channel Characteristics of OS FETs

Channel length dependence of field-effect mobility

(single-crystal Si FET)

Channel length dependence of field-effect mobility

（CAAC‐IGZO FET)

The field-effect mobility (μFE) of a CAAC-IGZO FET with a reduced channel length is close to that of a single-crystal Si FET with the same size

μ FE[

cm2 V

-1s

-1]

Channel length

0

20

5

10

15

10 nm 100 nm 1 μm 100 μm10 μm 10 nm 100 nm 1 μm 100 μm10 μm

Channel length

0

600

200

400

μ FE[

cm2 V

-1s

-1]

Theoretical Theoretical

30

Temperature Dependence of CAAC-IGZO FET

OS-FET

編集中編集中

L=048um GI=20nm

Vth

S値

ID_VG特性

単結晶 p-ch Si Tr （SOI）

L=035um GI=20nm L=035um GI=20nm

編集中 編集中

単結晶 n-ch Si Tr （SOI）

‐05

00

05

10

15

0 50 100 150 200 250

Vth[V]

基板温度 []

0

50

100

150

200

250

300

0 50 100 150 200 250

S‐Value[mVdec]

基板温度 []

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

Vg [V]

250

‐05

0

05

1

15

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

‐15

‐1

‐05

0

05

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

T = minus40C minus 25C 0C 25C 50C 100C 150C 200C 250C

CAAC-OS FETs have a sufficient onoff ratio even at 200C or higherThe S-value shows little change (or is constant) compared with Si FETs

Single‐crystal n‐ch Tr (SOI) Single‐crystal p‐ch Tr (SOI)OS FET

ID‐VGCharac‐teristics

Vth

S‐value

Substrate temperature [C] Substrate temperature [C] Substrate temperature [C]

Substrate temperature [C]Substrate temperature [C]Substrate temperature [C]

31

1E-07

1E-06

1E-05

1E-04

1E-03

1E-02

0 5 10 15 20 25 30V D [V]

ID [A

]Si transistorL =09um T ox=20nm

IGZO transistorL =09um T ox=20nm

4V 26V

L ＝ 09 μm W ＝ 10 μm TOX = 20 nm VG ＝ 2 V

n = 2

CAAC-IGZO transistors have a higher breakdown voltage than Si transistorsNo hot carrier degradation and avalanche breakdown are observed

Breakdown Voltage of CAAC-IGZO and Si FETs

32

Schematic Band Diagram of Channel Regionmdash OS FET vs n-ch Si FET

Inversion Depletion Accumulation

Vg gt 0 V (ON State) Vg lt 0 V (OFF State)Vg = 0V

CAAC-IGZO(S-channel)

n-ch Si

OS2CAAC-IGZO

OS3Gate E

GI GI

Gate E

Gate E

GI

Si

EC

EV

Ef

EfEC

EV

Eg=32eV

Eg=12eV

ElectronsA Arsquo

OS3

Holes

A ArsquoA Arsquo

33

M Murakami et al Proc AM-FPDrsquo12 Digest p 174 (2012)

CAAC-IGZO c-Si

1) Bandgap (Eg) 28ndash32 eV 112 eV

2) Intrinsic carrierconcentration 10minus9 cm3 10+11 cm3

3) Depletion layer km order μm order

4) Electron effective mass (meme)

023ndash025 019 (transverse)098 (longitudinal)

5) Hole effective mass (mhme)

11ndash40 016 (light)049 (heavy)

6) Structure Layered structure(Homologous) Diamond cubic

7) Conductivity i-type n-type n-type p-type

Comparison of Physical Properties between CAAC-IGZO and c-Si

34

Features of CAAC-IGZO as Device

CAAC‐IGZO c‐Si

1) Four-terminal circuitFour-terminal circuit MRAM and FeRAM are two-terminal circuits

2) Almost no short-channel effects Short-channel effects are most troublesome

3) Normally off Uncontrollable Vth high purity and intrinsic

Vth is controllable by channel doping with B

4) IonIoff ratio of 1020 IonIoff le 1010

5) nMOS onlyCMOS feasible with Si pMOS

CMOS Si nMOSSi pMOS

6) Bulk channel buried channel Shifting from surface-channel (planar) to bulk-channel (Fin)

35

4 30-nm Scaling of CAAC-IGZO FET

36

Trench Gate Self-aligned FET

L-direction W-direction

L-direction W-direction

CAAC-OS

Gate Electrode Gate Insulating Film

CAAC-OSDrain

ElectrodeSource

Electrode

Gate Electrode

Gate Insulating Film

48 nm

Gate Electrode

Gate Insulating Film

CAAC-OS34 nm

Source Electrode

Drain Electrode

CAAC-OS

Gate Insulating FilmGate Electrode

19 nm

50 nm

S-ch structure

FETrsquos active layer (CAAC-IGZO OS2 layer) is electrically surrounded by the gate electrodeWe call this FET structure a

surrounded-channel (S-ch) structure

37

Stacked Structure of OS FET and Si FET

pMOSSi

nMOSOS

GND

VDD

A Arsquo

B

Brsquo gate metal

source drain

gate insulator

CAAC-IGZO

electrode

gate

source drain

Si

SiO2

A Arsquo

B

Brsquo

OS FET

Si FET

High integration by stacking the CAAC-OS FET over the Si-FET

Si Substrate Si Substrate

W-directionL-direction

38

Comparison between CAAC-OS FET and Si nMOS FETItem CAAC-OS FET Si nMOS FET

1 Short-channel effect Small or none timesLarge (largest issue in Si NMOS FET)

2 Scaling le 30 nm (Possibility of 5 nm) Possible to ge 5 nm

3 Off-state current yAμm (10minus24 Aμm) times fAμm (10minus15 Aμm)

4 Mobility

Long channel Low High

Short channel Slightly decrease

Decrease (110 in 30-nm device)

5 Temperature characteristics

On-state current

Increase at high temperature

Decrease at high temperature

Off-state current Sufficiently low times

Drastically increase at high temperature

6 Drain breakdown voltage High Low7 Impact ionization Not observed Observed+2 +1 minus1 times minus2

39

Item CAAC-OS FET Si nMOS FET

8 Hot carrier degradation Not observed Large

9 Punch-through Not observed Strongly need balance with scaling

10 Frequency characteristics gt 30 GHz gt 300 GHz

11 Drift velocity Close to Si with channel length about 10 nm

Saturates with channel length about 100 nm

12 Sub-threshold value Small even with thick GI

Need thinner GI by miniaturizing

13 Dielectric anisotropy Observed Not observed

14 S-channel structure(Fin tri-gate type)

Extremely important and effective

Extremely important in shorter channel and effective

+25 minus1+2 +1 minus1 times minus2

Comparison between CAAC-OS FET and Si nMOS FET

40

5 CAAC-IGZO FET for LSI Application

41

Two-terminal circuit(diode)

Potential as Logic Circuit

Dependent control of input and output Need a transistor for four-terminal control Increased F2

Independently controllable inputs and outputs Desirable logic design Sufficiently low Ioff Practically an insulator

Four-terminal circuit

A B

C D

Input Output

42

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

2 What kind of crystal morphology does CAAC have

7

Discovered by SEL mass produced by Sharp

3 nm 3 nm

single crystalsingle crystal nano-crystalCAAC amorphous-like amorphous

Thickness 50 nm

CAAC nanocrystal

Classification of Oxide Semiconductor Materials

Thickness 50 nm

c-ax

is

Crystal structure of IGZO

88

2)

1) K Nomura T Kamiya H Ohta T Uruga M Hirano and H Hosono

Phys Rev B 75 035212 (2007) 2) Y Kurosawa et al

JSAP Autumn Meeting 2014 18p-A12-2

The simulation model of ldquoamorphous IGZO1)rdquo by Melt quench method

copyThe Japan Society of Applied Physics 2014

amorphous structure

Characteristics of CAAC-IGZO Film

Derived from quartz substrate

E-beam is incident parallel to the substrate surface

E-beam is incident perpendicularto the substrate surface

Rotation within (110) plane

Sample structure

electron diffraction (a-b plane)

X-ray diffraction (c-axis)

electron diffraction (c-axis)c-axis

a

b

Clear orientationNo orientation

Clearorientation

No orientation

CAAC c-axis-aligned a-b-plane-anchored crystalCAAC c-axis-aligned a-b-plane-anchored crystal

X-ray diffraction (a-b plane)

9

(d) CAAC crystal pellet (e) Cross-sectional image of unit pelletIn Ga or Zn O

(Chip)

Substrate

Cross-sectional TEM of CAAC-IGZO Film

08 nm

3 nm

(a) (b)TEM imageHR-TEM imageDetail of area in (a)

IGZO Film

Substrate

50 nm

10

平面TEM高分解能像FFT image processing-Extract data on a certain wavenumber range

Processing using an original program

Plan‐view TEM Crystal Lattice Image

FFT Filtered Image(FFTFast FourierTransform)

Lattice Extraction Image

Hexagonal Lattice Orientation Analysis amp

Color Mapping

Perfect regular hexagon

Neighboring lattice points(6 points)

Reference lattice point

1) Determine the orientation of a perfect regular hexagon so as to minimize the sum of the distances from the vertices of the perfect regular hexagon to six points neighboring a reference lattice point

Average distance a the average of distances from the reference lattice point to its neighboring six lattice points

2) Color each lattice point after the step 1) according to the difference from a reference angle In this study the modal angle was set to 30

6050403020100

ex

θ x

Average distance a

0 le θ lt 60

orientations of hexagons [degree]

Analysis Procedure Hexagonal LatticeOrientation Analysis amp Color Mapping

Processing using an original program

11

(a) A plan-view TEM image (b) A color mapping image obtained from an FFT filtered image of (a) The orientations of the hexagons are sorted by the angle (0minus60) and shown in different colors The colors of the adjoining grains are adjacent colors on the color scale

10 nm

(3)

(4)

(1)(2)

(a)

Plan-view Observations of CAAC-IGZO Film

(b)orientations of hexagons [degree]

60

50

40

30

20

10

0

12

(d)(a) (b) (c)

(d)(a) (c)(b)

(1)

(2)

Observations in Grain

Magnifying observations in a grain with a size of several tens of nanometers at the atomic level(a) Plan-view TEM images (b)(c) FFT filtered images (d) Color mapping imagesDotted lines denote boundaries between pellets Solid lines show a hexagon formed with lattice points

plan-view FFT filtered images color mapping

60

50

40

30

20

10

0

orientations of hexagons [degree]

Pellet

Hexagon formed with lattice points

Reg

ions

cor

resp

ondi

ng to

thos

e in

the

plan

-vie

w T

EM

imag

e of

the

wid

e ar

ea

13

In Ga or Zn O

066 nm

038 nm

ｚｚ

Side view of a unit cell

198 nm

181 nm

Surface of a unit cellHexagon formed with lattice points

07 nm

(Ga Zn)O

(Ga Zn)O

InO2

Homologous crystal structure

CAAC-OS pellet unit cellSemi hard material (a flexible crystal structure) by oxygen as a cushion between In Ga and Zn

Oxygen

Oxygen

14

Magnifying observations in a boundary portion between grains with a size of several tens of nanometers at the atomic level(a) Plan-view TEM images (b)(c) FFT filtered images (d) Color mapping imagesDeformed hexagons pentagons and heptagons are formed with lattice points at the boundary denoted by a dotted line and they are anchored to each other

Observations in Boundary Portion between Grains

60

50

40

30

20

10

0

orientations of hexagons [degree]

Boundary(3

)(4

)

plan-view FFT filtered images color mapping

(d)

(d)

(a)

(a) (c)

(b)

(b)

(c)R

egio

ns c

orre

spon

ding

to th

ose

in th

e pl

an-v

iew

TE

M im

age

of th

e w

ide

area

15

(a) and (c) Distribution of number of Voronoi polygons in single crystal IGZO and CAAC-IGZO (b) and (d) Distribution of Voronoi hexagons (yellow regions) and other polygons (blue regions) in the single crystal IGZO and the CAAC-IGZO

Distribution of Number of Voronoi Polygons

In the single crystal IGZO hexagonal Voronoi regions occupy almost the entire field of view In the CAAC-IGZO hexagons are the majority but pentagons and heptagons also appear

Single crystal IGZO CAAC-IGZOSingle crystal IGZO film [] CAAC-IGZO film []

Tetragon 01 07

Pentagon 12 155

Hexagon 982 683

Heptagon 04 145

Octagon 02 09

Nonagon 00 00

16

2 3 4 51

5 nmminus1

5 nmminus1

minus231degminus84degminus75 deg minus310degminus246deg

+118deg +15deg +135deg +04deg minus55deg2 3 4 51

(a)1 2 34 5

20 nm

(b) 12

3

4

5 20 nm

Panel (a) shows the points along the surface of the CAAC-IGZO film that were probed by NBED and the five remaining panels in the top row show the corresponding NBED patterns Panel (b) shows the points probed by NBED in the thickness of the film and the five remaining panels in the lower row show the corresponding NBED patterns The angle of the crystal axis is slightly shifted in both the surface and thickness directions

Nanobeam Electron Diffraction (NBED 1 nmɸ) Patterns of CAAC-IGZO Film

17

Nanobeam Electron Diffraction (NBED 1 nmɸ) Patterns of CAAC-IGZO Film

Broadanisotropic diffraction spots

Sharpcircular diffraction spots

The electron diffraction pattern of single-crystal IGZO has circular spots as shown in (b) Diffraction spots of CAAC-IGZO are not circular but anisotropic and broad

18

Schematic Band Diagram of IGZOSimple schematic diagram of defect levels in IGZO film

elec

tron

ener

gy [e

V]

surface shallow DOS(sDOS)

bulk shallow DOS(sDOS)

bulk deep DOS(dDOS)

Density of States (DOS) of IGZO

19

28-32 eV

Silicon oxide IGZO

CAAC-IGZO63 (gcm3)

nc-IGZO61 (gcm3)

a-like IGZO59 (gcm3)

αCPM Absorption coefficient estimated by a constant photocurrent method (CPM)

N Ishihara et al Proc AM-FPD12 143 (2012)J Koezuka et al SID2013 Symposium Digest 723 (2013)

A high density of deep-level states (dDOS) exists in the low-density IGZO filmThe higher the film density is (like CAAC) the lower the dDOS is

Light absorptions by IGZO films with different crystal structureswere measured to quantify the densities of deep energy trapstates (dDOS)

Density of States (DOS) of IGZO

a-like IGZO 53 times 100

20

Formation of Oxygen Vacancies (VO) in IGZO

software VASP

exchange correlation function

GGA

pseudo potential PAW

cut-off energy 800 eV

k-point 1times1times1VO are

likely to be formed

Crystal Amorphous

In Ga Zn O

-1180

-1178

-1176

-1174

-1172

-15 -10 -5 0 5 10 15

Tota

l Ene

rgy

[eV]

Distance from Interface [Aring]

InterfaceInterface

VO are highly likely to be formed

A comparison of formation of oxygen vacancies (VO) between amorphous and crystal structures was made by first-principles calculation The results indicate that VO are easily formed in the amorphous structure

21

Features of CAAC-IGZO as MaterialCAAC-IGZO c-Si

1)CAAC structure (not single-crystal nano-crystalline or amorphous)rarr No clear grain boundary is observed

lattice points to form a pentagon and heptagon

Single crystal is preferable because polycrystal has a high concentration of defects at grain boundaries2)

Crystal grains (pellets) are anchored to each other to form one big crystalrarr It can be used in VLSI devices on the scale of 5ndash60 nm

3) Not a close-packed structure rather has cushion propertiesA cubic dense structure Doped with B or P Formed by crystal pulling at approx 1420C4)

Although single-crystal IGZO is formed at very high temperatures of 1200ndash1500C CAAC-IGZO can be formed at 100ndash500C by sputteringrarr It can be placed between Si LSI and metal wire layers

5) Homologous layered structure (Semi hard structure) Diamond structure(hard)

6) Composed of four elements (In Ga Zn and O) Si alone

22

3 Performance of CAAC-IGZO FET

23

IdndashVg characteristics and mobilities of CAAC-IGZO FETs with channel lengths of (a) 2 μm and (b) 6 μm The channel widths are 50 μm

It may be possible to apply all kinds of displays (TV smartphone PC by using OEL LCD)

L = 2 μm (W = 50 μm) L = 6 μm (W = 50 μm)

High-mobility CAAC-IGZO FETs

24

(a) (b)

CAAC-IGZO TrIoff = 1times10minus22 Aμm

(100 yAμm)IonIoff = 1018

IndashV characteristics of CAAC-IGZO and Si transistors

Si TrIoff = 1times10minus12 Aμm

(1 pAμm)IonIoff = 109

Off-state Current of CAAC-IGZO and Si FETsUnit

zA (10minus21)

yA (10minus24)

aA (10minus18)

fA (10minus15)

pA (10minus12)

nA (10minus9)

μA (10minus6)

mA (10minus3)

25

How to Measure Off-state Current60

0 μm

360 μm L = 044 μmW = 10 mm(50 μmtimes200)Tox = 20 nm

A huge transistor with a channel width of 10 mm for off-state leakage current measurement (optical micrograph)

Concept of measurement

Node FN(Vout)

Behavior of potential at node FN (Vout) over time

Measuredtransistor

26

Arrhenius plot of off-state leakage current1)Change of Vout measured over time

1) S Yamazaki et al Jpn J Appl Phys vol 53 pp 04ED18 (2014)

At a gate voltage of minus3 V and 85Cthe off-state leakage current was 6 yAm (1 yA = 10minus24 A)Nonvolatility for 10 years at 85C is ensured

Off-state CurrentUnitAμm

mA (10minus3)μA (10minus6)nA (10minus9)pA (10minus12)fA (10minus15)aA (10minus18)zA (10minus21)yA (10minus24)Le

akag

e cu

rrent

[Aμ

m]

27

-5

0

5

10

15

20

25

30

RF

Gai

n [d

B]

周波数[Hz]109 1010 101130 GHz

Vd = 20 VVg = 20 V( gm max )

WL = 18 μm30 nm

Operation with a cutoff frequency of about 30 GHz is demonstratedThe off-state leakage current of an OS FET (W = 60 nm) is expected at 100 zA or less at 85C even for a 30-nm-node FET

Lower measurement limit

High Cutoff Frequency and Low Off-state Current (30 nm)

28

Frequency [Hz]30 GHz

LW = 30 18000 (60 nmtimes300 Parallel) nm

Short-channel Characteristics of OS FETs

Favorable FET characteristics were obtained with a 11-nm-thick gate insulating film when L = 32 nm

The graphs show that OS FETs are resistant to short-channel effects This is probably because they have a ldquosurrounded-channel (S-ch) structure with a thin active layerrdquo and

are ldquoaccumulation-mode devicesrdquo and ldquoCAAC-IGZO has dielectric anisotropyrdquo(S-ch structure an FET structure where the active layer is electrically surrounded by the gate electrode)

GI = 11 nm

29

0

5

10

15

20

001 01 1 10 100

μ FE

[cm

2middotV-1

middot s-1]

チャネル長 [μm]

理論

Planar TypeS‐ch Type

0

200

400

600

001 01 1 10 100

μ FE

[cm

2 middotV-1

middots-1

]チャネル長 [μm]

理論

Planar Type

Short-channel Characteristics of OS FETs

Channel length dependence of field-effect mobility

(single-crystal Si FET)

Channel length dependence of field-effect mobility

（CAAC‐IGZO FET)

The field-effect mobility (μFE) of a CAAC-IGZO FET with a reduced channel length is close to that of a single-crystal Si FET with the same size

μ FE[

cm2 V

-1s

-1]

Channel length

0

20

5

10

15

10 nm 100 nm 1 μm 100 μm10 μm 10 nm 100 nm 1 μm 100 μm10 μm

Channel length

0

600

200

400

μ FE[

cm2 V

-1s

-1]

Theoretical Theoretical

30

Temperature Dependence of CAAC-IGZO FET

OS-FET

編集中編集中

L=048um GI=20nm

Vth

S値

ID_VG特性

単結晶 p-ch Si Tr （SOI）

L=035um GI=20nm L=035um GI=20nm

編集中 編集中

単結晶 n-ch Si Tr （SOI）

‐05

00

05

10

15

0 50 100 150 200 250

Vth[V]

基板温度 []

0

50

100

150

200

250

300

0 50 100 150 200 250

S‐Value[mVdec]

基板温度 []

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

Vg [V]

250

‐05

0

05

1

15

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

‐15

‐1

‐05

0

05

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

T = minus40C minus 25C 0C 25C 50C 100C 150C 200C 250C

CAAC-OS FETs have a sufficient onoff ratio even at 200C or higherThe S-value shows little change (or is constant) compared with Si FETs

Single‐crystal n‐ch Tr (SOI) Single‐crystal p‐ch Tr (SOI)OS FET

ID‐VGCharac‐teristics

Vth

S‐value

Substrate temperature [C] Substrate temperature [C] Substrate temperature [C]

Substrate temperature [C]Substrate temperature [C]Substrate temperature [C]

31

1E-07

1E-06

1E-05

1E-04

1E-03

1E-02

0 5 10 15 20 25 30V D [V]

ID [A

]Si transistorL =09um T ox=20nm

IGZO transistorL =09um T ox=20nm

4V 26V

L ＝ 09 μm W ＝ 10 μm TOX = 20 nm VG ＝ 2 V

n = 2

CAAC-IGZO transistors have a higher breakdown voltage than Si transistorsNo hot carrier degradation and avalanche breakdown are observed

Breakdown Voltage of CAAC-IGZO and Si FETs

32

Schematic Band Diagram of Channel Regionmdash OS FET vs n-ch Si FET

Inversion Depletion Accumulation

Vg gt 0 V (ON State) Vg lt 0 V (OFF State)Vg = 0V

CAAC-IGZO(S-channel)

n-ch Si

OS2CAAC-IGZO

OS3Gate E

GI GI

Gate E

Gate E

GI

Si

EC

EV

Ef

EfEC

EV

Eg=32eV

Eg=12eV

ElectronsA Arsquo

OS3

Holes

A ArsquoA Arsquo

33

M Murakami et al Proc AM-FPDrsquo12 Digest p 174 (2012)

CAAC-IGZO c-Si

1) Bandgap (Eg) 28ndash32 eV 112 eV

2) Intrinsic carrierconcentration 10minus9 cm3 10+11 cm3

3) Depletion layer km order μm order

4) Electron effective mass (meme)

023ndash025 019 (transverse)098 (longitudinal)

5) Hole effective mass (mhme)

11ndash40 016 (light)049 (heavy)

6) Structure Layered structure(Homologous) Diamond cubic

7) Conductivity i-type n-type n-type p-type

Comparison of Physical Properties between CAAC-IGZO and c-Si

34

Features of CAAC-IGZO as Device

CAAC‐IGZO c‐Si

1) Four-terminal circuitFour-terminal circuit MRAM and FeRAM are two-terminal circuits

2) Almost no short-channel effects Short-channel effects are most troublesome

3) Normally off Uncontrollable Vth high purity and intrinsic

Vth is controllable by channel doping with B

4) IonIoff ratio of 1020 IonIoff le 1010

5) nMOS onlyCMOS feasible with Si pMOS

CMOS Si nMOSSi pMOS

6) Bulk channel buried channel Shifting from surface-channel (planar) to bulk-channel (Fin)

35

4 30-nm Scaling of CAAC-IGZO FET

36

Trench Gate Self-aligned FET

L-direction W-direction

L-direction W-direction

CAAC-OS

Gate Electrode Gate Insulating Film

CAAC-OSDrain

ElectrodeSource

Electrode

Gate Electrode

Gate Insulating Film

48 nm

Gate Electrode

Gate Insulating Film

CAAC-OS34 nm

Source Electrode

Drain Electrode

CAAC-OS

Gate Insulating FilmGate Electrode

19 nm

50 nm

S-ch structure

FETrsquos active layer (CAAC-IGZO OS2 layer) is electrically surrounded by the gate electrodeWe call this FET structure a

surrounded-channel (S-ch) structure

37

Stacked Structure of OS FET and Si FET

pMOSSi

nMOSOS

GND

VDD

A Arsquo

B

Brsquo gate metal

source drain

gate insulator

CAAC-IGZO

electrode

gate

source drain

Si

SiO2

A Arsquo

B

Brsquo

OS FET

Si FET

High integration by stacking the CAAC-OS FET over the Si-FET

Si Substrate Si Substrate

W-directionL-direction

38

Comparison between CAAC-OS FET and Si nMOS FETItem CAAC-OS FET Si nMOS FET

1 Short-channel effect Small or none timesLarge (largest issue in Si NMOS FET)

2 Scaling le 30 nm (Possibility of 5 nm) Possible to ge 5 nm

3 Off-state current yAμm (10minus24 Aμm) times fAμm (10minus15 Aμm)

4 Mobility

Long channel Low High

Short channel Slightly decrease

Decrease (110 in 30-nm device)

5 Temperature characteristics

On-state current

Increase at high temperature

Decrease at high temperature

Off-state current Sufficiently low times

Drastically increase at high temperature

6 Drain breakdown voltage High Low7 Impact ionization Not observed Observed+2 +1 minus1 times minus2

39

Item CAAC-OS FET Si nMOS FET

8 Hot carrier degradation Not observed Large

9 Punch-through Not observed Strongly need balance with scaling

10 Frequency characteristics gt 30 GHz gt 300 GHz

11 Drift velocity Close to Si with channel length about 10 nm

Saturates with channel length about 100 nm

12 Sub-threshold value Small even with thick GI

Need thinner GI by miniaturizing

13 Dielectric anisotropy Observed Not observed

14 S-channel structure(Fin tri-gate type)

Extremely important and effective

Extremely important in shorter channel and effective

+25 minus1+2 +1 minus1 times minus2

Comparison between CAAC-OS FET and Si nMOS FET

40

5 CAAC-IGZO FET for LSI Application

41

Two-terminal circuit(diode)

Potential as Logic Circuit

Dependent control of input and output Need a transistor for four-terminal control Increased F2

Independently controllable inputs and outputs Desirable logic design Sufficiently low Ioff Practically an insulator

Four-terminal circuit

A B

C D

Input Output

42

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

Discovered by SEL mass produced by Sharp

3 nm 3 nm

single crystalsingle crystal nano-crystalCAAC amorphous-like amorphous

Thickness 50 nm

CAAC nanocrystal

Classification of Oxide Semiconductor Materials

Thickness 50 nm

c-ax

is

Crystal structure of IGZO

88

2)

1) K Nomura T Kamiya H Ohta T Uruga M Hirano and H Hosono

Phys Rev B 75 035212 (2007) 2) Y Kurosawa et al

JSAP Autumn Meeting 2014 18p-A12-2

The simulation model of ldquoamorphous IGZO1)rdquo by Melt quench method

copyThe Japan Society of Applied Physics 2014

amorphous structure

Characteristics of CAAC-IGZO Film

Derived from quartz substrate

E-beam is incident parallel to the substrate surface

E-beam is incident perpendicularto the substrate surface

Rotation within (110) plane

Sample structure

electron diffraction (a-b plane)

X-ray diffraction (c-axis)

electron diffraction (c-axis)c-axis

a

b

Clear orientationNo orientation

Clearorientation

No orientation

CAAC c-axis-aligned a-b-plane-anchored crystalCAAC c-axis-aligned a-b-plane-anchored crystal

X-ray diffraction (a-b plane)

9

(d) CAAC crystal pellet (e) Cross-sectional image of unit pelletIn Ga or Zn O

(Chip)

Substrate

Cross-sectional TEM of CAAC-IGZO Film

08 nm

3 nm

(a) (b)TEM imageHR-TEM imageDetail of area in (a)

IGZO Film

Substrate

50 nm

10

平面TEM高分解能像FFT image processing-Extract data on a certain wavenumber range

Processing using an original program

Plan‐view TEM Crystal Lattice Image

FFT Filtered Image(FFTFast FourierTransform)

Lattice Extraction Image

Hexagonal Lattice Orientation Analysis amp

Color Mapping

Perfect regular hexagon

Neighboring lattice points(6 points)

Reference lattice point

1) Determine the orientation of a perfect regular hexagon so as to minimize the sum of the distances from the vertices of the perfect regular hexagon to six points neighboring a reference lattice point

Average distance a the average of distances from the reference lattice point to its neighboring six lattice points

2) Color each lattice point after the step 1) according to the difference from a reference angle In this study the modal angle was set to 30

6050403020100

ex

θ x

Average distance a

0 le θ lt 60

orientations of hexagons [degree]

Analysis Procedure Hexagonal LatticeOrientation Analysis amp Color Mapping

Processing using an original program

11

(a) A plan-view TEM image (b) A color mapping image obtained from an FFT filtered image of (a) The orientations of the hexagons are sorted by the angle (0minus60) and shown in different colors The colors of the adjoining grains are adjacent colors on the color scale

10 nm

(3)

(4)

(1)(2)

(a)

Plan-view Observations of CAAC-IGZO Film

(b)orientations of hexagons [degree]

60

50

40

30

20

10

0

12

(d)(a) (b) (c)

(d)(a) (c)(b)

(1)

(2)

Observations in Grain

Magnifying observations in a grain with a size of several tens of nanometers at the atomic level(a) Plan-view TEM images (b)(c) FFT filtered images (d) Color mapping imagesDotted lines denote boundaries between pellets Solid lines show a hexagon formed with lattice points

plan-view FFT filtered images color mapping

60

50

40

30

20

10

0

orientations of hexagons [degree]

Pellet

Hexagon formed with lattice points

Reg

ions

cor

resp

ondi

ng to

thos

e in

the

plan

-vie

w T

EM

imag

e of

the

wid

e ar

ea

13

In Ga or Zn O

066 nm

038 nm

ｚｚ

Side view of a unit cell

198 nm

181 nm

Surface of a unit cellHexagon formed with lattice points

07 nm

(Ga Zn)O

(Ga Zn)O

InO2

Homologous crystal structure

CAAC-OS pellet unit cellSemi hard material (a flexible crystal structure) by oxygen as a cushion between In Ga and Zn

Oxygen

Oxygen

14

Magnifying observations in a boundary portion between grains with a size of several tens of nanometers at the atomic level(a) Plan-view TEM images (b)(c) FFT filtered images (d) Color mapping imagesDeformed hexagons pentagons and heptagons are formed with lattice points at the boundary denoted by a dotted line and they are anchored to each other

Observations in Boundary Portion between Grains

60

50

40

30

20

10

0

orientations of hexagons [degree]

Boundary(3

)(4

)

plan-view FFT filtered images color mapping

(d)

(d)

(a)

(a) (c)

(b)

(b)

(c)R

egio

ns c

orre

spon

ding

to th

ose

in th

e pl

an-v

iew

TE

M im

age

of th

e w

ide

area

15

(a) and (c) Distribution of number of Voronoi polygons in single crystal IGZO and CAAC-IGZO (b) and (d) Distribution of Voronoi hexagons (yellow regions) and other polygons (blue regions) in the single crystal IGZO and the CAAC-IGZO

Distribution of Number of Voronoi Polygons

In the single crystal IGZO hexagonal Voronoi regions occupy almost the entire field of view In the CAAC-IGZO hexagons are the majority but pentagons and heptagons also appear

Single crystal IGZO CAAC-IGZOSingle crystal IGZO film [] CAAC-IGZO film []

Tetragon 01 07

Pentagon 12 155

Hexagon 982 683

Heptagon 04 145

Octagon 02 09

Nonagon 00 00

16

2 3 4 51

5 nmminus1

5 nmminus1

minus231degminus84degminus75 deg minus310degminus246deg

+118deg +15deg +135deg +04deg minus55deg2 3 4 51

(a)1 2 34 5

20 nm

(b) 12

3

4

5 20 nm

Panel (a) shows the points along the surface of the CAAC-IGZO film that were probed by NBED and the five remaining panels in the top row show the corresponding NBED patterns Panel (b) shows the points probed by NBED in the thickness of the film and the five remaining panels in the lower row show the corresponding NBED patterns The angle of the crystal axis is slightly shifted in both the surface and thickness directions

Nanobeam Electron Diffraction (NBED 1 nmɸ) Patterns of CAAC-IGZO Film

17

Nanobeam Electron Diffraction (NBED 1 nmɸ) Patterns of CAAC-IGZO Film

Broadanisotropic diffraction spots

Sharpcircular diffraction spots

The electron diffraction pattern of single-crystal IGZO has circular spots as shown in (b) Diffraction spots of CAAC-IGZO are not circular but anisotropic and broad

18

Schematic Band Diagram of IGZOSimple schematic diagram of defect levels in IGZO film

elec

tron

ener

gy [e

V]

surface shallow DOS(sDOS)

bulk shallow DOS(sDOS)

bulk deep DOS(dDOS)

Density of States (DOS) of IGZO

19

28-32 eV

Silicon oxide IGZO

CAAC-IGZO63 (gcm3)

nc-IGZO61 (gcm3)

a-like IGZO59 (gcm3)

αCPM Absorption coefficient estimated by a constant photocurrent method (CPM)

N Ishihara et al Proc AM-FPD12 143 (2012)J Koezuka et al SID2013 Symposium Digest 723 (2013)

A high density of deep-level states (dDOS) exists in the low-density IGZO filmThe higher the film density is (like CAAC) the lower the dDOS is

Light absorptions by IGZO films with different crystal structureswere measured to quantify the densities of deep energy trapstates (dDOS)

Density of States (DOS) of IGZO

a-like IGZO 53 times 100

20

Formation of Oxygen Vacancies (VO) in IGZO

software VASP

exchange correlation function

GGA

pseudo potential PAW

cut-off energy 800 eV

k-point 1times1times1VO are

likely to be formed

Crystal Amorphous

In Ga Zn O

-1180

-1178

-1176

-1174

-1172

-15 -10 -5 0 5 10 15

Tota

l Ene

rgy

[eV]

Distance from Interface [Aring]

InterfaceInterface

VO are highly likely to be formed

A comparison of formation of oxygen vacancies (VO) between amorphous and crystal structures was made by first-principles calculation The results indicate that VO are easily formed in the amorphous structure

21

Features of CAAC-IGZO as MaterialCAAC-IGZO c-Si

1)CAAC structure (not single-crystal nano-crystalline or amorphous)rarr No clear grain boundary is observed

lattice points to form a pentagon and heptagon

Single crystal is preferable because polycrystal has a high concentration of defects at grain boundaries2)

Crystal grains (pellets) are anchored to each other to form one big crystalrarr It can be used in VLSI devices on the scale of 5ndash60 nm

3) Not a close-packed structure rather has cushion propertiesA cubic dense structure Doped with B or P Formed by crystal pulling at approx 1420C4)

Although single-crystal IGZO is formed at very high temperatures of 1200ndash1500C CAAC-IGZO can be formed at 100ndash500C by sputteringrarr It can be placed between Si LSI and metal wire layers

5) Homologous layered structure (Semi hard structure) Diamond structure(hard)

6) Composed of four elements (In Ga Zn and O) Si alone

22

3 Performance of CAAC-IGZO FET

23

IdndashVg characteristics and mobilities of CAAC-IGZO FETs with channel lengths of (a) 2 μm and (b) 6 μm The channel widths are 50 μm

It may be possible to apply all kinds of displays (TV smartphone PC by using OEL LCD)

L = 2 μm (W = 50 μm) L = 6 μm (W = 50 μm)

High-mobility CAAC-IGZO FETs

24

(a) (b)

CAAC-IGZO TrIoff = 1times10minus22 Aμm

(100 yAμm)IonIoff = 1018

IndashV characteristics of CAAC-IGZO and Si transistors

Si TrIoff = 1times10minus12 Aμm

(1 pAμm)IonIoff = 109

Off-state Current of CAAC-IGZO and Si FETsUnit

zA (10minus21)

yA (10minus24)

aA (10minus18)

fA (10minus15)

pA (10minus12)

nA (10minus9)

μA (10minus6)

mA (10minus3)

25

How to Measure Off-state Current60

0 μm

360 μm L = 044 μmW = 10 mm(50 μmtimes200)Tox = 20 nm

A huge transistor with a channel width of 10 mm for off-state leakage current measurement (optical micrograph)

Concept of measurement

Node FN(Vout)

Behavior of potential at node FN (Vout) over time

Measuredtransistor

26

Arrhenius plot of off-state leakage current1)Change of Vout measured over time

1) S Yamazaki et al Jpn J Appl Phys vol 53 pp 04ED18 (2014)

At a gate voltage of minus3 V and 85Cthe off-state leakage current was 6 yAm (1 yA = 10minus24 A)Nonvolatility for 10 years at 85C is ensured

Off-state CurrentUnitAμm

mA (10minus3)μA (10minus6)nA (10minus9)pA (10minus12)fA (10minus15)aA (10minus18)zA (10minus21)yA (10minus24)Le

akag

e cu

rrent

[Aμ

m]

27

-5

0

5

10

15

20

25

30

RF

Gai

n [d

B]

周波数[Hz]109 1010 101130 GHz

Vd = 20 VVg = 20 V( gm max )

WL = 18 μm30 nm

Operation with a cutoff frequency of about 30 GHz is demonstratedThe off-state leakage current of an OS FET (W = 60 nm) is expected at 100 zA or less at 85C even for a 30-nm-node FET

Lower measurement limit

High Cutoff Frequency and Low Off-state Current (30 nm)

28

Frequency [Hz]30 GHz

LW = 30 18000 (60 nmtimes300 Parallel) nm

Short-channel Characteristics of OS FETs

Favorable FET characteristics were obtained with a 11-nm-thick gate insulating film when L = 32 nm

The graphs show that OS FETs are resistant to short-channel effects This is probably because they have a ldquosurrounded-channel (S-ch) structure with a thin active layerrdquo and

are ldquoaccumulation-mode devicesrdquo and ldquoCAAC-IGZO has dielectric anisotropyrdquo(S-ch structure an FET structure where the active layer is electrically surrounded by the gate electrode)

GI = 11 nm

29

0

5

10

15

20

001 01 1 10 100

μ FE

[cm

2middotV-1

middot s-1]

チャネル長 [μm]

理論

Planar TypeS‐ch Type

0

200

400

600

001 01 1 10 100

μ FE

[cm

2 middotV-1

middots-1

]チャネル長 [μm]

理論

Planar Type

Short-channel Characteristics of OS FETs

Channel length dependence of field-effect mobility

(single-crystal Si FET)

Channel length dependence of field-effect mobility

（CAAC‐IGZO FET)

The field-effect mobility (μFE) of a CAAC-IGZO FET with a reduced channel length is close to that of a single-crystal Si FET with the same size

μ FE[

cm2 V

-1s

-1]

Channel length

0

20

5

10

15

10 nm 100 nm 1 μm 100 μm10 μm 10 nm 100 nm 1 μm 100 μm10 μm

Channel length

0

600

200

400

μ FE[

cm2 V

-1s

-1]

Theoretical Theoretical

30

Temperature Dependence of CAAC-IGZO FET

OS-FET

編集中編集中

L=048um GI=20nm

Vth

S値

ID_VG特性

単結晶 p-ch Si Tr （SOI）

L=035um GI=20nm L=035um GI=20nm

編集中 編集中

単結晶 n-ch Si Tr （SOI）

‐05

00

05

10

15

0 50 100 150 200 250

Vth[V]

基板温度 []

0

50

100

150

200

250

300

0 50 100 150 200 250

S‐Value[mVdec]

基板温度 []

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

Vg [V]

250

‐05

0

05

1

15

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

‐15

‐1

‐05

0

05

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

T = minus40C minus 25C 0C 25C 50C 100C 150C 200C 250C

CAAC-OS FETs have a sufficient onoff ratio even at 200C or higherThe S-value shows little change (or is constant) compared with Si FETs

Single‐crystal n‐ch Tr (SOI) Single‐crystal p‐ch Tr (SOI)OS FET

ID‐VGCharac‐teristics

Vth

S‐value

Substrate temperature [C] Substrate temperature [C] Substrate temperature [C]

Substrate temperature [C]Substrate temperature [C]Substrate temperature [C]

31

1E-07

1E-06

1E-05

1E-04

1E-03

1E-02

0 5 10 15 20 25 30V D [V]

ID [A

]Si transistorL =09um T ox=20nm

IGZO transistorL =09um T ox=20nm

4V 26V

L ＝ 09 μm W ＝ 10 μm TOX = 20 nm VG ＝ 2 V

n = 2

CAAC-IGZO transistors have a higher breakdown voltage than Si transistorsNo hot carrier degradation and avalanche breakdown are observed

Breakdown Voltage of CAAC-IGZO and Si FETs

32

Schematic Band Diagram of Channel Regionmdash OS FET vs n-ch Si FET

Inversion Depletion Accumulation

Vg gt 0 V (ON State) Vg lt 0 V (OFF State)Vg = 0V

CAAC-IGZO(S-channel)

n-ch Si

OS2CAAC-IGZO

OS3Gate E

GI GI

Gate E

Gate E

GI

Si

EC

EV

Ef

EfEC

EV

Eg=32eV

Eg=12eV

ElectronsA Arsquo

OS3

Holes

A ArsquoA Arsquo

33

M Murakami et al Proc AM-FPDrsquo12 Digest p 174 (2012)

CAAC-IGZO c-Si

1) Bandgap (Eg) 28ndash32 eV 112 eV

2) Intrinsic carrierconcentration 10minus9 cm3 10+11 cm3

3) Depletion layer km order μm order

4) Electron effective mass (meme)

023ndash025 019 (transverse)098 (longitudinal)

5) Hole effective mass (mhme)

11ndash40 016 (light)049 (heavy)

6) Structure Layered structure(Homologous) Diamond cubic

7) Conductivity i-type n-type n-type p-type

Comparison of Physical Properties between CAAC-IGZO and c-Si

34

Features of CAAC-IGZO as Device

CAAC‐IGZO c‐Si

1) Four-terminal circuitFour-terminal circuit MRAM and FeRAM are two-terminal circuits

2) Almost no short-channel effects Short-channel effects are most troublesome

3) Normally off Uncontrollable Vth high purity and intrinsic

Vth is controllable by channel doping with B

4) IonIoff ratio of 1020 IonIoff le 1010

5) nMOS onlyCMOS feasible with Si pMOS

CMOS Si nMOSSi pMOS

6) Bulk channel buried channel Shifting from surface-channel (planar) to bulk-channel (Fin)

35

4 30-nm Scaling of CAAC-IGZO FET

36

Trench Gate Self-aligned FET

L-direction W-direction

L-direction W-direction

CAAC-OS

Gate Electrode Gate Insulating Film

CAAC-OSDrain

ElectrodeSource

Electrode

Gate Electrode

Gate Insulating Film

48 nm

Gate Electrode

Gate Insulating Film

CAAC-OS34 nm

Source Electrode

Drain Electrode

CAAC-OS

Gate Insulating FilmGate Electrode

19 nm

50 nm

S-ch structure

FETrsquos active layer (CAAC-IGZO OS2 layer) is electrically surrounded by the gate electrodeWe call this FET structure a

surrounded-channel (S-ch) structure

37

Stacked Structure of OS FET and Si FET

pMOSSi

nMOSOS

GND

VDD

A Arsquo

B

Brsquo gate metal

source drain

gate insulator

CAAC-IGZO

electrode

gate

source drain

Si

SiO2

A Arsquo

B

Brsquo

OS FET

Si FET

High integration by stacking the CAAC-OS FET over the Si-FET

Si Substrate Si Substrate

W-directionL-direction

38

Comparison between CAAC-OS FET and Si nMOS FETItem CAAC-OS FET Si nMOS FET

1 Short-channel effect Small or none timesLarge (largest issue in Si NMOS FET)

2 Scaling le 30 nm (Possibility of 5 nm) Possible to ge 5 nm

3 Off-state current yAμm (10minus24 Aμm) times fAμm (10minus15 Aμm)

4 Mobility

Long channel Low High

Short channel Slightly decrease

Decrease (110 in 30-nm device)

5 Temperature characteristics

On-state current

Increase at high temperature

Decrease at high temperature

Off-state current Sufficiently low times

Drastically increase at high temperature

6 Drain breakdown voltage High Low7 Impact ionization Not observed Observed+2 +1 minus1 times minus2

39

Item CAAC-OS FET Si nMOS FET

8 Hot carrier degradation Not observed Large

9 Punch-through Not observed Strongly need balance with scaling

10 Frequency characteristics gt 30 GHz gt 300 GHz

11 Drift velocity Close to Si with channel length about 10 nm

Saturates with channel length about 100 nm

12 Sub-threshold value Small even with thick GI

Need thinner GI by miniaturizing

13 Dielectric anisotropy Observed Not observed

14 S-channel structure(Fin tri-gate type)

Extremely important and effective

Extremely important in shorter channel and effective

+25 minus1+2 +1 minus1 times minus2

Comparison between CAAC-OS FET and Si nMOS FET

40

5 CAAC-IGZO FET for LSI Application

41

Two-terminal circuit(diode)

Potential as Logic Circuit

Dependent control of input and output Need a transistor for four-terminal control Increased F2

Independently controllable inputs and outputs Desirable logic design Sufficiently low Ioff Practically an insulator

Four-terminal circuit

A B

C D

Input Output

42

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

Characteristics of CAAC-IGZO Film

Derived from quartz substrate

E-beam is incident parallel to the substrate surface

E-beam is incident perpendicularto the substrate surface

Rotation within (110) plane

Sample structure

electron diffraction (a-b plane)

X-ray diffraction (c-axis)

electron diffraction (c-axis)c-axis

a

b

Clear orientationNo orientation

Clearorientation

No orientation

CAAC c-axis-aligned a-b-plane-anchored crystalCAAC c-axis-aligned a-b-plane-anchored crystal

X-ray diffraction (a-b plane)

9

(d) CAAC crystal pellet (e) Cross-sectional image of unit pelletIn Ga or Zn O

(Chip)

Substrate

Cross-sectional TEM of CAAC-IGZO Film

08 nm

3 nm

(a) (b)TEM imageHR-TEM imageDetail of area in (a)

IGZO Film

Substrate

50 nm

10

平面TEM高分解能像FFT image processing-Extract data on a certain wavenumber range

Processing using an original program

Plan‐view TEM Crystal Lattice Image

FFT Filtered Image(FFTFast FourierTransform)

Lattice Extraction Image

Hexagonal Lattice Orientation Analysis amp

Color Mapping

Perfect regular hexagon

Neighboring lattice points(6 points)

Reference lattice point

1) Determine the orientation of a perfect regular hexagon so as to minimize the sum of the distances from the vertices of the perfect regular hexagon to six points neighboring a reference lattice point

Average distance a the average of distances from the reference lattice point to its neighboring six lattice points

2) Color each lattice point after the step 1) according to the difference from a reference angle In this study the modal angle was set to 30

6050403020100

ex

θ x

Average distance a

0 le θ lt 60

orientations of hexagons [degree]

Analysis Procedure Hexagonal LatticeOrientation Analysis amp Color Mapping

Processing using an original program

11

(a) A plan-view TEM image (b) A color mapping image obtained from an FFT filtered image of (a) The orientations of the hexagons are sorted by the angle (0minus60) and shown in different colors The colors of the adjoining grains are adjacent colors on the color scale

10 nm

(3)

(4)

(1)(2)

(a)

Plan-view Observations of CAAC-IGZO Film

(b)orientations of hexagons [degree]

60

50

40

30

20

10

0

12

(d)(a) (b) (c)

(d)(a) (c)(b)

(1)

(2)

Observations in Grain

Magnifying observations in a grain with a size of several tens of nanometers at the atomic level(a) Plan-view TEM images (b)(c) FFT filtered images (d) Color mapping imagesDotted lines denote boundaries between pellets Solid lines show a hexagon formed with lattice points

plan-view FFT filtered images color mapping

60

50

40

30

20

10

0

orientations of hexagons [degree]

Pellet

Hexagon formed with lattice points

Reg

ions

cor

resp

ondi

ng to

thos

e in

the

plan

-vie

w T

EM

imag

e of

the

wid

e ar

ea

13

In Ga or Zn O

066 nm

038 nm

ｚｚ

Side view of a unit cell

198 nm

181 nm

Surface of a unit cellHexagon formed with lattice points

07 nm

(Ga Zn)O

(Ga Zn)O

InO2

Homologous crystal structure

CAAC-OS pellet unit cellSemi hard material (a flexible crystal structure) by oxygen as a cushion between In Ga and Zn

Oxygen

Oxygen

14

Magnifying observations in a boundary portion between grains with a size of several tens of nanometers at the atomic level(a) Plan-view TEM images (b)(c) FFT filtered images (d) Color mapping imagesDeformed hexagons pentagons and heptagons are formed with lattice points at the boundary denoted by a dotted line and they are anchored to each other

Observations in Boundary Portion between Grains

60

50

40

30

20

10

0

orientations of hexagons [degree]

Boundary(3

)(4

)

plan-view FFT filtered images color mapping

(d)

(d)

(a)

(a) (c)

(b)

(b)

(c)R

egio

ns c

orre

spon

ding

to th

ose

in th

e pl

an-v

iew

TE

M im

age

of th

e w

ide

area

15

(a) and (c) Distribution of number of Voronoi polygons in single crystal IGZO and CAAC-IGZO (b) and (d) Distribution of Voronoi hexagons (yellow regions) and other polygons (blue regions) in the single crystal IGZO and the CAAC-IGZO

Distribution of Number of Voronoi Polygons

In the single crystal IGZO hexagonal Voronoi regions occupy almost the entire field of view In the CAAC-IGZO hexagons are the majority but pentagons and heptagons also appear

Single crystal IGZO CAAC-IGZOSingle crystal IGZO film [] CAAC-IGZO film []

Tetragon 01 07

Pentagon 12 155

Hexagon 982 683

Heptagon 04 145

Octagon 02 09

Nonagon 00 00

16

2 3 4 51

5 nmminus1

5 nmminus1

minus231degminus84degminus75 deg minus310degminus246deg

+118deg +15deg +135deg +04deg minus55deg2 3 4 51

(a)1 2 34 5

20 nm

(b) 12

3

4

5 20 nm

Panel (a) shows the points along the surface of the CAAC-IGZO film that were probed by NBED and the five remaining panels in the top row show the corresponding NBED patterns Panel (b) shows the points probed by NBED in the thickness of the film and the five remaining panels in the lower row show the corresponding NBED patterns The angle of the crystal axis is slightly shifted in both the surface and thickness directions

Nanobeam Electron Diffraction (NBED 1 nmɸ) Patterns of CAAC-IGZO Film

17

Nanobeam Electron Diffraction (NBED 1 nmɸ) Patterns of CAAC-IGZO Film

Broadanisotropic diffraction spots

Sharpcircular diffraction spots

The electron diffraction pattern of single-crystal IGZO has circular spots as shown in (b) Diffraction spots of CAAC-IGZO are not circular but anisotropic and broad

18

Schematic Band Diagram of IGZOSimple schematic diagram of defect levels in IGZO film

elec

tron

ener

gy [e

V]

surface shallow DOS(sDOS)

bulk shallow DOS(sDOS)

bulk deep DOS(dDOS)

Density of States (DOS) of IGZO

19

28-32 eV

Silicon oxide IGZO

CAAC-IGZO63 (gcm3)

nc-IGZO61 (gcm3)

a-like IGZO59 (gcm3)

αCPM Absorption coefficient estimated by a constant photocurrent method (CPM)

N Ishihara et al Proc AM-FPD12 143 (2012)J Koezuka et al SID2013 Symposium Digest 723 (2013)

A high density of deep-level states (dDOS) exists in the low-density IGZO filmThe higher the film density is (like CAAC) the lower the dDOS is

Light absorptions by IGZO films with different crystal structureswere measured to quantify the densities of deep energy trapstates (dDOS)

Density of States (DOS) of IGZO

a-like IGZO 53 times 100

20

Formation of Oxygen Vacancies (VO) in IGZO

software VASP

exchange correlation function

GGA

pseudo potential PAW

cut-off energy 800 eV

k-point 1times1times1VO are

likely to be formed

Crystal Amorphous

In Ga Zn O

-1180

-1178

-1176

-1174

-1172

-15 -10 -5 0 5 10 15

Tota

l Ene

rgy

[eV]

Distance from Interface [Aring]

InterfaceInterface

VO are highly likely to be formed

A comparison of formation of oxygen vacancies (VO) between amorphous and crystal structures was made by first-principles calculation The results indicate that VO are easily formed in the amorphous structure

21

Features of CAAC-IGZO as MaterialCAAC-IGZO c-Si

1)CAAC structure (not single-crystal nano-crystalline or amorphous)rarr No clear grain boundary is observed

lattice points to form a pentagon and heptagon

Single crystal is preferable because polycrystal has a high concentration of defects at grain boundaries2)

Crystal grains (pellets) are anchored to each other to form one big crystalrarr It can be used in VLSI devices on the scale of 5ndash60 nm

3) Not a close-packed structure rather has cushion propertiesA cubic dense structure Doped with B or P Formed by crystal pulling at approx 1420C4)

Although single-crystal IGZO is formed at very high temperatures of 1200ndash1500C CAAC-IGZO can be formed at 100ndash500C by sputteringrarr It can be placed between Si LSI and metal wire layers

5) Homologous layered structure (Semi hard structure) Diamond structure(hard)

6) Composed of four elements (In Ga Zn and O) Si alone

22

3 Performance of CAAC-IGZO FET

23

IdndashVg characteristics and mobilities of CAAC-IGZO FETs with channel lengths of (a) 2 μm and (b) 6 μm The channel widths are 50 μm

It may be possible to apply all kinds of displays (TV smartphone PC by using OEL LCD)

L = 2 μm (W = 50 μm) L = 6 μm (W = 50 μm)

High-mobility CAAC-IGZO FETs

24

(a) (b)

CAAC-IGZO TrIoff = 1times10minus22 Aμm

(100 yAμm)IonIoff = 1018

IndashV characteristics of CAAC-IGZO and Si transistors

Si TrIoff = 1times10minus12 Aμm

(1 pAμm)IonIoff = 109

Off-state Current of CAAC-IGZO and Si FETsUnit

zA (10minus21)

yA (10minus24)

aA (10minus18)

fA (10minus15)

pA (10minus12)

nA (10minus9)

μA (10minus6)

mA (10minus3)

25

How to Measure Off-state Current60

0 μm

360 μm L = 044 μmW = 10 mm(50 μmtimes200)Tox = 20 nm

A huge transistor with a channel width of 10 mm for off-state leakage current measurement (optical micrograph)

Concept of measurement

Node FN(Vout)

Behavior of potential at node FN (Vout) over time

Measuredtransistor

26

Arrhenius plot of off-state leakage current1)Change of Vout measured over time

1) S Yamazaki et al Jpn J Appl Phys vol 53 pp 04ED18 (2014)

At a gate voltage of minus3 V and 85Cthe off-state leakage current was 6 yAm (1 yA = 10minus24 A)Nonvolatility for 10 years at 85C is ensured

Off-state CurrentUnitAμm

mA (10minus3)μA (10minus6)nA (10minus9)pA (10minus12)fA (10minus15)aA (10minus18)zA (10minus21)yA (10minus24)Le

akag

e cu

rrent

[Aμ

m]

27

-5

0

5

10

15

20

25

30

RF

Gai

n [d

B]

周波数[Hz]109 1010 101130 GHz

Vd = 20 VVg = 20 V( gm max )

WL = 18 μm30 nm

Operation with a cutoff frequency of about 30 GHz is demonstratedThe off-state leakage current of an OS FET (W = 60 nm) is expected at 100 zA or less at 85C even for a 30-nm-node FET

Lower measurement limit

High Cutoff Frequency and Low Off-state Current (30 nm)

28

Frequency [Hz]30 GHz

LW = 30 18000 (60 nmtimes300 Parallel) nm

Short-channel Characteristics of OS FETs

Favorable FET characteristics were obtained with a 11-nm-thick gate insulating film when L = 32 nm

The graphs show that OS FETs are resistant to short-channel effects This is probably because they have a ldquosurrounded-channel (S-ch) structure with a thin active layerrdquo and

are ldquoaccumulation-mode devicesrdquo and ldquoCAAC-IGZO has dielectric anisotropyrdquo(S-ch structure an FET structure where the active layer is electrically surrounded by the gate electrode)

GI = 11 nm

29

0

5

10

15

20

001 01 1 10 100

μ FE

[cm

2middotV-1

middot s-1]

チャネル長 [μm]

理論

Planar TypeS‐ch Type

0

200

400

600

001 01 1 10 100

μ FE

[cm

2 middotV-1

middots-1

]チャネル長 [μm]

理論

Planar Type

Short-channel Characteristics of OS FETs

Channel length dependence of field-effect mobility

(single-crystal Si FET)

Channel length dependence of field-effect mobility

（CAAC‐IGZO FET)

The field-effect mobility (μFE) of a CAAC-IGZO FET with a reduced channel length is close to that of a single-crystal Si FET with the same size

μ FE[

cm2 V

-1s

-1]

Channel length

0

20

5

10

15

10 nm 100 nm 1 μm 100 μm10 μm 10 nm 100 nm 1 μm 100 μm10 μm

Channel length

0

600

200

400

μ FE[

cm2 V

-1s

-1]

Theoretical Theoretical

30

Temperature Dependence of CAAC-IGZO FET

OS-FET

編集中編集中

L=048um GI=20nm

Vth

S値

ID_VG特性

単結晶 p-ch Si Tr （SOI）

L=035um GI=20nm L=035um GI=20nm

編集中 編集中

単結晶 n-ch Si Tr （SOI）

‐05

00

05

10

15

0 50 100 150 200 250

Vth[V]

基板温度 []

0

50

100

150

200

250

300

0 50 100 150 200 250

S‐Value[mVdec]

基板温度 []

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

Vg [V]

250

‐05

0

05

1

15

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

‐15

‐1

‐05

0

05

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

T = minus40C minus 25C 0C 25C 50C 100C 150C 200C 250C

CAAC-OS FETs have a sufficient onoff ratio even at 200C or higherThe S-value shows little change (or is constant) compared with Si FETs

Single‐crystal n‐ch Tr (SOI) Single‐crystal p‐ch Tr (SOI)OS FET

ID‐VGCharac‐teristics

Vth

S‐value

Substrate temperature [C] Substrate temperature [C] Substrate temperature [C]

Substrate temperature [C]Substrate temperature [C]Substrate temperature [C]

31

1E-07

1E-06

1E-05

1E-04

1E-03

1E-02

0 5 10 15 20 25 30V D [V]

ID [A

]Si transistorL =09um T ox=20nm

IGZO transistorL =09um T ox=20nm

4V 26V

L ＝ 09 μm W ＝ 10 μm TOX = 20 nm VG ＝ 2 V

n = 2

CAAC-IGZO transistors have a higher breakdown voltage than Si transistorsNo hot carrier degradation and avalanche breakdown are observed

Breakdown Voltage of CAAC-IGZO and Si FETs

32

Schematic Band Diagram of Channel Regionmdash OS FET vs n-ch Si FET

Inversion Depletion Accumulation

Vg gt 0 V (ON State) Vg lt 0 V (OFF State)Vg = 0V

CAAC-IGZO(S-channel)

n-ch Si

OS2CAAC-IGZO

OS3Gate E

GI GI

Gate E

Gate E

GI

Si

EC

EV

Ef

EfEC

EV

Eg=32eV

Eg=12eV

ElectronsA Arsquo

OS3

Holes

A ArsquoA Arsquo

33

M Murakami et al Proc AM-FPDrsquo12 Digest p 174 (2012)

CAAC-IGZO c-Si

1) Bandgap (Eg) 28ndash32 eV 112 eV

2) Intrinsic carrierconcentration 10minus9 cm3 10+11 cm3

3) Depletion layer km order μm order

4) Electron effective mass (meme)

023ndash025 019 (transverse)098 (longitudinal)

5) Hole effective mass (mhme)

11ndash40 016 (light)049 (heavy)

6) Structure Layered structure(Homologous) Diamond cubic

7) Conductivity i-type n-type n-type p-type

Comparison of Physical Properties between CAAC-IGZO and c-Si

34

Features of CAAC-IGZO as Device

CAAC‐IGZO c‐Si

1) Four-terminal circuitFour-terminal circuit MRAM and FeRAM are two-terminal circuits

2) Almost no short-channel effects Short-channel effects are most troublesome

3) Normally off Uncontrollable Vth high purity and intrinsic

Vth is controllable by channel doping with B

4) IonIoff ratio of 1020 IonIoff le 1010

5) nMOS onlyCMOS feasible with Si pMOS

CMOS Si nMOSSi pMOS

6) Bulk channel buried channel Shifting from surface-channel (planar) to bulk-channel (Fin)

35

4 30-nm Scaling of CAAC-IGZO FET

36

Trench Gate Self-aligned FET

L-direction W-direction

L-direction W-direction

CAAC-OS

Gate Electrode Gate Insulating Film

CAAC-OSDrain

ElectrodeSource

Electrode

Gate Electrode

Gate Insulating Film

48 nm

Gate Electrode

Gate Insulating Film

CAAC-OS34 nm

Source Electrode

Drain Electrode

CAAC-OS

Gate Insulating FilmGate Electrode

19 nm

50 nm

S-ch structure

FETrsquos active layer (CAAC-IGZO OS2 layer) is electrically surrounded by the gate electrodeWe call this FET structure a

surrounded-channel (S-ch) structure

37

Stacked Structure of OS FET and Si FET

pMOSSi

nMOSOS

GND

VDD

A Arsquo

B

Brsquo gate metal

source drain

gate insulator

CAAC-IGZO

electrode

gate

source drain

Si

SiO2

A Arsquo

B

Brsquo

OS FET

Si FET

High integration by stacking the CAAC-OS FET over the Si-FET

Si Substrate Si Substrate

W-directionL-direction

38

Comparison between CAAC-OS FET and Si nMOS FETItem CAAC-OS FET Si nMOS FET

1 Short-channel effect Small or none timesLarge (largest issue in Si NMOS FET)

2 Scaling le 30 nm (Possibility of 5 nm) Possible to ge 5 nm

3 Off-state current yAμm (10minus24 Aμm) times fAμm (10minus15 Aμm)

4 Mobility

Long channel Low High

Short channel Slightly decrease

Decrease (110 in 30-nm device)

5 Temperature characteristics

On-state current

Increase at high temperature

Decrease at high temperature

Off-state current Sufficiently low times

Drastically increase at high temperature

6 Drain breakdown voltage High Low7 Impact ionization Not observed Observed+2 +1 minus1 times minus2

39

Item CAAC-OS FET Si nMOS FET

8 Hot carrier degradation Not observed Large

9 Punch-through Not observed Strongly need balance with scaling

10 Frequency characteristics gt 30 GHz gt 300 GHz

11 Drift velocity Close to Si with channel length about 10 nm

Saturates with channel length about 100 nm

12 Sub-threshold value Small even with thick GI

Need thinner GI by miniaturizing

13 Dielectric anisotropy Observed Not observed

14 S-channel structure(Fin tri-gate type)

Extremely important and effective

Extremely important in shorter channel and effective

+25 minus1+2 +1 minus1 times minus2

Comparison between CAAC-OS FET and Si nMOS FET

40

5 CAAC-IGZO FET for LSI Application

41

Two-terminal circuit(diode)

Potential as Logic Circuit

Dependent control of input and output Need a transistor for four-terminal control Increased F2

Independently controllable inputs and outputs Desirable logic design Sufficiently low Ioff Practically an insulator

Four-terminal circuit

A B

C D

Input Output

42

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

(d) CAAC crystal pellet (e) Cross-sectional image of unit pelletIn Ga or Zn O

(Chip)

Substrate

Cross-sectional TEM of CAAC-IGZO Film

08 nm

3 nm

(a) (b)TEM imageHR-TEM imageDetail of area in (a)

IGZO Film

Substrate

50 nm

10

平面TEM高分解能像FFT image processing-Extract data on a certain wavenumber range

Processing using an original program

Plan‐view TEM Crystal Lattice Image

FFT Filtered Image(FFTFast FourierTransform)

Lattice Extraction Image

Hexagonal Lattice Orientation Analysis amp

Color Mapping

Perfect regular hexagon

Neighboring lattice points(6 points)

Reference lattice point

1) Determine the orientation of a perfect regular hexagon so as to minimize the sum of the distances from the vertices of the perfect regular hexagon to six points neighboring a reference lattice point

Average distance a the average of distances from the reference lattice point to its neighboring six lattice points

2) Color each lattice point after the step 1) according to the difference from a reference angle In this study the modal angle was set to 30

6050403020100

ex

θ x

Average distance a

0 le θ lt 60

orientations of hexagons [degree]

Analysis Procedure Hexagonal LatticeOrientation Analysis amp Color Mapping

Processing using an original program

11

(a) A plan-view TEM image (b) A color mapping image obtained from an FFT filtered image of (a) The orientations of the hexagons are sorted by the angle (0minus60) and shown in different colors The colors of the adjoining grains are adjacent colors on the color scale

10 nm

(3)

(4)

(1)(2)

(a)

Plan-view Observations of CAAC-IGZO Film

(b)orientations of hexagons [degree]

60

50

40

30

20

10

0

12

(d)(a) (b) (c)

(d)(a) (c)(b)

(1)

(2)

Observations in Grain

Magnifying observations in a grain with a size of several tens of nanometers at the atomic level(a) Plan-view TEM images (b)(c) FFT filtered images (d) Color mapping imagesDotted lines denote boundaries between pellets Solid lines show a hexagon formed with lattice points

plan-view FFT filtered images color mapping

60

50

40

30

20

10

0

orientations of hexagons [degree]

Pellet

Hexagon formed with lattice points

Reg

ions

cor

resp

ondi

ng to

thos

e in

the

plan

-vie

w T

EM

imag

e of

the

wid

e ar

ea

13

In Ga or Zn O

066 nm

038 nm

ｚｚ

Side view of a unit cell

198 nm

181 nm

Surface of a unit cellHexagon formed with lattice points

07 nm

(Ga Zn)O

(Ga Zn)O

InO2

Homologous crystal structure

CAAC-OS pellet unit cellSemi hard material (a flexible crystal structure) by oxygen as a cushion between In Ga and Zn

Oxygen

Oxygen

14

Magnifying observations in a boundary portion between grains with a size of several tens of nanometers at the atomic level(a) Plan-view TEM images (b)(c) FFT filtered images (d) Color mapping imagesDeformed hexagons pentagons and heptagons are formed with lattice points at the boundary denoted by a dotted line and they are anchored to each other

Observations in Boundary Portion between Grains

60

50

40

30

20

10

0

orientations of hexagons [degree]

Boundary(3

)(4

)

plan-view FFT filtered images color mapping

(d)

(d)

(a)

(a) (c)

(b)

(b)

(c)R

egio

ns c

orre

spon

ding

to th

ose

in th

e pl

an-v

iew

TE

M im

age

of th

e w

ide

area

15

(a) and (c) Distribution of number of Voronoi polygons in single crystal IGZO and CAAC-IGZO (b) and (d) Distribution of Voronoi hexagons (yellow regions) and other polygons (blue regions) in the single crystal IGZO and the CAAC-IGZO

Distribution of Number of Voronoi Polygons

In the single crystal IGZO hexagonal Voronoi regions occupy almost the entire field of view In the CAAC-IGZO hexagons are the majority but pentagons and heptagons also appear

Single crystal IGZO CAAC-IGZOSingle crystal IGZO film [] CAAC-IGZO film []

Tetragon 01 07

Pentagon 12 155

Hexagon 982 683

Heptagon 04 145

Octagon 02 09

Nonagon 00 00

16

2 3 4 51

5 nmminus1

5 nmminus1

minus231degminus84degminus75 deg minus310degminus246deg

+118deg +15deg +135deg +04deg minus55deg2 3 4 51

(a)1 2 34 5

20 nm

(b) 12

3

4

5 20 nm

Panel (a) shows the points along the surface of the CAAC-IGZO film that were probed by NBED and the five remaining panels in the top row show the corresponding NBED patterns Panel (b) shows the points probed by NBED in the thickness of the film and the five remaining panels in the lower row show the corresponding NBED patterns The angle of the crystal axis is slightly shifted in both the surface and thickness directions

Nanobeam Electron Diffraction (NBED 1 nmɸ) Patterns of CAAC-IGZO Film

17

Nanobeam Electron Diffraction (NBED 1 nmɸ) Patterns of CAAC-IGZO Film

Broadanisotropic diffraction spots

Sharpcircular diffraction spots

The electron diffraction pattern of single-crystal IGZO has circular spots as shown in (b) Diffraction spots of CAAC-IGZO are not circular but anisotropic and broad

18

Schematic Band Diagram of IGZOSimple schematic diagram of defect levels in IGZO film

elec

tron

ener

gy [e

V]

surface shallow DOS(sDOS)

bulk shallow DOS(sDOS)

bulk deep DOS(dDOS)

Density of States (DOS) of IGZO

19

28-32 eV

Silicon oxide IGZO

CAAC-IGZO63 (gcm3)

nc-IGZO61 (gcm3)

a-like IGZO59 (gcm3)

αCPM Absorption coefficient estimated by a constant photocurrent method (CPM)

N Ishihara et al Proc AM-FPD12 143 (2012)J Koezuka et al SID2013 Symposium Digest 723 (2013)

A high density of deep-level states (dDOS) exists in the low-density IGZO filmThe higher the film density is (like CAAC) the lower the dDOS is

Light absorptions by IGZO films with different crystal structureswere measured to quantify the densities of deep energy trapstates (dDOS)

Density of States (DOS) of IGZO

a-like IGZO 53 times 100

20

Formation of Oxygen Vacancies (VO) in IGZO

software VASP

exchange correlation function

GGA

pseudo potential PAW

cut-off energy 800 eV

k-point 1times1times1VO are

likely to be formed

Crystal Amorphous

In Ga Zn O

-1180

-1178

-1176

-1174

-1172

-15 -10 -5 0 5 10 15

Tota

l Ene

rgy

[eV]

Distance from Interface [Aring]

InterfaceInterface

VO are highly likely to be formed

A comparison of formation of oxygen vacancies (VO) between amorphous and crystal structures was made by first-principles calculation The results indicate that VO are easily formed in the amorphous structure

21

Features of CAAC-IGZO as MaterialCAAC-IGZO c-Si

1)CAAC structure (not single-crystal nano-crystalline or amorphous)rarr No clear grain boundary is observed

lattice points to form a pentagon and heptagon

Single crystal is preferable because polycrystal has a high concentration of defects at grain boundaries2)

Crystal grains (pellets) are anchored to each other to form one big crystalrarr It can be used in VLSI devices on the scale of 5ndash60 nm

3) Not a close-packed structure rather has cushion propertiesA cubic dense structure Doped with B or P Formed by crystal pulling at approx 1420C4)

Although single-crystal IGZO is formed at very high temperatures of 1200ndash1500C CAAC-IGZO can be formed at 100ndash500C by sputteringrarr It can be placed between Si LSI and metal wire layers

5) Homologous layered structure (Semi hard structure) Diamond structure(hard)

6) Composed of four elements (In Ga Zn and O) Si alone

22

3 Performance of CAAC-IGZO FET

23

IdndashVg characteristics and mobilities of CAAC-IGZO FETs with channel lengths of (a) 2 μm and (b) 6 μm The channel widths are 50 μm

It may be possible to apply all kinds of displays (TV smartphone PC by using OEL LCD)

L = 2 μm (W = 50 μm) L = 6 μm (W = 50 μm)

High-mobility CAAC-IGZO FETs

24

(a) (b)

CAAC-IGZO TrIoff = 1times10minus22 Aμm

(100 yAμm)IonIoff = 1018

IndashV characteristics of CAAC-IGZO and Si transistors

Si TrIoff = 1times10minus12 Aμm

(1 pAμm)IonIoff = 109

Off-state Current of CAAC-IGZO and Si FETsUnit

zA (10minus21)

yA (10minus24)

aA (10minus18)

fA (10minus15)

pA (10minus12)

nA (10minus9)

μA (10minus6)

mA (10minus3)

25

How to Measure Off-state Current60

0 μm

360 μm L = 044 μmW = 10 mm(50 μmtimes200)Tox = 20 nm

A huge transistor with a channel width of 10 mm for off-state leakage current measurement (optical micrograph)

Concept of measurement

Node FN(Vout)

Behavior of potential at node FN (Vout) over time

Measuredtransistor

26

Arrhenius plot of off-state leakage current1)Change of Vout measured over time

1) S Yamazaki et al Jpn J Appl Phys vol 53 pp 04ED18 (2014)

At a gate voltage of minus3 V and 85Cthe off-state leakage current was 6 yAm (1 yA = 10minus24 A)Nonvolatility for 10 years at 85C is ensured

Off-state CurrentUnitAμm

mA (10minus3)μA (10minus6)nA (10minus9)pA (10minus12)fA (10minus15)aA (10minus18)zA (10minus21)yA (10minus24)Le

akag

e cu

rrent

[Aμ

m]

27

-5

0

5

10

15

20

25

30

RF

Gai

n [d

B]

周波数[Hz]109 1010 101130 GHz

Vd = 20 VVg = 20 V( gm max )

WL = 18 μm30 nm

Operation with a cutoff frequency of about 30 GHz is demonstratedThe off-state leakage current of an OS FET (W = 60 nm) is expected at 100 zA or less at 85C even for a 30-nm-node FET

Lower measurement limit

High Cutoff Frequency and Low Off-state Current (30 nm)

28

Frequency [Hz]30 GHz

LW = 30 18000 (60 nmtimes300 Parallel) nm

Short-channel Characteristics of OS FETs

Favorable FET characteristics were obtained with a 11-nm-thick gate insulating film when L = 32 nm

The graphs show that OS FETs are resistant to short-channel effects This is probably because they have a ldquosurrounded-channel (S-ch) structure with a thin active layerrdquo and

are ldquoaccumulation-mode devicesrdquo and ldquoCAAC-IGZO has dielectric anisotropyrdquo(S-ch structure an FET structure where the active layer is electrically surrounded by the gate electrode)

GI = 11 nm

29

0

5

10

15

20

001 01 1 10 100

μ FE

[cm

2middotV-1

middot s-1]

チャネル長 [μm]

理論

Planar TypeS‐ch Type

0

200

400

600

001 01 1 10 100

μ FE

[cm

2 middotV-1

middots-1

]チャネル長 [μm]

理論

Planar Type

Short-channel Characteristics of OS FETs

Channel length dependence of field-effect mobility

(single-crystal Si FET)

Channel length dependence of field-effect mobility

（CAAC‐IGZO FET)

The field-effect mobility (μFE) of a CAAC-IGZO FET with a reduced channel length is close to that of a single-crystal Si FET with the same size

μ FE[

cm2 V

-1s

-1]

Channel length

0

20

5

10

15

10 nm 100 nm 1 μm 100 μm10 μm 10 nm 100 nm 1 μm 100 μm10 μm

Channel length

0

600

200

400

μ FE[

cm2 V

-1s

-1]

Theoretical Theoretical

30

Temperature Dependence of CAAC-IGZO FET

OS-FET

編集中編集中

L=048um GI=20nm

Vth

S値

ID_VG特性

単結晶 p-ch Si Tr （SOI）

L=035um GI=20nm L=035um GI=20nm

編集中 編集中

単結晶 n-ch Si Tr （SOI）

‐05

00

05

10

15

0 50 100 150 200 250

Vth[V]

基板温度 []

0

50

100

150

200

250

300

0 50 100 150 200 250

S‐Value[mVdec]

基板温度 []

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

Vg [V]

250

‐05

0

05

1

15

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

‐15

‐1

‐05

0

05

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

T = minus40C minus 25C 0C 25C 50C 100C 150C 200C 250C

CAAC-OS FETs have a sufficient onoff ratio even at 200C or higherThe S-value shows little change (or is constant) compared with Si FETs

Single‐crystal n‐ch Tr (SOI) Single‐crystal p‐ch Tr (SOI)OS FET

ID‐VGCharac‐teristics

Vth

S‐value

Substrate temperature [C] Substrate temperature [C] Substrate temperature [C]

Substrate temperature [C]Substrate temperature [C]Substrate temperature [C]

31

1E-07

1E-06

1E-05

1E-04

1E-03

1E-02

0 5 10 15 20 25 30V D [V]

ID [A

]Si transistorL =09um T ox=20nm

IGZO transistorL =09um T ox=20nm

4V 26V

L ＝ 09 μm W ＝ 10 μm TOX = 20 nm VG ＝ 2 V

n = 2

CAAC-IGZO transistors have a higher breakdown voltage than Si transistorsNo hot carrier degradation and avalanche breakdown are observed

Breakdown Voltage of CAAC-IGZO and Si FETs

32

Schematic Band Diagram of Channel Regionmdash OS FET vs n-ch Si FET

Inversion Depletion Accumulation

Vg gt 0 V (ON State) Vg lt 0 V (OFF State)Vg = 0V

CAAC-IGZO(S-channel)

n-ch Si

OS2CAAC-IGZO

OS3Gate E

GI GI

Gate E

Gate E

GI

Si

EC

EV

Ef

EfEC

EV

Eg=32eV

Eg=12eV

ElectronsA Arsquo

OS3

Holes

A ArsquoA Arsquo

33

M Murakami et al Proc AM-FPDrsquo12 Digest p 174 (2012)

CAAC-IGZO c-Si

1) Bandgap (Eg) 28ndash32 eV 112 eV

2) Intrinsic carrierconcentration 10minus9 cm3 10+11 cm3

3) Depletion layer km order μm order

4) Electron effective mass (meme)

023ndash025 019 (transverse)098 (longitudinal)

5) Hole effective mass (mhme)

11ndash40 016 (light)049 (heavy)

6) Structure Layered structure(Homologous) Diamond cubic

7) Conductivity i-type n-type n-type p-type

Comparison of Physical Properties between CAAC-IGZO and c-Si

34

Features of CAAC-IGZO as Device

CAAC‐IGZO c‐Si

1) Four-terminal circuitFour-terminal circuit MRAM and FeRAM are two-terminal circuits

2) Almost no short-channel effects Short-channel effects are most troublesome

3) Normally off Uncontrollable Vth high purity and intrinsic

Vth is controllable by channel doping with B

4) IonIoff ratio of 1020 IonIoff le 1010

5) nMOS onlyCMOS feasible with Si pMOS

CMOS Si nMOSSi pMOS

6) Bulk channel buried channel Shifting from surface-channel (planar) to bulk-channel (Fin)

35

4 30-nm Scaling of CAAC-IGZO FET

36

Trench Gate Self-aligned FET

L-direction W-direction

L-direction W-direction

CAAC-OS

Gate Electrode Gate Insulating Film

CAAC-OSDrain

ElectrodeSource

Electrode

Gate Electrode

Gate Insulating Film

48 nm

Gate Electrode

Gate Insulating Film

CAAC-OS34 nm

Source Electrode

Drain Electrode

CAAC-OS

Gate Insulating FilmGate Electrode

19 nm

50 nm

S-ch structure

FETrsquos active layer (CAAC-IGZO OS2 layer) is electrically surrounded by the gate electrodeWe call this FET structure a

surrounded-channel (S-ch) structure

37

Stacked Structure of OS FET and Si FET

pMOSSi

nMOSOS

GND

VDD

A Arsquo

B

Brsquo gate metal

source drain

gate insulator

CAAC-IGZO

electrode

gate

source drain

Si

SiO2

A Arsquo

B

Brsquo

OS FET

Si FET

High integration by stacking the CAAC-OS FET over the Si-FET

Si Substrate Si Substrate

W-directionL-direction

38

Comparison between CAAC-OS FET and Si nMOS FETItem CAAC-OS FET Si nMOS FET

1 Short-channel effect Small or none timesLarge (largest issue in Si NMOS FET)

2 Scaling le 30 nm (Possibility of 5 nm) Possible to ge 5 nm

3 Off-state current yAμm (10minus24 Aμm) times fAμm (10minus15 Aμm)

4 Mobility

Long channel Low High

Short channel Slightly decrease

Decrease (110 in 30-nm device)

5 Temperature characteristics

On-state current

Increase at high temperature

Decrease at high temperature

Off-state current Sufficiently low times

Drastically increase at high temperature

6 Drain breakdown voltage High Low7 Impact ionization Not observed Observed+2 +1 minus1 times minus2

39

Item CAAC-OS FET Si nMOS FET

8 Hot carrier degradation Not observed Large

9 Punch-through Not observed Strongly need balance with scaling

10 Frequency characteristics gt 30 GHz gt 300 GHz

11 Drift velocity Close to Si with channel length about 10 nm

Saturates with channel length about 100 nm

12 Sub-threshold value Small even with thick GI

Need thinner GI by miniaturizing

13 Dielectric anisotropy Observed Not observed

14 S-channel structure(Fin tri-gate type)

Extremely important and effective

Extremely important in shorter channel and effective

+25 minus1+2 +1 minus1 times minus2

Comparison between CAAC-OS FET and Si nMOS FET

40

5 CAAC-IGZO FET for LSI Application

41

Two-terminal circuit(diode)

Potential as Logic Circuit

Dependent control of input and output Need a transistor for four-terminal control Increased F2

Independently controllable inputs and outputs Desirable logic design Sufficiently low Ioff Practically an insulator

Four-terminal circuit

A B

C D

Input Output

42

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

平面TEM高分解能像FFT image processing-Extract data on a certain wavenumber range

Processing using an original program

Plan‐view TEM Crystal Lattice Image

FFT Filtered Image(FFTFast FourierTransform)

Lattice Extraction Image

Hexagonal Lattice Orientation Analysis amp

Color Mapping

Perfect regular hexagon

Neighboring lattice points(6 points)

Reference lattice point

1) Determine the orientation of a perfect regular hexagon so as to minimize the sum of the distances from the vertices of the perfect regular hexagon to six points neighboring a reference lattice point

Average distance a the average of distances from the reference lattice point to its neighboring six lattice points

2) Color each lattice point after the step 1) according to the difference from a reference angle In this study the modal angle was set to 30

6050403020100

ex

θ x

Average distance a

0 le θ lt 60

orientations of hexagons [degree]

Analysis Procedure Hexagonal LatticeOrientation Analysis amp Color Mapping

Processing using an original program

11

(a) A plan-view TEM image (b) A color mapping image obtained from an FFT filtered image of (a) The orientations of the hexagons are sorted by the angle (0minus60) and shown in different colors The colors of the adjoining grains are adjacent colors on the color scale

10 nm

(3)

(4)

(1)(2)

(a)

Plan-view Observations of CAAC-IGZO Film

(b)orientations of hexagons [degree]

60

50

40

30

20

10

0

12

(d)(a) (b) (c)

(d)(a) (c)(b)

(1)

(2)

Observations in Grain

Magnifying observations in a grain with a size of several tens of nanometers at the atomic level(a) Plan-view TEM images (b)(c) FFT filtered images (d) Color mapping imagesDotted lines denote boundaries between pellets Solid lines show a hexagon formed with lattice points

plan-view FFT filtered images color mapping

60

50

40

30

20

10

0

orientations of hexagons [degree]

Pellet

Hexagon formed with lattice points

Reg

ions

cor

resp

ondi

ng to

thos

e in

the

plan

-vie

w T

EM

imag

e of

the

wid

e ar

ea

13

In Ga or Zn O

066 nm

038 nm

ｚｚ

Side view of a unit cell

198 nm

181 nm

Surface of a unit cellHexagon formed with lattice points

07 nm

(Ga Zn)O

(Ga Zn)O

InO2

Homologous crystal structure

CAAC-OS pellet unit cellSemi hard material (a flexible crystal structure) by oxygen as a cushion between In Ga and Zn

Oxygen

Oxygen

14

Magnifying observations in a boundary portion between grains with a size of several tens of nanometers at the atomic level(a) Plan-view TEM images (b)(c) FFT filtered images (d) Color mapping imagesDeformed hexagons pentagons and heptagons are formed with lattice points at the boundary denoted by a dotted line and they are anchored to each other

Observations in Boundary Portion between Grains

60

50

40

30

20

10

0

orientations of hexagons [degree]

Boundary(3

)(4

)

plan-view FFT filtered images color mapping

(d)

(d)

(a)

(a) (c)

(b)

(b)

(c)R

egio

ns c

orre

spon

ding

to th

ose

in th

e pl

an-v

iew

TE

M im

age

of th

e w

ide

area

15

(a) and (c) Distribution of number of Voronoi polygons in single crystal IGZO and CAAC-IGZO (b) and (d) Distribution of Voronoi hexagons (yellow regions) and other polygons (blue regions) in the single crystal IGZO and the CAAC-IGZO

Distribution of Number of Voronoi Polygons

In the single crystal IGZO hexagonal Voronoi regions occupy almost the entire field of view In the CAAC-IGZO hexagons are the majority but pentagons and heptagons also appear

Single crystal IGZO CAAC-IGZOSingle crystal IGZO film [] CAAC-IGZO film []

Tetragon 01 07

Pentagon 12 155

Hexagon 982 683

Heptagon 04 145

Octagon 02 09

Nonagon 00 00

16

2 3 4 51

5 nmminus1

5 nmminus1

minus231degminus84degminus75 deg minus310degminus246deg

+118deg +15deg +135deg +04deg minus55deg2 3 4 51

(a)1 2 34 5

20 nm

(b) 12

3

4

5 20 nm

Panel (a) shows the points along the surface of the CAAC-IGZO film that were probed by NBED and the five remaining panels in the top row show the corresponding NBED patterns Panel (b) shows the points probed by NBED in the thickness of the film and the five remaining panels in the lower row show the corresponding NBED patterns The angle of the crystal axis is slightly shifted in both the surface and thickness directions

Nanobeam Electron Diffraction (NBED 1 nmɸ) Patterns of CAAC-IGZO Film

17

Nanobeam Electron Diffraction (NBED 1 nmɸ) Patterns of CAAC-IGZO Film

Broadanisotropic diffraction spots

Sharpcircular diffraction spots

The electron diffraction pattern of single-crystal IGZO has circular spots as shown in (b) Diffraction spots of CAAC-IGZO are not circular but anisotropic and broad

18

Schematic Band Diagram of IGZOSimple schematic diagram of defect levels in IGZO film

elec

tron

ener

gy [e

V]

surface shallow DOS(sDOS)

bulk shallow DOS(sDOS)

bulk deep DOS(dDOS)

Density of States (DOS) of IGZO

19

28-32 eV

Silicon oxide IGZO

CAAC-IGZO63 (gcm3)

nc-IGZO61 (gcm3)

a-like IGZO59 (gcm3)

αCPM Absorption coefficient estimated by a constant photocurrent method (CPM)

N Ishihara et al Proc AM-FPD12 143 (2012)J Koezuka et al SID2013 Symposium Digest 723 (2013)

A high density of deep-level states (dDOS) exists in the low-density IGZO filmThe higher the film density is (like CAAC) the lower the dDOS is

Light absorptions by IGZO films with different crystal structureswere measured to quantify the densities of deep energy trapstates (dDOS)

Density of States (DOS) of IGZO

a-like IGZO 53 times 100

20

Formation of Oxygen Vacancies (VO) in IGZO

software VASP

exchange correlation function

GGA

pseudo potential PAW

cut-off energy 800 eV

k-point 1times1times1VO are

likely to be formed

Crystal Amorphous

In Ga Zn O

-1180

-1178

-1176

-1174

-1172

-15 -10 -5 0 5 10 15

Tota

l Ene

rgy

[eV]

Distance from Interface [Aring]

InterfaceInterface

VO are highly likely to be formed

A comparison of formation of oxygen vacancies (VO) between amorphous and crystal structures was made by first-principles calculation The results indicate that VO are easily formed in the amorphous structure

21

Features of CAAC-IGZO as MaterialCAAC-IGZO c-Si

1)CAAC structure (not single-crystal nano-crystalline or amorphous)rarr No clear grain boundary is observed

lattice points to form a pentagon and heptagon

Single crystal is preferable because polycrystal has a high concentration of defects at grain boundaries2)

Crystal grains (pellets) are anchored to each other to form one big crystalrarr It can be used in VLSI devices on the scale of 5ndash60 nm

3) Not a close-packed structure rather has cushion propertiesA cubic dense structure Doped with B or P Formed by crystal pulling at approx 1420C4)

Although single-crystal IGZO is formed at very high temperatures of 1200ndash1500C CAAC-IGZO can be formed at 100ndash500C by sputteringrarr It can be placed between Si LSI and metal wire layers

5) Homologous layered structure (Semi hard structure) Diamond structure(hard)

6) Composed of four elements (In Ga Zn and O) Si alone

22

3 Performance of CAAC-IGZO FET

23

IdndashVg characteristics and mobilities of CAAC-IGZO FETs with channel lengths of (a) 2 μm and (b) 6 μm The channel widths are 50 μm

It may be possible to apply all kinds of displays (TV smartphone PC by using OEL LCD)

L = 2 μm (W = 50 μm) L = 6 μm (W = 50 μm)

High-mobility CAAC-IGZO FETs

24

(a) (b)

CAAC-IGZO TrIoff = 1times10minus22 Aμm

(100 yAμm)IonIoff = 1018

IndashV characteristics of CAAC-IGZO and Si transistors

Si TrIoff = 1times10minus12 Aμm

(1 pAμm)IonIoff = 109

Off-state Current of CAAC-IGZO and Si FETsUnit

zA (10minus21)

yA (10minus24)

aA (10minus18)

fA (10minus15)

pA (10minus12)

nA (10minus9)

μA (10minus6)

mA (10minus3)

25

How to Measure Off-state Current60

0 μm

360 μm L = 044 μmW = 10 mm(50 μmtimes200)Tox = 20 nm

A huge transistor with a channel width of 10 mm for off-state leakage current measurement (optical micrograph)

Concept of measurement

Node FN(Vout)

Behavior of potential at node FN (Vout) over time

Measuredtransistor

26

Arrhenius plot of off-state leakage current1)Change of Vout measured over time

1) S Yamazaki et al Jpn J Appl Phys vol 53 pp 04ED18 (2014)

At a gate voltage of minus3 V and 85Cthe off-state leakage current was 6 yAm (1 yA = 10minus24 A)Nonvolatility for 10 years at 85C is ensured

Off-state CurrentUnitAμm

mA (10minus3)μA (10minus6)nA (10minus9)pA (10minus12)fA (10minus15)aA (10minus18)zA (10minus21)yA (10minus24)Le

akag

e cu

rrent

[Aμ

m]

27

-5

0

5

10

15

20

25

30

RF

Gai

n [d

B]

周波数[Hz]109 1010 101130 GHz

Vd = 20 VVg = 20 V( gm max )

WL = 18 μm30 nm

Operation with a cutoff frequency of about 30 GHz is demonstratedThe off-state leakage current of an OS FET (W = 60 nm) is expected at 100 zA or less at 85C even for a 30-nm-node FET

Lower measurement limit

High Cutoff Frequency and Low Off-state Current (30 nm)

28

Frequency [Hz]30 GHz

LW = 30 18000 (60 nmtimes300 Parallel) nm

Short-channel Characteristics of OS FETs

Favorable FET characteristics were obtained with a 11-nm-thick gate insulating film when L = 32 nm

The graphs show that OS FETs are resistant to short-channel effects This is probably because they have a ldquosurrounded-channel (S-ch) structure with a thin active layerrdquo and

are ldquoaccumulation-mode devicesrdquo and ldquoCAAC-IGZO has dielectric anisotropyrdquo(S-ch structure an FET structure where the active layer is electrically surrounded by the gate electrode)

GI = 11 nm

29

0

5

10

15

20

001 01 1 10 100

μ FE

[cm

2middotV-1

middot s-1]

チャネル長 [μm]

理論

Planar TypeS‐ch Type

0

200

400

600

001 01 1 10 100

μ FE

[cm

2 middotV-1

middots-1

]チャネル長 [μm]

理論

Planar Type

Short-channel Characteristics of OS FETs

Channel length dependence of field-effect mobility

(single-crystal Si FET)

Channel length dependence of field-effect mobility

（CAAC‐IGZO FET)

The field-effect mobility (μFE) of a CAAC-IGZO FET with a reduced channel length is close to that of a single-crystal Si FET with the same size

μ FE[

cm2 V

-1s

-1]

Channel length

0

20

5

10

15

10 nm 100 nm 1 μm 100 μm10 μm 10 nm 100 nm 1 μm 100 μm10 μm

Channel length

0

600

200

400

μ FE[

cm2 V

-1s

-1]

Theoretical Theoretical

30

Temperature Dependence of CAAC-IGZO FET

OS-FET

編集中編集中

L=048um GI=20nm

Vth

S値

ID_VG特性

単結晶 p-ch Si Tr （SOI）

L=035um GI=20nm L=035um GI=20nm

編集中 編集中

単結晶 n-ch Si Tr （SOI）

‐05

00

05

10

15

0 50 100 150 200 250

Vth[V]

基板温度 []

0

50

100

150

200

250

300

0 50 100 150 200 250

S‐Value[mVdec]

基板温度 []

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

Vg [V]

250

‐05

0

05

1

15

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

‐15

‐1

‐05

0

05

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

T = minus40C minus 25C 0C 25C 50C 100C 150C 200C 250C

CAAC-OS FETs have a sufficient onoff ratio even at 200C or higherThe S-value shows little change (or is constant) compared with Si FETs

Single‐crystal n‐ch Tr (SOI) Single‐crystal p‐ch Tr (SOI)OS FET

ID‐VGCharac‐teristics

Vth

S‐value

Substrate temperature [C] Substrate temperature [C] Substrate temperature [C]

Substrate temperature [C]Substrate temperature [C]Substrate temperature [C]

31

1E-07

1E-06

1E-05

1E-04

1E-03

1E-02

0 5 10 15 20 25 30V D [V]

ID [A

]Si transistorL =09um T ox=20nm

IGZO transistorL =09um T ox=20nm

4V 26V

L ＝ 09 μm W ＝ 10 μm TOX = 20 nm VG ＝ 2 V

n = 2

CAAC-IGZO transistors have a higher breakdown voltage than Si transistorsNo hot carrier degradation and avalanche breakdown are observed

Breakdown Voltage of CAAC-IGZO and Si FETs

32

Schematic Band Diagram of Channel Regionmdash OS FET vs n-ch Si FET

Inversion Depletion Accumulation

Vg gt 0 V (ON State) Vg lt 0 V (OFF State)Vg = 0V

CAAC-IGZO(S-channel)

n-ch Si

OS2CAAC-IGZO

OS3Gate E

GI GI

Gate E

Gate E

GI

Si

EC

EV

Ef

EfEC

EV

Eg=32eV

Eg=12eV

ElectronsA Arsquo

OS3

Holes

A ArsquoA Arsquo

33

M Murakami et al Proc AM-FPDrsquo12 Digest p 174 (2012)

CAAC-IGZO c-Si

1) Bandgap (Eg) 28ndash32 eV 112 eV

2) Intrinsic carrierconcentration 10minus9 cm3 10+11 cm3

3) Depletion layer km order μm order

4) Electron effective mass (meme)

023ndash025 019 (transverse)098 (longitudinal)

5) Hole effective mass (mhme)

11ndash40 016 (light)049 (heavy)

6) Structure Layered structure(Homologous) Diamond cubic

7) Conductivity i-type n-type n-type p-type

Comparison of Physical Properties between CAAC-IGZO and c-Si

34

Features of CAAC-IGZO as Device

CAAC‐IGZO c‐Si

1) Four-terminal circuitFour-terminal circuit MRAM and FeRAM are two-terminal circuits

2) Almost no short-channel effects Short-channel effects are most troublesome

3) Normally off Uncontrollable Vth high purity and intrinsic

Vth is controllable by channel doping with B

4) IonIoff ratio of 1020 IonIoff le 1010

5) nMOS onlyCMOS feasible with Si pMOS

CMOS Si nMOSSi pMOS

6) Bulk channel buried channel Shifting from surface-channel (planar) to bulk-channel (Fin)

35

4 30-nm Scaling of CAAC-IGZO FET

36

Trench Gate Self-aligned FET

L-direction W-direction

L-direction W-direction

CAAC-OS

Gate Electrode Gate Insulating Film

CAAC-OSDrain

ElectrodeSource

Electrode

Gate Electrode

Gate Insulating Film

48 nm

Gate Electrode

Gate Insulating Film

CAAC-OS34 nm

Source Electrode

Drain Electrode

CAAC-OS

Gate Insulating FilmGate Electrode

19 nm

50 nm

S-ch structure

FETrsquos active layer (CAAC-IGZO OS2 layer) is electrically surrounded by the gate electrodeWe call this FET structure a

surrounded-channel (S-ch) structure

37

Stacked Structure of OS FET and Si FET

pMOSSi

nMOSOS

GND

VDD

A Arsquo

B

Brsquo gate metal

source drain

gate insulator

CAAC-IGZO

electrode

gate

source drain

Si

SiO2

A Arsquo

B

Brsquo

OS FET

Si FET

High integration by stacking the CAAC-OS FET over the Si-FET

Si Substrate Si Substrate

W-directionL-direction

38

Comparison between CAAC-OS FET and Si nMOS FETItem CAAC-OS FET Si nMOS FET

1 Short-channel effect Small or none timesLarge (largest issue in Si NMOS FET)

2 Scaling le 30 nm (Possibility of 5 nm) Possible to ge 5 nm

3 Off-state current yAμm (10minus24 Aμm) times fAμm (10minus15 Aμm)

4 Mobility

Long channel Low High

Short channel Slightly decrease

Decrease (110 in 30-nm device)

5 Temperature characteristics

On-state current

Increase at high temperature

Decrease at high temperature

Off-state current Sufficiently low times

Drastically increase at high temperature

6 Drain breakdown voltage High Low7 Impact ionization Not observed Observed+2 +1 minus1 times minus2

39

Item CAAC-OS FET Si nMOS FET

8 Hot carrier degradation Not observed Large

9 Punch-through Not observed Strongly need balance with scaling

10 Frequency characteristics gt 30 GHz gt 300 GHz

11 Drift velocity Close to Si with channel length about 10 nm

Saturates with channel length about 100 nm

12 Sub-threshold value Small even with thick GI

Need thinner GI by miniaturizing

13 Dielectric anisotropy Observed Not observed

14 S-channel structure(Fin tri-gate type)

Extremely important and effective

Extremely important in shorter channel and effective

+25 minus1+2 +1 minus1 times minus2

Comparison between CAAC-OS FET and Si nMOS FET

40

5 CAAC-IGZO FET for LSI Application

41

Two-terminal circuit(diode)

Potential as Logic Circuit

Dependent control of input and output Need a transistor for four-terminal control Increased F2

Independently controllable inputs and outputs Desirable logic design Sufficiently low Ioff Practically an insulator

Four-terminal circuit

A B

C D

Input Output

42

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

(a) A plan-view TEM image (b) A color mapping image obtained from an FFT filtered image of (a) The orientations of the hexagons are sorted by the angle (0minus60) and shown in different colors The colors of the adjoining grains are adjacent colors on the color scale

10 nm

(3)

(4)

(1)(2)

(a)

Plan-view Observations of CAAC-IGZO Film

(b)orientations of hexagons [degree]

60

50

40

30

20

10

0

12

(d)(a) (b) (c)

(d)(a) (c)(b)

(1)

(2)

Observations in Grain

Magnifying observations in a grain with a size of several tens of nanometers at the atomic level(a) Plan-view TEM images (b)(c) FFT filtered images (d) Color mapping imagesDotted lines denote boundaries between pellets Solid lines show a hexagon formed with lattice points

plan-view FFT filtered images color mapping

60

50

40

30

20

10

0

orientations of hexagons [degree]

Pellet

Hexagon formed with lattice points

Reg

ions

cor

resp

ondi

ng to

thos

e in

the

plan

-vie

w T

EM

imag

e of

the

wid

e ar

ea

13

In Ga or Zn O

066 nm

038 nm

ｚｚ

Side view of a unit cell

198 nm

181 nm

Surface of a unit cellHexagon formed with lattice points

07 nm

(Ga Zn)O

(Ga Zn)O

InO2

Homologous crystal structure

CAAC-OS pellet unit cellSemi hard material (a flexible crystal structure) by oxygen as a cushion between In Ga and Zn

Oxygen

Oxygen

14

Magnifying observations in a boundary portion between grains with a size of several tens of nanometers at the atomic level(a) Plan-view TEM images (b)(c) FFT filtered images (d) Color mapping imagesDeformed hexagons pentagons and heptagons are formed with lattice points at the boundary denoted by a dotted line and they are anchored to each other

Observations in Boundary Portion between Grains

60

50

40

30

20

10

0

orientations of hexagons [degree]

Boundary(3

)(4

)

plan-view FFT filtered images color mapping

(d)

(d)

(a)

(a) (c)

(b)

(b)

(c)R

egio

ns c

orre

spon

ding

to th

ose

in th

e pl

an-v

iew

TE

M im

age

of th

e w

ide

area

15

(a) and (c) Distribution of number of Voronoi polygons in single crystal IGZO and CAAC-IGZO (b) and (d) Distribution of Voronoi hexagons (yellow regions) and other polygons (blue regions) in the single crystal IGZO and the CAAC-IGZO

Distribution of Number of Voronoi Polygons

In the single crystal IGZO hexagonal Voronoi regions occupy almost the entire field of view In the CAAC-IGZO hexagons are the majority but pentagons and heptagons also appear

Single crystal IGZO CAAC-IGZOSingle crystal IGZO film [] CAAC-IGZO film []

Tetragon 01 07

Pentagon 12 155

Hexagon 982 683

Heptagon 04 145

Octagon 02 09

Nonagon 00 00

16

2 3 4 51

5 nmminus1

5 nmminus1

minus231degminus84degminus75 deg minus310degminus246deg

+118deg +15deg +135deg +04deg minus55deg2 3 4 51

(a)1 2 34 5

20 nm

(b) 12

3

4

5 20 nm

Panel (a) shows the points along the surface of the CAAC-IGZO film that were probed by NBED and the five remaining panels in the top row show the corresponding NBED patterns Panel (b) shows the points probed by NBED in the thickness of the film and the five remaining panels in the lower row show the corresponding NBED patterns The angle of the crystal axis is slightly shifted in both the surface and thickness directions

Nanobeam Electron Diffraction (NBED 1 nmɸ) Patterns of CAAC-IGZO Film

17

Nanobeam Electron Diffraction (NBED 1 nmɸ) Patterns of CAAC-IGZO Film

Broadanisotropic diffraction spots

Sharpcircular diffraction spots

The electron diffraction pattern of single-crystal IGZO has circular spots as shown in (b) Diffraction spots of CAAC-IGZO are not circular but anisotropic and broad

18

Schematic Band Diagram of IGZOSimple schematic diagram of defect levels in IGZO film

elec

tron

ener

gy [e

V]

surface shallow DOS(sDOS)

bulk shallow DOS(sDOS)

bulk deep DOS(dDOS)

Density of States (DOS) of IGZO

19

28-32 eV

Silicon oxide IGZO

CAAC-IGZO63 (gcm3)

nc-IGZO61 (gcm3)

a-like IGZO59 (gcm3)

αCPM Absorption coefficient estimated by a constant photocurrent method (CPM)

N Ishihara et al Proc AM-FPD12 143 (2012)J Koezuka et al SID2013 Symposium Digest 723 (2013)

A high density of deep-level states (dDOS) exists in the low-density IGZO filmThe higher the film density is (like CAAC) the lower the dDOS is

Light absorptions by IGZO films with different crystal structureswere measured to quantify the densities of deep energy trapstates (dDOS)

Density of States (DOS) of IGZO

a-like IGZO 53 times 100

20

Formation of Oxygen Vacancies (VO) in IGZO

software VASP

exchange correlation function

GGA

pseudo potential PAW

cut-off energy 800 eV

k-point 1times1times1VO are

likely to be formed

Crystal Amorphous

In Ga Zn O

-1180

-1178

-1176

-1174

-1172

-15 -10 -5 0 5 10 15

Tota

l Ene

rgy

[eV]

Distance from Interface [Aring]

InterfaceInterface

VO are highly likely to be formed

A comparison of formation of oxygen vacancies (VO) between amorphous and crystal structures was made by first-principles calculation The results indicate that VO are easily formed in the amorphous structure

21

Features of CAAC-IGZO as MaterialCAAC-IGZO c-Si

1)CAAC structure (not single-crystal nano-crystalline or amorphous)rarr No clear grain boundary is observed

lattice points to form a pentagon and heptagon

Single crystal is preferable because polycrystal has a high concentration of defects at grain boundaries2)

Crystal grains (pellets) are anchored to each other to form one big crystalrarr It can be used in VLSI devices on the scale of 5ndash60 nm

3) Not a close-packed structure rather has cushion propertiesA cubic dense structure Doped with B or P Formed by crystal pulling at approx 1420C4)

Although single-crystal IGZO is formed at very high temperatures of 1200ndash1500C CAAC-IGZO can be formed at 100ndash500C by sputteringrarr It can be placed between Si LSI and metal wire layers

5) Homologous layered structure (Semi hard structure) Diamond structure(hard)

6) Composed of four elements (In Ga Zn and O) Si alone

22

3 Performance of CAAC-IGZO FET

23

IdndashVg characteristics and mobilities of CAAC-IGZO FETs with channel lengths of (a) 2 μm and (b) 6 μm The channel widths are 50 μm

It may be possible to apply all kinds of displays (TV smartphone PC by using OEL LCD)

L = 2 μm (W = 50 μm) L = 6 μm (W = 50 μm)

High-mobility CAAC-IGZO FETs

24

(a) (b)

CAAC-IGZO TrIoff = 1times10minus22 Aμm

(100 yAμm)IonIoff = 1018

IndashV characteristics of CAAC-IGZO and Si transistors

Si TrIoff = 1times10minus12 Aμm

(1 pAμm)IonIoff = 109

Off-state Current of CAAC-IGZO and Si FETsUnit

zA (10minus21)

yA (10minus24)

aA (10minus18)

fA (10minus15)

pA (10minus12)

nA (10minus9)

μA (10minus6)

mA (10minus3)

25

How to Measure Off-state Current60

0 μm

360 μm L = 044 μmW = 10 mm(50 μmtimes200)Tox = 20 nm

A huge transistor with a channel width of 10 mm for off-state leakage current measurement (optical micrograph)

Concept of measurement

Node FN(Vout)

Behavior of potential at node FN (Vout) over time

Measuredtransistor

26

Arrhenius plot of off-state leakage current1)Change of Vout measured over time

1) S Yamazaki et al Jpn J Appl Phys vol 53 pp 04ED18 (2014)

At a gate voltage of minus3 V and 85Cthe off-state leakage current was 6 yAm (1 yA = 10minus24 A)Nonvolatility for 10 years at 85C is ensured

Off-state CurrentUnitAμm

mA (10minus3)μA (10minus6)nA (10minus9)pA (10minus12)fA (10minus15)aA (10minus18)zA (10minus21)yA (10minus24)Le

akag

e cu

rrent

[Aμ

m]

27

-5

0

5

10

15

20

25

30

RF

Gai

n [d

B]

周波数[Hz]109 1010 101130 GHz

Vd = 20 VVg = 20 V( gm max )

WL = 18 μm30 nm

Operation with a cutoff frequency of about 30 GHz is demonstratedThe off-state leakage current of an OS FET (W = 60 nm) is expected at 100 zA or less at 85C even for a 30-nm-node FET

Lower measurement limit

High Cutoff Frequency and Low Off-state Current (30 nm)

28

Frequency [Hz]30 GHz

LW = 30 18000 (60 nmtimes300 Parallel) nm

Short-channel Characteristics of OS FETs

Favorable FET characteristics were obtained with a 11-nm-thick gate insulating film when L = 32 nm

The graphs show that OS FETs are resistant to short-channel effects This is probably because they have a ldquosurrounded-channel (S-ch) structure with a thin active layerrdquo and

are ldquoaccumulation-mode devicesrdquo and ldquoCAAC-IGZO has dielectric anisotropyrdquo(S-ch structure an FET structure where the active layer is electrically surrounded by the gate electrode)

GI = 11 nm

29

0

5

10

15

20

001 01 1 10 100

μ FE

[cm

2middotV-1

middot s-1]

チャネル長 [μm]

理論

Planar TypeS‐ch Type

0

200

400

600

001 01 1 10 100

μ FE

[cm

2 middotV-1

middots-1

]チャネル長 [μm]

理論

Planar Type

Short-channel Characteristics of OS FETs

Channel length dependence of field-effect mobility

(single-crystal Si FET)

Channel length dependence of field-effect mobility

（CAAC‐IGZO FET)

The field-effect mobility (μFE) of a CAAC-IGZO FET with a reduced channel length is close to that of a single-crystal Si FET with the same size

μ FE[

cm2 V

-1s

-1]

Channel length

0

20

5

10

15

10 nm 100 nm 1 μm 100 μm10 μm 10 nm 100 nm 1 μm 100 μm10 μm

Channel length

0

600

200

400

μ FE[

cm2 V

-1s

-1]

Theoretical Theoretical

30

Temperature Dependence of CAAC-IGZO FET

OS-FET

編集中編集中

L=048um GI=20nm

Vth

S値

ID_VG特性

単結晶 p-ch Si Tr （SOI）

L=035um GI=20nm L=035um GI=20nm

編集中 編集中

単結晶 n-ch Si Tr （SOI）

‐05

00

05

10

15

0 50 100 150 200 250

Vth[V]

基板温度 []

0

50

100

150

200

250

300

0 50 100 150 200 250

S‐Value[mVdec]

基板温度 []

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

Vg [V]

250

‐05

0

05

1

15

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

‐15

‐1

‐05

0

05

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

T = minus40C minus 25C 0C 25C 50C 100C 150C 200C 250C

CAAC-OS FETs have a sufficient onoff ratio even at 200C or higherThe S-value shows little change (or is constant) compared with Si FETs

Single‐crystal n‐ch Tr (SOI) Single‐crystal p‐ch Tr (SOI)OS FET

ID‐VGCharac‐teristics

Vth

S‐value

Substrate temperature [C] Substrate temperature [C] Substrate temperature [C]

Substrate temperature [C]Substrate temperature [C]Substrate temperature [C]

31

1E-07

1E-06

1E-05

1E-04

1E-03

1E-02

0 5 10 15 20 25 30V D [V]

ID [A

]Si transistorL =09um T ox=20nm

IGZO transistorL =09um T ox=20nm

4V 26V

L ＝ 09 μm W ＝ 10 μm TOX = 20 nm VG ＝ 2 V

n = 2

CAAC-IGZO transistors have a higher breakdown voltage than Si transistorsNo hot carrier degradation and avalanche breakdown are observed

Breakdown Voltage of CAAC-IGZO and Si FETs

32

Schematic Band Diagram of Channel Regionmdash OS FET vs n-ch Si FET

Inversion Depletion Accumulation

Vg gt 0 V (ON State) Vg lt 0 V (OFF State)Vg = 0V

CAAC-IGZO(S-channel)

n-ch Si

OS2CAAC-IGZO

OS3Gate E

GI GI

Gate E

Gate E

GI

Si

EC

EV

Ef

EfEC

EV

Eg=32eV

Eg=12eV

ElectronsA Arsquo

OS3

Holes

A ArsquoA Arsquo

33

M Murakami et al Proc AM-FPDrsquo12 Digest p 174 (2012)

CAAC-IGZO c-Si

1) Bandgap (Eg) 28ndash32 eV 112 eV

2) Intrinsic carrierconcentration 10minus9 cm3 10+11 cm3

3) Depletion layer km order μm order

4) Electron effective mass (meme)

023ndash025 019 (transverse)098 (longitudinal)

5) Hole effective mass (mhme)

11ndash40 016 (light)049 (heavy)

6) Structure Layered structure(Homologous) Diamond cubic

7) Conductivity i-type n-type n-type p-type

Comparison of Physical Properties between CAAC-IGZO and c-Si

34

Features of CAAC-IGZO as Device

CAAC‐IGZO c‐Si

1) Four-terminal circuitFour-terminal circuit MRAM and FeRAM are two-terminal circuits

2) Almost no short-channel effects Short-channel effects are most troublesome

3) Normally off Uncontrollable Vth high purity and intrinsic

Vth is controllable by channel doping with B

4) IonIoff ratio of 1020 IonIoff le 1010

5) nMOS onlyCMOS feasible with Si pMOS

CMOS Si nMOSSi pMOS

6) Bulk channel buried channel Shifting from surface-channel (planar) to bulk-channel (Fin)

35

4 30-nm Scaling of CAAC-IGZO FET

36

Trench Gate Self-aligned FET

L-direction W-direction

L-direction W-direction

CAAC-OS

Gate Electrode Gate Insulating Film

CAAC-OSDrain

ElectrodeSource

Electrode

Gate Electrode

Gate Insulating Film

48 nm

Gate Electrode

Gate Insulating Film

CAAC-OS34 nm

Source Electrode

Drain Electrode

CAAC-OS

Gate Insulating FilmGate Electrode

19 nm

50 nm

S-ch structure

FETrsquos active layer (CAAC-IGZO OS2 layer) is electrically surrounded by the gate electrodeWe call this FET structure a

surrounded-channel (S-ch) structure

37

Stacked Structure of OS FET and Si FET

pMOSSi

nMOSOS

GND

VDD

A Arsquo

B

Brsquo gate metal

source drain

gate insulator

CAAC-IGZO

electrode

gate

source drain

Si

SiO2

A Arsquo

B

Brsquo

OS FET

Si FET

High integration by stacking the CAAC-OS FET over the Si-FET

Si Substrate Si Substrate

W-directionL-direction

38

Comparison between CAAC-OS FET and Si nMOS FETItem CAAC-OS FET Si nMOS FET

1 Short-channel effect Small or none timesLarge (largest issue in Si NMOS FET)

2 Scaling le 30 nm (Possibility of 5 nm) Possible to ge 5 nm

3 Off-state current yAμm (10minus24 Aμm) times fAμm (10minus15 Aμm)

4 Mobility

Long channel Low High

Short channel Slightly decrease

Decrease (110 in 30-nm device)

5 Temperature characteristics

On-state current

Increase at high temperature

Decrease at high temperature

Off-state current Sufficiently low times

Drastically increase at high temperature

6 Drain breakdown voltage High Low7 Impact ionization Not observed Observed+2 +1 minus1 times minus2

39

Item CAAC-OS FET Si nMOS FET

8 Hot carrier degradation Not observed Large

9 Punch-through Not observed Strongly need balance with scaling

10 Frequency characteristics gt 30 GHz gt 300 GHz

11 Drift velocity Close to Si with channel length about 10 nm

Saturates with channel length about 100 nm

12 Sub-threshold value Small even with thick GI

Need thinner GI by miniaturizing

13 Dielectric anisotropy Observed Not observed

14 S-channel structure(Fin tri-gate type)

Extremely important and effective

Extremely important in shorter channel and effective

+25 minus1+2 +1 minus1 times minus2

Comparison between CAAC-OS FET and Si nMOS FET

40

5 CAAC-IGZO FET for LSI Application

41

Two-terminal circuit(diode)

Potential as Logic Circuit

Dependent control of input and output Need a transistor for four-terminal control Increased F2

Independently controllable inputs and outputs Desirable logic design Sufficiently low Ioff Practically an insulator

Four-terminal circuit

A B

C D

Input Output

42

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

(d)(a) (b) (c)

(d)(a) (c)(b)

(1)

(2)

Observations in Grain

Magnifying observations in a grain with a size of several tens of nanometers at the atomic level(a) Plan-view TEM images (b)(c) FFT filtered images (d) Color mapping imagesDotted lines denote boundaries between pellets Solid lines show a hexagon formed with lattice points

plan-view FFT filtered images color mapping

60

50

40

30

20

10

0

orientations of hexagons [degree]

Pellet

Hexagon formed with lattice points

Reg

ions

cor

resp

ondi

ng to

thos

e in

the

plan

-vie

w T

EM

imag

e of

the

wid

e ar

ea

13

In Ga or Zn O

066 nm

038 nm

ｚｚ

Side view of a unit cell

198 nm

181 nm

Surface of a unit cellHexagon formed with lattice points

07 nm

(Ga Zn)O

(Ga Zn)O

InO2

Homologous crystal structure

CAAC-OS pellet unit cellSemi hard material (a flexible crystal structure) by oxygen as a cushion between In Ga and Zn

Oxygen

Oxygen

14

Magnifying observations in a boundary portion between grains with a size of several tens of nanometers at the atomic level(a) Plan-view TEM images (b)(c) FFT filtered images (d) Color mapping imagesDeformed hexagons pentagons and heptagons are formed with lattice points at the boundary denoted by a dotted line and they are anchored to each other

Observations in Boundary Portion between Grains

60

50

40

30

20

10

0

orientations of hexagons [degree]

Boundary(3

)(4

)

plan-view FFT filtered images color mapping

(d)

(d)

(a)

(a) (c)

(b)

(b)

(c)R

egio

ns c

orre

spon

ding

to th

ose

in th

e pl

an-v

iew

TE

M im

age

of th

e w

ide

area

15

(a) and (c) Distribution of number of Voronoi polygons in single crystal IGZO and CAAC-IGZO (b) and (d) Distribution of Voronoi hexagons (yellow regions) and other polygons (blue regions) in the single crystal IGZO and the CAAC-IGZO

Distribution of Number of Voronoi Polygons

In the single crystal IGZO hexagonal Voronoi regions occupy almost the entire field of view In the CAAC-IGZO hexagons are the majority but pentagons and heptagons also appear

Single crystal IGZO CAAC-IGZOSingle crystal IGZO film [] CAAC-IGZO film []

Tetragon 01 07

Pentagon 12 155

Hexagon 982 683

Heptagon 04 145

Octagon 02 09

Nonagon 00 00

16

2 3 4 51

5 nmminus1

5 nmminus1

minus231degminus84degminus75 deg minus310degminus246deg

+118deg +15deg +135deg +04deg minus55deg2 3 4 51

(a)1 2 34 5

20 nm

(b) 12

3

4

5 20 nm

Panel (a) shows the points along the surface of the CAAC-IGZO film that were probed by NBED and the five remaining panels in the top row show the corresponding NBED patterns Panel (b) shows the points probed by NBED in the thickness of the film and the five remaining panels in the lower row show the corresponding NBED patterns The angle of the crystal axis is slightly shifted in both the surface and thickness directions

Nanobeam Electron Diffraction (NBED 1 nmɸ) Patterns of CAAC-IGZO Film

17

Nanobeam Electron Diffraction (NBED 1 nmɸ) Patterns of CAAC-IGZO Film

Broadanisotropic diffraction spots

Sharpcircular diffraction spots

The electron diffraction pattern of single-crystal IGZO has circular spots as shown in (b) Diffraction spots of CAAC-IGZO are not circular but anisotropic and broad

18

Schematic Band Diagram of IGZOSimple schematic diagram of defect levels in IGZO film

elec

tron

ener

gy [e

V]

surface shallow DOS(sDOS)

bulk shallow DOS(sDOS)

bulk deep DOS(dDOS)

Density of States (DOS) of IGZO

19

28-32 eV

Silicon oxide IGZO

CAAC-IGZO63 (gcm3)

nc-IGZO61 (gcm3)

a-like IGZO59 (gcm3)

αCPM Absorption coefficient estimated by a constant photocurrent method (CPM)

N Ishihara et al Proc AM-FPD12 143 (2012)J Koezuka et al SID2013 Symposium Digest 723 (2013)

A high density of deep-level states (dDOS) exists in the low-density IGZO filmThe higher the film density is (like CAAC) the lower the dDOS is

Light absorptions by IGZO films with different crystal structureswere measured to quantify the densities of deep energy trapstates (dDOS)

Density of States (DOS) of IGZO

a-like IGZO 53 times 100

20

Formation of Oxygen Vacancies (VO) in IGZO

software VASP

exchange correlation function

GGA

pseudo potential PAW

cut-off energy 800 eV

k-point 1times1times1VO are

likely to be formed

Crystal Amorphous

In Ga Zn O

-1180

-1178

-1176

-1174

-1172

-15 -10 -5 0 5 10 15

Tota

l Ene

rgy

[eV]

Distance from Interface [Aring]

InterfaceInterface

VO are highly likely to be formed

A comparison of formation of oxygen vacancies (VO) between amorphous and crystal structures was made by first-principles calculation The results indicate that VO are easily formed in the amorphous structure

21

Features of CAAC-IGZO as MaterialCAAC-IGZO c-Si

1)CAAC structure (not single-crystal nano-crystalline or amorphous)rarr No clear grain boundary is observed

lattice points to form a pentagon and heptagon

Single crystal is preferable because polycrystal has a high concentration of defects at grain boundaries2)

Crystal grains (pellets) are anchored to each other to form one big crystalrarr It can be used in VLSI devices on the scale of 5ndash60 nm

3) Not a close-packed structure rather has cushion propertiesA cubic dense structure Doped with B or P Formed by crystal pulling at approx 1420C4)

Although single-crystal IGZO is formed at very high temperatures of 1200ndash1500C CAAC-IGZO can be formed at 100ndash500C by sputteringrarr It can be placed between Si LSI and metal wire layers

5) Homologous layered structure (Semi hard structure) Diamond structure(hard)

6) Composed of four elements (In Ga Zn and O) Si alone

22

3 Performance of CAAC-IGZO FET

23

IdndashVg characteristics and mobilities of CAAC-IGZO FETs with channel lengths of (a) 2 μm and (b) 6 μm The channel widths are 50 μm

It may be possible to apply all kinds of displays (TV smartphone PC by using OEL LCD)

L = 2 μm (W = 50 μm) L = 6 μm (W = 50 μm)

High-mobility CAAC-IGZO FETs

24

(a) (b)

CAAC-IGZO TrIoff = 1times10minus22 Aμm

(100 yAμm)IonIoff = 1018

IndashV characteristics of CAAC-IGZO and Si transistors

Si TrIoff = 1times10minus12 Aμm

(1 pAμm)IonIoff = 109

Off-state Current of CAAC-IGZO and Si FETsUnit

zA (10minus21)

yA (10minus24)

aA (10minus18)

fA (10minus15)

pA (10minus12)

nA (10minus9)

μA (10minus6)

mA (10minus3)

25

How to Measure Off-state Current60

0 μm

360 μm L = 044 μmW = 10 mm(50 μmtimes200)Tox = 20 nm

A huge transistor with a channel width of 10 mm for off-state leakage current measurement (optical micrograph)

Concept of measurement

Node FN(Vout)

Behavior of potential at node FN (Vout) over time

Measuredtransistor

26

Arrhenius plot of off-state leakage current1)Change of Vout measured over time

1) S Yamazaki et al Jpn J Appl Phys vol 53 pp 04ED18 (2014)

At a gate voltage of minus3 V and 85Cthe off-state leakage current was 6 yAm (1 yA = 10minus24 A)Nonvolatility for 10 years at 85C is ensured

Off-state CurrentUnitAμm

mA (10minus3)μA (10minus6)nA (10minus9)pA (10minus12)fA (10minus15)aA (10minus18)zA (10minus21)yA (10minus24)Le

akag

e cu

rrent

[Aμ

m]

27

-5

0

5

10

15

20

25

30

RF

Gai

n [d

B]

周波数[Hz]109 1010 101130 GHz

Vd = 20 VVg = 20 V( gm max )

WL = 18 μm30 nm

Operation with a cutoff frequency of about 30 GHz is demonstratedThe off-state leakage current of an OS FET (W = 60 nm) is expected at 100 zA or less at 85C even for a 30-nm-node FET

Lower measurement limit

High Cutoff Frequency and Low Off-state Current (30 nm)

28

Frequency [Hz]30 GHz

LW = 30 18000 (60 nmtimes300 Parallel) nm

Short-channel Characteristics of OS FETs

Favorable FET characteristics were obtained with a 11-nm-thick gate insulating film when L = 32 nm

The graphs show that OS FETs are resistant to short-channel effects This is probably because they have a ldquosurrounded-channel (S-ch) structure with a thin active layerrdquo and

are ldquoaccumulation-mode devicesrdquo and ldquoCAAC-IGZO has dielectric anisotropyrdquo(S-ch structure an FET structure where the active layer is electrically surrounded by the gate electrode)

GI = 11 nm

29

0

5

10

15

20

001 01 1 10 100

μ FE

[cm

2middotV-1

middot s-1]

チャネル長 [μm]

理論

Planar TypeS‐ch Type

0

200

400

600

001 01 1 10 100

μ FE

[cm

2 middotV-1

middots-1

]チャネル長 [μm]

理論

Planar Type

Short-channel Characteristics of OS FETs

Channel length dependence of field-effect mobility

(single-crystal Si FET)

Channel length dependence of field-effect mobility

（CAAC‐IGZO FET)

The field-effect mobility (μFE) of a CAAC-IGZO FET with a reduced channel length is close to that of a single-crystal Si FET with the same size

μ FE[

cm2 V

-1s

-1]

Channel length

0

20

5

10

15

10 nm 100 nm 1 μm 100 μm10 μm 10 nm 100 nm 1 μm 100 μm10 μm

Channel length

0

600

200

400

μ FE[

cm2 V

-1s

-1]

Theoretical Theoretical

30

Temperature Dependence of CAAC-IGZO FET

OS-FET

編集中編集中

L=048um GI=20nm

Vth

S値

ID_VG特性

単結晶 p-ch Si Tr （SOI）

L=035um GI=20nm L=035um GI=20nm

編集中 編集中

単結晶 n-ch Si Tr （SOI）

‐05

00

05

10

15

0 50 100 150 200 250

Vth[V]

基板温度 []

0

50

100

150

200

250

300

0 50 100 150 200 250

S‐Value[mVdec]

基板温度 []

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

Vg [V]

250

‐05

0

05

1

15

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

‐15

‐1

‐05

0

05

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

T = minus40C minus 25C 0C 25C 50C 100C 150C 200C 250C

CAAC-OS FETs have a sufficient onoff ratio even at 200C or higherThe S-value shows little change (or is constant) compared with Si FETs

Single‐crystal n‐ch Tr (SOI) Single‐crystal p‐ch Tr (SOI)OS FET

ID‐VGCharac‐teristics

Vth

S‐value

Substrate temperature [C] Substrate temperature [C] Substrate temperature [C]

Substrate temperature [C]Substrate temperature [C]Substrate temperature [C]

31

1E-07

1E-06

1E-05

1E-04

1E-03

1E-02

0 5 10 15 20 25 30V D [V]

ID [A

]Si transistorL =09um T ox=20nm

IGZO transistorL =09um T ox=20nm

4V 26V

L ＝ 09 μm W ＝ 10 μm TOX = 20 nm VG ＝ 2 V

n = 2

CAAC-IGZO transistors have a higher breakdown voltage than Si transistorsNo hot carrier degradation and avalanche breakdown are observed

Breakdown Voltage of CAAC-IGZO and Si FETs

32

Schematic Band Diagram of Channel Regionmdash OS FET vs n-ch Si FET

Inversion Depletion Accumulation

Vg gt 0 V (ON State) Vg lt 0 V (OFF State)Vg = 0V

CAAC-IGZO(S-channel)

n-ch Si

OS2CAAC-IGZO

OS3Gate E

GI GI

Gate E

Gate E

GI

Si

EC

EV

Ef

EfEC

EV

Eg=32eV

Eg=12eV

ElectronsA Arsquo

OS3

Holes

A ArsquoA Arsquo

33

M Murakami et al Proc AM-FPDrsquo12 Digest p 174 (2012)

CAAC-IGZO c-Si

1) Bandgap (Eg) 28ndash32 eV 112 eV

2) Intrinsic carrierconcentration 10minus9 cm3 10+11 cm3

3) Depletion layer km order μm order

4) Electron effective mass (meme)

023ndash025 019 (transverse)098 (longitudinal)

5) Hole effective mass (mhme)

11ndash40 016 (light)049 (heavy)

6) Structure Layered structure(Homologous) Diamond cubic

7) Conductivity i-type n-type n-type p-type

Comparison of Physical Properties between CAAC-IGZO and c-Si

34

Features of CAAC-IGZO as Device

CAAC‐IGZO c‐Si

1) Four-terminal circuitFour-terminal circuit MRAM and FeRAM are two-terminal circuits

2) Almost no short-channel effects Short-channel effects are most troublesome

3) Normally off Uncontrollable Vth high purity and intrinsic

Vth is controllable by channel doping with B

4) IonIoff ratio of 1020 IonIoff le 1010

5) nMOS onlyCMOS feasible with Si pMOS

CMOS Si nMOSSi pMOS

6) Bulk channel buried channel Shifting from surface-channel (planar) to bulk-channel (Fin)

35

4 30-nm Scaling of CAAC-IGZO FET

36

Trench Gate Self-aligned FET

L-direction W-direction

L-direction W-direction

CAAC-OS

Gate Electrode Gate Insulating Film

CAAC-OSDrain

ElectrodeSource

Electrode

Gate Electrode

Gate Insulating Film

48 nm

Gate Electrode

Gate Insulating Film

CAAC-OS34 nm

Source Electrode

Drain Electrode

CAAC-OS

Gate Insulating FilmGate Electrode

19 nm

50 nm

S-ch structure

FETrsquos active layer (CAAC-IGZO OS2 layer) is electrically surrounded by the gate electrodeWe call this FET structure a

surrounded-channel (S-ch) structure

37

Stacked Structure of OS FET and Si FET

pMOSSi

nMOSOS

GND

VDD

A Arsquo

B

Brsquo gate metal

source drain

gate insulator

CAAC-IGZO

electrode

gate

source drain

Si

SiO2

A Arsquo

B

Brsquo

OS FET

Si FET

High integration by stacking the CAAC-OS FET over the Si-FET

Si Substrate Si Substrate

W-directionL-direction

38

Comparison between CAAC-OS FET and Si nMOS FETItem CAAC-OS FET Si nMOS FET

1 Short-channel effect Small or none timesLarge (largest issue in Si NMOS FET)

2 Scaling le 30 nm (Possibility of 5 nm) Possible to ge 5 nm

3 Off-state current yAμm (10minus24 Aμm) times fAμm (10minus15 Aμm)

4 Mobility

Long channel Low High

Short channel Slightly decrease

Decrease (110 in 30-nm device)

5 Temperature characteristics

On-state current

Increase at high temperature

Decrease at high temperature

Off-state current Sufficiently low times

Drastically increase at high temperature

6 Drain breakdown voltage High Low7 Impact ionization Not observed Observed+2 +1 minus1 times minus2

39

Item CAAC-OS FET Si nMOS FET

8 Hot carrier degradation Not observed Large

9 Punch-through Not observed Strongly need balance with scaling

10 Frequency characteristics gt 30 GHz gt 300 GHz

11 Drift velocity Close to Si with channel length about 10 nm

Saturates with channel length about 100 nm

12 Sub-threshold value Small even with thick GI

Need thinner GI by miniaturizing

13 Dielectric anisotropy Observed Not observed

14 S-channel structure(Fin tri-gate type)

Extremely important and effective

Extremely important in shorter channel and effective

+25 minus1+2 +1 minus1 times minus2

Comparison between CAAC-OS FET and Si nMOS FET

40

5 CAAC-IGZO FET for LSI Application

41

Two-terminal circuit(diode)

Potential as Logic Circuit

Dependent control of input and output Need a transistor for four-terminal control Increased F2

Independently controllable inputs and outputs Desirable logic design Sufficiently low Ioff Practically an insulator

Four-terminal circuit

A B

C D

Input Output

42

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

In Ga or Zn O

066 nm

038 nm

ｚｚ

Side view of a unit cell

198 nm

181 nm

Surface of a unit cellHexagon formed with lattice points

07 nm

(Ga Zn)O

(Ga Zn)O

InO2

Homologous crystal structure

CAAC-OS pellet unit cellSemi hard material (a flexible crystal structure) by oxygen as a cushion between In Ga and Zn

Oxygen

Oxygen

14

Magnifying observations in a boundary portion between grains with a size of several tens of nanometers at the atomic level(a) Plan-view TEM images (b)(c) FFT filtered images (d) Color mapping imagesDeformed hexagons pentagons and heptagons are formed with lattice points at the boundary denoted by a dotted line and they are anchored to each other

Observations in Boundary Portion between Grains

60

50

40

30

20

10

0

orientations of hexagons [degree]

Boundary(3

)(4

)

plan-view FFT filtered images color mapping

(d)

(d)

(a)

(a) (c)

(b)

(b)

(c)R

egio

ns c

orre

spon

ding

to th

ose

in th

e pl

an-v

iew

TE

M im

age

of th

e w

ide

area

15

(a) and (c) Distribution of number of Voronoi polygons in single crystal IGZO and CAAC-IGZO (b) and (d) Distribution of Voronoi hexagons (yellow regions) and other polygons (blue regions) in the single crystal IGZO and the CAAC-IGZO

Distribution of Number of Voronoi Polygons

In the single crystal IGZO hexagonal Voronoi regions occupy almost the entire field of view In the CAAC-IGZO hexagons are the majority but pentagons and heptagons also appear

Single crystal IGZO CAAC-IGZOSingle crystal IGZO film [] CAAC-IGZO film []

Tetragon 01 07

Pentagon 12 155

Hexagon 982 683

Heptagon 04 145

Octagon 02 09

Nonagon 00 00

16

2 3 4 51

5 nmminus1

5 nmminus1

minus231degminus84degminus75 deg minus310degminus246deg

+118deg +15deg +135deg +04deg minus55deg2 3 4 51

(a)1 2 34 5

20 nm

(b) 12

3

4

5 20 nm

Panel (a) shows the points along the surface of the CAAC-IGZO film that were probed by NBED and the five remaining panels in the top row show the corresponding NBED patterns Panel (b) shows the points probed by NBED in the thickness of the film and the five remaining panels in the lower row show the corresponding NBED patterns The angle of the crystal axis is slightly shifted in both the surface and thickness directions

Nanobeam Electron Diffraction (NBED 1 nmɸ) Patterns of CAAC-IGZO Film

17

Nanobeam Electron Diffraction (NBED 1 nmɸ) Patterns of CAAC-IGZO Film

Broadanisotropic diffraction spots

Sharpcircular diffraction spots

The electron diffraction pattern of single-crystal IGZO has circular spots as shown in (b) Diffraction spots of CAAC-IGZO are not circular but anisotropic and broad

18

Schematic Band Diagram of IGZOSimple schematic diagram of defect levels in IGZO film

elec

tron

ener

gy [e

V]

surface shallow DOS(sDOS)

bulk shallow DOS(sDOS)

bulk deep DOS(dDOS)

Density of States (DOS) of IGZO

19

28-32 eV

Silicon oxide IGZO

CAAC-IGZO63 (gcm3)

nc-IGZO61 (gcm3)

a-like IGZO59 (gcm3)

αCPM Absorption coefficient estimated by a constant photocurrent method (CPM)

N Ishihara et al Proc AM-FPD12 143 (2012)J Koezuka et al SID2013 Symposium Digest 723 (2013)

A high density of deep-level states (dDOS) exists in the low-density IGZO filmThe higher the film density is (like CAAC) the lower the dDOS is

Light absorptions by IGZO films with different crystal structureswere measured to quantify the densities of deep energy trapstates (dDOS)

Density of States (DOS) of IGZO

a-like IGZO 53 times 100

20

Formation of Oxygen Vacancies (VO) in IGZO

software VASP

exchange correlation function

GGA

pseudo potential PAW

cut-off energy 800 eV

k-point 1times1times1VO are

likely to be formed

Crystal Amorphous

In Ga Zn O

-1180

-1178

-1176

-1174

-1172

-15 -10 -5 0 5 10 15

Tota

l Ene

rgy

[eV]

Distance from Interface [Aring]

InterfaceInterface

VO are highly likely to be formed

A comparison of formation of oxygen vacancies (VO) between amorphous and crystal structures was made by first-principles calculation The results indicate that VO are easily formed in the amorphous structure

21

Features of CAAC-IGZO as MaterialCAAC-IGZO c-Si

1)CAAC structure (not single-crystal nano-crystalline or amorphous)rarr No clear grain boundary is observed

lattice points to form a pentagon and heptagon

Single crystal is preferable because polycrystal has a high concentration of defects at grain boundaries2)

Crystal grains (pellets) are anchored to each other to form one big crystalrarr It can be used in VLSI devices on the scale of 5ndash60 nm

3) Not a close-packed structure rather has cushion propertiesA cubic dense structure Doped with B or P Formed by crystal pulling at approx 1420C4)

Although single-crystal IGZO is formed at very high temperatures of 1200ndash1500C CAAC-IGZO can be formed at 100ndash500C by sputteringrarr It can be placed between Si LSI and metal wire layers

5) Homologous layered structure (Semi hard structure) Diamond structure(hard)

6) Composed of four elements (In Ga Zn and O) Si alone

22

3 Performance of CAAC-IGZO FET

23

IdndashVg characteristics and mobilities of CAAC-IGZO FETs with channel lengths of (a) 2 μm and (b) 6 μm The channel widths are 50 μm

It may be possible to apply all kinds of displays (TV smartphone PC by using OEL LCD)

L = 2 μm (W = 50 μm) L = 6 μm (W = 50 μm)

High-mobility CAAC-IGZO FETs

24

(a) (b)

CAAC-IGZO TrIoff = 1times10minus22 Aμm

(100 yAμm)IonIoff = 1018

IndashV characteristics of CAAC-IGZO and Si transistors

Si TrIoff = 1times10minus12 Aμm

(1 pAμm)IonIoff = 109

Off-state Current of CAAC-IGZO and Si FETsUnit

zA (10minus21)

yA (10minus24)

aA (10minus18)

fA (10minus15)

pA (10minus12)

nA (10minus9)

μA (10minus6)

mA (10minus3)

25

How to Measure Off-state Current60

0 μm

360 μm L = 044 μmW = 10 mm(50 μmtimes200)Tox = 20 nm

A huge transistor with a channel width of 10 mm for off-state leakage current measurement (optical micrograph)

Concept of measurement

Node FN(Vout)

Behavior of potential at node FN (Vout) over time

Measuredtransistor

26

Arrhenius plot of off-state leakage current1)Change of Vout measured over time

1) S Yamazaki et al Jpn J Appl Phys vol 53 pp 04ED18 (2014)

At a gate voltage of minus3 V and 85Cthe off-state leakage current was 6 yAm (1 yA = 10minus24 A)Nonvolatility for 10 years at 85C is ensured

Off-state CurrentUnitAμm

mA (10minus3)μA (10minus6)nA (10minus9)pA (10minus12)fA (10minus15)aA (10minus18)zA (10minus21)yA (10minus24)Le

akag

e cu

rrent

[Aμ

m]

27

-5

0

5

10

15

20

25

30

RF

Gai

n [d

B]

周波数[Hz]109 1010 101130 GHz

Vd = 20 VVg = 20 V( gm max )

WL = 18 μm30 nm

Operation with a cutoff frequency of about 30 GHz is demonstratedThe off-state leakage current of an OS FET (W = 60 nm) is expected at 100 zA or less at 85C even for a 30-nm-node FET

Lower measurement limit

High Cutoff Frequency and Low Off-state Current (30 nm)

28

Frequency [Hz]30 GHz

LW = 30 18000 (60 nmtimes300 Parallel) nm

Short-channel Characteristics of OS FETs

Favorable FET characteristics were obtained with a 11-nm-thick gate insulating film when L = 32 nm

The graphs show that OS FETs are resistant to short-channel effects This is probably because they have a ldquosurrounded-channel (S-ch) structure with a thin active layerrdquo and

are ldquoaccumulation-mode devicesrdquo and ldquoCAAC-IGZO has dielectric anisotropyrdquo(S-ch structure an FET structure where the active layer is electrically surrounded by the gate electrode)

GI = 11 nm

29

0

5

10

15

20

001 01 1 10 100

μ FE

[cm

2middotV-1

middot s-1]

チャネル長 [μm]

理論

Planar TypeS‐ch Type

0

200

400

600

001 01 1 10 100

μ FE

[cm

2 middotV-1

middots-1

]チャネル長 [μm]

理論

Planar Type

Short-channel Characteristics of OS FETs

Channel length dependence of field-effect mobility

(single-crystal Si FET)

Channel length dependence of field-effect mobility

（CAAC‐IGZO FET)

The field-effect mobility (μFE) of a CAAC-IGZO FET with a reduced channel length is close to that of a single-crystal Si FET with the same size

μ FE[

cm2 V

-1s

-1]

Channel length

0

20

5

10

15

10 nm 100 nm 1 μm 100 μm10 μm 10 nm 100 nm 1 μm 100 μm10 μm

Channel length

0

600

200

400

μ FE[

cm2 V

-1s

-1]

Theoretical Theoretical

30

Temperature Dependence of CAAC-IGZO FET

OS-FET

編集中編集中

L=048um GI=20nm

Vth

S値

ID_VG特性

単結晶 p-ch Si Tr （SOI）

L=035um GI=20nm L=035um GI=20nm

編集中 編集中

単結晶 n-ch Si Tr （SOI）

‐05

00

05

10

15

0 50 100 150 200 250

Vth[V]

基板温度 []

0

50

100

150

200

250

300

0 50 100 150 200 250

S‐Value[mVdec]

基板温度 []

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

Vg [V]

250

‐05

0

05

1

15

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

‐15

‐1

‐05

0

05

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

T = minus40C minus 25C 0C 25C 50C 100C 150C 200C 250C

CAAC-OS FETs have a sufficient onoff ratio even at 200C or higherThe S-value shows little change (or is constant) compared with Si FETs

Single‐crystal n‐ch Tr (SOI) Single‐crystal p‐ch Tr (SOI)OS FET

ID‐VGCharac‐teristics

Vth

S‐value

Substrate temperature [C] Substrate temperature [C] Substrate temperature [C]

Substrate temperature [C]Substrate temperature [C]Substrate temperature [C]

31

1E-07

1E-06

1E-05

1E-04

1E-03

1E-02

0 5 10 15 20 25 30V D [V]

ID [A

]Si transistorL =09um T ox=20nm

IGZO transistorL =09um T ox=20nm

4V 26V

L ＝ 09 μm W ＝ 10 μm TOX = 20 nm VG ＝ 2 V

n = 2

CAAC-IGZO transistors have a higher breakdown voltage than Si transistorsNo hot carrier degradation and avalanche breakdown are observed

Breakdown Voltage of CAAC-IGZO and Si FETs

32

Schematic Band Diagram of Channel Regionmdash OS FET vs n-ch Si FET

Inversion Depletion Accumulation

Vg gt 0 V (ON State) Vg lt 0 V (OFF State)Vg = 0V

CAAC-IGZO(S-channel)

n-ch Si

OS2CAAC-IGZO

OS3Gate E

GI GI

Gate E

Gate E

GI

Si

EC

EV

Ef

EfEC

EV

Eg=32eV

Eg=12eV

ElectronsA Arsquo

OS3

Holes

A ArsquoA Arsquo

33

M Murakami et al Proc AM-FPDrsquo12 Digest p 174 (2012)

CAAC-IGZO c-Si

1) Bandgap (Eg) 28ndash32 eV 112 eV

2) Intrinsic carrierconcentration 10minus9 cm3 10+11 cm3

3) Depletion layer km order μm order

4) Electron effective mass (meme)

023ndash025 019 (transverse)098 (longitudinal)

5) Hole effective mass (mhme)

11ndash40 016 (light)049 (heavy)

6) Structure Layered structure(Homologous) Diamond cubic

7) Conductivity i-type n-type n-type p-type

Comparison of Physical Properties between CAAC-IGZO and c-Si

34

Features of CAAC-IGZO as Device

CAAC‐IGZO c‐Si

1) Four-terminal circuitFour-terminal circuit MRAM and FeRAM are two-terminal circuits

2) Almost no short-channel effects Short-channel effects are most troublesome

3) Normally off Uncontrollable Vth high purity and intrinsic

Vth is controllable by channel doping with B

4) IonIoff ratio of 1020 IonIoff le 1010

5) nMOS onlyCMOS feasible with Si pMOS

CMOS Si nMOSSi pMOS

6) Bulk channel buried channel Shifting from surface-channel (planar) to bulk-channel (Fin)

35

4 30-nm Scaling of CAAC-IGZO FET

36

Trench Gate Self-aligned FET

L-direction W-direction

L-direction W-direction

CAAC-OS

Gate Electrode Gate Insulating Film

CAAC-OSDrain

ElectrodeSource

Electrode

Gate Electrode

Gate Insulating Film

48 nm

Gate Electrode

Gate Insulating Film

CAAC-OS34 nm

Source Electrode

Drain Electrode

CAAC-OS

Gate Insulating FilmGate Electrode

19 nm

50 nm

S-ch structure

FETrsquos active layer (CAAC-IGZO OS2 layer) is electrically surrounded by the gate electrodeWe call this FET structure a

surrounded-channel (S-ch) structure

37

Stacked Structure of OS FET and Si FET

pMOSSi

nMOSOS

GND

VDD

A Arsquo

B

Brsquo gate metal

source drain

gate insulator

CAAC-IGZO

electrode

gate

source drain

Si

SiO2

A Arsquo

B

Brsquo

OS FET

Si FET

High integration by stacking the CAAC-OS FET over the Si-FET

Si Substrate Si Substrate

W-directionL-direction

38

Comparison between CAAC-OS FET and Si nMOS FETItem CAAC-OS FET Si nMOS FET

1 Short-channel effect Small or none timesLarge (largest issue in Si NMOS FET)

2 Scaling le 30 nm (Possibility of 5 nm) Possible to ge 5 nm

3 Off-state current yAμm (10minus24 Aμm) times fAμm (10minus15 Aμm)

4 Mobility

Long channel Low High

Short channel Slightly decrease

Decrease (110 in 30-nm device)

5 Temperature characteristics

On-state current

Increase at high temperature

Decrease at high temperature

Off-state current Sufficiently low times

Drastically increase at high temperature

6 Drain breakdown voltage High Low7 Impact ionization Not observed Observed+2 +1 minus1 times minus2

39

Item CAAC-OS FET Si nMOS FET

8 Hot carrier degradation Not observed Large

9 Punch-through Not observed Strongly need balance with scaling

10 Frequency characteristics gt 30 GHz gt 300 GHz

11 Drift velocity Close to Si with channel length about 10 nm

Saturates with channel length about 100 nm

12 Sub-threshold value Small even with thick GI

Need thinner GI by miniaturizing

13 Dielectric anisotropy Observed Not observed

14 S-channel structure(Fin tri-gate type)

Extremely important and effective

Extremely important in shorter channel and effective

+25 minus1+2 +1 minus1 times minus2

Comparison between CAAC-OS FET and Si nMOS FET

40

5 CAAC-IGZO FET for LSI Application

41

Two-terminal circuit(diode)

Potential as Logic Circuit

Dependent control of input and output Need a transistor for four-terminal control Increased F2

Independently controllable inputs and outputs Desirable logic design Sufficiently low Ioff Practically an insulator

Four-terminal circuit

A B

C D

Input Output

42

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

Magnifying observations in a boundary portion between grains with a size of several tens of nanometers at the atomic level(a) Plan-view TEM images (b)(c) FFT filtered images (d) Color mapping imagesDeformed hexagons pentagons and heptagons are formed with lattice points at the boundary denoted by a dotted line and they are anchored to each other

Observations in Boundary Portion between Grains

60

50

40

30

20

10

0

orientations of hexagons [degree]

Boundary(3

)(4

)

plan-view FFT filtered images color mapping

(d)

(d)

(a)

(a) (c)

(b)

(b)

(c)R

egio

ns c

orre

spon

ding

to th

ose

in th

e pl

an-v

iew

TE

M im

age

of th

e w

ide

area

15

(a) and (c) Distribution of number of Voronoi polygons in single crystal IGZO and CAAC-IGZO (b) and (d) Distribution of Voronoi hexagons (yellow regions) and other polygons (blue regions) in the single crystal IGZO and the CAAC-IGZO

Distribution of Number of Voronoi Polygons

In the single crystal IGZO hexagonal Voronoi regions occupy almost the entire field of view In the CAAC-IGZO hexagons are the majority but pentagons and heptagons also appear

Single crystal IGZO CAAC-IGZOSingle crystal IGZO film [] CAAC-IGZO film []

Tetragon 01 07

Pentagon 12 155

Hexagon 982 683

Heptagon 04 145

Octagon 02 09

Nonagon 00 00

16

2 3 4 51

5 nmminus1

5 nmminus1

minus231degminus84degminus75 deg minus310degminus246deg

+118deg +15deg +135deg +04deg minus55deg2 3 4 51

(a)1 2 34 5

20 nm

(b) 12

3

4

5 20 nm

Panel (a) shows the points along the surface of the CAAC-IGZO film that were probed by NBED and the five remaining panels in the top row show the corresponding NBED patterns Panel (b) shows the points probed by NBED in the thickness of the film and the five remaining panels in the lower row show the corresponding NBED patterns The angle of the crystal axis is slightly shifted in both the surface and thickness directions

Nanobeam Electron Diffraction (NBED 1 nmɸ) Patterns of CAAC-IGZO Film

17

Nanobeam Electron Diffraction (NBED 1 nmɸ) Patterns of CAAC-IGZO Film

Broadanisotropic diffraction spots

Sharpcircular diffraction spots

The electron diffraction pattern of single-crystal IGZO has circular spots as shown in (b) Diffraction spots of CAAC-IGZO are not circular but anisotropic and broad

18

Schematic Band Diagram of IGZOSimple schematic diagram of defect levels in IGZO film

elec

tron

ener

gy [e

V]

surface shallow DOS(sDOS)

bulk shallow DOS(sDOS)

bulk deep DOS(dDOS)

Density of States (DOS) of IGZO

19

28-32 eV

Silicon oxide IGZO

CAAC-IGZO63 (gcm3)

nc-IGZO61 (gcm3)

a-like IGZO59 (gcm3)

αCPM Absorption coefficient estimated by a constant photocurrent method (CPM)

N Ishihara et al Proc AM-FPD12 143 (2012)J Koezuka et al SID2013 Symposium Digest 723 (2013)

A high density of deep-level states (dDOS) exists in the low-density IGZO filmThe higher the film density is (like CAAC) the lower the dDOS is

Light absorptions by IGZO films with different crystal structureswere measured to quantify the densities of deep energy trapstates (dDOS)

Density of States (DOS) of IGZO

a-like IGZO 53 times 100

20

Formation of Oxygen Vacancies (VO) in IGZO

software VASP

exchange correlation function

GGA

pseudo potential PAW

cut-off energy 800 eV

k-point 1times1times1VO are

likely to be formed

Crystal Amorphous

In Ga Zn O

-1180

-1178

-1176

-1174

-1172

-15 -10 -5 0 5 10 15

Tota

l Ene

rgy

[eV]

Distance from Interface [Aring]

InterfaceInterface

VO are highly likely to be formed

A comparison of formation of oxygen vacancies (VO) between amorphous and crystal structures was made by first-principles calculation The results indicate that VO are easily formed in the amorphous structure

21

Features of CAAC-IGZO as MaterialCAAC-IGZO c-Si

1)CAAC structure (not single-crystal nano-crystalline or amorphous)rarr No clear grain boundary is observed

lattice points to form a pentagon and heptagon

Single crystal is preferable because polycrystal has a high concentration of defects at grain boundaries2)

Crystal grains (pellets) are anchored to each other to form one big crystalrarr It can be used in VLSI devices on the scale of 5ndash60 nm

3) Not a close-packed structure rather has cushion propertiesA cubic dense structure Doped with B or P Formed by crystal pulling at approx 1420C4)

Although single-crystal IGZO is formed at very high temperatures of 1200ndash1500C CAAC-IGZO can be formed at 100ndash500C by sputteringrarr It can be placed between Si LSI and metal wire layers

5) Homologous layered structure (Semi hard structure) Diamond structure(hard)

6) Composed of four elements (In Ga Zn and O) Si alone

22

3 Performance of CAAC-IGZO FET

23

IdndashVg characteristics and mobilities of CAAC-IGZO FETs with channel lengths of (a) 2 μm and (b) 6 μm The channel widths are 50 μm

It may be possible to apply all kinds of displays (TV smartphone PC by using OEL LCD)

L = 2 μm (W = 50 μm) L = 6 μm (W = 50 μm)

High-mobility CAAC-IGZO FETs

24

(a) (b)

CAAC-IGZO TrIoff = 1times10minus22 Aμm

(100 yAμm)IonIoff = 1018

IndashV characteristics of CAAC-IGZO and Si transistors

Si TrIoff = 1times10minus12 Aμm

(1 pAμm)IonIoff = 109

Off-state Current of CAAC-IGZO and Si FETsUnit

zA (10minus21)

yA (10minus24)

aA (10minus18)

fA (10minus15)

pA (10minus12)

nA (10minus9)

μA (10minus6)

mA (10minus3)

25

How to Measure Off-state Current60

0 μm

360 μm L = 044 μmW = 10 mm(50 μmtimes200)Tox = 20 nm

A huge transistor with a channel width of 10 mm for off-state leakage current measurement (optical micrograph)

Concept of measurement

Node FN(Vout)

Behavior of potential at node FN (Vout) over time

Measuredtransistor

26

Arrhenius plot of off-state leakage current1)Change of Vout measured over time

1) S Yamazaki et al Jpn J Appl Phys vol 53 pp 04ED18 (2014)

At a gate voltage of minus3 V and 85Cthe off-state leakage current was 6 yAm (1 yA = 10minus24 A)Nonvolatility for 10 years at 85C is ensured

Off-state CurrentUnitAμm

mA (10minus3)μA (10minus6)nA (10minus9)pA (10minus12)fA (10minus15)aA (10minus18)zA (10minus21)yA (10minus24)Le

akag

e cu

rrent

[Aμ

m]

27

-5

0

5

10

15

20

25

30

RF

Gai

n [d

B]

周波数[Hz]109 1010 101130 GHz

Vd = 20 VVg = 20 V( gm max )

WL = 18 μm30 nm

Operation with a cutoff frequency of about 30 GHz is demonstratedThe off-state leakage current of an OS FET (W = 60 nm) is expected at 100 zA or less at 85C even for a 30-nm-node FET

Lower measurement limit

High Cutoff Frequency and Low Off-state Current (30 nm)

28

Frequency [Hz]30 GHz

LW = 30 18000 (60 nmtimes300 Parallel) nm

Short-channel Characteristics of OS FETs

Favorable FET characteristics were obtained with a 11-nm-thick gate insulating film when L = 32 nm

The graphs show that OS FETs are resistant to short-channel effects This is probably because they have a ldquosurrounded-channel (S-ch) structure with a thin active layerrdquo and

are ldquoaccumulation-mode devicesrdquo and ldquoCAAC-IGZO has dielectric anisotropyrdquo(S-ch structure an FET structure where the active layer is electrically surrounded by the gate electrode)

GI = 11 nm

29

0

5

10

15

20

001 01 1 10 100

μ FE

[cm

2middotV-1

middot s-1]

チャネル長 [μm]

理論

Planar TypeS‐ch Type

0

200

400

600

001 01 1 10 100

μ FE

[cm

2 middotV-1

middots-1

]チャネル長 [μm]

理論

Planar Type

Short-channel Characteristics of OS FETs

Channel length dependence of field-effect mobility

(single-crystal Si FET)

Channel length dependence of field-effect mobility

（CAAC‐IGZO FET)

The field-effect mobility (μFE) of a CAAC-IGZO FET with a reduced channel length is close to that of a single-crystal Si FET with the same size

μ FE[

cm2 V

-1s

-1]

Channel length

0

20

5

10

15

10 nm 100 nm 1 μm 100 μm10 μm 10 nm 100 nm 1 μm 100 μm10 μm

Channel length

0

600

200

400

μ FE[

cm2 V

-1s

-1]

Theoretical Theoretical

30

Temperature Dependence of CAAC-IGZO FET

OS-FET

編集中編集中

L=048um GI=20nm

Vth

S値

ID_VG特性

単結晶 p-ch Si Tr （SOI）

L=035um GI=20nm L=035um GI=20nm

編集中 編集中

単結晶 n-ch Si Tr （SOI）

‐05

00

05

10

15

0 50 100 150 200 250

Vth[V]

基板温度 []

0

50

100

150

200

250

300

0 50 100 150 200 250

S‐Value[mVdec]

基板温度 []

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

Vg [V]

250

‐05

0

05

1

15

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

‐15

‐1

‐05

0

05

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

T = minus40C minus 25C 0C 25C 50C 100C 150C 200C 250C

CAAC-OS FETs have a sufficient onoff ratio even at 200C or higherThe S-value shows little change (or is constant) compared with Si FETs

Single‐crystal n‐ch Tr (SOI) Single‐crystal p‐ch Tr (SOI)OS FET

ID‐VGCharac‐teristics

Vth

S‐value

Substrate temperature [C] Substrate temperature [C] Substrate temperature [C]

Substrate temperature [C]Substrate temperature [C]Substrate temperature [C]

31

1E-07

1E-06

1E-05

1E-04

1E-03

1E-02

0 5 10 15 20 25 30V D [V]

ID [A

]Si transistorL =09um T ox=20nm

IGZO transistorL =09um T ox=20nm

4V 26V

L ＝ 09 μm W ＝ 10 μm TOX = 20 nm VG ＝ 2 V

n = 2

CAAC-IGZO transistors have a higher breakdown voltage than Si transistorsNo hot carrier degradation and avalanche breakdown are observed

Breakdown Voltage of CAAC-IGZO and Si FETs

32

Schematic Band Diagram of Channel Regionmdash OS FET vs n-ch Si FET

Inversion Depletion Accumulation

Vg gt 0 V (ON State) Vg lt 0 V (OFF State)Vg = 0V

CAAC-IGZO(S-channel)

n-ch Si

OS2CAAC-IGZO

OS3Gate E

GI GI

Gate E

Gate E

GI

Si

EC

EV

Ef

EfEC

EV

Eg=32eV

Eg=12eV

ElectronsA Arsquo

OS3

Holes

A ArsquoA Arsquo

33

M Murakami et al Proc AM-FPDrsquo12 Digest p 174 (2012)

CAAC-IGZO c-Si

1) Bandgap (Eg) 28ndash32 eV 112 eV

2) Intrinsic carrierconcentration 10minus9 cm3 10+11 cm3

3) Depletion layer km order μm order

4) Electron effective mass (meme)

023ndash025 019 (transverse)098 (longitudinal)

5) Hole effective mass (mhme)

11ndash40 016 (light)049 (heavy)

6) Structure Layered structure(Homologous) Diamond cubic

7) Conductivity i-type n-type n-type p-type

Comparison of Physical Properties between CAAC-IGZO and c-Si

34

Features of CAAC-IGZO as Device

CAAC‐IGZO c‐Si

1) Four-terminal circuitFour-terminal circuit MRAM and FeRAM are two-terminal circuits

2) Almost no short-channel effects Short-channel effects are most troublesome

3) Normally off Uncontrollable Vth high purity and intrinsic

Vth is controllable by channel doping with B

4) IonIoff ratio of 1020 IonIoff le 1010

5) nMOS onlyCMOS feasible with Si pMOS

CMOS Si nMOSSi pMOS

6) Bulk channel buried channel Shifting from surface-channel (planar) to bulk-channel (Fin)

35

4 30-nm Scaling of CAAC-IGZO FET

36

Trench Gate Self-aligned FET

L-direction W-direction

L-direction W-direction

CAAC-OS

Gate Electrode Gate Insulating Film

CAAC-OSDrain

ElectrodeSource

Electrode

Gate Electrode

Gate Insulating Film

48 nm

Gate Electrode

Gate Insulating Film

CAAC-OS34 nm

Source Electrode

Drain Electrode

CAAC-OS

Gate Insulating FilmGate Electrode

19 nm

50 nm

S-ch structure

FETrsquos active layer (CAAC-IGZO OS2 layer) is electrically surrounded by the gate electrodeWe call this FET structure a

surrounded-channel (S-ch) structure

37

Stacked Structure of OS FET and Si FET

pMOSSi

nMOSOS

GND

VDD

A Arsquo

B

Brsquo gate metal

source drain

gate insulator

CAAC-IGZO

electrode

gate

source drain

Si

SiO2

A Arsquo

B

Brsquo

OS FET

Si FET

High integration by stacking the CAAC-OS FET over the Si-FET

Si Substrate Si Substrate

W-directionL-direction

38

Comparison between CAAC-OS FET and Si nMOS FETItem CAAC-OS FET Si nMOS FET

1 Short-channel effect Small or none timesLarge (largest issue in Si NMOS FET)

2 Scaling le 30 nm (Possibility of 5 nm) Possible to ge 5 nm

3 Off-state current yAμm (10minus24 Aμm) times fAμm (10minus15 Aμm)

4 Mobility

Long channel Low High

Short channel Slightly decrease

Decrease (110 in 30-nm device)

5 Temperature characteristics

On-state current

Increase at high temperature

Decrease at high temperature

Off-state current Sufficiently low times

Drastically increase at high temperature

6 Drain breakdown voltage High Low7 Impact ionization Not observed Observed+2 +1 minus1 times minus2

39

Item CAAC-OS FET Si nMOS FET

8 Hot carrier degradation Not observed Large

9 Punch-through Not observed Strongly need balance with scaling

10 Frequency characteristics gt 30 GHz gt 300 GHz

11 Drift velocity Close to Si with channel length about 10 nm

Saturates with channel length about 100 nm

12 Sub-threshold value Small even with thick GI

Need thinner GI by miniaturizing

13 Dielectric anisotropy Observed Not observed

14 S-channel structure(Fin tri-gate type)

Extremely important and effective

Extremely important in shorter channel and effective

+25 minus1+2 +1 minus1 times minus2

Comparison between CAAC-OS FET and Si nMOS FET

40

5 CAAC-IGZO FET for LSI Application

41

Two-terminal circuit(diode)

Potential as Logic Circuit

Dependent control of input and output Need a transistor for four-terminal control Increased F2

Independently controllable inputs and outputs Desirable logic design Sufficiently low Ioff Practically an insulator

Four-terminal circuit

A B

C D

Input Output

42

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

(a) and (c) Distribution of number of Voronoi polygons in single crystal IGZO and CAAC-IGZO (b) and (d) Distribution of Voronoi hexagons (yellow regions) and other polygons (blue regions) in the single crystal IGZO and the CAAC-IGZO

Distribution of Number of Voronoi Polygons

In the single crystal IGZO hexagonal Voronoi regions occupy almost the entire field of view In the CAAC-IGZO hexagons are the majority but pentagons and heptagons also appear

Single crystal IGZO CAAC-IGZOSingle crystal IGZO film [] CAAC-IGZO film []

Tetragon 01 07

Pentagon 12 155

Hexagon 982 683

Heptagon 04 145

Octagon 02 09

Nonagon 00 00

16

2 3 4 51

5 nmminus1

5 nmminus1

minus231degminus84degminus75 deg minus310degminus246deg

+118deg +15deg +135deg +04deg minus55deg2 3 4 51

(a)1 2 34 5

20 nm

(b) 12

3

4

5 20 nm

Panel (a) shows the points along the surface of the CAAC-IGZO film that were probed by NBED and the five remaining panels in the top row show the corresponding NBED patterns Panel (b) shows the points probed by NBED in the thickness of the film and the five remaining panels in the lower row show the corresponding NBED patterns The angle of the crystal axis is slightly shifted in both the surface and thickness directions

Nanobeam Electron Diffraction (NBED 1 nmɸ) Patterns of CAAC-IGZO Film

17

Nanobeam Electron Diffraction (NBED 1 nmɸ) Patterns of CAAC-IGZO Film

Broadanisotropic diffraction spots

Sharpcircular diffraction spots

The electron diffraction pattern of single-crystal IGZO has circular spots as shown in (b) Diffraction spots of CAAC-IGZO are not circular but anisotropic and broad

18

Schematic Band Diagram of IGZOSimple schematic diagram of defect levels in IGZO film

elec

tron

ener

gy [e

V]

surface shallow DOS(sDOS)

bulk shallow DOS(sDOS)

bulk deep DOS(dDOS)

Density of States (DOS) of IGZO

19

28-32 eV

Silicon oxide IGZO

CAAC-IGZO63 (gcm3)

nc-IGZO61 (gcm3)

a-like IGZO59 (gcm3)

αCPM Absorption coefficient estimated by a constant photocurrent method (CPM)

N Ishihara et al Proc AM-FPD12 143 (2012)J Koezuka et al SID2013 Symposium Digest 723 (2013)

A high density of deep-level states (dDOS) exists in the low-density IGZO filmThe higher the film density is (like CAAC) the lower the dDOS is

Light absorptions by IGZO films with different crystal structureswere measured to quantify the densities of deep energy trapstates (dDOS)

Density of States (DOS) of IGZO

a-like IGZO 53 times 100

20

Formation of Oxygen Vacancies (VO) in IGZO

software VASP

exchange correlation function

GGA

pseudo potential PAW

cut-off energy 800 eV

k-point 1times1times1VO are

likely to be formed

Crystal Amorphous

In Ga Zn O

-1180

-1178

-1176

-1174

-1172

-15 -10 -5 0 5 10 15

Tota

l Ene

rgy

[eV]

Distance from Interface [Aring]

InterfaceInterface

VO are highly likely to be formed

A comparison of formation of oxygen vacancies (VO) between amorphous and crystal structures was made by first-principles calculation The results indicate that VO are easily formed in the amorphous structure

21

Features of CAAC-IGZO as MaterialCAAC-IGZO c-Si

1)CAAC structure (not single-crystal nano-crystalline or amorphous)rarr No clear grain boundary is observed

lattice points to form a pentagon and heptagon

Single crystal is preferable because polycrystal has a high concentration of defects at grain boundaries2)

Crystal grains (pellets) are anchored to each other to form one big crystalrarr It can be used in VLSI devices on the scale of 5ndash60 nm

3) Not a close-packed structure rather has cushion propertiesA cubic dense structure Doped with B or P Formed by crystal pulling at approx 1420C4)

Although single-crystal IGZO is formed at very high temperatures of 1200ndash1500C CAAC-IGZO can be formed at 100ndash500C by sputteringrarr It can be placed between Si LSI and metal wire layers

5) Homologous layered structure (Semi hard structure) Diamond structure(hard)

6) Composed of four elements (In Ga Zn and O) Si alone

22

3 Performance of CAAC-IGZO FET

23

IdndashVg characteristics and mobilities of CAAC-IGZO FETs with channel lengths of (a) 2 μm and (b) 6 μm The channel widths are 50 μm

It may be possible to apply all kinds of displays (TV smartphone PC by using OEL LCD)

L = 2 μm (W = 50 μm) L = 6 μm (W = 50 μm)

High-mobility CAAC-IGZO FETs

24

(a) (b)

CAAC-IGZO TrIoff = 1times10minus22 Aμm

(100 yAμm)IonIoff = 1018

IndashV characteristics of CAAC-IGZO and Si transistors

Si TrIoff = 1times10minus12 Aμm

(1 pAμm)IonIoff = 109

Off-state Current of CAAC-IGZO and Si FETsUnit

zA (10minus21)

yA (10minus24)

aA (10minus18)

fA (10minus15)

pA (10minus12)

nA (10minus9)

μA (10minus6)

mA (10minus3)

25

How to Measure Off-state Current60

0 μm

360 μm L = 044 μmW = 10 mm(50 μmtimes200)Tox = 20 nm

A huge transistor with a channel width of 10 mm for off-state leakage current measurement (optical micrograph)

Concept of measurement

Node FN(Vout)

Behavior of potential at node FN (Vout) over time

Measuredtransistor

26

Arrhenius plot of off-state leakage current1)Change of Vout measured over time

1) S Yamazaki et al Jpn J Appl Phys vol 53 pp 04ED18 (2014)

At a gate voltage of minus3 V and 85Cthe off-state leakage current was 6 yAm (1 yA = 10minus24 A)Nonvolatility for 10 years at 85C is ensured

Off-state CurrentUnitAμm

mA (10minus3)μA (10minus6)nA (10minus9)pA (10minus12)fA (10minus15)aA (10minus18)zA (10minus21)yA (10minus24)Le

akag

e cu

rrent

[Aμ

m]

27

-5

0

5

10

15

20

25

30

RF

Gai

n [d

B]

周波数[Hz]109 1010 101130 GHz

Vd = 20 VVg = 20 V( gm max )

WL = 18 μm30 nm

Operation with a cutoff frequency of about 30 GHz is demonstratedThe off-state leakage current of an OS FET (W = 60 nm) is expected at 100 zA or less at 85C even for a 30-nm-node FET

Lower measurement limit

High Cutoff Frequency and Low Off-state Current (30 nm)

28

Frequency [Hz]30 GHz

LW = 30 18000 (60 nmtimes300 Parallel) nm

Short-channel Characteristics of OS FETs

Favorable FET characteristics were obtained with a 11-nm-thick gate insulating film when L = 32 nm

The graphs show that OS FETs are resistant to short-channel effects This is probably because they have a ldquosurrounded-channel (S-ch) structure with a thin active layerrdquo and

are ldquoaccumulation-mode devicesrdquo and ldquoCAAC-IGZO has dielectric anisotropyrdquo(S-ch structure an FET structure where the active layer is electrically surrounded by the gate electrode)

GI = 11 nm

29

0

5

10

15

20

001 01 1 10 100

μ FE

[cm

2middotV-1

middot s-1]

チャネル長 [μm]

理論

Planar TypeS‐ch Type

0

200

400

600

001 01 1 10 100

μ FE

[cm

2 middotV-1

middots-1

]チャネル長 [μm]

理論

Planar Type

Short-channel Characteristics of OS FETs

Channel length dependence of field-effect mobility

(single-crystal Si FET)

Channel length dependence of field-effect mobility

（CAAC‐IGZO FET)

The field-effect mobility (μFE) of a CAAC-IGZO FET with a reduced channel length is close to that of a single-crystal Si FET with the same size

μ FE[

cm2 V

-1s

-1]

Channel length

0

20

5

10

15

10 nm 100 nm 1 μm 100 μm10 μm 10 nm 100 nm 1 μm 100 μm10 μm

Channel length

0

600

200

400

μ FE[

cm2 V

-1s

-1]

Theoretical Theoretical

30

Temperature Dependence of CAAC-IGZO FET

OS-FET

編集中編集中

L=048um GI=20nm

Vth

S値

ID_VG特性

単結晶 p-ch Si Tr （SOI）

L=035um GI=20nm L=035um GI=20nm

編集中 編集中

単結晶 n-ch Si Tr （SOI）

‐05

00

05

10

15

0 50 100 150 200 250

Vth[V]

基板温度 []

0

50

100

150

200

250

300

0 50 100 150 200 250

S‐Value[mVdec]

基板温度 []

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

Vg [V]

250

‐05

0

05

1

15

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

‐15

‐1

‐05

0

05

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

T = minus40C minus 25C 0C 25C 50C 100C 150C 200C 250C

CAAC-OS FETs have a sufficient onoff ratio even at 200C or higherThe S-value shows little change (or is constant) compared with Si FETs

Single‐crystal n‐ch Tr (SOI) Single‐crystal p‐ch Tr (SOI)OS FET

ID‐VGCharac‐teristics

Vth

S‐value

Substrate temperature [C] Substrate temperature [C] Substrate temperature [C]

Substrate temperature [C]Substrate temperature [C]Substrate temperature [C]

31

1E-07

1E-06

1E-05

1E-04

1E-03

1E-02

0 5 10 15 20 25 30V D [V]

ID [A

]Si transistorL =09um T ox=20nm

IGZO transistorL =09um T ox=20nm

4V 26V

L ＝ 09 μm W ＝ 10 μm TOX = 20 nm VG ＝ 2 V

n = 2

CAAC-IGZO transistors have a higher breakdown voltage than Si transistorsNo hot carrier degradation and avalanche breakdown are observed

Breakdown Voltage of CAAC-IGZO and Si FETs

32

Schematic Band Diagram of Channel Regionmdash OS FET vs n-ch Si FET

Inversion Depletion Accumulation

Vg gt 0 V (ON State) Vg lt 0 V (OFF State)Vg = 0V

CAAC-IGZO(S-channel)

n-ch Si

OS2CAAC-IGZO

OS3Gate E

GI GI

Gate E

Gate E

GI

Si

EC

EV

Ef

EfEC

EV

Eg=32eV

Eg=12eV

ElectronsA Arsquo

OS3

Holes

A ArsquoA Arsquo

33

M Murakami et al Proc AM-FPDrsquo12 Digest p 174 (2012)

CAAC-IGZO c-Si

1) Bandgap (Eg) 28ndash32 eV 112 eV

2) Intrinsic carrierconcentration 10minus9 cm3 10+11 cm3

3) Depletion layer km order μm order

4) Electron effective mass (meme)

023ndash025 019 (transverse)098 (longitudinal)

5) Hole effective mass (mhme)

11ndash40 016 (light)049 (heavy)

6) Structure Layered structure(Homologous) Diamond cubic

7) Conductivity i-type n-type n-type p-type

Comparison of Physical Properties between CAAC-IGZO and c-Si

34

Features of CAAC-IGZO as Device

CAAC‐IGZO c‐Si

1) Four-terminal circuitFour-terminal circuit MRAM and FeRAM are two-terminal circuits

2) Almost no short-channel effects Short-channel effects are most troublesome

3) Normally off Uncontrollable Vth high purity and intrinsic

Vth is controllable by channel doping with B

4) IonIoff ratio of 1020 IonIoff le 1010

5) nMOS onlyCMOS feasible with Si pMOS

CMOS Si nMOSSi pMOS

6) Bulk channel buried channel Shifting from surface-channel (planar) to bulk-channel (Fin)

35

4 30-nm Scaling of CAAC-IGZO FET

36

Trench Gate Self-aligned FET

L-direction W-direction

L-direction W-direction

CAAC-OS

Gate Electrode Gate Insulating Film

CAAC-OSDrain

ElectrodeSource

Electrode

Gate Electrode

Gate Insulating Film

48 nm

Gate Electrode

Gate Insulating Film

CAAC-OS34 nm

Source Electrode

Drain Electrode

CAAC-OS

Gate Insulating FilmGate Electrode

19 nm

50 nm

S-ch structure

FETrsquos active layer (CAAC-IGZO OS2 layer) is electrically surrounded by the gate electrodeWe call this FET structure a

surrounded-channel (S-ch) structure

37

Stacked Structure of OS FET and Si FET

pMOSSi

nMOSOS

GND

VDD

A Arsquo

B

Brsquo gate metal

source drain

gate insulator

CAAC-IGZO

electrode

gate

source drain

Si

SiO2

A Arsquo

B

Brsquo

OS FET

Si FET

High integration by stacking the CAAC-OS FET over the Si-FET

Si Substrate Si Substrate

W-directionL-direction

38

Comparison between CAAC-OS FET and Si nMOS FETItem CAAC-OS FET Si nMOS FET

1 Short-channel effect Small or none timesLarge (largest issue in Si NMOS FET)

2 Scaling le 30 nm (Possibility of 5 nm) Possible to ge 5 nm

3 Off-state current yAμm (10minus24 Aμm) times fAμm (10minus15 Aμm)

4 Mobility

Long channel Low High

Short channel Slightly decrease

Decrease (110 in 30-nm device)

5 Temperature characteristics

On-state current

Increase at high temperature

Decrease at high temperature

Off-state current Sufficiently low times

Drastically increase at high temperature

6 Drain breakdown voltage High Low7 Impact ionization Not observed Observed+2 +1 minus1 times minus2

39

Item CAAC-OS FET Si nMOS FET

8 Hot carrier degradation Not observed Large

9 Punch-through Not observed Strongly need balance with scaling

10 Frequency characteristics gt 30 GHz gt 300 GHz

11 Drift velocity Close to Si with channel length about 10 nm

Saturates with channel length about 100 nm

12 Sub-threshold value Small even with thick GI

Need thinner GI by miniaturizing

13 Dielectric anisotropy Observed Not observed

14 S-channel structure(Fin tri-gate type)

Extremely important and effective

Extremely important in shorter channel and effective

+25 minus1+2 +1 minus1 times minus2

Comparison between CAAC-OS FET and Si nMOS FET

40

5 CAAC-IGZO FET for LSI Application

41

Two-terminal circuit(diode)

Potential as Logic Circuit

Dependent control of input and output Need a transistor for four-terminal control Increased F2

Independently controllable inputs and outputs Desirable logic design Sufficiently low Ioff Practically an insulator

Four-terminal circuit

A B

C D

Input Output

42

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

2 3 4 51

5 nmminus1

5 nmminus1

minus231degminus84degminus75 deg minus310degminus246deg

+118deg +15deg +135deg +04deg minus55deg2 3 4 51

(a)1 2 34 5

20 nm

(b) 12

3

4

5 20 nm

Panel (a) shows the points along the surface of the CAAC-IGZO film that were probed by NBED and the five remaining panels in the top row show the corresponding NBED patterns Panel (b) shows the points probed by NBED in the thickness of the film and the five remaining panels in the lower row show the corresponding NBED patterns The angle of the crystal axis is slightly shifted in both the surface and thickness directions

Nanobeam Electron Diffraction (NBED 1 nmɸ) Patterns of CAAC-IGZO Film

17

Nanobeam Electron Diffraction (NBED 1 nmɸ) Patterns of CAAC-IGZO Film

Broadanisotropic diffraction spots

Sharpcircular diffraction spots

The electron diffraction pattern of single-crystal IGZO has circular spots as shown in (b) Diffraction spots of CAAC-IGZO are not circular but anisotropic and broad

18

Schematic Band Diagram of IGZOSimple schematic diagram of defect levels in IGZO film

elec

tron

ener

gy [e

V]

surface shallow DOS(sDOS)

bulk shallow DOS(sDOS)

bulk deep DOS(dDOS)

Density of States (DOS) of IGZO

19

28-32 eV

Silicon oxide IGZO

CAAC-IGZO63 (gcm3)

nc-IGZO61 (gcm3)

a-like IGZO59 (gcm3)

αCPM Absorption coefficient estimated by a constant photocurrent method (CPM)

N Ishihara et al Proc AM-FPD12 143 (2012)J Koezuka et al SID2013 Symposium Digest 723 (2013)

A high density of deep-level states (dDOS) exists in the low-density IGZO filmThe higher the film density is (like CAAC) the lower the dDOS is

Light absorptions by IGZO films with different crystal structureswere measured to quantify the densities of deep energy trapstates (dDOS)

Density of States (DOS) of IGZO

a-like IGZO 53 times 100

20

Formation of Oxygen Vacancies (VO) in IGZO

software VASP

exchange correlation function

GGA

pseudo potential PAW

cut-off energy 800 eV

k-point 1times1times1VO are

likely to be formed

Crystal Amorphous

In Ga Zn O

-1180

-1178

-1176

-1174

-1172

-15 -10 -5 0 5 10 15

Tota

l Ene

rgy

[eV]

Distance from Interface [Aring]

InterfaceInterface

VO are highly likely to be formed

A comparison of formation of oxygen vacancies (VO) between amorphous and crystal structures was made by first-principles calculation The results indicate that VO are easily formed in the amorphous structure

21

Features of CAAC-IGZO as MaterialCAAC-IGZO c-Si

1)CAAC structure (not single-crystal nano-crystalline or amorphous)rarr No clear grain boundary is observed

lattice points to form a pentagon and heptagon

Single crystal is preferable because polycrystal has a high concentration of defects at grain boundaries2)

Crystal grains (pellets) are anchored to each other to form one big crystalrarr It can be used in VLSI devices on the scale of 5ndash60 nm

3) Not a close-packed structure rather has cushion propertiesA cubic dense structure Doped with B or P Formed by crystal pulling at approx 1420C4)

Although single-crystal IGZO is formed at very high temperatures of 1200ndash1500C CAAC-IGZO can be formed at 100ndash500C by sputteringrarr It can be placed between Si LSI and metal wire layers

5) Homologous layered structure (Semi hard structure) Diamond structure(hard)

6) Composed of four elements (In Ga Zn and O) Si alone

22

3 Performance of CAAC-IGZO FET

23

IdndashVg characteristics and mobilities of CAAC-IGZO FETs with channel lengths of (a) 2 μm and (b) 6 μm The channel widths are 50 μm

It may be possible to apply all kinds of displays (TV smartphone PC by using OEL LCD)

L = 2 μm (W = 50 μm) L = 6 μm (W = 50 μm)

High-mobility CAAC-IGZO FETs

24

(a) (b)

CAAC-IGZO TrIoff = 1times10minus22 Aμm

(100 yAμm)IonIoff = 1018

IndashV characteristics of CAAC-IGZO and Si transistors

Si TrIoff = 1times10minus12 Aμm

(1 pAμm)IonIoff = 109

Off-state Current of CAAC-IGZO and Si FETsUnit

zA (10minus21)

yA (10minus24)

aA (10minus18)

fA (10minus15)

pA (10minus12)

nA (10minus9)

μA (10minus6)

mA (10minus3)

25

How to Measure Off-state Current60

0 μm

360 μm L = 044 μmW = 10 mm(50 μmtimes200)Tox = 20 nm

A huge transistor with a channel width of 10 mm for off-state leakage current measurement (optical micrograph)

Concept of measurement

Node FN(Vout)

Behavior of potential at node FN (Vout) over time

Measuredtransistor

26

Arrhenius plot of off-state leakage current1)Change of Vout measured over time

1) S Yamazaki et al Jpn J Appl Phys vol 53 pp 04ED18 (2014)

At a gate voltage of minus3 V and 85Cthe off-state leakage current was 6 yAm (1 yA = 10minus24 A)Nonvolatility for 10 years at 85C is ensured

Off-state CurrentUnitAμm

mA (10minus3)μA (10minus6)nA (10minus9)pA (10minus12)fA (10minus15)aA (10minus18)zA (10minus21)yA (10minus24)Le

akag

e cu

rrent

[Aμ

m]

27

-5

0

5

10

15

20

25

30

RF

Gai

n [d

B]

周波数[Hz]109 1010 101130 GHz

Vd = 20 VVg = 20 V( gm max )

WL = 18 μm30 nm

Operation with a cutoff frequency of about 30 GHz is demonstratedThe off-state leakage current of an OS FET (W = 60 nm) is expected at 100 zA or less at 85C even for a 30-nm-node FET

Lower measurement limit

High Cutoff Frequency and Low Off-state Current (30 nm)

28

Frequency [Hz]30 GHz

LW = 30 18000 (60 nmtimes300 Parallel) nm

Short-channel Characteristics of OS FETs

Favorable FET characteristics were obtained with a 11-nm-thick gate insulating film when L = 32 nm

The graphs show that OS FETs are resistant to short-channel effects This is probably because they have a ldquosurrounded-channel (S-ch) structure with a thin active layerrdquo and

are ldquoaccumulation-mode devicesrdquo and ldquoCAAC-IGZO has dielectric anisotropyrdquo(S-ch structure an FET structure where the active layer is electrically surrounded by the gate electrode)

GI = 11 nm

29

0

5

10

15

20

001 01 1 10 100

μ FE

[cm

2middotV-1

middot s-1]

チャネル長 [μm]

理論

Planar TypeS‐ch Type

0

200

400

600

001 01 1 10 100

μ FE

[cm

2 middotV-1

middots-1

]チャネル長 [μm]

理論

Planar Type

Short-channel Characteristics of OS FETs

Channel length dependence of field-effect mobility

(single-crystal Si FET)

Channel length dependence of field-effect mobility

（CAAC‐IGZO FET)

The field-effect mobility (μFE) of a CAAC-IGZO FET with a reduced channel length is close to that of a single-crystal Si FET with the same size

μ FE[

cm2 V

-1s

-1]

Channel length

0

20

5

10

15

10 nm 100 nm 1 μm 100 μm10 μm 10 nm 100 nm 1 μm 100 μm10 μm

Channel length

0

600

200

400

μ FE[

cm2 V

-1s

-1]

Theoretical Theoretical

30

Temperature Dependence of CAAC-IGZO FET

OS-FET

編集中編集中

L=048um GI=20nm

Vth

S値

ID_VG特性

単結晶 p-ch Si Tr （SOI）

L=035um GI=20nm L=035um GI=20nm

編集中 編集中

単結晶 n-ch Si Tr （SOI）

‐05

00

05

10

15

0 50 100 150 200 250

Vth[V]

基板温度 []

0

50

100

150

200

250

300

0 50 100 150 200 250

S‐Value[mVdec]

基板温度 []

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

Vg [V]

250

‐05

0

05

1

15

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

‐15

‐1

‐05

0

05

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

T = minus40C minus 25C 0C 25C 50C 100C 150C 200C 250C

CAAC-OS FETs have a sufficient onoff ratio even at 200C or higherThe S-value shows little change (or is constant) compared with Si FETs

Single‐crystal n‐ch Tr (SOI) Single‐crystal p‐ch Tr (SOI)OS FET

ID‐VGCharac‐teristics

Vth

S‐value

Substrate temperature [C] Substrate temperature [C] Substrate temperature [C]

Substrate temperature [C]Substrate temperature [C]Substrate temperature [C]

31

1E-07

1E-06

1E-05

1E-04

1E-03

1E-02

0 5 10 15 20 25 30V D [V]

ID [A

]Si transistorL =09um T ox=20nm

IGZO transistorL =09um T ox=20nm

4V 26V

L ＝ 09 μm W ＝ 10 μm TOX = 20 nm VG ＝ 2 V

n = 2

CAAC-IGZO transistors have a higher breakdown voltage than Si transistorsNo hot carrier degradation and avalanche breakdown are observed

Breakdown Voltage of CAAC-IGZO and Si FETs

32

Schematic Band Diagram of Channel Regionmdash OS FET vs n-ch Si FET

Inversion Depletion Accumulation

Vg gt 0 V (ON State) Vg lt 0 V (OFF State)Vg = 0V

CAAC-IGZO(S-channel)

n-ch Si

OS2CAAC-IGZO

OS3Gate E

GI GI

Gate E

Gate E

GI

Si

EC

EV

Ef

EfEC

EV

Eg=32eV

Eg=12eV

ElectronsA Arsquo

OS3

Holes

A ArsquoA Arsquo

33

M Murakami et al Proc AM-FPDrsquo12 Digest p 174 (2012)

CAAC-IGZO c-Si

1) Bandgap (Eg) 28ndash32 eV 112 eV

2) Intrinsic carrierconcentration 10minus9 cm3 10+11 cm3

3) Depletion layer km order μm order

4) Electron effective mass (meme)

023ndash025 019 (transverse)098 (longitudinal)

5) Hole effective mass (mhme)

11ndash40 016 (light)049 (heavy)

6) Structure Layered structure(Homologous) Diamond cubic

7) Conductivity i-type n-type n-type p-type

Comparison of Physical Properties between CAAC-IGZO and c-Si

34

Features of CAAC-IGZO as Device

CAAC‐IGZO c‐Si

1) Four-terminal circuitFour-terminal circuit MRAM and FeRAM are two-terminal circuits

2) Almost no short-channel effects Short-channel effects are most troublesome

3) Normally off Uncontrollable Vth high purity and intrinsic

Vth is controllable by channel doping with B

4) IonIoff ratio of 1020 IonIoff le 1010

5) nMOS onlyCMOS feasible with Si pMOS

CMOS Si nMOSSi pMOS

6) Bulk channel buried channel Shifting from surface-channel (planar) to bulk-channel (Fin)

35

4 30-nm Scaling of CAAC-IGZO FET

36

Trench Gate Self-aligned FET

L-direction W-direction

L-direction W-direction

CAAC-OS

Gate Electrode Gate Insulating Film

CAAC-OSDrain

ElectrodeSource

Electrode

Gate Electrode

Gate Insulating Film

48 nm

Gate Electrode

Gate Insulating Film

CAAC-OS34 nm

Source Electrode

Drain Electrode

CAAC-OS

Gate Insulating FilmGate Electrode

19 nm

50 nm

S-ch structure

FETrsquos active layer (CAAC-IGZO OS2 layer) is electrically surrounded by the gate electrodeWe call this FET structure a

surrounded-channel (S-ch) structure

37

Stacked Structure of OS FET and Si FET

pMOSSi

nMOSOS

GND

VDD

A Arsquo

B

Brsquo gate metal

source drain

gate insulator

CAAC-IGZO

electrode

gate

source drain

Si

SiO2

A Arsquo

B

Brsquo

OS FET

Si FET

High integration by stacking the CAAC-OS FET over the Si-FET

Si Substrate Si Substrate

W-directionL-direction

38

Comparison between CAAC-OS FET and Si nMOS FETItem CAAC-OS FET Si nMOS FET

1 Short-channel effect Small or none timesLarge (largest issue in Si NMOS FET)

2 Scaling le 30 nm (Possibility of 5 nm) Possible to ge 5 nm

3 Off-state current yAμm (10minus24 Aμm) times fAμm (10minus15 Aμm)

4 Mobility

Long channel Low High

Short channel Slightly decrease

Decrease (110 in 30-nm device)

5 Temperature characteristics

On-state current

Increase at high temperature

Decrease at high temperature

Off-state current Sufficiently low times

Drastically increase at high temperature

6 Drain breakdown voltage High Low7 Impact ionization Not observed Observed+2 +1 minus1 times minus2

39

Item CAAC-OS FET Si nMOS FET

8 Hot carrier degradation Not observed Large

9 Punch-through Not observed Strongly need balance with scaling

10 Frequency characteristics gt 30 GHz gt 300 GHz

11 Drift velocity Close to Si with channel length about 10 nm

Saturates with channel length about 100 nm

12 Sub-threshold value Small even with thick GI

Need thinner GI by miniaturizing

13 Dielectric anisotropy Observed Not observed

14 S-channel structure(Fin tri-gate type)

Extremely important and effective

Extremely important in shorter channel and effective

+25 minus1+2 +1 minus1 times minus2

Comparison between CAAC-OS FET and Si nMOS FET

40

5 CAAC-IGZO FET for LSI Application

41

Two-terminal circuit(diode)

Potential as Logic Circuit

Dependent control of input and output Need a transistor for four-terminal control Increased F2

Independently controllable inputs and outputs Desirable logic design Sufficiently low Ioff Practically an insulator

Four-terminal circuit

A B

C D

Input Output

42

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

Nanobeam Electron Diffraction (NBED 1 nmɸ) Patterns of CAAC-IGZO Film

Broadanisotropic diffraction spots

Sharpcircular diffraction spots

The electron diffraction pattern of single-crystal IGZO has circular spots as shown in (b) Diffraction spots of CAAC-IGZO are not circular but anisotropic and broad

18

Schematic Band Diagram of IGZOSimple schematic diagram of defect levels in IGZO film

elec

tron

ener

gy [e

V]

surface shallow DOS(sDOS)

bulk shallow DOS(sDOS)

bulk deep DOS(dDOS)

Density of States (DOS) of IGZO

19

28-32 eV

Silicon oxide IGZO

CAAC-IGZO63 (gcm3)

nc-IGZO61 (gcm3)

a-like IGZO59 (gcm3)

αCPM Absorption coefficient estimated by a constant photocurrent method (CPM)

N Ishihara et al Proc AM-FPD12 143 (2012)J Koezuka et al SID2013 Symposium Digest 723 (2013)

A high density of deep-level states (dDOS) exists in the low-density IGZO filmThe higher the film density is (like CAAC) the lower the dDOS is

Light absorptions by IGZO films with different crystal structureswere measured to quantify the densities of deep energy trapstates (dDOS)

Density of States (DOS) of IGZO

a-like IGZO 53 times 100

20

Formation of Oxygen Vacancies (VO) in IGZO

software VASP

exchange correlation function

GGA

pseudo potential PAW

cut-off energy 800 eV

k-point 1times1times1VO are

likely to be formed

Crystal Amorphous

In Ga Zn O

-1180

-1178

-1176

-1174

-1172

-15 -10 -5 0 5 10 15

Tota

l Ene

rgy

[eV]

Distance from Interface [Aring]

InterfaceInterface

VO are highly likely to be formed

A comparison of formation of oxygen vacancies (VO) between amorphous and crystal structures was made by first-principles calculation The results indicate that VO are easily formed in the amorphous structure

21

Features of CAAC-IGZO as MaterialCAAC-IGZO c-Si

1)CAAC structure (not single-crystal nano-crystalline or amorphous)rarr No clear grain boundary is observed

lattice points to form a pentagon and heptagon

Single crystal is preferable because polycrystal has a high concentration of defects at grain boundaries2)

Crystal grains (pellets) are anchored to each other to form one big crystalrarr It can be used in VLSI devices on the scale of 5ndash60 nm

3) Not a close-packed structure rather has cushion propertiesA cubic dense structure Doped with B or P Formed by crystal pulling at approx 1420C4)

Although single-crystal IGZO is formed at very high temperatures of 1200ndash1500C CAAC-IGZO can be formed at 100ndash500C by sputteringrarr It can be placed between Si LSI and metal wire layers

5) Homologous layered structure (Semi hard structure) Diamond structure(hard)

6) Composed of four elements (In Ga Zn and O) Si alone

22

3 Performance of CAAC-IGZO FET

23

IdndashVg characteristics and mobilities of CAAC-IGZO FETs with channel lengths of (a) 2 μm and (b) 6 μm The channel widths are 50 μm

It may be possible to apply all kinds of displays (TV smartphone PC by using OEL LCD)

L = 2 μm (W = 50 μm) L = 6 μm (W = 50 μm)

High-mobility CAAC-IGZO FETs

24

(a) (b)

CAAC-IGZO TrIoff = 1times10minus22 Aμm

(100 yAμm)IonIoff = 1018

IndashV characteristics of CAAC-IGZO and Si transistors

Si TrIoff = 1times10minus12 Aμm

(1 pAμm)IonIoff = 109

Off-state Current of CAAC-IGZO and Si FETsUnit

zA (10minus21)

yA (10minus24)

aA (10minus18)

fA (10minus15)

pA (10minus12)

nA (10minus9)

μA (10minus6)

mA (10minus3)

25

How to Measure Off-state Current60

0 μm

360 μm L = 044 μmW = 10 mm(50 μmtimes200)Tox = 20 nm

A huge transistor with a channel width of 10 mm for off-state leakage current measurement (optical micrograph)

Concept of measurement

Node FN(Vout)

Behavior of potential at node FN (Vout) over time

Measuredtransistor

26

Arrhenius plot of off-state leakage current1)Change of Vout measured over time

1) S Yamazaki et al Jpn J Appl Phys vol 53 pp 04ED18 (2014)

At a gate voltage of minus3 V and 85Cthe off-state leakage current was 6 yAm (1 yA = 10minus24 A)Nonvolatility for 10 years at 85C is ensured

Off-state CurrentUnitAμm

mA (10minus3)μA (10minus6)nA (10minus9)pA (10minus12)fA (10minus15)aA (10minus18)zA (10minus21)yA (10minus24)Le

akag

e cu

rrent

[Aμ

m]

27

-5

0

5

10

15

20

25

30

RF

Gai

n [d

B]

周波数[Hz]109 1010 101130 GHz

Vd = 20 VVg = 20 V( gm max )

WL = 18 μm30 nm

Operation with a cutoff frequency of about 30 GHz is demonstratedThe off-state leakage current of an OS FET (W = 60 nm) is expected at 100 zA or less at 85C even for a 30-nm-node FET

Lower measurement limit

High Cutoff Frequency and Low Off-state Current (30 nm)

28

Frequency [Hz]30 GHz

LW = 30 18000 (60 nmtimes300 Parallel) nm

Short-channel Characteristics of OS FETs

Favorable FET characteristics were obtained with a 11-nm-thick gate insulating film when L = 32 nm

The graphs show that OS FETs are resistant to short-channel effects This is probably because they have a ldquosurrounded-channel (S-ch) structure with a thin active layerrdquo and

are ldquoaccumulation-mode devicesrdquo and ldquoCAAC-IGZO has dielectric anisotropyrdquo(S-ch structure an FET structure where the active layer is electrically surrounded by the gate electrode)

GI = 11 nm

29

0

5

10

15

20

001 01 1 10 100

μ FE

[cm

2middotV-1

middot s-1]

チャネル長 [μm]

理論

Planar TypeS‐ch Type

0

200

400

600

001 01 1 10 100

μ FE

[cm

2 middotV-1

middots-1

]チャネル長 [μm]

理論

Planar Type

Short-channel Characteristics of OS FETs

Channel length dependence of field-effect mobility

(single-crystal Si FET)

Channel length dependence of field-effect mobility

（CAAC‐IGZO FET)

The field-effect mobility (μFE) of a CAAC-IGZO FET with a reduced channel length is close to that of a single-crystal Si FET with the same size

μ FE[

cm2 V

-1s

-1]

Channel length

0

20

5

10

15

10 nm 100 nm 1 μm 100 μm10 μm 10 nm 100 nm 1 μm 100 μm10 μm

Channel length

0

600

200

400

μ FE[

cm2 V

-1s

-1]

Theoretical Theoretical

30

Temperature Dependence of CAAC-IGZO FET

OS-FET

編集中編集中

L=048um GI=20nm

Vth

S値

ID_VG特性

単結晶 p-ch Si Tr （SOI）

L=035um GI=20nm L=035um GI=20nm

編集中 編集中

単結晶 n-ch Si Tr （SOI）

‐05

00

05

10

15

0 50 100 150 200 250

Vth[V]

基板温度 []

0

50

100

150

200

250

300

0 50 100 150 200 250

S‐Value[mVdec]

基板温度 []

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

Vg [V]

250

‐05

0

05

1

15

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

‐15

‐1

‐05

0

05

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

T = minus40C minus 25C 0C 25C 50C 100C 150C 200C 250C

CAAC-OS FETs have a sufficient onoff ratio even at 200C or higherThe S-value shows little change (or is constant) compared with Si FETs

Single‐crystal n‐ch Tr (SOI) Single‐crystal p‐ch Tr (SOI)OS FET

ID‐VGCharac‐teristics

Vth

S‐value

Substrate temperature [C] Substrate temperature [C] Substrate temperature [C]

Substrate temperature [C]Substrate temperature [C]Substrate temperature [C]

31

1E-07

1E-06

1E-05

1E-04

1E-03

1E-02

0 5 10 15 20 25 30V D [V]

ID [A

]Si transistorL =09um T ox=20nm

IGZO transistorL =09um T ox=20nm

4V 26V

L ＝ 09 μm W ＝ 10 μm TOX = 20 nm VG ＝ 2 V

n = 2

CAAC-IGZO transistors have a higher breakdown voltage than Si transistorsNo hot carrier degradation and avalanche breakdown are observed

Breakdown Voltage of CAAC-IGZO and Si FETs

32

Schematic Band Diagram of Channel Regionmdash OS FET vs n-ch Si FET

Inversion Depletion Accumulation

Vg gt 0 V (ON State) Vg lt 0 V (OFF State)Vg = 0V

CAAC-IGZO(S-channel)

n-ch Si

OS2CAAC-IGZO

OS3Gate E

GI GI

Gate E

Gate E

GI

Si

EC

EV

Ef

EfEC

EV

Eg=32eV

Eg=12eV

ElectronsA Arsquo

OS3

Holes

A ArsquoA Arsquo

33

M Murakami et al Proc AM-FPDrsquo12 Digest p 174 (2012)

CAAC-IGZO c-Si

1) Bandgap (Eg) 28ndash32 eV 112 eV

2) Intrinsic carrierconcentration 10minus9 cm3 10+11 cm3

3) Depletion layer km order μm order

4) Electron effective mass (meme)

023ndash025 019 (transverse)098 (longitudinal)

5) Hole effective mass (mhme)

11ndash40 016 (light)049 (heavy)

6) Structure Layered structure(Homologous) Diamond cubic

7) Conductivity i-type n-type n-type p-type

Comparison of Physical Properties between CAAC-IGZO and c-Si

34

Features of CAAC-IGZO as Device

CAAC‐IGZO c‐Si

1) Four-terminal circuitFour-terminal circuit MRAM and FeRAM are two-terminal circuits

2) Almost no short-channel effects Short-channel effects are most troublesome

3) Normally off Uncontrollable Vth high purity and intrinsic

Vth is controllable by channel doping with B

4) IonIoff ratio of 1020 IonIoff le 1010

5) nMOS onlyCMOS feasible with Si pMOS

CMOS Si nMOSSi pMOS

6) Bulk channel buried channel Shifting from surface-channel (planar) to bulk-channel (Fin)

35

4 30-nm Scaling of CAAC-IGZO FET

36

Trench Gate Self-aligned FET

L-direction W-direction

L-direction W-direction

CAAC-OS

Gate Electrode Gate Insulating Film

CAAC-OSDrain

ElectrodeSource

Electrode

Gate Electrode

Gate Insulating Film

48 nm

Gate Electrode

Gate Insulating Film

CAAC-OS34 nm

Source Electrode

Drain Electrode

CAAC-OS

Gate Insulating FilmGate Electrode

19 nm

50 nm

S-ch structure

FETrsquos active layer (CAAC-IGZO OS2 layer) is electrically surrounded by the gate electrodeWe call this FET structure a

surrounded-channel (S-ch) structure

37

Stacked Structure of OS FET and Si FET

pMOSSi

nMOSOS

GND

VDD

A Arsquo

B

Brsquo gate metal

source drain

gate insulator

CAAC-IGZO

electrode

gate

source drain

Si

SiO2

A Arsquo

B

Brsquo

OS FET

Si FET

High integration by stacking the CAAC-OS FET over the Si-FET

Si Substrate Si Substrate

W-directionL-direction

38

Comparison between CAAC-OS FET and Si nMOS FETItem CAAC-OS FET Si nMOS FET

1 Short-channel effect Small or none timesLarge (largest issue in Si NMOS FET)

2 Scaling le 30 nm (Possibility of 5 nm) Possible to ge 5 nm

3 Off-state current yAμm (10minus24 Aμm) times fAμm (10minus15 Aμm)

4 Mobility

Long channel Low High

Short channel Slightly decrease

Decrease (110 in 30-nm device)

5 Temperature characteristics

On-state current

Increase at high temperature

Decrease at high temperature

Off-state current Sufficiently low times

Drastically increase at high temperature

6 Drain breakdown voltage High Low7 Impact ionization Not observed Observed+2 +1 minus1 times minus2

39

Item CAAC-OS FET Si nMOS FET

8 Hot carrier degradation Not observed Large

9 Punch-through Not observed Strongly need balance with scaling

10 Frequency characteristics gt 30 GHz gt 300 GHz

11 Drift velocity Close to Si with channel length about 10 nm

Saturates with channel length about 100 nm

12 Sub-threshold value Small even with thick GI

Need thinner GI by miniaturizing

13 Dielectric anisotropy Observed Not observed

14 S-channel structure(Fin tri-gate type)

Extremely important and effective

Extremely important in shorter channel and effective

+25 minus1+2 +1 minus1 times minus2

Comparison between CAAC-OS FET and Si nMOS FET

40

5 CAAC-IGZO FET for LSI Application

41

Two-terminal circuit(diode)

Potential as Logic Circuit

Dependent control of input and output Need a transistor for four-terminal control Increased F2

Independently controllable inputs and outputs Desirable logic design Sufficiently low Ioff Practically an insulator

Four-terminal circuit

A B

C D

Input Output

42

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

Schematic Band Diagram of IGZOSimple schematic diagram of defect levels in IGZO film

elec

tron

ener

gy [e

V]

surface shallow DOS(sDOS)

bulk shallow DOS(sDOS)

bulk deep DOS(dDOS)

Density of States (DOS) of IGZO

19

28-32 eV

Silicon oxide IGZO

CAAC-IGZO63 (gcm3)

nc-IGZO61 (gcm3)

a-like IGZO59 (gcm3)

αCPM Absorption coefficient estimated by a constant photocurrent method (CPM)

N Ishihara et al Proc AM-FPD12 143 (2012)J Koezuka et al SID2013 Symposium Digest 723 (2013)

A high density of deep-level states (dDOS) exists in the low-density IGZO filmThe higher the film density is (like CAAC) the lower the dDOS is

Light absorptions by IGZO films with different crystal structureswere measured to quantify the densities of deep energy trapstates (dDOS)

Density of States (DOS) of IGZO

a-like IGZO 53 times 100

20

Formation of Oxygen Vacancies (VO) in IGZO

software VASP

exchange correlation function

GGA

pseudo potential PAW

cut-off energy 800 eV

k-point 1times1times1VO are

likely to be formed

Crystal Amorphous

In Ga Zn O

-1180

-1178

-1176

-1174

-1172

-15 -10 -5 0 5 10 15

Tota

l Ene

rgy

[eV]

Distance from Interface [Aring]

InterfaceInterface

VO are highly likely to be formed

A comparison of formation of oxygen vacancies (VO) between amorphous and crystal structures was made by first-principles calculation The results indicate that VO are easily formed in the amorphous structure

21

Features of CAAC-IGZO as MaterialCAAC-IGZO c-Si

1)CAAC structure (not single-crystal nano-crystalline or amorphous)rarr No clear grain boundary is observed

lattice points to form a pentagon and heptagon

Single crystal is preferable because polycrystal has a high concentration of defects at grain boundaries2)

Crystal grains (pellets) are anchored to each other to form one big crystalrarr It can be used in VLSI devices on the scale of 5ndash60 nm

3) Not a close-packed structure rather has cushion propertiesA cubic dense structure Doped with B or P Formed by crystal pulling at approx 1420C4)

Although single-crystal IGZO is formed at very high temperatures of 1200ndash1500C CAAC-IGZO can be formed at 100ndash500C by sputteringrarr It can be placed between Si LSI and metal wire layers

5) Homologous layered structure (Semi hard structure) Diamond structure(hard)

6) Composed of four elements (In Ga Zn and O) Si alone

22

3 Performance of CAAC-IGZO FET

23

IdndashVg characteristics and mobilities of CAAC-IGZO FETs with channel lengths of (a) 2 μm and (b) 6 μm The channel widths are 50 μm

It may be possible to apply all kinds of displays (TV smartphone PC by using OEL LCD)

L = 2 μm (W = 50 μm) L = 6 μm (W = 50 μm)

High-mobility CAAC-IGZO FETs

24

(a) (b)

CAAC-IGZO TrIoff = 1times10minus22 Aμm

(100 yAμm)IonIoff = 1018

IndashV characteristics of CAAC-IGZO and Si transistors

Si TrIoff = 1times10minus12 Aμm

(1 pAμm)IonIoff = 109

Off-state Current of CAAC-IGZO and Si FETsUnit

zA (10minus21)

yA (10minus24)

aA (10minus18)

fA (10minus15)

pA (10minus12)

nA (10minus9)

μA (10minus6)

mA (10minus3)

25

How to Measure Off-state Current60

0 μm

360 μm L = 044 μmW = 10 mm(50 μmtimes200)Tox = 20 nm

A huge transistor with a channel width of 10 mm for off-state leakage current measurement (optical micrograph)

Concept of measurement

Node FN(Vout)

Behavior of potential at node FN (Vout) over time

Measuredtransistor

26

Arrhenius plot of off-state leakage current1)Change of Vout measured over time

1) S Yamazaki et al Jpn J Appl Phys vol 53 pp 04ED18 (2014)

At a gate voltage of minus3 V and 85Cthe off-state leakage current was 6 yAm (1 yA = 10minus24 A)Nonvolatility for 10 years at 85C is ensured

Off-state CurrentUnitAμm

mA (10minus3)μA (10minus6)nA (10minus9)pA (10minus12)fA (10minus15)aA (10minus18)zA (10minus21)yA (10minus24)Le

akag

e cu

rrent

[Aμ

m]

27

-5

0

5

10

15

20

25

30

RF

Gai

n [d

B]

周波数[Hz]109 1010 101130 GHz

Vd = 20 VVg = 20 V( gm max )

WL = 18 μm30 nm

Operation with a cutoff frequency of about 30 GHz is demonstratedThe off-state leakage current of an OS FET (W = 60 nm) is expected at 100 zA or less at 85C even for a 30-nm-node FET

Lower measurement limit

High Cutoff Frequency and Low Off-state Current (30 nm)

28

Frequency [Hz]30 GHz

LW = 30 18000 (60 nmtimes300 Parallel) nm

Short-channel Characteristics of OS FETs

Favorable FET characteristics were obtained with a 11-nm-thick gate insulating film when L = 32 nm

The graphs show that OS FETs are resistant to short-channel effects This is probably because they have a ldquosurrounded-channel (S-ch) structure with a thin active layerrdquo and

are ldquoaccumulation-mode devicesrdquo and ldquoCAAC-IGZO has dielectric anisotropyrdquo(S-ch structure an FET structure where the active layer is electrically surrounded by the gate electrode)

GI = 11 nm

29

0

5

10

15

20

001 01 1 10 100

μ FE

[cm

2middotV-1

middot s-1]

チャネル長 [μm]

理論

Planar TypeS‐ch Type

0

200

400

600

001 01 1 10 100

μ FE

[cm

2 middotV-1

middots-1

]チャネル長 [μm]

理論

Planar Type

Short-channel Characteristics of OS FETs

Channel length dependence of field-effect mobility

(single-crystal Si FET)

Channel length dependence of field-effect mobility

（CAAC‐IGZO FET)

The field-effect mobility (μFE) of a CAAC-IGZO FET with a reduced channel length is close to that of a single-crystal Si FET with the same size

μ FE[

cm2 V

-1s

-1]

Channel length

0

20

5

10

15

10 nm 100 nm 1 μm 100 μm10 μm 10 nm 100 nm 1 μm 100 μm10 μm

Channel length

0

600

200

400

μ FE[

cm2 V

-1s

-1]

Theoretical Theoretical

30

Temperature Dependence of CAAC-IGZO FET

OS-FET

編集中編集中

L=048um GI=20nm

Vth

S値

ID_VG特性

単結晶 p-ch Si Tr （SOI）

L=035um GI=20nm L=035um GI=20nm

編集中 編集中

単結晶 n-ch Si Tr （SOI）

‐05

00

05

10

15

0 50 100 150 200 250

Vth[V]

基板温度 []

0

50

100

150

200

250

300

0 50 100 150 200 250

S‐Value[mVdec]

基板温度 []

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

Vg [V]

250

‐05

0

05

1

15

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

‐15

‐1

‐05

0

05

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

T = minus40C minus 25C 0C 25C 50C 100C 150C 200C 250C

CAAC-OS FETs have a sufficient onoff ratio even at 200C or higherThe S-value shows little change (or is constant) compared with Si FETs

Single‐crystal n‐ch Tr (SOI) Single‐crystal p‐ch Tr (SOI)OS FET

ID‐VGCharac‐teristics

Vth

S‐value

Substrate temperature [C] Substrate temperature [C] Substrate temperature [C]

Substrate temperature [C]Substrate temperature [C]Substrate temperature [C]

31

1E-07

1E-06

1E-05

1E-04

1E-03

1E-02

0 5 10 15 20 25 30V D [V]

ID [A

]Si transistorL =09um T ox=20nm

IGZO transistorL =09um T ox=20nm

4V 26V

L ＝ 09 μm W ＝ 10 μm TOX = 20 nm VG ＝ 2 V

n = 2

CAAC-IGZO transistors have a higher breakdown voltage than Si transistorsNo hot carrier degradation and avalanche breakdown are observed

Breakdown Voltage of CAAC-IGZO and Si FETs

32

Schematic Band Diagram of Channel Regionmdash OS FET vs n-ch Si FET

Inversion Depletion Accumulation

Vg gt 0 V (ON State) Vg lt 0 V (OFF State)Vg = 0V

CAAC-IGZO(S-channel)

n-ch Si

OS2CAAC-IGZO

OS3Gate E

GI GI

Gate E

Gate E

GI

Si

EC

EV

Ef

EfEC

EV

Eg=32eV

Eg=12eV

ElectronsA Arsquo

OS3

Holes

A ArsquoA Arsquo

33

M Murakami et al Proc AM-FPDrsquo12 Digest p 174 (2012)

CAAC-IGZO c-Si

1) Bandgap (Eg) 28ndash32 eV 112 eV

2) Intrinsic carrierconcentration 10minus9 cm3 10+11 cm3

3) Depletion layer km order μm order

4) Electron effective mass (meme)

023ndash025 019 (transverse)098 (longitudinal)

5) Hole effective mass (mhme)

11ndash40 016 (light)049 (heavy)

6) Structure Layered structure(Homologous) Diamond cubic

7) Conductivity i-type n-type n-type p-type

Comparison of Physical Properties between CAAC-IGZO and c-Si

34

Features of CAAC-IGZO as Device

CAAC‐IGZO c‐Si

1) Four-terminal circuitFour-terminal circuit MRAM and FeRAM are two-terminal circuits

2) Almost no short-channel effects Short-channel effects are most troublesome

3) Normally off Uncontrollable Vth high purity and intrinsic

Vth is controllable by channel doping with B

4) IonIoff ratio of 1020 IonIoff le 1010

5) nMOS onlyCMOS feasible with Si pMOS

CMOS Si nMOSSi pMOS

6) Bulk channel buried channel Shifting from surface-channel (planar) to bulk-channel (Fin)

35

4 30-nm Scaling of CAAC-IGZO FET

36

Trench Gate Self-aligned FET

L-direction W-direction

L-direction W-direction

CAAC-OS

Gate Electrode Gate Insulating Film

CAAC-OSDrain

ElectrodeSource

Electrode

Gate Electrode

Gate Insulating Film

48 nm

Gate Electrode

Gate Insulating Film

CAAC-OS34 nm

Source Electrode

Drain Electrode

CAAC-OS

Gate Insulating FilmGate Electrode

19 nm

50 nm

S-ch structure

FETrsquos active layer (CAAC-IGZO OS2 layer) is electrically surrounded by the gate electrodeWe call this FET structure a

surrounded-channel (S-ch) structure

37

Stacked Structure of OS FET and Si FET

pMOSSi

nMOSOS

GND

VDD

A Arsquo

B

Brsquo gate metal

source drain

gate insulator

CAAC-IGZO

electrode

gate

source drain

Si

SiO2

A Arsquo

B

Brsquo

OS FET

Si FET

High integration by stacking the CAAC-OS FET over the Si-FET

Si Substrate Si Substrate

W-directionL-direction

38

Comparison between CAAC-OS FET and Si nMOS FETItem CAAC-OS FET Si nMOS FET

1 Short-channel effect Small or none timesLarge (largest issue in Si NMOS FET)

2 Scaling le 30 nm (Possibility of 5 nm) Possible to ge 5 nm

3 Off-state current yAμm (10minus24 Aμm) times fAμm (10minus15 Aμm)

4 Mobility

Long channel Low High

Short channel Slightly decrease

Decrease (110 in 30-nm device)

5 Temperature characteristics

On-state current

Increase at high temperature

Decrease at high temperature

Off-state current Sufficiently low times

Drastically increase at high temperature

6 Drain breakdown voltage High Low7 Impact ionization Not observed Observed+2 +1 minus1 times minus2

39

Item CAAC-OS FET Si nMOS FET

8 Hot carrier degradation Not observed Large

9 Punch-through Not observed Strongly need balance with scaling

10 Frequency characteristics gt 30 GHz gt 300 GHz

11 Drift velocity Close to Si with channel length about 10 nm

Saturates with channel length about 100 nm

12 Sub-threshold value Small even with thick GI

Need thinner GI by miniaturizing

13 Dielectric anisotropy Observed Not observed

14 S-channel structure(Fin tri-gate type)

Extremely important and effective

Extremely important in shorter channel and effective

+25 minus1+2 +1 minus1 times minus2

Comparison between CAAC-OS FET and Si nMOS FET

40

5 CAAC-IGZO FET for LSI Application

41

Two-terminal circuit(diode)

Potential as Logic Circuit

Dependent control of input and output Need a transistor for four-terminal control Increased F2

Independently controllable inputs and outputs Desirable logic design Sufficiently low Ioff Practically an insulator

Four-terminal circuit

A B

C D

Input Output

42

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

CAAC-IGZO63 (gcm3)

nc-IGZO61 (gcm3)

a-like IGZO59 (gcm3)

αCPM Absorption coefficient estimated by a constant photocurrent method (CPM)

N Ishihara et al Proc AM-FPD12 143 (2012)J Koezuka et al SID2013 Symposium Digest 723 (2013)

A high density of deep-level states (dDOS) exists in the low-density IGZO filmThe higher the film density is (like CAAC) the lower the dDOS is

Light absorptions by IGZO films with different crystal structureswere measured to quantify the densities of deep energy trapstates (dDOS)

Density of States (DOS) of IGZO

a-like IGZO 53 times 100

20

Formation of Oxygen Vacancies (VO) in IGZO

software VASP

exchange correlation function

GGA

pseudo potential PAW

cut-off energy 800 eV

k-point 1times1times1VO are

likely to be formed

Crystal Amorphous

In Ga Zn O

-1180

-1178

-1176

-1174

-1172

-15 -10 -5 0 5 10 15

Tota

l Ene

rgy

[eV]

Distance from Interface [Aring]

InterfaceInterface

VO are highly likely to be formed

A comparison of formation of oxygen vacancies (VO) between amorphous and crystal structures was made by first-principles calculation The results indicate that VO are easily formed in the amorphous structure

21

Features of CAAC-IGZO as MaterialCAAC-IGZO c-Si

1)CAAC structure (not single-crystal nano-crystalline or amorphous)rarr No clear grain boundary is observed

lattice points to form a pentagon and heptagon

Single crystal is preferable because polycrystal has a high concentration of defects at grain boundaries2)

Crystal grains (pellets) are anchored to each other to form one big crystalrarr It can be used in VLSI devices on the scale of 5ndash60 nm

3) Not a close-packed structure rather has cushion propertiesA cubic dense structure Doped with B or P Formed by crystal pulling at approx 1420C4)

Although single-crystal IGZO is formed at very high temperatures of 1200ndash1500C CAAC-IGZO can be formed at 100ndash500C by sputteringrarr It can be placed between Si LSI and metal wire layers

5) Homologous layered structure (Semi hard structure) Diamond structure(hard)

6) Composed of four elements (In Ga Zn and O) Si alone

22

3 Performance of CAAC-IGZO FET

23

IdndashVg characteristics and mobilities of CAAC-IGZO FETs with channel lengths of (a) 2 μm and (b) 6 μm The channel widths are 50 μm

It may be possible to apply all kinds of displays (TV smartphone PC by using OEL LCD)

L = 2 μm (W = 50 μm) L = 6 μm (W = 50 μm)

High-mobility CAAC-IGZO FETs

24

(a) (b)

CAAC-IGZO TrIoff = 1times10minus22 Aμm

(100 yAμm)IonIoff = 1018

IndashV characteristics of CAAC-IGZO and Si transistors

Si TrIoff = 1times10minus12 Aμm

(1 pAμm)IonIoff = 109

Off-state Current of CAAC-IGZO and Si FETsUnit

zA (10minus21)

yA (10minus24)

aA (10minus18)

fA (10minus15)

pA (10minus12)

nA (10minus9)

μA (10minus6)

mA (10minus3)

25

How to Measure Off-state Current60

0 μm

360 μm L = 044 μmW = 10 mm(50 μmtimes200)Tox = 20 nm

A huge transistor with a channel width of 10 mm for off-state leakage current measurement (optical micrograph)

Concept of measurement

Node FN(Vout)

Behavior of potential at node FN (Vout) over time

Measuredtransistor

26

Arrhenius plot of off-state leakage current1)Change of Vout measured over time

1) S Yamazaki et al Jpn J Appl Phys vol 53 pp 04ED18 (2014)

At a gate voltage of minus3 V and 85Cthe off-state leakage current was 6 yAm (1 yA = 10minus24 A)Nonvolatility for 10 years at 85C is ensured

Off-state CurrentUnitAμm

mA (10minus3)μA (10minus6)nA (10minus9)pA (10minus12)fA (10minus15)aA (10minus18)zA (10minus21)yA (10minus24)Le

akag

e cu

rrent

[Aμ

m]

27

-5

0

5

10

15

20

25

30

RF

Gai

n [d

B]

周波数[Hz]109 1010 101130 GHz

Vd = 20 VVg = 20 V( gm max )

WL = 18 μm30 nm

Operation with a cutoff frequency of about 30 GHz is demonstratedThe off-state leakage current of an OS FET (W = 60 nm) is expected at 100 zA or less at 85C even for a 30-nm-node FET

Lower measurement limit

High Cutoff Frequency and Low Off-state Current (30 nm)

28

Frequency [Hz]30 GHz

LW = 30 18000 (60 nmtimes300 Parallel) nm

Short-channel Characteristics of OS FETs

Favorable FET characteristics were obtained with a 11-nm-thick gate insulating film when L = 32 nm

The graphs show that OS FETs are resistant to short-channel effects This is probably because they have a ldquosurrounded-channel (S-ch) structure with a thin active layerrdquo and

are ldquoaccumulation-mode devicesrdquo and ldquoCAAC-IGZO has dielectric anisotropyrdquo(S-ch structure an FET structure where the active layer is electrically surrounded by the gate electrode)

GI = 11 nm

29

0

5

10

15

20

001 01 1 10 100

μ FE

[cm

2middotV-1

middot s-1]

チャネル長 [μm]

理論

Planar TypeS‐ch Type

0

200

400

600

001 01 1 10 100

μ FE

[cm

2 middotV-1

middots-1

]チャネル長 [μm]

理論

Planar Type

Short-channel Characteristics of OS FETs

Channel length dependence of field-effect mobility

(single-crystal Si FET)

Channel length dependence of field-effect mobility

（CAAC‐IGZO FET)

The field-effect mobility (μFE) of a CAAC-IGZO FET with a reduced channel length is close to that of a single-crystal Si FET with the same size

μ FE[

cm2 V

-1s

-1]

Channel length

0

20

5

10

15

10 nm 100 nm 1 μm 100 μm10 μm 10 nm 100 nm 1 μm 100 μm10 μm

Channel length

0

600

200

400

μ FE[

cm2 V

-1s

-1]

Theoretical Theoretical

30

Temperature Dependence of CAAC-IGZO FET

OS-FET

編集中編集中

L=048um GI=20nm

Vth

S値

ID_VG特性

単結晶 p-ch Si Tr （SOI）

L=035um GI=20nm L=035um GI=20nm

編集中 編集中

単結晶 n-ch Si Tr （SOI）

‐05

00

05

10

15

0 50 100 150 200 250

Vth[V]

基板温度 []

0

50

100

150

200

250

300

0 50 100 150 200 250

S‐Value[mVdec]

基板温度 []

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

Vg [V]

250

‐05

0

05

1

15

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

‐15

‐1

‐05

0

05

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

T = minus40C minus 25C 0C 25C 50C 100C 150C 200C 250C

CAAC-OS FETs have a sufficient onoff ratio even at 200C or higherThe S-value shows little change (or is constant) compared with Si FETs

Single‐crystal n‐ch Tr (SOI) Single‐crystal p‐ch Tr (SOI)OS FET

ID‐VGCharac‐teristics

Vth

S‐value

Substrate temperature [C] Substrate temperature [C] Substrate temperature [C]

Substrate temperature [C]Substrate temperature [C]Substrate temperature [C]

31

1E-07

1E-06

1E-05

1E-04

1E-03

1E-02

0 5 10 15 20 25 30V D [V]

ID [A

]Si transistorL =09um T ox=20nm

IGZO transistorL =09um T ox=20nm

4V 26V

L ＝ 09 μm W ＝ 10 μm TOX = 20 nm VG ＝ 2 V

n = 2

CAAC-IGZO transistors have a higher breakdown voltage than Si transistorsNo hot carrier degradation and avalanche breakdown are observed

Breakdown Voltage of CAAC-IGZO and Si FETs

32

Schematic Band Diagram of Channel Regionmdash OS FET vs n-ch Si FET

Inversion Depletion Accumulation

Vg gt 0 V (ON State) Vg lt 0 V (OFF State)Vg = 0V

CAAC-IGZO(S-channel)

n-ch Si

OS2CAAC-IGZO

OS3Gate E

GI GI

Gate E

Gate E

GI

Si

EC

EV

Ef

EfEC

EV

Eg=32eV

Eg=12eV

ElectronsA Arsquo

OS3

Holes

A ArsquoA Arsquo

33

M Murakami et al Proc AM-FPDrsquo12 Digest p 174 (2012)

CAAC-IGZO c-Si

1) Bandgap (Eg) 28ndash32 eV 112 eV

2) Intrinsic carrierconcentration 10minus9 cm3 10+11 cm3

3) Depletion layer km order μm order

4) Electron effective mass (meme)

023ndash025 019 (transverse)098 (longitudinal)

5) Hole effective mass (mhme)

11ndash40 016 (light)049 (heavy)

6) Structure Layered structure(Homologous) Diamond cubic

7) Conductivity i-type n-type n-type p-type

Comparison of Physical Properties between CAAC-IGZO and c-Si

34

Features of CAAC-IGZO as Device

CAAC‐IGZO c‐Si

1) Four-terminal circuitFour-terminal circuit MRAM and FeRAM are two-terminal circuits

2) Almost no short-channel effects Short-channel effects are most troublesome

3) Normally off Uncontrollable Vth high purity and intrinsic

Vth is controllable by channel doping with B

4) IonIoff ratio of 1020 IonIoff le 1010

5) nMOS onlyCMOS feasible with Si pMOS

CMOS Si nMOSSi pMOS

6) Bulk channel buried channel Shifting from surface-channel (planar) to bulk-channel (Fin)

35

4 30-nm Scaling of CAAC-IGZO FET

36

Trench Gate Self-aligned FET

L-direction W-direction

L-direction W-direction

CAAC-OS

Gate Electrode Gate Insulating Film

CAAC-OSDrain

ElectrodeSource

Electrode

Gate Electrode

Gate Insulating Film

48 nm

Gate Electrode

Gate Insulating Film

CAAC-OS34 nm

Source Electrode

Drain Electrode

CAAC-OS

Gate Insulating FilmGate Electrode

19 nm

50 nm

S-ch structure

FETrsquos active layer (CAAC-IGZO OS2 layer) is electrically surrounded by the gate electrodeWe call this FET structure a

surrounded-channel (S-ch) structure

37

Stacked Structure of OS FET and Si FET

pMOSSi

nMOSOS

GND

VDD

A Arsquo

B

Brsquo gate metal

source drain

gate insulator

CAAC-IGZO

electrode

gate

source drain

Si

SiO2

A Arsquo

B

Brsquo

OS FET

Si FET

High integration by stacking the CAAC-OS FET over the Si-FET

Si Substrate Si Substrate

W-directionL-direction

38

Comparison between CAAC-OS FET and Si nMOS FETItem CAAC-OS FET Si nMOS FET

1 Short-channel effect Small or none timesLarge (largest issue in Si NMOS FET)

2 Scaling le 30 nm (Possibility of 5 nm) Possible to ge 5 nm

3 Off-state current yAμm (10minus24 Aμm) times fAμm (10minus15 Aμm)

4 Mobility

Long channel Low High

Short channel Slightly decrease

Decrease (110 in 30-nm device)

5 Temperature characteristics

On-state current

Increase at high temperature

Decrease at high temperature

Off-state current Sufficiently low times

Drastically increase at high temperature

6 Drain breakdown voltage High Low7 Impact ionization Not observed Observed+2 +1 minus1 times minus2

39

Item CAAC-OS FET Si nMOS FET

8 Hot carrier degradation Not observed Large

9 Punch-through Not observed Strongly need balance with scaling

10 Frequency characteristics gt 30 GHz gt 300 GHz

11 Drift velocity Close to Si with channel length about 10 nm

Saturates with channel length about 100 nm

12 Sub-threshold value Small even with thick GI

Need thinner GI by miniaturizing

13 Dielectric anisotropy Observed Not observed

14 S-channel structure(Fin tri-gate type)

Extremely important and effective

Extremely important in shorter channel and effective

+25 minus1+2 +1 minus1 times minus2

Comparison between CAAC-OS FET and Si nMOS FET

40

5 CAAC-IGZO FET for LSI Application

41

Two-terminal circuit(diode)

Potential as Logic Circuit

Dependent control of input and output Need a transistor for four-terminal control Increased F2

Independently controllable inputs and outputs Desirable logic design Sufficiently low Ioff Practically an insulator

Four-terminal circuit

A B

C D

Input Output

42

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

Formation of Oxygen Vacancies (VO) in IGZO

software VASP

exchange correlation function

GGA

pseudo potential PAW

cut-off energy 800 eV

k-point 1times1times1VO are

likely to be formed

Crystal Amorphous

In Ga Zn O

-1180

-1178

-1176

-1174

-1172

-15 -10 -5 0 5 10 15

Tota

l Ene

rgy

[eV]

Distance from Interface [Aring]

InterfaceInterface

VO are highly likely to be formed

A comparison of formation of oxygen vacancies (VO) between amorphous and crystal structures was made by first-principles calculation The results indicate that VO are easily formed in the amorphous structure

21

Features of CAAC-IGZO as MaterialCAAC-IGZO c-Si

1)CAAC structure (not single-crystal nano-crystalline or amorphous)rarr No clear grain boundary is observed

lattice points to form a pentagon and heptagon

Single crystal is preferable because polycrystal has a high concentration of defects at grain boundaries2)

Crystal grains (pellets) are anchored to each other to form one big crystalrarr It can be used in VLSI devices on the scale of 5ndash60 nm

3) Not a close-packed structure rather has cushion propertiesA cubic dense structure Doped with B or P Formed by crystal pulling at approx 1420C4)

Although single-crystal IGZO is formed at very high temperatures of 1200ndash1500C CAAC-IGZO can be formed at 100ndash500C by sputteringrarr It can be placed between Si LSI and metal wire layers

5) Homologous layered structure (Semi hard structure) Diamond structure(hard)

6) Composed of four elements (In Ga Zn and O) Si alone

22

3 Performance of CAAC-IGZO FET

23

IdndashVg characteristics and mobilities of CAAC-IGZO FETs with channel lengths of (a) 2 μm and (b) 6 μm The channel widths are 50 μm

It may be possible to apply all kinds of displays (TV smartphone PC by using OEL LCD)

L = 2 μm (W = 50 μm) L = 6 μm (W = 50 μm)

High-mobility CAAC-IGZO FETs

24

(a) (b)

CAAC-IGZO TrIoff = 1times10minus22 Aμm

(100 yAμm)IonIoff = 1018

IndashV characteristics of CAAC-IGZO and Si transistors

Si TrIoff = 1times10minus12 Aμm

(1 pAμm)IonIoff = 109

Off-state Current of CAAC-IGZO and Si FETsUnit

zA (10minus21)

yA (10minus24)

aA (10minus18)

fA (10minus15)

pA (10minus12)

nA (10minus9)

μA (10minus6)

mA (10minus3)

25

How to Measure Off-state Current60

0 μm

360 μm L = 044 μmW = 10 mm(50 μmtimes200)Tox = 20 nm

A huge transistor with a channel width of 10 mm for off-state leakage current measurement (optical micrograph)

Concept of measurement

Node FN(Vout)

Behavior of potential at node FN (Vout) over time

Measuredtransistor

26

Arrhenius plot of off-state leakage current1)Change of Vout measured over time

1) S Yamazaki et al Jpn J Appl Phys vol 53 pp 04ED18 (2014)

At a gate voltage of minus3 V and 85Cthe off-state leakage current was 6 yAm (1 yA = 10minus24 A)Nonvolatility for 10 years at 85C is ensured

Off-state CurrentUnitAμm

mA (10minus3)μA (10minus6)nA (10minus9)pA (10minus12)fA (10minus15)aA (10minus18)zA (10minus21)yA (10minus24)Le

akag

e cu

rrent

[Aμ

m]

27

-5

0

5

10

15

20

25

30

RF

Gai

n [d

B]

周波数[Hz]109 1010 101130 GHz

Vd = 20 VVg = 20 V( gm max )

WL = 18 μm30 nm

Operation with a cutoff frequency of about 30 GHz is demonstratedThe off-state leakage current of an OS FET (W = 60 nm) is expected at 100 zA or less at 85C even for a 30-nm-node FET

Lower measurement limit

High Cutoff Frequency and Low Off-state Current (30 nm)

28

Frequency [Hz]30 GHz

LW = 30 18000 (60 nmtimes300 Parallel) nm

Short-channel Characteristics of OS FETs

Favorable FET characteristics were obtained with a 11-nm-thick gate insulating film when L = 32 nm

The graphs show that OS FETs are resistant to short-channel effects This is probably because they have a ldquosurrounded-channel (S-ch) structure with a thin active layerrdquo and

are ldquoaccumulation-mode devicesrdquo and ldquoCAAC-IGZO has dielectric anisotropyrdquo(S-ch structure an FET structure where the active layer is electrically surrounded by the gate electrode)

GI = 11 nm

29

0

5

10

15

20

001 01 1 10 100

μ FE

[cm

2middotV-1

middot s-1]

チャネル長 [μm]

理論

Planar TypeS‐ch Type

0

200

400

600

001 01 1 10 100

μ FE

[cm

2 middotV-1

middots-1

]チャネル長 [μm]

理論

Planar Type

Short-channel Characteristics of OS FETs

Channel length dependence of field-effect mobility

(single-crystal Si FET)

Channel length dependence of field-effect mobility

（CAAC‐IGZO FET)

The field-effect mobility (μFE) of a CAAC-IGZO FET with a reduced channel length is close to that of a single-crystal Si FET with the same size

μ FE[

cm2 V

-1s

-1]

Channel length

0

20

5

10

15

10 nm 100 nm 1 μm 100 μm10 μm 10 nm 100 nm 1 μm 100 μm10 μm

Channel length

0

600

200

400

μ FE[

cm2 V

-1s

-1]

Theoretical Theoretical

30

Temperature Dependence of CAAC-IGZO FET

OS-FET

編集中編集中

L=048um GI=20nm

Vth

S値

ID_VG特性

単結晶 p-ch Si Tr （SOI）

L=035um GI=20nm L=035um GI=20nm

編集中 編集中

単結晶 n-ch Si Tr （SOI）

‐05

00

05

10

15

0 50 100 150 200 250

Vth[V]

基板温度 []

0

50

100

150

200

250

300

0 50 100 150 200 250

S‐Value[mVdec]

基板温度 []

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

Vg [V]

250

‐05

0

05

1

15

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

‐15

‐1

‐05

0

05

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

T = minus40C minus 25C 0C 25C 50C 100C 150C 200C 250C

CAAC-OS FETs have a sufficient onoff ratio even at 200C or higherThe S-value shows little change (or is constant) compared with Si FETs

Single‐crystal n‐ch Tr (SOI) Single‐crystal p‐ch Tr (SOI)OS FET

ID‐VGCharac‐teristics

Vth

S‐value

Substrate temperature [C] Substrate temperature [C] Substrate temperature [C]

Substrate temperature [C]Substrate temperature [C]Substrate temperature [C]

31

1E-07

1E-06

1E-05

1E-04

1E-03

1E-02

0 5 10 15 20 25 30V D [V]

ID [A

]Si transistorL =09um T ox=20nm

IGZO transistorL =09um T ox=20nm

4V 26V

L ＝ 09 μm W ＝ 10 μm TOX = 20 nm VG ＝ 2 V

n = 2

CAAC-IGZO transistors have a higher breakdown voltage than Si transistorsNo hot carrier degradation and avalanche breakdown are observed

Breakdown Voltage of CAAC-IGZO and Si FETs

32

Schematic Band Diagram of Channel Regionmdash OS FET vs n-ch Si FET

Inversion Depletion Accumulation

Vg gt 0 V (ON State) Vg lt 0 V (OFF State)Vg = 0V

CAAC-IGZO(S-channel)

n-ch Si

OS2CAAC-IGZO

OS3Gate E

GI GI

Gate E

Gate E

GI

Si

EC

EV

Ef

EfEC

EV

Eg=32eV

Eg=12eV

ElectronsA Arsquo

OS3

Holes

A ArsquoA Arsquo

33

M Murakami et al Proc AM-FPDrsquo12 Digest p 174 (2012)

CAAC-IGZO c-Si

1) Bandgap (Eg) 28ndash32 eV 112 eV

2) Intrinsic carrierconcentration 10minus9 cm3 10+11 cm3

3) Depletion layer km order μm order

4) Electron effective mass (meme)

023ndash025 019 (transverse)098 (longitudinal)

5) Hole effective mass (mhme)

11ndash40 016 (light)049 (heavy)

6) Structure Layered structure(Homologous) Diamond cubic

7) Conductivity i-type n-type n-type p-type

Comparison of Physical Properties between CAAC-IGZO and c-Si

34

Features of CAAC-IGZO as Device

CAAC‐IGZO c‐Si

1) Four-terminal circuitFour-terminal circuit MRAM and FeRAM are two-terminal circuits

2) Almost no short-channel effects Short-channel effects are most troublesome

3) Normally off Uncontrollable Vth high purity and intrinsic

Vth is controllable by channel doping with B

4) IonIoff ratio of 1020 IonIoff le 1010

5) nMOS onlyCMOS feasible with Si pMOS

CMOS Si nMOSSi pMOS

6) Bulk channel buried channel Shifting from surface-channel (planar) to bulk-channel (Fin)

35

4 30-nm Scaling of CAAC-IGZO FET

36

Trench Gate Self-aligned FET

L-direction W-direction

L-direction W-direction

CAAC-OS

Gate Electrode Gate Insulating Film

CAAC-OSDrain

ElectrodeSource

Electrode

Gate Electrode

Gate Insulating Film

48 nm

Gate Electrode

Gate Insulating Film

CAAC-OS34 nm

Source Electrode

Drain Electrode

CAAC-OS

Gate Insulating FilmGate Electrode

19 nm

50 nm

S-ch structure

FETrsquos active layer (CAAC-IGZO OS2 layer) is electrically surrounded by the gate electrodeWe call this FET structure a

surrounded-channel (S-ch) structure

37

Stacked Structure of OS FET and Si FET

pMOSSi

nMOSOS

GND

VDD

A Arsquo

B

Brsquo gate metal

source drain

gate insulator

CAAC-IGZO

electrode

gate

source drain

Si

SiO2

A Arsquo

B

Brsquo

OS FET

Si FET

High integration by stacking the CAAC-OS FET over the Si-FET

Si Substrate Si Substrate

W-directionL-direction

38

Comparison between CAAC-OS FET and Si nMOS FETItem CAAC-OS FET Si nMOS FET

1 Short-channel effect Small or none timesLarge (largest issue in Si NMOS FET)

2 Scaling le 30 nm (Possibility of 5 nm) Possible to ge 5 nm

3 Off-state current yAμm (10minus24 Aμm) times fAμm (10minus15 Aμm)

4 Mobility

Long channel Low High

Short channel Slightly decrease

Decrease (110 in 30-nm device)

5 Temperature characteristics

On-state current

Increase at high temperature

Decrease at high temperature

Off-state current Sufficiently low times

Drastically increase at high temperature

6 Drain breakdown voltage High Low7 Impact ionization Not observed Observed+2 +1 minus1 times minus2

39

Item CAAC-OS FET Si nMOS FET

8 Hot carrier degradation Not observed Large

9 Punch-through Not observed Strongly need balance with scaling

10 Frequency characteristics gt 30 GHz gt 300 GHz

11 Drift velocity Close to Si with channel length about 10 nm

Saturates with channel length about 100 nm

12 Sub-threshold value Small even with thick GI

Need thinner GI by miniaturizing

13 Dielectric anisotropy Observed Not observed

14 S-channel structure(Fin tri-gate type)

Extremely important and effective

Extremely important in shorter channel and effective

+25 minus1+2 +1 minus1 times minus2

Comparison between CAAC-OS FET and Si nMOS FET

40

5 CAAC-IGZO FET for LSI Application

41

Two-terminal circuit(diode)

Potential as Logic Circuit

Dependent control of input and output Need a transistor for four-terminal control Increased F2

Independently controllable inputs and outputs Desirable logic design Sufficiently low Ioff Practically an insulator

Four-terminal circuit

A B

C D

Input Output

42

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

Features of CAAC-IGZO as MaterialCAAC-IGZO c-Si

1)CAAC structure (not single-crystal nano-crystalline or amorphous)rarr No clear grain boundary is observed

lattice points to form a pentagon and heptagon

Single crystal is preferable because polycrystal has a high concentration of defects at grain boundaries2)

Crystal grains (pellets) are anchored to each other to form one big crystalrarr It can be used in VLSI devices on the scale of 5ndash60 nm

3) Not a close-packed structure rather has cushion propertiesA cubic dense structure Doped with B or P Formed by crystal pulling at approx 1420C4)

Although single-crystal IGZO is formed at very high temperatures of 1200ndash1500C CAAC-IGZO can be formed at 100ndash500C by sputteringrarr It can be placed between Si LSI and metal wire layers

5) Homologous layered structure (Semi hard structure) Diamond structure(hard)

6) Composed of four elements (In Ga Zn and O) Si alone

22

3 Performance of CAAC-IGZO FET

23

IdndashVg characteristics and mobilities of CAAC-IGZO FETs with channel lengths of (a) 2 μm and (b) 6 μm The channel widths are 50 μm

It may be possible to apply all kinds of displays (TV smartphone PC by using OEL LCD)

L = 2 μm (W = 50 μm) L = 6 μm (W = 50 μm)

High-mobility CAAC-IGZO FETs

24

(a) (b)

CAAC-IGZO TrIoff = 1times10minus22 Aμm

(100 yAμm)IonIoff = 1018

IndashV characteristics of CAAC-IGZO and Si transistors

Si TrIoff = 1times10minus12 Aμm

(1 pAμm)IonIoff = 109

Off-state Current of CAAC-IGZO and Si FETsUnit

zA (10minus21)

yA (10minus24)

aA (10minus18)

fA (10minus15)

pA (10minus12)

nA (10minus9)

μA (10minus6)

mA (10minus3)

25

How to Measure Off-state Current60

0 μm

360 μm L = 044 μmW = 10 mm(50 μmtimes200)Tox = 20 nm

A huge transistor with a channel width of 10 mm for off-state leakage current measurement (optical micrograph)

Concept of measurement

Node FN(Vout)

Behavior of potential at node FN (Vout) over time

Measuredtransistor

26

Arrhenius plot of off-state leakage current1)Change of Vout measured over time

1) S Yamazaki et al Jpn J Appl Phys vol 53 pp 04ED18 (2014)

At a gate voltage of minus3 V and 85Cthe off-state leakage current was 6 yAm (1 yA = 10minus24 A)Nonvolatility for 10 years at 85C is ensured

Off-state CurrentUnitAμm

mA (10minus3)μA (10minus6)nA (10minus9)pA (10minus12)fA (10minus15)aA (10minus18)zA (10minus21)yA (10minus24)Le

akag

e cu

rrent

[Aμ

m]

27

-5

0

5

10

15

20

25

30

RF

Gai

n [d

B]

周波数[Hz]109 1010 101130 GHz

Vd = 20 VVg = 20 V( gm max )

WL = 18 μm30 nm

Operation with a cutoff frequency of about 30 GHz is demonstratedThe off-state leakage current of an OS FET (W = 60 nm) is expected at 100 zA or less at 85C even for a 30-nm-node FET

Lower measurement limit

High Cutoff Frequency and Low Off-state Current (30 nm)

28

Frequency [Hz]30 GHz

LW = 30 18000 (60 nmtimes300 Parallel) nm

Short-channel Characteristics of OS FETs

Favorable FET characteristics were obtained with a 11-nm-thick gate insulating film when L = 32 nm

The graphs show that OS FETs are resistant to short-channel effects This is probably because they have a ldquosurrounded-channel (S-ch) structure with a thin active layerrdquo and

are ldquoaccumulation-mode devicesrdquo and ldquoCAAC-IGZO has dielectric anisotropyrdquo(S-ch structure an FET structure where the active layer is electrically surrounded by the gate electrode)

GI = 11 nm

29

0

5

10

15

20

001 01 1 10 100

μ FE

[cm

2middotV-1

middot s-1]

チャネル長 [μm]

理論

Planar TypeS‐ch Type

0

200

400

600

001 01 1 10 100

μ FE

[cm

2 middotV-1

middots-1

]チャネル長 [μm]

理論

Planar Type

Short-channel Characteristics of OS FETs

Channel length dependence of field-effect mobility

(single-crystal Si FET)

Channel length dependence of field-effect mobility

（CAAC‐IGZO FET)

The field-effect mobility (μFE) of a CAAC-IGZO FET with a reduced channel length is close to that of a single-crystal Si FET with the same size

μ FE[

cm2 V

-1s

-1]

Channel length

0

20

5

10

15

10 nm 100 nm 1 μm 100 μm10 μm 10 nm 100 nm 1 μm 100 μm10 μm

Channel length

0

600

200

400

μ FE[

cm2 V

-1s

-1]

Theoretical Theoretical

30

Temperature Dependence of CAAC-IGZO FET

OS-FET

編集中編集中

L=048um GI=20nm

Vth

S値

ID_VG特性

単結晶 p-ch Si Tr （SOI）

L=035um GI=20nm L=035um GI=20nm

編集中 編集中

単結晶 n-ch Si Tr （SOI）

‐05

00

05

10

15

0 50 100 150 200 250

Vth[V]

基板温度 []

0

50

100

150

200

250

300

0 50 100 150 200 250

S‐Value[mVdec]

基板温度 []

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

Vg [V]

250

‐05

0

05

1

15

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

‐15

‐1

‐05

0

05

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

T = minus40C minus 25C 0C 25C 50C 100C 150C 200C 250C

CAAC-OS FETs have a sufficient onoff ratio even at 200C or higherThe S-value shows little change (or is constant) compared with Si FETs

Single‐crystal n‐ch Tr (SOI) Single‐crystal p‐ch Tr (SOI)OS FET

ID‐VGCharac‐teristics

Vth

S‐value

Substrate temperature [C] Substrate temperature [C] Substrate temperature [C]

Substrate temperature [C]Substrate temperature [C]Substrate temperature [C]

31

1E-07

1E-06

1E-05

1E-04

1E-03

1E-02

0 5 10 15 20 25 30V D [V]

ID [A

]Si transistorL =09um T ox=20nm

IGZO transistorL =09um T ox=20nm

4V 26V

L ＝ 09 μm W ＝ 10 μm TOX = 20 nm VG ＝ 2 V

n = 2

CAAC-IGZO transistors have a higher breakdown voltage than Si transistorsNo hot carrier degradation and avalanche breakdown are observed

Breakdown Voltage of CAAC-IGZO and Si FETs

32

Schematic Band Diagram of Channel Regionmdash OS FET vs n-ch Si FET

Inversion Depletion Accumulation

Vg gt 0 V (ON State) Vg lt 0 V (OFF State)Vg = 0V

CAAC-IGZO(S-channel)

n-ch Si

OS2CAAC-IGZO

OS3Gate E

GI GI

Gate E

Gate E

GI

Si

EC

EV

Ef

EfEC

EV

Eg=32eV

Eg=12eV

ElectronsA Arsquo

OS3

Holes

A ArsquoA Arsquo

33

M Murakami et al Proc AM-FPDrsquo12 Digest p 174 (2012)

CAAC-IGZO c-Si

1) Bandgap (Eg) 28ndash32 eV 112 eV

2) Intrinsic carrierconcentration 10minus9 cm3 10+11 cm3

3) Depletion layer km order μm order

4) Electron effective mass (meme)

023ndash025 019 (transverse)098 (longitudinal)

5) Hole effective mass (mhme)

11ndash40 016 (light)049 (heavy)

6) Structure Layered structure(Homologous) Diamond cubic

7) Conductivity i-type n-type n-type p-type

Comparison of Physical Properties between CAAC-IGZO and c-Si

34

Features of CAAC-IGZO as Device

CAAC‐IGZO c‐Si

1) Four-terminal circuitFour-terminal circuit MRAM and FeRAM are two-terminal circuits

2) Almost no short-channel effects Short-channel effects are most troublesome

3) Normally off Uncontrollable Vth high purity and intrinsic

Vth is controllable by channel doping with B

4) IonIoff ratio of 1020 IonIoff le 1010

5) nMOS onlyCMOS feasible with Si pMOS

CMOS Si nMOSSi pMOS

6) Bulk channel buried channel Shifting from surface-channel (planar) to bulk-channel (Fin)

35

4 30-nm Scaling of CAAC-IGZO FET

36

Trench Gate Self-aligned FET

L-direction W-direction

L-direction W-direction

CAAC-OS

Gate Electrode Gate Insulating Film

CAAC-OSDrain

ElectrodeSource

Electrode

Gate Electrode

Gate Insulating Film

48 nm

Gate Electrode

Gate Insulating Film

CAAC-OS34 nm

Source Electrode

Drain Electrode

CAAC-OS

Gate Insulating FilmGate Electrode

19 nm

50 nm

S-ch structure

FETrsquos active layer (CAAC-IGZO OS2 layer) is electrically surrounded by the gate electrodeWe call this FET structure a

surrounded-channel (S-ch) structure

37

Stacked Structure of OS FET and Si FET

pMOSSi

nMOSOS

GND

VDD

A Arsquo

B

Brsquo gate metal

source drain

gate insulator

CAAC-IGZO

electrode

gate

source drain

Si

SiO2

A Arsquo

B

Brsquo

OS FET

Si FET

High integration by stacking the CAAC-OS FET over the Si-FET

Si Substrate Si Substrate

W-directionL-direction

38

Comparison between CAAC-OS FET and Si nMOS FETItem CAAC-OS FET Si nMOS FET

1 Short-channel effect Small or none timesLarge (largest issue in Si NMOS FET)

2 Scaling le 30 nm (Possibility of 5 nm) Possible to ge 5 nm

3 Off-state current yAμm (10minus24 Aμm) times fAμm (10minus15 Aμm)

4 Mobility

Long channel Low High

Short channel Slightly decrease

Decrease (110 in 30-nm device)

5 Temperature characteristics

On-state current

Increase at high temperature

Decrease at high temperature

Off-state current Sufficiently low times

Drastically increase at high temperature

6 Drain breakdown voltage High Low7 Impact ionization Not observed Observed+2 +1 minus1 times minus2

39

Item CAAC-OS FET Si nMOS FET

8 Hot carrier degradation Not observed Large

9 Punch-through Not observed Strongly need balance with scaling

10 Frequency characteristics gt 30 GHz gt 300 GHz

11 Drift velocity Close to Si with channel length about 10 nm

Saturates with channel length about 100 nm

12 Sub-threshold value Small even with thick GI

Need thinner GI by miniaturizing

13 Dielectric anisotropy Observed Not observed

14 S-channel structure(Fin tri-gate type)

Extremely important and effective

Extremely important in shorter channel and effective

+25 minus1+2 +1 minus1 times minus2

Comparison between CAAC-OS FET and Si nMOS FET

40

5 CAAC-IGZO FET for LSI Application

41

Two-terminal circuit(diode)

Potential as Logic Circuit

Dependent control of input and output Need a transistor for four-terminal control Increased F2

Independently controllable inputs and outputs Desirable logic design Sufficiently low Ioff Practically an insulator

Four-terminal circuit

A B

C D

Input Output

42

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

3 Performance of CAAC-IGZO FET

23

IdndashVg characteristics and mobilities of CAAC-IGZO FETs with channel lengths of (a) 2 μm and (b) 6 μm The channel widths are 50 μm

It may be possible to apply all kinds of displays (TV smartphone PC by using OEL LCD)

L = 2 μm (W = 50 μm) L = 6 μm (W = 50 μm)

High-mobility CAAC-IGZO FETs

24

(a) (b)

CAAC-IGZO TrIoff = 1times10minus22 Aμm

(100 yAμm)IonIoff = 1018

IndashV characteristics of CAAC-IGZO and Si transistors

Si TrIoff = 1times10minus12 Aμm

(1 pAμm)IonIoff = 109

Off-state Current of CAAC-IGZO and Si FETsUnit

zA (10minus21)

yA (10minus24)

aA (10minus18)

fA (10minus15)

pA (10minus12)

nA (10minus9)

μA (10minus6)

mA (10minus3)

25

How to Measure Off-state Current60

0 μm

360 μm L = 044 μmW = 10 mm(50 μmtimes200)Tox = 20 nm

A huge transistor with a channel width of 10 mm for off-state leakage current measurement (optical micrograph)

Concept of measurement

Node FN(Vout)

Behavior of potential at node FN (Vout) over time

Measuredtransistor

26

Arrhenius plot of off-state leakage current1)Change of Vout measured over time

1) S Yamazaki et al Jpn J Appl Phys vol 53 pp 04ED18 (2014)

At a gate voltage of minus3 V and 85Cthe off-state leakage current was 6 yAm (1 yA = 10minus24 A)Nonvolatility for 10 years at 85C is ensured

Off-state CurrentUnitAμm

mA (10minus3)μA (10minus6)nA (10minus9)pA (10minus12)fA (10minus15)aA (10minus18)zA (10minus21)yA (10minus24)Le

akag

e cu

rrent

[Aμ

m]

27

-5

0

5

10

15

20

25

30

RF

Gai

n [d

B]

周波数[Hz]109 1010 101130 GHz

Vd = 20 VVg = 20 V( gm max )

WL = 18 μm30 nm

Operation with a cutoff frequency of about 30 GHz is demonstratedThe off-state leakage current of an OS FET (W = 60 nm) is expected at 100 zA or less at 85C even for a 30-nm-node FET

Lower measurement limit

High Cutoff Frequency and Low Off-state Current (30 nm)

28

Frequency [Hz]30 GHz

LW = 30 18000 (60 nmtimes300 Parallel) nm

Short-channel Characteristics of OS FETs

Favorable FET characteristics were obtained with a 11-nm-thick gate insulating film when L = 32 nm

The graphs show that OS FETs are resistant to short-channel effects This is probably because they have a ldquosurrounded-channel (S-ch) structure with a thin active layerrdquo and

are ldquoaccumulation-mode devicesrdquo and ldquoCAAC-IGZO has dielectric anisotropyrdquo(S-ch structure an FET structure where the active layer is electrically surrounded by the gate electrode)

GI = 11 nm

29

0

5

10

15

20

001 01 1 10 100

μ FE

[cm

2middotV-1

middot s-1]

チャネル長 [μm]

理論

Planar TypeS‐ch Type

0

200

400

600

001 01 1 10 100

μ FE

[cm

2 middotV-1

middots-1

]チャネル長 [μm]

理論

Planar Type

Short-channel Characteristics of OS FETs

Channel length dependence of field-effect mobility

(single-crystal Si FET)

Channel length dependence of field-effect mobility

（CAAC‐IGZO FET)

The field-effect mobility (μFE) of a CAAC-IGZO FET with a reduced channel length is close to that of a single-crystal Si FET with the same size

μ FE[

cm2 V

-1s

-1]

Channel length

0

20

5

10

15

10 nm 100 nm 1 μm 100 μm10 μm 10 nm 100 nm 1 μm 100 μm10 μm

Channel length

0

600

200

400

μ FE[

cm2 V

-1s

-1]

Theoretical Theoretical

30

Temperature Dependence of CAAC-IGZO FET

OS-FET

編集中編集中

L=048um GI=20nm

Vth

S値

ID_VG特性

単結晶 p-ch Si Tr （SOI）

L=035um GI=20nm L=035um GI=20nm

編集中 編集中

単結晶 n-ch Si Tr （SOI）

‐05

00

05

10

15

0 50 100 150 200 250

Vth[V]

基板温度 []

0

50

100

150

200

250

300

0 50 100 150 200 250

S‐Value[mVdec]

基板温度 []

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

Vg [V]

250

‐05

0

05

1

15

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

‐15

‐1

‐05

0

05

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

T = minus40C minus 25C 0C 25C 50C 100C 150C 200C 250C

CAAC-OS FETs have a sufficient onoff ratio even at 200C or higherThe S-value shows little change (or is constant) compared with Si FETs

Single‐crystal n‐ch Tr (SOI) Single‐crystal p‐ch Tr (SOI)OS FET

ID‐VGCharac‐teristics

Vth

S‐value

Substrate temperature [C] Substrate temperature [C] Substrate temperature [C]

Substrate temperature [C]Substrate temperature [C]Substrate temperature [C]

31

1E-07

1E-06

1E-05

1E-04

1E-03

1E-02

0 5 10 15 20 25 30V D [V]

ID [A

]Si transistorL =09um T ox=20nm

IGZO transistorL =09um T ox=20nm

4V 26V

L ＝ 09 μm W ＝ 10 μm TOX = 20 nm VG ＝ 2 V

n = 2

CAAC-IGZO transistors have a higher breakdown voltage than Si transistorsNo hot carrier degradation and avalanche breakdown are observed

Breakdown Voltage of CAAC-IGZO and Si FETs

32

Schematic Band Diagram of Channel Regionmdash OS FET vs n-ch Si FET

Inversion Depletion Accumulation

Vg gt 0 V (ON State) Vg lt 0 V (OFF State)Vg = 0V

CAAC-IGZO(S-channel)

n-ch Si

OS2CAAC-IGZO

OS3Gate E

GI GI

Gate E

Gate E

GI

Si

EC

EV

Ef

EfEC

EV

Eg=32eV

Eg=12eV

ElectronsA Arsquo

OS3

Holes

A ArsquoA Arsquo

33

M Murakami et al Proc AM-FPDrsquo12 Digest p 174 (2012)

CAAC-IGZO c-Si

1) Bandgap (Eg) 28ndash32 eV 112 eV

2) Intrinsic carrierconcentration 10minus9 cm3 10+11 cm3

3) Depletion layer km order μm order

4) Electron effective mass (meme)

023ndash025 019 (transverse)098 (longitudinal)

5) Hole effective mass (mhme)

11ndash40 016 (light)049 (heavy)

6) Structure Layered structure(Homologous) Diamond cubic

7) Conductivity i-type n-type n-type p-type

Comparison of Physical Properties between CAAC-IGZO and c-Si

34

Features of CAAC-IGZO as Device

CAAC‐IGZO c‐Si

1) Four-terminal circuitFour-terminal circuit MRAM and FeRAM are two-terminal circuits

2) Almost no short-channel effects Short-channel effects are most troublesome

3) Normally off Uncontrollable Vth high purity and intrinsic

Vth is controllable by channel doping with B

4) IonIoff ratio of 1020 IonIoff le 1010

5) nMOS onlyCMOS feasible with Si pMOS

CMOS Si nMOSSi pMOS

6) Bulk channel buried channel Shifting from surface-channel (planar) to bulk-channel (Fin)

35

4 30-nm Scaling of CAAC-IGZO FET

36

Trench Gate Self-aligned FET

L-direction W-direction

L-direction W-direction

CAAC-OS

Gate Electrode Gate Insulating Film

CAAC-OSDrain

ElectrodeSource

Electrode

Gate Electrode

Gate Insulating Film

48 nm

Gate Electrode

Gate Insulating Film

CAAC-OS34 nm

Source Electrode

Drain Electrode

CAAC-OS

Gate Insulating FilmGate Electrode

19 nm

50 nm

S-ch structure

FETrsquos active layer (CAAC-IGZO OS2 layer) is electrically surrounded by the gate electrodeWe call this FET structure a

surrounded-channel (S-ch) structure

37

Stacked Structure of OS FET and Si FET

pMOSSi

nMOSOS

GND

VDD

A Arsquo

B

Brsquo gate metal

source drain

gate insulator

CAAC-IGZO

electrode

gate

source drain

Si

SiO2

A Arsquo

B

Brsquo

OS FET

Si FET

High integration by stacking the CAAC-OS FET over the Si-FET

Si Substrate Si Substrate

W-directionL-direction

38

Comparison between CAAC-OS FET and Si nMOS FETItem CAAC-OS FET Si nMOS FET

1 Short-channel effect Small or none timesLarge (largest issue in Si NMOS FET)

2 Scaling le 30 nm (Possibility of 5 nm) Possible to ge 5 nm

3 Off-state current yAμm (10minus24 Aμm) times fAμm (10minus15 Aμm)

4 Mobility

Long channel Low High

Short channel Slightly decrease

Decrease (110 in 30-nm device)

5 Temperature characteristics

On-state current

Increase at high temperature

Decrease at high temperature

Off-state current Sufficiently low times

Drastically increase at high temperature

6 Drain breakdown voltage High Low7 Impact ionization Not observed Observed+2 +1 minus1 times minus2

39

Item CAAC-OS FET Si nMOS FET

8 Hot carrier degradation Not observed Large

9 Punch-through Not observed Strongly need balance with scaling

10 Frequency characteristics gt 30 GHz gt 300 GHz

11 Drift velocity Close to Si with channel length about 10 nm

Saturates with channel length about 100 nm

12 Sub-threshold value Small even with thick GI

Need thinner GI by miniaturizing

13 Dielectric anisotropy Observed Not observed

14 S-channel structure(Fin tri-gate type)

Extremely important and effective

Extremely important in shorter channel and effective

+25 minus1+2 +1 minus1 times minus2

Comparison between CAAC-OS FET and Si nMOS FET

40

5 CAAC-IGZO FET for LSI Application

41

Two-terminal circuit(diode)

Potential as Logic Circuit

Dependent control of input and output Need a transistor for four-terminal control Increased F2

Independently controllable inputs and outputs Desirable logic design Sufficiently low Ioff Practically an insulator

Four-terminal circuit

A B

C D

Input Output

42

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

IdndashVg characteristics and mobilities of CAAC-IGZO FETs with channel lengths of (a) 2 μm and (b) 6 μm The channel widths are 50 μm

It may be possible to apply all kinds of displays (TV smartphone PC by using OEL LCD)

L = 2 μm (W = 50 μm) L = 6 μm (W = 50 μm)

High-mobility CAAC-IGZO FETs

24

(a) (b)

CAAC-IGZO TrIoff = 1times10minus22 Aμm

(100 yAμm)IonIoff = 1018

IndashV characteristics of CAAC-IGZO and Si transistors

Si TrIoff = 1times10minus12 Aμm

(1 pAμm)IonIoff = 109

Off-state Current of CAAC-IGZO and Si FETsUnit

zA (10minus21)

yA (10minus24)

aA (10minus18)

fA (10minus15)

pA (10minus12)

nA (10minus9)

μA (10minus6)

mA (10minus3)

25

How to Measure Off-state Current60

0 μm

360 μm L = 044 μmW = 10 mm(50 μmtimes200)Tox = 20 nm

A huge transistor with a channel width of 10 mm for off-state leakage current measurement (optical micrograph)

Concept of measurement

Node FN(Vout)

Behavior of potential at node FN (Vout) over time

Measuredtransistor

26

Arrhenius plot of off-state leakage current1)Change of Vout measured over time

1) S Yamazaki et al Jpn J Appl Phys vol 53 pp 04ED18 (2014)

At a gate voltage of minus3 V and 85Cthe off-state leakage current was 6 yAm (1 yA = 10minus24 A)Nonvolatility for 10 years at 85C is ensured

Off-state CurrentUnitAμm

mA (10minus3)μA (10minus6)nA (10minus9)pA (10minus12)fA (10minus15)aA (10minus18)zA (10minus21)yA (10minus24)Le

akag

e cu

rrent

[Aμ

m]

27

-5

0

5

10

15

20

25

30

RF

Gai

n [d

B]

周波数[Hz]109 1010 101130 GHz

Vd = 20 VVg = 20 V( gm max )

WL = 18 μm30 nm

Operation with a cutoff frequency of about 30 GHz is demonstratedThe off-state leakage current of an OS FET (W = 60 nm) is expected at 100 zA or less at 85C even for a 30-nm-node FET

Lower measurement limit

High Cutoff Frequency and Low Off-state Current (30 nm)

28

Frequency [Hz]30 GHz

LW = 30 18000 (60 nmtimes300 Parallel) nm

Short-channel Characteristics of OS FETs

Favorable FET characteristics were obtained with a 11-nm-thick gate insulating film when L = 32 nm

The graphs show that OS FETs are resistant to short-channel effects This is probably because they have a ldquosurrounded-channel (S-ch) structure with a thin active layerrdquo and

are ldquoaccumulation-mode devicesrdquo and ldquoCAAC-IGZO has dielectric anisotropyrdquo(S-ch structure an FET structure where the active layer is electrically surrounded by the gate electrode)

GI = 11 nm

29

0

5

10

15

20

001 01 1 10 100

μ FE

[cm

2middotV-1

middot s-1]

チャネル長 [μm]

理論

Planar TypeS‐ch Type

0

200

400

600

001 01 1 10 100

μ FE

[cm

2 middotV-1

middots-1

]チャネル長 [μm]

理論

Planar Type

Short-channel Characteristics of OS FETs

Channel length dependence of field-effect mobility

(single-crystal Si FET)

Channel length dependence of field-effect mobility

（CAAC‐IGZO FET)

The field-effect mobility (μFE) of a CAAC-IGZO FET with a reduced channel length is close to that of a single-crystal Si FET with the same size

μ FE[

cm2 V

-1s

-1]

Channel length

0

20

5

10

15

10 nm 100 nm 1 μm 100 μm10 μm 10 nm 100 nm 1 μm 100 μm10 μm

Channel length

0

600

200

400

μ FE[

cm2 V

-1s

-1]

Theoretical Theoretical

30

Temperature Dependence of CAAC-IGZO FET

OS-FET

編集中編集中

L=048um GI=20nm

Vth

S値

ID_VG特性

単結晶 p-ch Si Tr （SOI）

L=035um GI=20nm L=035um GI=20nm

編集中 編集中

単結晶 n-ch Si Tr （SOI）

‐05

00

05

10

15

0 50 100 150 200 250

Vth[V]

基板温度 []

0

50

100

150

200

250

300

0 50 100 150 200 250

S‐Value[mVdec]

基板温度 []

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

Vg [V]

250

‐05

0

05

1

15

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

‐15

‐1

‐05

0

05

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

T = minus40C minus 25C 0C 25C 50C 100C 150C 200C 250C

CAAC-OS FETs have a sufficient onoff ratio even at 200C or higherThe S-value shows little change (or is constant) compared with Si FETs

Single‐crystal n‐ch Tr (SOI) Single‐crystal p‐ch Tr (SOI)OS FET

ID‐VGCharac‐teristics

Vth

S‐value

Substrate temperature [C] Substrate temperature [C] Substrate temperature [C]

Substrate temperature [C]Substrate temperature [C]Substrate temperature [C]

31

1E-07

1E-06

1E-05

1E-04

1E-03

1E-02

0 5 10 15 20 25 30V D [V]

ID [A

]Si transistorL =09um T ox=20nm

IGZO transistorL =09um T ox=20nm

4V 26V

L ＝ 09 μm W ＝ 10 μm TOX = 20 nm VG ＝ 2 V

n = 2

CAAC-IGZO transistors have a higher breakdown voltage than Si transistorsNo hot carrier degradation and avalanche breakdown are observed

Breakdown Voltage of CAAC-IGZO and Si FETs

32

Schematic Band Diagram of Channel Regionmdash OS FET vs n-ch Si FET

Inversion Depletion Accumulation

Vg gt 0 V (ON State) Vg lt 0 V (OFF State)Vg = 0V

CAAC-IGZO(S-channel)

n-ch Si

OS2CAAC-IGZO

OS3Gate E

GI GI

Gate E

Gate E

GI

Si

EC

EV

Ef

EfEC

EV

Eg=32eV

Eg=12eV

ElectronsA Arsquo

OS3

Holes

A ArsquoA Arsquo

33

M Murakami et al Proc AM-FPDrsquo12 Digest p 174 (2012)

CAAC-IGZO c-Si

1) Bandgap (Eg) 28ndash32 eV 112 eV

2) Intrinsic carrierconcentration 10minus9 cm3 10+11 cm3

3) Depletion layer km order μm order

4) Electron effective mass (meme)

023ndash025 019 (transverse)098 (longitudinal)

5) Hole effective mass (mhme)

11ndash40 016 (light)049 (heavy)

6) Structure Layered structure(Homologous) Diamond cubic

7) Conductivity i-type n-type n-type p-type

Comparison of Physical Properties between CAAC-IGZO and c-Si

34

Features of CAAC-IGZO as Device

CAAC‐IGZO c‐Si

1) Four-terminal circuitFour-terminal circuit MRAM and FeRAM are two-terminal circuits

2) Almost no short-channel effects Short-channel effects are most troublesome

3) Normally off Uncontrollable Vth high purity and intrinsic

Vth is controllable by channel doping with B

4) IonIoff ratio of 1020 IonIoff le 1010

5) nMOS onlyCMOS feasible with Si pMOS

CMOS Si nMOSSi pMOS

6) Bulk channel buried channel Shifting from surface-channel (planar) to bulk-channel (Fin)

35

4 30-nm Scaling of CAAC-IGZO FET

36

Trench Gate Self-aligned FET

L-direction W-direction

L-direction W-direction

CAAC-OS

Gate Electrode Gate Insulating Film

CAAC-OSDrain

ElectrodeSource

Electrode

Gate Electrode

Gate Insulating Film

48 nm

Gate Electrode

Gate Insulating Film

CAAC-OS34 nm

Source Electrode

Drain Electrode

CAAC-OS

Gate Insulating FilmGate Electrode

19 nm

50 nm

S-ch structure

FETrsquos active layer (CAAC-IGZO OS2 layer) is electrically surrounded by the gate electrodeWe call this FET structure a

surrounded-channel (S-ch) structure

37

Stacked Structure of OS FET and Si FET

pMOSSi

nMOSOS

GND

VDD

A Arsquo

B

Brsquo gate metal

source drain

gate insulator

CAAC-IGZO

electrode

gate

source drain

Si

SiO2

A Arsquo

B

Brsquo

OS FET

Si FET

High integration by stacking the CAAC-OS FET over the Si-FET

Si Substrate Si Substrate

W-directionL-direction

38

Comparison between CAAC-OS FET and Si nMOS FETItem CAAC-OS FET Si nMOS FET

1 Short-channel effect Small or none timesLarge (largest issue in Si NMOS FET)

2 Scaling le 30 nm (Possibility of 5 nm) Possible to ge 5 nm

3 Off-state current yAμm (10minus24 Aμm) times fAμm (10minus15 Aμm)

4 Mobility

Long channel Low High

Short channel Slightly decrease

Decrease (110 in 30-nm device)

5 Temperature characteristics

On-state current

Increase at high temperature

Decrease at high temperature

Off-state current Sufficiently low times

Drastically increase at high temperature

6 Drain breakdown voltage High Low7 Impact ionization Not observed Observed+2 +1 minus1 times minus2

39

Item CAAC-OS FET Si nMOS FET

8 Hot carrier degradation Not observed Large

9 Punch-through Not observed Strongly need balance with scaling

10 Frequency characteristics gt 30 GHz gt 300 GHz

11 Drift velocity Close to Si with channel length about 10 nm

Saturates with channel length about 100 nm

12 Sub-threshold value Small even with thick GI

Need thinner GI by miniaturizing

13 Dielectric anisotropy Observed Not observed

14 S-channel structure(Fin tri-gate type)

Extremely important and effective

Extremely important in shorter channel and effective

+25 minus1+2 +1 minus1 times minus2

Comparison between CAAC-OS FET and Si nMOS FET

40

5 CAAC-IGZO FET for LSI Application

41

Two-terminal circuit(diode)

Potential as Logic Circuit

Dependent control of input and output Need a transistor for four-terminal control Increased F2

Independently controllable inputs and outputs Desirable logic design Sufficiently low Ioff Practically an insulator

Four-terminal circuit

A B

C D

Input Output

42

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

CAAC-IGZO TrIoff = 1times10minus22 Aμm

(100 yAμm)IonIoff = 1018

IndashV characteristics of CAAC-IGZO and Si transistors

Si TrIoff = 1times10minus12 Aμm

(1 pAμm)IonIoff = 109

Off-state Current of CAAC-IGZO and Si FETsUnit

zA (10minus21)

yA (10minus24)

aA (10minus18)

fA (10minus15)

pA (10minus12)

nA (10minus9)

μA (10minus6)

mA (10minus3)

25

How to Measure Off-state Current60

0 μm

360 μm L = 044 μmW = 10 mm(50 μmtimes200)Tox = 20 nm

A huge transistor with a channel width of 10 mm for off-state leakage current measurement (optical micrograph)

Concept of measurement

Node FN(Vout)

Behavior of potential at node FN (Vout) over time

Measuredtransistor

26

Arrhenius plot of off-state leakage current1)Change of Vout measured over time

1) S Yamazaki et al Jpn J Appl Phys vol 53 pp 04ED18 (2014)

At a gate voltage of minus3 V and 85Cthe off-state leakage current was 6 yAm (1 yA = 10minus24 A)Nonvolatility for 10 years at 85C is ensured

Off-state CurrentUnitAμm

mA (10minus3)μA (10minus6)nA (10minus9)pA (10minus12)fA (10minus15)aA (10minus18)zA (10minus21)yA (10minus24)Le

akag

e cu

rrent

[Aμ

m]

27

-5

0

5

10

15

20

25

30

RF

Gai

n [d

B]

周波数[Hz]109 1010 101130 GHz

Vd = 20 VVg = 20 V( gm max )

WL = 18 μm30 nm

Operation with a cutoff frequency of about 30 GHz is demonstratedThe off-state leakage current of an OS FET (W = 60 nm) is expected at 100 zA or less at 85C even for a 30-nm-node FET

Lower measurement limit

High Cutoff Frequency and Low Off-state Current (30 nm)

28

Frequency [Hz]30 GHz

LW = 30 18000 (60 nmtimes300 Parallel) nm

Short-channel Characteristics of OS FETs

Favorable FET characteristics were obtained with a 11-nm-thick gate insulating film when L = 32 nm

The graphs show that OS FETs are resistant to short-channel effects This is probably because they have a ldquosurrounded-channel (S-ch) structure with a thin active layerrdquo and

are ldquoaccumulation-mode devicesrdquo and ldquoCAAC-IGZO has dielectric anisotropyrdquo(S-ch structure an FET structure where the active layer is electrically surrounded by the gate electrode)

GI = 11 nm

29

0

5

10

15

20

001 01 1 10 100

μ FE

[cm

2middotV-1

middot s-1]

チャネル長 [μm]

理論

Planar TypeS‐ch Type

0

200

400

600

001 01 1 10 100

μ FE

[cm

2 middotV-1

middots-1

]チャネル長 [μm]

理論

Planar Type

Short-channel Characteristics of OS FETs

Channel length dependence of field-effect mobility

(single-crystal Si FET)

Channel length dependence of field-effect mobility

（CAAC‐IGZO FET)

The field-effect mobility (μFE) of a CAAC-IGZO FET with a reduced channel length is close to that of a single-crystal Si FET with the same size

μ FE[

cm2 V

-1s

-1]

Channel length

0

20

5

10

15

10 nm 100 nm 1 μm 100 μm10 μm 10 nm 100 nm 1 μm 100 μm10 μm

Channel length

0

600

200

400

μ FE[

cm2 V

-1s

-1]

Theoretical Theoretical

30

Temperature Dependence of CAAC-IGZO FET

OS-FET

編集中編集中

L=048um GI=20nm

Vth

S値

ID_VG特性

単結晶 p-ch Si Tr （SOI）

L=035um GI=20nm L=035um GI=20nm

編集中 編集中

単結晶 n-ch Si Tr （SOI）

‐05

00

05

10

15

0 50 100 150 200 250

Vth[V]

基板温度 []

0

50

100

150

200

250

300

0 50 100 150 200 250

S‐Value[mVdec]

基板温度 []

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

Vg [V]

250

‐05

0

05

1

15

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

‐15

‐1

‐05

0

05

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

T = minus40C minus 25C 0C 25C 50C 100C 150C 200C 250C

CAAC-OS FETs have a sufficient onoff ratio even at 200C or higherThe S-value shows little change (or is constant) compared with Si FETs

Single‐crystal n‐ch Tr (SOI) Single‐crystal p‐ch Tr (SOI)OS FET

ID‐VGCharac‐teristics

Vth

S‐value

Substrate temperature [C] Substrate temperature [C] Substrate temperature [C]

Substrate temperature [C]Substrate temperature [C]Substrate temperature [C]

31

1E-07

1E-06

1E-05

1E-04

1E-03

1E-02

0 5 10 15 20 25 30V D [V]

ID [A

]Si transistorL =09um T ox=20nm

IGZO transistorL =09um T ox=20nm

4V 26V

L ＝ 09 μm W ＝ 10 μm TOX = 20 nm VG ＝ 2 V

n = 2

CAAC-IGZO transistors have a higher breakdown voltage than Si transistorsNo hot carrier degradation and avalanche breakdown are observed

Breakdown Voltage of CAAC-IGZO and Si FETs

32

Schematic Band Diagram of Channel Regionmdash OS FET vs n-ch Si FET

Inversion Depletion Accumulation

Vg gt 0 V (ON State) Vg lt 0 V (OFF State)Vg = 0V

CAAC-IGZO(S-channel)

n-ch Si

OS2CAAC-IGZO

OS3Gate E

GI GI

Gate E

Gate E

GI

Si

EC

EV

Ef

EfEC

EV

Eg=32eV

Eg=12eV

ElectronsA Arsquo

OS3

Holes

A ArsquoA Arsquo

33

M Murakami et al Proc AM-FPDrsquo12 Digest p 174 (2012)

CAAC-IGZO c-Si

1) Bandgap (Eg) 28ndash32 eV 112 eV

2) Intrinsic carrierconcentration 10minus9 cm3 10+11 cm3

3) Depletion layer km order μm order

4) Electron effective mass (meme)

023ndash025 019 (transverse)098 (longitudinal)

5) Hole effective mass (mhme)

11ndash40 016 (light)049 (heavy)

6) Structure Layered structure(Homologous) Diamond cubic

7) Conductivity i-type n-type n-type p-type

Comparison of Physical Properties between CAAC-IGZO and c-Si

34

Features of CAAC-IGZO as Device

CAAC‐IGZO c‐Si

1) Four-terminal circuitFour-terminal circuit MRAM and FeRAM are two-terminal circuits

2) Almost no short-channel effects Short-channel effects are most troublesome

3) Normally off Uncontrollable Vth high purity and intrinsic

Vth is controllable by channel doping with B

4) IonIoff ratio of 1020 IonIoff le 1010

5) nMOS onlyCMOS feasible with Si pMOS

CMOS Si nMOSSi pMOS

6) Bulk channel buried channel Shifting from surface-channel (planar) to bulk-channel (Fin)

35

4 30-nm Scaling of CAAC-IGZO FET

36

Trench Gate Self-aligned FET

L-direction W-direction

L-direction W-direction

CAAC-OS

Gate Electrode Gate Insulating Film

CAAC-OSDrain

ElectrodeSource

Electrode

Gate Electrode

Gate Insulating Film

48 nm

Gate Electrode

Gate Insulating Film

CAAC-OS34 nm

Source Electrode

Drain Electrode

CAAC-OS

Gate Insulating FilmGate Electrode

19 nm

50 nm

S-ch structure

FETrsquos active layer (CAAC-IGZO OS2 layer) is electrically surrounded by the gate electrodeWe call this FET structure a

surrounded-channel (S-ch) structure

37

Stacked Structure of OS FET and Si FET

pMOSSi

nMOSOS

GND

VDD

A Arsquo

B

Brsquo gate metal

source drain

gate insulator

CAAC-IGZO

electrode

gate

source drain

Si

SiO2

A Arsquo

B

Brsquo

OS FET

Si FET

High integration by stacking the CAAC-OS FET over the Si-FET

Si Substrate Si Substrate

W-directionL-direction

38

Comparison between CAAC-OS FET and Si nMOS FETItem CAAC-OS FET Si nMOS FET

1 Short-channel effect Small or none timesLarge (largest issue in Si NMOS FET)

2 Scaling le 30 nm (Possibility of 5 nm) Possible to ge 5 nm

3 Off-state current yAμm (10minus24 Aμm) times fAμm (10minus15 Aμm)

4 Mobility

Long channel Low High

Short channel Slightly decrease

Decrease (110 in 30-nm device)

5 Temperature characteristics

On-state current

Increase at high temperature

Decrease at high temperature

Off-state current Sufficiently low times

Drastically increase at high temperature

6 Drain breakdown voltage High Low7 Impact ionization Not observed Observed+2 +1 minus1 times minus2

39

Item CAAC-OS FET Si nMOS FET

8 Hot carrier degradation Not observed Large

9 Punch-through Not observed Strongly need balance with scaling

10 Frequency characteristics gt 30 GHz gt 300 GHz

11 Drift velocity Close to Si with channel length about 10 nm

Saturates with channel length about 100 nm

12 Sub-threshold value Small even with thick GI

Need thinner GI by miniaturizing

13 Dielectric anisotropy Observed Not observed

14 S-channel structure(Fin tri-gate type)

Extremely important and effective

Extremely important in shorter channel and effective

+25 minus1+2 +1 minus1 times minus2

Comparison between CAAC-OS FET and Si nMOS FET

40

5 CAAC-IGZO FET for LSI Application

41

Two-terminal circuit(diode)

Potential as Logic Circuit

Dependent control of input and output Need a transistor for four-terminal control Increased F2

Independently controllable inputs and outputs Desirable logic design Sufficiently low Ioff Practically an insulator

Four-terminal circuit

A B

C D

Input Output

42

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

How to Measure Off-state Current60

0 μm

360 μm L = 044 μmW = 10 mm(50 μmtimes200)Tox = 20 nm

A huge transistor with a channel width of 10 mm for off-state leakage current measurement (optical micrograph)

Concept of measurement

Node FN(Vout)

Behavior of potential at node FN (Vout) over time

Measuredtransistor

26

Arrhenius plot of off-state leakage current1)Change of Vout measured over time

1) S Yamazaki et al Jpn J Appl Phys vol 53 pp 04ED18 (2014)

At a gate voltage of minus3 V and 85Cthe off-state leakage current was 6 yAm (1 yA = 10minus24 A)Nonvolatility for 10 years at 85C is ensured

Off-state CurrentUnitAμm

mA (10minus3)μA (10minus6)nA (10minus9)pA (10minus12)fA (10minus15)aA (10minus18)zA (10minus21)yA (10minus24)Le

akag

e cu

rrent

[Aμ

m]

27

-5

0

5

10

15

20

25

30

RF

Gai

n [d

B]

周波数[Hz]109 1010 101130 GHz

Vd = 20 VVg = 20 V( gm max )

WL = 18 μm30 nm

Operation with a cutoff frequency of about 30 GHz is demonstratedThe off-state leakage current of an OS FET (W = 60 nm) is expected at 100 zA or less at 85C even for a 30-nm-node FET

Lower measurement limit

High Cutoff Frequency and Low Off-state Current (30 nm)

28

Frequency [Hz]30 GHz

LW = 30 18000 (60 nmtimes300 Parallel) nm

Short-channel Characteristics of OS FETs

Favorable FET characteristics were obtained with a 11-nm-thick gate insulating film when L = 32 nm

The graphs show that OS FETs are resistant to short-channel effects This is probably because they have a ldquosurrounded-channel (S-ch) structure with a thin active layerrdquo and

are ldquoaccumulation-mode devicesrdquo and ldquoCAAC-IGZO has dielectric anisotropyrdquo(S-ch structure an FET structure where the active layer is electrically surrounded by the gate electrode)

GI = 11 nm

29

0

5

10

15

20

001 01 1 10 100

μ FE

[cm

2middotV-1

middot s-1]

チャネル長 [μm]

理論

Planar TypeS‐ch Type

0

200

400

600

001 01 1 10 100

μ FE

[cm

2 middotV-1

middots-1

]チャネル長 [μm]

理論

Planar Type

Short-channel Characteristics of OS FETs

Channel length dependence of field-effect mobility

(single-crystal Si FET)

Channel length dependence of field-effect mobility

（CAAC‐IGZO FET)

The field-effect mobility (μFE) of a CAAC-IGZO FET with a reduced channel length is close to that of a single-crystal Si FET with the same size

μ FE[

cm2 V

-1s

-1]

Channel length

0

20

5

10

15

10 nm 100 nm 1 μm 100 μm10 μm 10 nm 100 nm 1 μm 100 μm10 μm

Channel length

0

600

200

400

μ FE[

cm2 V

-1s

-1]

Theoretical Theoretical

30

Temperature Dependence of CAAC-IGZO FET

OS-FET

編集中編集中

L=048um GI=20nm

Vth

S値

ID_VG特性

単結晶 p-ch Si Tr （SOI）

L=035um GI=20nm L=035um GI=20nm

編集中 編集中

単結晶 n-ch Si Tr （SOI）

‐05

00

05

10

15

0 50 100 150 200 250

Vth[V]

基板温度 []

0

50

100

150

200

250

300

0 50 100 150 200 250

S‐Value[mVdec]

基板温度 []

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

Vg [V]

250

‐05

0

05

1

15

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

‐15

‐1

‐05

0

05

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

T = minus40C minus 25C 0C 25C 50C 100C 150C 200C 250C

CAAC-OS FETs have a sufficient onoff ratio even at 200C or higherThe S-value shows little change (or is constant) compared with Si FETs

Single‐crystal n‐ch Tr (SOI) Single‐crystal p‐ch Tr (SOI)OS FET

ID‐VGCharac‐teristics

Vth

S‐value

Substrate temperature [C] Substrate temperature [C] Substrate temperature [C]

Substrate temperature [C]Substrate temperature [C]Substrate temperature [C]

31

1E-07

1E-06

1E-05

1E-04

1E-03

1E-02

0 5 10 15 20 25 30V D [V]

ID [A

]Si transistorL =09um T ox=20nm

IGZO transistorL =09um T ox=20nm

4V 26V

L ＝ 09 μm W ＝ 10 μm TOX = 20 nm VG ＝ 2 V

n = 2

CAAC-IGZO transistors have a higher breakdown voltage than Si transistorsNo hot carrier degradation and avalanche breakdown are observed

Breakdown Voltage of CAAC-IGZO and Si FETs

32

Schematic Band Diagram of Channel Regionmdash OS FET vs n-ch Si FET

Inversion Depletion Accumulation

Vg gt 0 V (ON State) Vg lt 0 V (OFF State)Vg = 0V

CAAC-IGZO(S-channel)

n-ch Si

OS2CAAC-IGZO

OS3Gate E

GI GI

Gate E

Gate E

GI

Si

EC

EV

Ef

EfEC

EV

Eg=32eV

Eg=12eV

ElectronsA Arsquo

OS3

Holes

A ArsquoA Arsquo

33

M Murakami et al Proc AM-FPDrsquo12 Digest p 174 (2012)

CAAC-IGZO c-Si

1) Bandgap (Eg) 28ndash32 eV 112 eV

2) Intrinsic carrierconcentration 10minus9 cm3 10+11 cm3

3) Depletion layer km order μm order

4) Electron effective mass (meme)

023ndash025 019 (transverse)098 (longitudinal)

5) Hole effective mass (mhme)

11ndash40 016 (light)049 (heavy)

6) Structure Layered structure(Homologous) Diamond cubic

7) Conductivity i-type n-type n-type p-type

Comparison of Physical Properties between CAAC-IGZO and c-Si

34

Features of CAAC-IGZO as Device

CAAC‐IGZO c‐Si

1) Four-terminal circuitFour-terminal circuit MRAM and FeRAM are two-terminal circuits

2) Almost no short-channel effects Short-channel effects are most troublesome

3) Normally off Uncontrollable Vth high purity and intrinsic

Vth is controllable by channel doping with B

4) IonIoff ratio of 1020 IonIoff le 1010

5) nMOS onlyCMOS feasible with Si pMOS

CMOS Si nMOSSi pMOS

6) Bulk channel buried channel Shifting from surface-channel (planar) to bulk-channel (Fin)

35

4 30-nm Scaling of CAAC-IGZO FET

36

Trench Gate Self-aligned FET

L-direction W-direction

L-direction W-direction

CAAC-OS

Gate Electrode Gate Insulating Film

CAAC-OSDrain

ElectrodeSource

Electrode

Gate Electrode

Gate Insulating Film

48 nm

Gate Electrode

Gate Insulating Film

CAAC-OS34 nm

Source Electrode

Drain Electrode

CAAC-OS

Gate Insulating FilmGate Electrode

19 nm

50 nm

S-ch structure

FETrsquos active layer (CAAC-IGZO OS2 layer) is electrically surrounded by the gate electrodeWe call this FET structure a

surrounded-channel (S-ch) structure

37

Stacked Structure of OS FET and Si FET

pMOSSi

nMOSOS

GND

VDD

A Arsquo

B

Brsquo gate metal

source drain

gate insulator

CAAC-IGZO

electrode

gate

source drain

Si

SiO2

A Arsquo

B

Brsquo

OS FET

Si FET

High integration by stacking the CAAC-OS FET over the Si-FET

Si Substrate Si Substrate

W-directionL-direction

38

Comparison between CAAC-OS FET and Si nMOS FETItem CAAC-OS FET Si nMOS FET

1 Short-channel effect Small or none timesLarge (largest issue in Si NMOS FET)

2 Scaling le 30 nm (Possibility of 5 nm) Possible to ge 5 nm

3 Off-state current yAμm (10minus24 Aμm) times fAμm (10minus15 Aμm)

4 Mobility

Long channel Low High

Short channel Slightly decrease

Decrease (110 in 30-nm device)

5 Temperature characteristics

On-state current

Increase at high temperature

Decrease at high temperature

Off-state current Sufficiently low times

Drastically increase at high temperature

6 Drain breakdown voltage High Low7 Impact ionization Not observed Observed+2 +1 minus1 times minus2

39

Item CAAC-OS FET Si nMOS FET

8 Hot carrier degradation Not observed Large

9 Punch-through Not observed Strongly need balance with scaling

10 Frequency characteristics gt 30 GHz gt 300 GHz

11 Drift velocity Close to Si with channel length about 10 nm

Saturates with channel length about 100 nm

12 Sub-threshold value Small even with thick GI

Need thinner GI by miniaturizing

13 Dielectric anisotropy Observed Not observed

14 S-channel structure(Fin tri-gate type)

Extremely important and effective

Extremely important in shorter channel and effective

+25 minus1+2 +1 minus1 times minus2

Comparison between CAAC-OS FET and Si nMOS FET

40

5 CAAC-IGZO FET for LSI Application

41

Two-terminal circuit(diode)

Potential as Logic Circuit

Dependent control of input and output Need a transistor for four-terminal control Increased F2

Independently controllable inputs and outputs Desirable logic design Sufficiently low Ioff Practically an insulator

Four-terminal circuit

A B

C D

Input Output

42

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

Arrhenius plot of off-state leakage current1)Change of Vout measured over time

1) S Yamazaki et al Jpn J Appl Phys vol 53 pp 04ED18 (2014)

At a gate voltage of minus3 V and 85Cthe off-state leakage current was 6 yAm (1 yA = 10minus24 A)Nonvolatility for 10 years at 85C is ensured

Off-state CurrentUnitAμm

mA (10minus3)μA (10minus6)nA (10minus9)pA (10minus12)fA (10minus15)aA (10minus18)zA (10minus21)yA (10minus24)Le

akag

e cu

rrent

[Aμ

m]

27

-5

0

5

10

15

20

25

30

RF

Gai

n [d

B]

周波数[Hz]109 1010 101130 GHz

Vd = 20 VVg = 20 V( gm max )

WL = 18 μm30 nm

Operation with a cutoff frequency of about 30 GHz is demonstratedThe off-state leakage current of an OS FET (W = 60 nm) is expected at 100 zA or less at 85C even for a 30-nm-node FET

Lower measurement limit

High Cutoff Frequency and Low Off-state Current (30 nm)

28

Frequency [Hz]30 GHz

LW = 30 18000 (60 nmtimes300 Parallel) nm

Short-channel Characteristics of OS FETs

Favorable FET characteristics were obtained with a 11-nm-thick gate insulating film when L = 32 nm

The graphs show that OS FETs are resistant to short-channel effects This is probably because they have a ldquosurrounded-channel (S-ch) structure with a thin active layerrdquo and

are ldquoaccumulation-mode devicesrdquo and ldquoCAAC-IGZO has dielectric anisotropyrdquo(S-ch structure an FET structure where the active layer is electrically surrounded by the gate electrode)

GI = 11 nm

29

0

5

10

15

20

001 01 1 10 100

μ FE

[cm

2middotV-1

middot s-1]

チャネル長 [μm]

理論

Planar TypeS‐ch Type

0

200

400

600

001 01 1 10 100

μ FE

[cm

2 middotV-1

middots-1

]チャネル長 [μm]

理論

Planar Type

Short-channel Characteristics of OS FETs

Channel length dependence of field-effect mobility

(single-crystal Si FET)

Channel length dependence of field-effect mobility

（CAAC‐IGZO FET)

The field-effect mobility (μFE) of a CAAC-IGZO FET with a reduced channel length is close to that of a single-crystal Si FET with the same size

μ FE[

cm2 V

-1s

-1]

Channel length

0

20

5

10

15

10 nm 100 nm 1 μm 100 μm10 μm 10 nm 100 nm 1 μm 100 μm10 μm

Channel length

0

600

200

400

μ FE[

cm2 V

-1s

-1]

Theoretical Theoretical

30

Temperature Dependence of CAAC-IGZO FET

OS-FET

編集中編集中

L=048um GI=20nm

Vth

S値

ID_VG特性

単結晶 p-ch Si Tr （SOI）

L=035um GI=20nm L=035um GI=20nm

編集中 編集中

単結晶 n-ch Si Tr （SOI）

‐05

00

05

10

15

0 50 100 150 200 250

Vth[V]

基板温度 []

0

50

100

150

200

250

300

0 50 100 150 200 250

S‐Value[mVdec]

基板温度 []

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

Vg [V]

250

‐05

0

05

1

15

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

‐15

‐1

‐05

0

05

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

T = minus40C minus 25C 0C 25C 50C 100C 150C 200C 250C

CAAC-OS FETs have a sufficient onoff ratio even at 200C or higherThe S-value shows little change (or is constant) compared with Si FETs

Single‐crystal n‐ch Tr (SOI) Single‐crystal p‐ch Tr (SOI)OS FET

ID‐VGCharac‐teristics

Vth

S‐value

Substrate temperature [C] Substrate temperature [C] Substrate temperature [C]

Substrate temperature [C]Substrate temperature [C]Substrate temperature [C]

31

1E-07

1E-06

1E-05

1E-04

1E-03

1E-02

0 5 10 15 20 25 30V D [V]

ID [A

]Si transistorL =09um T ox=20nm

IGZO transistorL =09um T ox=20nm

4V 26V

L ＝ 09 μm W ＝ 10 μm TOX = 20 nm VG ＝ 2 V

n = 2

CAAC-IGZO transistors have a higher breakdown voltage than Si transistorsNo hot carrier degradation and avalanche breakdown are observed

Breakdown Voltage of CAAC-IGZO and Si FETs

32

Schematic Band Diagram of Channel Regionmdash OS FET vs n-ch Si FET

Inversion Depletion Accumulation

Vg gt 0 V (ON State) Vg lt 0 V (OFF State)Vg = 0V

CAAC-IGZO(S-channel)

n-ch Si

OS2CAAC-IGZO

OS3Gate E

GI GI

Gate E

Gate E

GI

Si

EC

EV

Ef

EfEC

EV

Eg=32eV

Eg=12eV

ElectronsA Arsquo

OS3

Holes

A ArsquoA Arsquo

33

M Murakami et al Proc AM-FPDrsquo12 Digest p 174 (2012)

CAAC-IGZO c-Si

1) Bandgap (Eg) 28ndash32 eV 112 eV

2) Intrinsic carrierconcentration 10minus9 cm3 10+11 cm3

3) Depletion layer km order μm order

4) Electron effective mass (meme)

023ndash025 019 (transverse)098 (longitudinal)

5) Hole effective mass (mhme)

11ndash40 016 (light)049 (heavy)

6) Structure Layered structure(Homologous) Diamond cubic

7) Conductivity i-type n-type n-type p-type

Comparison of Physical Properties between CAAC-IGZO and c-Si

34

Features of CAAC-IGZO as Device

CAAC‐IGZO c‐Si

1) Four-terminal circuitFour-terminal circuit MRAM and FeRAM are two-terminal circuits

2) Almost no short-channel effects Short-channel effects are most troublesome

3) Normally off Uncontrollable Vth high purity and intrinsic

Vth is controllable by channel doping with B

4) IonIoff ratio of 1020 IonIoff le 1010

5) nMOS onlyCMOS feasible with Si pMOS

CMOS Si nMOSSi pMOS

6) Bulk channel buried channel Shifting from surface-channel (planar) to bulk-channel (Fin)

35

4 30-nm Scaling of CAAC-IGZO FET

36

Trench Gate Self-aligned FET

L-direction W-direction

L-direction W-direction

CAAC-OS

Gate Electrode Gate Insulating Film

CAAC-OSDrain

ElectrodeSource

Electrode

Gate Electrode

Gate Insulating Film

48 nm

Gate Electrode

Gate Insulating Film

CAAC-OS34 nm

Source Electrode

Drain Electrode

CAAC-OS

Gate Insulating FilmGate Electrode

19 nm

50 nm

S-ch structure

FETrsquos active layer (CAAC-IGZO OS2 layer) is electrically surrounded by the gate electrodeWe call this FET structure a

surrounded-channel (S-ch) structure

37

Stacked Structure of OS FET and Si FET

pMOSSi

nMOSOS

GND

VDD

A Arsquo

B

Brsquo gate metal

source drain

gate insulator

CAAC-IGZO

electrode

gate

source drain

Si

SiO2

A Arsquo

B

Brsquo

OS FET

Si FET

High integration by stacking the CAAC-OS FET over the Si-FET

Si Substrate Si Substrate

W-directionL-direction

38

Comparison between CAAC-OS FET and Si nMOS FETItem CAAC-OS FET Si nMOS FET

1 Short-channel effect Small or none timesLarge (largest issue in Si NMOS FET)

2 Scaling le 30 nm (Possibility of 5 nm) Possible to ge 5 nm

3 Off-state current yAμm (10minus24 Aμm) times fAμm (10minus15 Aμm)

4 Mobility

Long channel Low High

Short channel Slightly decrease

Decrease (110 in 30-nm device)

5 Temperature characteristics

On-state current

Increase at high temperature

Decrease at high temperature

Off-state current Sufficiently low times

Drastically increase at high temperature

6 Drain breakdown voltage High Low7 Impact ionization Not observed Observed+2 +1 minus1 times minus2

39

Item CAAC-OS FET Si nMOS FET

8 Hot carrier degradation Not observed Large

9 Punch-through Not observed Strongly need balance with scaling

10 Frequency characteristics gt 30 GHz gt 300 GHz

11 Drift velocity Close to Si with channel length about 10 nm

Saturates with channel length about 100 nm

12 Sub-threshold value Small even with thick GI

Need thinner GI by miniaturizing

13 Dielectric anisotropy Observed Not observed

14 S-channel structure(Fin tri-gate type)

Extremely important and effective

Extremely important in shorter channel and effective

+25 minus1+2 +1 minus1 times minus2

Comparison between CAAC-OS FET and Si nMOS FET

40

5 CAAC-IGZO FET for LSI Application

41

Two-terminal circuit(diode)

Potential as Logic Circuit

Dependent control of input and output Need a transistor for four-terminal control Increased F2

Independently controllable inputs and outputs Desirable logic design Sufficiently low Ioff Practically an insulator

Four-terminal circuit

A B

C D

Input Output

42

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

-5

0

5

10

15

20

25

30

RF

Gai

n [d

B]

周波数[Hz]109 1010 101130 GHz

Vd = 20 VVg = 20 V( gm max )

WL = 18 μm30 nm

Operation with a cutoff frequency of about 30 GHz is demonstratedThe off-state leakage current of an OS FET (W = 60 nm) is expected at 100 zA or less at 85C even for a 30-nm-node FET

Lower measurement limit

High Cutoff Frequency and Low Off-state Current (30 nm)

28

Frequency [Hz]30 GHz

LW = 30 18000 (60 nmtimes300 Parallel) nm

Short-channel Characteristics of OS FETs

Favorable FET characteristics were obtained with a 11-nm-thick gate insulating film when L = 32 nm

The graphs show that OS FETs are resistant to short-channel effects This is probably because they have a ldquosurrounded-channel (S-ch) structure with a thin active layerrdquo and

are ldquoaccumulation-mode devicesrdquo and ldquoCAAC-IGZO has dielectric anisotropyrdquo(S-ch structure an FET structure where the active layer is electrically surrounded by the gate electrode)

GI = 11 nm

29

0

5

10

15

20

001 01 1 10 100

μ FE

[cm

2middotV-1

middot s-1]

チャネル長 [μm]

理論

Planar TypeS‐ch Type

0

200

400

600

001 01 1 10 100

μ FE

[cm

2 middotV-1

middots-1

]チャネル長 [μm]

理論

Planar Type

Short-channel Characteristics of OS FETs

Channel length dependence of field-effect mobility

(single-crystal Si FET)

Channel length dependence of field-effect mobility

（CAAC‐IGZO FET)

The field-effect mobility (μFE) of a CAAC-IGZO FET with a reduced channel length is close to that of a single-crystal Si FET with the same size

μ FE[

cm2 V

-1s

-1]

Channel length

0

20

5

10

15

10 nm 100 nm 1 μm 100 μm10 μm 10 nm 100 nm 1 μm 100 μm10 μm

Channel length

0

600

200

400

μ FE[

cm2 V

-1s

-1]

Theoretical Theoretical

30

Temperature Dependence of CAAC-IGZO FET

OS-FET

編集中編集中

L=048um GI=20nm

Vth

S値

ID_VG特性

単結晶 p-ch Si Tr （SOI）

L=035um GI=20nm L=035um GI=20nm

編集中 編集中

単結晶 n-ch Si Tr （SOI）

‐05

00

05

10

15

0 50 100 150 200 250

Vth[V]

基板温度 []

0

50

100

150

200

250

300

0 50 100 150 200 250

S‐Value[mVdec]

基板温度 []

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

Vg [V]

250

‐05

0

05

1

15

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

‐15

‐1

‐05

0

05

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

T = minus40C minus 25C 0C 25C 50C 100C 150C 200C 250C

CAAC-OS FETs have a sufficient onoff ratio even at 200C or higherThe S-value shows little change (or is constant) compared with Si FETs

Single‐crystal n‐ch Tr (SOI) Single‐crystal p‐ch Tr (SOI)OS FET

ID‐VGCharac‐teristics

Vth

S‐value

Substrate temperature [C] Substrate temperature [C] Substrate temperature [C]

Substrate temperature [C]Substrate temperature [C]Substrate temperature [C]

31

1E-07

1E-06

1E-05

1E-04

1E-03

1E-02

0 5 10 15 20 25 30V D [V]

ID [A

]Si transistorL =09um T ox=20nm

IGZO transistorL =09um T ox=20nm

4V 26V

L ＝ 09 μm W ＝ 10 μm TOX = 20 nm VG ＝ 2 V

n = 2

CAAC-IGZO transistors have a higher breakdown voltage than Si transistorsNo hot carrier degradation and avalanche breakdown are observed

Breakdown Voltage of CAAC-IGZO and Si FETs

32

Schematic Band Diagram of Channel Regionmdash OS FET vs n-ch Si FET

Inversion Depletion Accumulation

Vg gt 0 V (ON State) Vg lt 0 V (OFF State)Vg = 0V

CAAC-IGZO(S-channel)

n-ch Si

OS2CAAC-IGZO

OS3Gate E

GI GI

Gate E

Gate E

GI

Si

EC

EV

Ef

EfEC

EV

Eg=32eV

Eg=12eV

ElectronsA Arsquo

OS3

Holes

A ArsquoA Arsquo

33

M Murakami et al Proc AM-FPDrsquo12 Digest p 174 (2012)

CAAC-IGZO c-Si

1) Bandgap (Eg) 28ndash32 eV 112 eV

2) Intrinsic carrierconcentration 10minus9 cm3 10+11 cm3

3) Depletion layer km order μm order

4) Electron effective mass (meme)

023ndash025 019 (transverse)098 (longitudinal)

5) Hole effective mass (mhme)

11ndash40 016 (light)049 (heavy)

6) Structure Layered structure(Homologous) Diamond cubic

7) Conductivity i-type n-type n-type p-type

Comparison of Physical Properties between CAAC-IGZO and c-Si

34

Features of CAAC-IGZO as Device

CAAC‐IGZO c‐Si

1) Four-terminal circuitFour-terminal circuit MRAM and FeRAM are two-terminal circuits

2) Almost no short-channel effects Short-channel effects are most troublesome

3) Normally off Uncontrollable Vth high purity and intrinsic

Vth is controllable by channel doping with B

4) IonIoff ratio of 1020 IonIoff le 1010

5) nMOS onlyCMOS feasible with Si pMOS

CMOS Si nMOSSi pMOS

6) Bulk channel buried channel Shifting from surface-channel (planar) to bulk-channel (Fin)

35

4 30-nm Scaling of CAAC-IGZO FET

36

Trench Gate Self-aligned FET

L-direction W-direction

L-direction W-direction

CAAC-OS

Gate Electrode Gate Insulating Film

CAAC-OSDrain

ElectrodeSource

Electrode

Gate Electrode

Gate Insulating Film

48 nm

Gate Electrode

Gate Insulating Film

CAAC-OS34 nm

Source Electrode

Drain Electrode

CAAC-OS

Gate Insulating FilmGate Electrode

19 nm

50 nm

S-ch structure

FETrsquos active layer (CAAC-IGZO OS2 layer) is electrically surrounded by the gate electrodeWe call this FET structure a

surrounded-channel (S-ch) structure

37

Stacked Structure of OS FET and Si FET

pMOSSi

nMOSOS

GND

VDD

A Arsquo

B

Brsquo gate metal

source drain

gate insulator

CAAC-IGZO

electrode

gate

source drain

Si

SiO2

A Arsquo

B

Brsquo

OS FET

Si FET

High integration by stacking the CAAC-OS FET over the Si-FET

Si Substrate Si Substrate

W-directionL-direction

38

Comparison between CAAC-OS FET and Si nMOS FETItem CAAC-OS FET Si nMOS FET

1 Short-channel effect Small or none timesLarge (largest issue in Si NMOS FET)

2 Scaling le 30 nm (Possibility of 5 nm) Possible to ge 5 nm

3 Off-state current yAμm (10minus24 Aμm) times fAμm (10minus15 Aμm)

4 Mobility

Long channel Low High

Short channel Slightly decrease

Decrease (110 in 30-nm device)

5 Temperature characteristics

On-state current

Increase at high temperature

Decrease at high temperature

Off-state current Sufficiently low times

Drastically increase at high temperature

6 Drain breakdown voltage High Low7 Impact ionization Not observed Observed+2 +1 minus1 times minus2

39

Item CAAC-OS FET Si nMOS FET

8 Hot carrier degradation Not observed Large

9 Punch-through Not observed Strongly need balance with scaling

10 Frequency characteristics gt 30 GHz gt 300 GHz

11 Drift velocity Close to Si with channel length about 10 nm

Saturates with channel length about 100 nm

12 Sub-threshold value Small even with thick GI

Need thinner GI by miniaturizing

13 Dielectric anisotropy Observed Not observed

14 S-channel structure(Fin tri-gate type)

Extremely important and effective

Extremely important in shorter channel and effective

+25 minus1+2 +1 minus1 times minus2

Comparison between CAAC-OS FET and Si nMOS FET

40

5 CAAC-IGZO FET for LSI Application

41

Two-terminal circuit(diode)

Potential as Logic Circuit

Dependent control of input and output Need a transistor for four-terminal control Increased F2

Independently controllable inputs and outputs Desirable logic design Sufficiently low Ioff Practically an insulator

Four-terminal circuit

A B

C D

Input Output

42

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

Short-channel Characteristics of OS FETs

Favorable FET characteristics were obtained with a 11-nm-thick gate insulating film when L = 32 nm

The graphs show that OS FETs are resistant to short-channel effects This is probably because they have a ldquosurrounded-channel (S-ch) structure with a thin active layerrdquo and

are ldquoaccumulation-mode devicesrdquo and ldquoCAAC-IGZO has dielectric anisotropyrdquo(S-ch structure an FET structure where the active layer is electrically surrounded by the gate electrode)

GI = 11 nm

29

0

5

10

15

20

001 01 1 10 100

μ FE

[cm

2middotV-1

middot s-1]

チャネル長 [μm]

理論

Planar TypeS‐ch Type

0

200

400

600

001 01 1 10 100

μ FE

[cm

2 middotV-1

middots-1

]チャネル長 [μm]

理論

Planar Type

Short-channel Characteristics of OS FETs

Channel length dependence of field-effect mobility

(single-crystal Si FET)

Channel length dependence of field-effect mobility

（CAAC‐IGZO FET)

The field-effect mobility (μFE) of a CAAC-IGZO FET with a reduced channel length is close to that of a single-crystal Si FET with the same size

μ FE[

cm2 V

-1s

-1]

Channel length

0

20

5

10

15

10 nm 100 nm 1 μm 100 μm10 μm 10 nm 100 nm 1 μm 100 μm10 μm

Channel length

0

600

200

400

μ FE[

cm2 V

-1s

-1]

Theoretical Theoretical

30

Temperature Dependence of CAAC-IGZO FET

OS-FET

編集中編集中

L=048um GI=20nm

Vth

S値

ID_VG特性

単結晶 p-ch Si Tr （SOI）

L=035um GI=20nm L=035um GI=20nm

編集中 編集中

単結晶 n-ch Si Tr （SOI）

‐05

00

05

10

15

0 50 100 150 200 250

Vth[V]

基板温度 []

0

50

100

150

200

250

300

0 50 100 150 200 250

S‐Value[mVdec]

基板温度 []

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

Vg [V]

250

‐05

0

05

1

15

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

‐15

‐1

‐05

0

05

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

T = minus40C minus 25C 0C 25C 50C 100C 150C 200C 250C

CAAC-OS FETs have a sufficient onoff ratio even at 200C or higherThe S-value shows little change (or is constant) compared with Si FETs

Single‐crystal n‐ch Tr (SOI) Single‐crystal p‐ch Tr (SOI)OS FET

ID‐VGCharac‐teristics

Vth

S‐value

Substrate temperature [C] Substrate temperature [C] Substrate temperature [C]

Substrate temperature [C]Substrate temperature [C]Substrate temperature [C]

31

1E-07

1E-06

1E-05

1E-04

1E-03

1E-02

0 5 10 15 20 25 30V D [V]

ID [A

]Si transistorL =09um T ox=20nm

IGZO transistorL =09um T ox=20nm

4V 26V

L ＝ 09 μm W ＝ 10 μm TOX = 20 nm VG ＝ 2 V

n = 2

CAAC-IGZO transistors have a higher breakdown voltage than Si transistorsNo hot carrier degradation and avalanche breakdown are observed

Breakdown Voltage of CAAC-IGZO and Si FETs

32

Schematic Band Diagram of Channel Regionmdash OS FET vs n-ch Si FET

Inversion Depletion Accumulation

Vg gt 0 V (ON State) Vg lt 0 V (OFF State)Vg = 0V

CAAC-IGZO(S-channel)

n-ch Si

OS2CAAC-IGZO

OS3Gate E

GI GI

Gate E

Gate E

GI

Si

EC

EV

Ef

EfEC

EV

Eg=32eV

Eg=12eV

ElectronsA Arsquo

OS3

Holes

A ArsquoA Arsquo

33

M Murakami et al Proc AM-FPDrsquo12 Digest p 174 (2012)

CAAC-IGZO c-Si

1) Bandgap (Eg) 28ndash32 eV 112 eV

2) Intrinsic carrierconcentration 10minus9 cm3 10+11 cm3

3) Depletion layer km order μm order

4) Electron effective mass (meme)

023ndash025 019 (transverse)098 (longitudinal)

5) Hole effective mass (mhme)

11ndash40 016 (light)049 (heavy)

6) Structure Layered structure(Homologous) Diamond cubic

7) Conductivity i-type n-type n-type p-type

Comparison of Physical Properties between CAAC-IGZO and c-Si

34

Features of CAAC-IGZO as Device

CAAC‐IGZO c‐Si

1) Four-terminal circuitFour-terminal circuit MRAM and FeRAM are two-terminal circuits

2) Almost no short-channel effects Short-channel effects are most troublesome

3) Normally off Uncontrollable Vth high purity and intrinsic

Vth is controllable by channel doping with B

4) IonIoff ratio of 1020 IonIoff le 1010

5) nMOS onlyCMOS feasible with Si pMOS

CMOS Si nMOSSi pMOS

6) Bulk channel buried channel Shifting from surface-channel (planar) to bulk-channel (Fin)

35

4 30-nm Scaling of CAAC-IGZO FET

36

Trench Gate Self-aligned FET

L-direction W-direction

L-direction W-direction

CAAC-OS

Gate Electrode Gate Insulating Film

CAAC-OSDrain

ElectrodeSource

Electrode

Gate Electrode

Gate Insulating Film

48 nm

Gate Electrode

Gate Insulating Film

CAAC-OS34 nm

Source Electrode

Drain Electrode

CAAC-OS

Gate Insulating FilmGate Electrode

19 nm

50 nm

S-ch structure

FETrsquos active layer (CAAC-IGZO OS2 layer) is electrically surrounded by the gate electrodeWe call this FET structure a

surrounded-channel (S-ch) structure

37

Stacked Structure of OS FET and Si FET

pMOSSi

nMOSOS

GND

VDD

A Arsquo

B

Brsquo gate metal

source drain

gate insulator

CAAC-IGZO

electrode

gate

source drain

Si

SiO2

A Arsquo

B

Brsquo

OS FET

Si FET

High integration by stacking the CAAC-OS FET over the Si-FET

Si Substrate Si Substrate

W-directionL-direction

38

Comparison between CAAC-OS FET and Si nMOS FETItem CAAC-OS FET Si nMOS FET

1 Short-channel effect Small or none timesLarge (largest issue in Si NMOS FET)

2 Scaling le 30 nm (Possibility of 5 nm) Possible to ge 5 nm

3 Off-state current yAμm (10minus24 Aμm) times fAμm (10minus15 Aμm)

4 Mobility

Long channel Low High

Short channel Slightly decrease

Decrease (110 in 30-nm device)

5 Temperature characteristics

On-state current

Increase at high temperature

Decrease at high temperature

Off-state current Sufficiently low times

Drastically increase at high temperature

6 Drain breakdown voltage High Low7 Impact ionization Not observed Observed+2 +1 minus1 times minus2

39

Item CAAC-OS FET Si nMOS FET

8 Hot carrier degradation Not observed Large

9 Punch-through Not observed Strongly need balance with scaling

10 Frequency characteristics gt 30 GHz gt 300 GHz

11 Drift velocity Close to Si with channel length about 10 nm

Saturates with channel length about 100 nm

12 Sub-threshold value Small even with thick GI

Need thinner GI by miniaturizing

13 Dielectric anisotropy Observed Not observed

14 S-channel structure(Fin tri-gate type)

Extremely important and effective

Extremely important in shorter channel and effective

+25 minus1+2 +1 minus1 times minus2

Comparison between CAAC-OS FET and Si nMOS FET

40

5 CAAC-IGZO FET for LSI Application

41

Two-terminal circuit(diode)

Potential as Logic Circuit

Dependent control of input and output Need a transistor for four-terminal control Increased F2

Independently controllable inputs and outputs Desirable logic design Sufficiently low Ioff Practically an insulator

Four-terminal circuit

A B

C D

Input Output

42

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

0

5

10

15

20

001 01 1 10 100

μ FE

[cm

2middotV-1

middot s-1]

チャネル長 [μm]

理論

Planar TypeS‐ch Type

0

200

400

600

001 01 1 10 100

μ FE

[cm

2 middotV-1

middots-1

]チャネル長 [μm]

理論

Planar Type

Short-channel Characteristics of OS FETs

Channel length dependence of field-effect mobility

(single-crystal Si FET)

Channel length dependence of field-effect mobility

（CAAC‐IGZO FET)

The field-effect mobility (μFE) of a CAAC-IGZO FET with a reduced channel length is close to that of a single-crystal Si FET with the same size

μ FE[

cm2 V

-1s

-1]

Channel length

0

20

5

10

15

10 nm 100 nm 1 μm 100 μm10 μm 10 nm 100 nm 1 μm 100 μm10 μm

Channel length

0

600

200

400

μ FE[

cm2 V

-1s

-1]

Theoretical Theoretical

30

Temperature Dependence of CAAC-IGZO FET

OS-FET

編集中編集中

L=048um GI=20nm

Vth

S値

ID_VG特性

単結晶 p-ch Si Tr （SOI）

L=035um GI=20nm L=035um GI=20nm

編集中 編集中

単結晶 n-ch Si Tr （SOI）

‐05

00

05

10

15

0 50 100 150 200 250

Vth[V]

基板温度 []

0

50

100

150

200

250

300

0 50 100 150 200 250

S‐Value[mVdec]

基板温度 []

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

Vg [V]

250

‐05

0

05

1

15

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

‐15

‐1

‐05

0

05

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

T = minus40C minus 25C 0C 25C 50C 100C 150C 200C 250C

CAAC-OS FETs have a sufficient onoff ratio even at 200C or higherThe S-value shows little change (or is constant) compared with Si FETs

Single‐crystal n‐ch Tr (SOI) Single‐crystal p‐ch Tr (SOI)OS FET

ID‐VGCharac‐teristics

Vth

S‐value

Substrate temperature [C] Substrate temperature [C] Substrate temperature [C]

Substrate temperature [C]Substrate temperature [C]Substrate temperature [C]

31

1E-07

1E-06

1E-05

1E-04

1E-03

1E-02

0 5 10 15 20 25 30V D [V]

ID [A

]Si transistorL =09um T ox=20nm

IGZO transistorL =09um T ox=20nm

4V 26V

L ＝ 09 μm W ＝ 10 μm TOX = 20 nm VG ＝ 2 V

n = 2

CAAC-IGZO transistors have a higher breakdown voltage than Si transistorsNo hot carrier degradation and avalanche breakdown are observed

Breakdown Voltage of CAAC-IGZO and Si FETs

32

Schematic Band Diagram of Channel Regionmdash OS FET vs n-ch Si FET

Inversion Depletion Accumulation

Vg gt 0 V (ON State) Vg lt 0 V (OFF State)Vg = 0V

CAAC-IGZO(S-channel)

n-ch Si

OS2CAAC-IGZO

OS3Gate E

GI GI

Gate E

Gate E

GI

Si

EC

EV

Ef

EfEC

EV

Eg=32eV

Eg=12eV

ElectronsA Arsquo

OS3

Holes

A ArsquoA Arsquo

33

M Murakami et al Proc AM-FPDrsquo12 Digest p 174 (2012)

CAAC-IGZO c-Si

1) Bandgap (Eg) 28ndash32 eV 112 eV

2) Intrinsic carrierconcentration 10minus9 cm3 10+11 cm3

3) Depletion layer km order μm order

4) Electron effective mass (meme)

023ndash025 019 (transverse)098 (longitudinal)

5) Hole effective mass (mhme)

11ndash40 016 (light)049 (heavy)

6) Structure Layered structure(Homologous) Diamond cubic

7) Conductivity i-type n-type n-type p-type

Comparison of Physical Properties between CAAC-IGZO and c-Si

34

Features of CAAC-IGZO as Device

CAAC‐IGZO c‐Si

1) Four-terminal circuitFour-terminal circuit MRAM and FeRAM are two-terminal circuits

2) Almost no short-channel effects Short-channel effects are most troublesome

3) Normally off Uncontrollable Vth high purity and intrinsic

Vth is controllable by channel doping with B

4) IonIoff ratio of 1020 IonIoff le 1010

5) nMOS onlyCMOS feasible with Si pMOS

CMOS Si nMOSSi pMOS

6) Bulk channel buried channel Shifting from surface-channel (planar) to bulk-channel (Fin)

35

4 30-nm Scaling of CAAC-IGZO FET

36

Trench Gate Self-aligned FET

L-direction W-direction

L-direction W-direction

CAAC-OS

Gate Electrode Gate Insulating Film

CAAC-OSDrain

ElectrodeSource

Electrode

Gate Electrode

Gate Insulating Film

48 nm

Gate Electrode

Gate Insulating Film

CAAC-OS34 nm

Source Electrode

Drain Electrode

CAAC-OS

Gate Insulating FilmGate Electrode

19 nm

50 nm

S-ch structure

FETrsquos active layer (CAAC-IGZO OS2 layer) is electrically surrounded by the gate electrodeWe call this FET structure a

surrounded-channel (S-ch) structure

37

Stacked Structure of OS FET and Si FET

pMOSSi

nMOSOS

GND

VDD

A Arsquo

B

Brsquo gate metal

source drain

gate insulator

CAAC-IGZO

electrode

gate

source drain

Si

SiO2

A Arsquo

B

Brsquo

OS FET

Si FET

High integration by stacking the CAAC-OS FET over the Si-FET

Si Substrate Si Substrate

W-directionL-direction

38

Comparison between CAAC-OS FET and Si nMOS FETItem CAAC-OS FET Si nMOS FET

1 Short-channel effect Small or none timesLarge (largest issue in Si NMOS FET)

2 Scaling le 30 nm (Possibility of 5 nm) Possible to ge 5 nm

3 Off-state current yAμm (10minus24 Aμm) times fAμm (10minus15 Aμm)

4 Mobility

Long channel Low High

Short channel Slightly decrease

Decrease (110 in 30-nm device)

5 Temperature characteristics

On-state current

Increase at high temperature

Decrease at high temperature

Off-state current Sufficiently low times

Drastically increase at high temperature

6 Drain breakdown voltage High Low7 Impact ionization Not observed Observed+2 +1 minus1 times minus2

39

Item CAAC-OS FET Si nMOS FET

8 Hot carrier degradation Not observed Large

9 Punch-through Not observed Strongly need balance with scaling

10 Frequency characteristics gt 30 GHz gt 300 GHz

11 Drift velocity Close to Si with channel length about 10 nm

Saturates with channel length about 100 nm

12 Sub-threshold value Small even with thick GI

Need thinner GI by miniaturizing

13 Dielectric anisotropy Observed Not observed

14 S-channel structure(Fin tri-gate type)

Extremely important and effective

Extremely important in shorter channel and effective

+25 minus1+2 +1 minus1 times minus2

Comparison between CAAC-OS FET and Si nMOS FET

40

5 CAAC-IGZO FET for LSI Application

41

Two-terminal circuit(diode)

Potential as Logic Circuit

Dependent control of input and output Need a transistor for four-terminal control Increased F2

Independently controllable inputs and outputs Desirable logic design Sufficiently low Ioff Practically an insulator

Four-terminal circuit

A B

C D

Input Output

42

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

Temperature Dependence of CAAC-IGZO FET

OS-FET

編集中編集中

L=048um GI=20nm

Vth

S値

ID_VG特性

単結晶 p-ch Si Tr （SOI）

L=035um GI=20nm L=035um GI=20nm

編集中 編集中

単結晶 n-ch Si Tr （SOI）

‐05

00

05

10

15

0 50 100 150 200 250

Vth[V]

基板温度 []

0

50

100

150

200

250

300

0 50 100 150 200 250

S‐Value[mVdec]

基板温度 []

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

VG [V]

250

1E-131E-121E-111E-101E-091E-081E-071E-061E-051E-041E-03

-3 -2 -1 0 1 2 3

ID [A

um

]

Vg [V]

250

‐05

0

05

1

15

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

‐15

‐1

‐05

0

05

0 50 100 150 200 250

Vth[V]

基板温度[]

0

50

100

150

200

250

300

0 50 100 150 200 250

Svalue[m

Vdec]

基板温度[]

T = minus40C minus 25C 0C 25C 50C 100C 150C 200C 250C

CAAC-OS FETs have a sufficient onoff ratio even at 200C or higherThe S-value shows little change (or is constant) compared with Si FETs

Single‐crystal n‐ch Tr (SOI) Single‐crystal p‐ch Tr (SOI)OS FET

ID‐VGCharac‐teristics

Vth

S‐value

Substrate temperature [C] Substrate temperature [C] Substrate temperature [C]

Substrate temperature [C]Substrate temperature [C]Substrate temperature [C]

31

1E-07

1E-06

1E-05

1E-04

1E-03

1E-02

0 5 10 15 20 25 30V D [V]

ID [A

]Si transistorL =09um T ox=20nm

IGZO transistorL =09um T ox=20nm

4V 26V

L ＝ 09 μm W ＝ 10 μm TOX = 20 nm VG ＝ 2 V

n = 2

CAAC-IGZO transistors have a higher breakdown voltage than Si transistorsNo hot carrier degradation and avalanche breakdown are observed

Breakdown Voltage of CAAC-IGZO and Si FETs

32

Schematic Band Diagram of Channel Regionmdash OS FET vs n-ch Si FET

Inversion Depletion Accumulation

Vg gt 0 V (ON State) Vg lt 0 V (OFF State)Vg = 0V

CAAC-IGZO(S-channel)

n-ch Si

OS2CAAC-IGZO

OS3Gate E

GI GI

Gate E

Gate E

GI

Si

EC

EV

Ef

EfEC

EV

Eg=32eV

Eg=12eV

ElectronsA Arsquo

OS3

Holes

A ArsquoA Arsquo

33

M Murakami et al Proc AM-FPDrsquo12 Digest p 174 (2012)

CAAC-IGZO c-Si

1) Bandgap (Eg) 28ndash32 eV 112 eV

2) Intrinsic carrierconcentration 10minus9 cm3 10+11 cm3

3) Depletion layer km order μm order

4) Electron effective mass (meme)

023ndash025 019 (transverse)098 (longitudinal)

5) Hole effective mass (mhme)

11ndash40 016 (light)049 (heavy)

6) Structure Layered structure(Homologous) Diamond cubic

7) Conductivity i-type n-type n-type p-type

Comparison of Physical Properties between CAAC-IGZO and c-Si

34

Features of CAAC-IGZO as Device

CAAC‐IGZO c‐Si

1) Four-terminal circuitFour-terminal circuit MRAM and FeRAM are two-terminal circuits

2) Almost no short-channel effects Short-channel effects are most troublesome

3) Normally off Uncontrollable Vth high purity and intrinsic

Vth is controllable by channel doping with B

4) IonIoff ratio of 1020 IonIoff le 1010

5) nMOS onlyCMOS feasible with Si pMOS

CMOS Si nMOSSi pMOS

6) Bulk channel buried channel Shifting from surface-channel (planar) to bulk-channel (Fin)

35

4 30-nm Scaling of CAAC-IGZO FET

36

Trench Gate Self-aligned FET

L-direction W-direction

L-direction W-direction

CAAC-OS

Gate Electrode Gate Insulating Film

CAAC-OSDrain

ElectrodeSource

Electrode

Gate Electrode

Gate Insulating Film

48 nm

Gate Electrode

Gate Insulating Film

CAAC-OS34 nm

Source Electrode

Drain Electrode

CAAC-OS

Gate Insulating FilmGate Electrode

19 nm

50 nm

S-ch structure

FETrsquos active layer (CAAC-IGZO OS2 layer) is electrically surrounded by the gate electrodeWe call this FET structure a

surrounded-channel (S-ch) structure

37

Stacked Structure of OS FET and Si FET

pMOSSi

nMOSOS

GND

VDD

A Arsquo

B

Brsquo gate metal

source drain

gate insulator

CAAC-IGZO

electrode

gate

source drain

Si

SiO2

A Arsquo

B

Brsquo

OS FET

Si FET

High integration by stacking the CAAC-OS FET over the Si-FET

Si Substrate Si Substrate

W-directionL-direction

38

Comparison between CAAC-OS FET and Si nMOS FETItem CAAC-OS FET Si nMOS FET

1 Short-channel effect Small or none timesLarge (largest issue in Si NMOS FET)

2 Scaling le 30 nm (Possibility of 5 nm) Possible to ge 5 nm

3 Off-state current yAμm (10minus24 Aμm) times fAμm (10minus15 Aμm)

4 Mobility

Long channel Low High

Short channel Slightly decrease

Decrease (110 in 30-nm device)

5 Temperature characteristics

On-state current

Increase at high temperature

Decrease at high temperature

Off-state current Sufficiently low times

Drastically increase at high temperature

6 Drain breakdown voltage High Low7 Impact ionization Not observed Observed+2 +1 minus1 times minus2

39

Item CAAC-OS FET Si nMOS FET

8 Hot carrier degradation Not observed Large

9 Punch-through Not observed Strongly need balance with scaling

10 Frequency characteristics gt 30 GHz gt 300 GHz

11 Drift velocity Close to Si with channel length about 10 nm

Saturates with channel length about 100 nm

12 Sub-threshold value Small even with thick GI

Need thinner GI by miniaturizing

13 Dielectric anisotropy Observed Not observed

14 S-channel structure(Fin tri-gate type)

Extremely important and effective

Extremely important in shorter channel and effective

+25 minus1+2 +1 minus1 times minus2

Comparison between CAAC-OS FET and Si nMOS FET

40

5 CAAC-IGZO FET for LSI Application

41

Two-terminal circuit(diode)

Potential as Logic Circuit

Dependent control of input and output Need a transistor for four-terminal control Increased F2

Independently controllable inputs and outputs Desirable logic design Sufficiently low Ioff Practically an insulator

Four-terminal circuit

A B

C D

Input Output

42

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

1E-07

1E-06

1E-05

1E-04

1E-03

1E-02

0 5 10 15 20 25 30V D [V]

ID [A

]Si transistorL =09um T ox=20nm

IGZO transistorL =09um T ox=20nm

4V 26V

L ＝ 09 μm W ＝ 10 μm TOX = 20 nm VG ＝ 2 V

n = 2

CAAC-IGZO transistors have a higher breakdown voltage than Si transistorsNo hot carrier degradation and avalanche breakdown are observed

Breakdown Voltage of CAAC-IGZO and Si FETs

32

Schematic Band Diagram of Channel Regionmdash OS FET vs n-ch Si FET

Inversion Depletion Accumulation

Vg gt 0 V (ON State) Vg lt 0 V (OFF State)Vg = 0V

CAAC-IGZO(S-channel)

n-ch Si

OS2CAAC-IGZO

OS3Gate E

GI GI

Gate E

Gate E

GI

Si

EC

EV

Ef

EfEC

EV

Eg=32eV

Eg=12eV

ElectronsA Arsquo

OS3

Holes

A ArsquoA Arsquo

33

M Murakami et al Proc AM-FPDrsquo12 Digest p 174 (2012)

CAAC-IGZO c-Si

1) Bandgap (Eg) 28ndash32 eV 112 eV

2) Intrinsic carrierconcentration 10minus9 cm3 10+11 cm3

3) Depletion layer km order μm order

4) Electron effective mass (meme)

023ndash025 019 (transverse)098 (longitudinal)

5) Hole effective mass (mhme)

11ndash40 016 (light)049 (heavy)

6) Structure Layered structure(Homologous) Diamond cubic

7) Conductivity i-type n-type n-type p-type

Comparison of Physical Properties between CAAC-IGZO and c-Si

34

Features of CAAC-IGZO as Device

CAAC‐IGZO c‐Si

1) Four-terminal circuitFour-terminal circuit MRAM and FeRAM are two-terminal circuits

2) Almost no short-channel effects Short-channel effects are most troublesome

3) Normally off Uncontrollable Vth high purity and intrinsic

Vth is controllable by channel doping with B

4) IonIoff ratio of 1020 IonIoff le 1010

5) nMOS onlyCMOS feasible with Si pMOS

CMOS Si nMOSSi pMOS

6) Bulk channel buried channel Shifting from surface-channel (planar) to bulk-channel (Fin)

35

4 30-nm Scaling of CAAC-IGZO FET

36

Trench Gate Self-aligned FET

L-direction W-direction

L-direction W-direction

CAAC-OS

Gate Electrode Gate Insulating Film

CAAC-OSDrain

ElectrodeSource

Electrode

Gate Electrode

Gate Insulating Film

48 nm

Gate Electrode

Gate Insulating Film

CAAC-OS34 nm

Source Electrode

Drain Electrode

CAAC-OS

Gate Insulating FilmGate Electrode

19 nm

50 nm

S-ch structure

FETrsquos active layer (CAAC-IGZO OS2 layer) is electrically surrounded by the gate electrodeWe call this FET structure a

surrounded-channel (S-ch) structure

37

Stacked Structure of OS FET and Si FET

pMOSSi

nMOSOS

GND

VDD

A Arsquo

B

Brsquo gate metal

source drain

gate insulator

CAAC-IGZO

electrode

gate

source drain

Si

SiO2

A Arsquo

B

Brsquo

OS FET

Si FET

High integration by stacking the CAAC-OS FET over the Si-FET

Si Substrate Si Substrate

W-directionL-direction

38

Comparison between CAAC-OS FET and Si nMOS FETItem CAAC-OS FET Si nMOS FET

1 Short-channel effect Small or none timesLarge (largest issue in Si NMOS FET)

2 Scaling le 30 nm (Possibility of 5 nm) Possible to ge 5 nm

3 Off-state current yAμm (10minus24 Aμm) times fAμm (10minus15 Aμm)

4 Mobility

Long channel Low High

Short channel Slightly decrease

Decrease (110 in 30-nm device)

5 Temperature characteristics

On-state current

Increase at high temperature

Decrease at high temperature

Off-state current Sufficiently low times

Drastically increase at high temperature

6 Drain breakdown voltage High Low7 Impact ionization Not observed Observed+2 +1 minus1 times minus2

39

Item CAAC-OS FET Si nMOS FET

8 Hot carrier degradation Not observed Large

9 Punch-through Not observed Strongly need balance with scaling

10 Frequency characteristics gt 30 GHz gt 300 GHz

11 Drift velocity Close to Si with channel length about 10 nm

Saturates with channel length about 100 nm

12 Sub-threshold value Small even with thick GI

Need thinner GI by miniaturizing

13 Dielectric anisotropy Observed Not observed

14 S-channel structure(Fin tri-gate type)

Extremely important and effective

Extremely important in shorter channel and effective

+25 minus1+2 +1 minus1 times minus2

Comparison between CAAC-OS FET and Si nMOS FET

40

5 CAAC-IGZO FET for LSI Application

41

Two-terminal circuit(diode)

Potential as Logic Circuit

Dependent control of input and output Need a transistor for four-terminal control Increased F2

Independently controllable inputs and outputs Desirable logic design Sufficiently low Ioff Practically an insulator

Four-terminal circuit

A B

C D

Input Output

42

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

Schematic Band Diagram of Channel Regionmdash OS FET vs n-ch Si FET

Inversion Depletion Accumulation

Vg gt 0 V (ON State) Vg lt 0 V (OFF State)Vg = 0V

CAAC-IGZO(S-channel)

n-ch Si

OS2CAAC-IGZO

OS3Gate E

GI GI

Gate E

Gate E

GI

Si

EC

EV

Ef

EfEC

EV

Eg=32eV

Eg=12eV

ElectronsA Arsquo

OS3

Holes

A ArsquoA Arsquo

33

M Murakami et al Proc AM-FPDrsquo12 Digest p 174 (2012)

CAAC-IGZO c-Si

1) Bandgap (Eg) 28ndash32 eV 112 eV

2) Intrinsic carrierconcentration 10minus9 cm3 10+11 cm3

3) Depletion layer km order μm order

4) Electron effective mass (meme)

023ndash025 019 (transverse)098 (longitudinal)

5) Hole effective mass (mhme)

11ndash40 016 (light)049 (heavy)

6) Structure Layered structure(Homologous) Diamond cubic

7) Conductivity i-type n-type n-type p-type

Comparison of Physical Properties between CAAC-IGZO and c-Si

34

Features of CAAC-IGZO as Device

CAAC‐IGZO c‐Si

1) Four-terminal circuitFour-terminal circuit MRAM and FeRAM are two-terminal circuits

2) Almost no short-channel effects Short-channel effects are most troublesome

3) Normally off Uncontrollable Vth high purity and intrinsic

Vth is controllable by channel doping with B

4) IonIoff ratio of 1020 IonIoff le 1010

5) nMOS onlyCMOS feasible with Si pMOS

CMOS Si nMOSSi pMOS

6) Bulk channel buried channel Shifting from surface-channel (planar) to bulk-channel (Fin)

35

4 30-nm Scaling of CAAC-IGZO FET

36

Trench Gate Self-aligned FET

L-direction W-direction

L-direction W-direction

CAAC-OS

Gate Electrode Gate Insulating Film

CAAC-OSDrain

ElectrodeSource

Electrode

Gate Electrode

Gate Insulating Film

48 nm

Gate Electrode

Gate Insulating Film

CAAC-OS34 nm

Source Electrode

Drain Electrode

CAAC-OS

Gate Insulating FilmGate Electrode

19 nm

50 nm

S-ch structure

FETrsquos active layer (CAAC-IGZO OS2 layer) is electrically surrounded by the gate electrodeWe call this FET structure a

surrounded-channel (S-ch) structure

37

Stacked Structure of OS FET and Si FET

pMOSSi

nMOSOS

GND

VDD

A Arsquo

B

Brsquo gate metal

source drain

gate insulator

CAAC-IGZO

electrode

gate

source drain

Si

SiO2

A Arsquo

B

Brsquo

OS FET

Si FET

High integration by stacking the CAAC-OS FET over the Si-FET

Si Substrate Si Substrate

W-directionL-direction

38

Comparison between CAAC-OS FET and Si nMOS FETItem CAAC-OS FET Si nMOS FET

1 Short-channel effect Small or none timesLarge (largest issue in Si NMOS FET)

2 Scaling le 30 nm (Possibility of 5 nm) Possible to ge 5 nm

3 Off-state current yAμm (10minus24 Aμm) times fAμm (10minus15 Aμm)

4 Mobility

Long channel Low High

Short channel Slightly decrease

Decrease (110 in 30-nm device)

5 Temperature characteristics

On-state current

Increase at high temperature

Decrease at high temperature

Off-state current Sufficiently low times

Drastically increase at high temperature

6 Drain breakdown voltage High Low7 Impact ionization Not observed Observed+2 +1 minus1 times minus2

39

Item CAAC-OS FET Si nMOS FET

8 Hot carrier degradation Not observed Large

9 Punch-through Not observed Strongly need balance with scaling

10 Frequency characteristics gt 30 GHz gt 300 GHz

11 Drift velocity Close to Si with channel length about 10 nm

Saturates with channel length about 100 nm

12 Sub-threshold value Small even with thick GI

Need thinner GI by miniaturizing

13 Dielectric anisotropy Observed Not observed

14 S-channel structure(Fin tri-gate type)

Extremely important and effective

Extremely important in shorter channel and effective

+25 minus1+2 +1 minus1 times minus2

Comparison between CAAC-OS FET and Si nMOS FET

40

5 CAAC-IGZO FET for LSI Application

41

Two-terminal circuit(diode)

Potential as Logic Circuit

Dependent control of input and output Need a transistor for four-terminal control Increased F2

Independently controllable inputs and outputs Desirable logic design Sufficiently low Ioff Practically an insulator

Four-terminal circuit

A B

C D

Input Output

42

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

M Murakami et al Proc AM-FPDrsquo12 Digest p 174 (2012)

CAAC-IGZO c-Si

1) Bandgap (Eg) 28ndash32 eV 112 eV

2) Intrinsic carrierconcentration 10minus9 cm3 10+11 cm3

3) Depletion layer km order μm order

4) Electron effective mass (meme)

023ndash025 019 (transverse)098 (longitudinal)

5) Hole effective mass (mhme)

11ndash40 016 (light)049 (heavy)

6) Structure Layered structure(Homologous) Diamond cubic

7) Conductivity i-type n-type n-type p-type

Comparison of Physical Properties between CAAC-IGZO and c-Si

34

Features of CAAC-IGZO as Device

CAAC‐IGZO c‐Si

1) Four-terminal circuitFour-terminal circuit MRAM and FeRAM are two-terminal circuits

2) Almost no short-channel effects Short-channel effects are most troublesome

3) Normally off Uncontrollable Vth high purity and intrinsic

Vth is controllable by channel doping with B

4) IonIoff ratio of 1020 IonIoff le 1010

5) nMOS onlyCMOS feasible with Si pMOS

CMOS Si nMOSSi pMOS

6) Bulk channel buried channel Shifting from surface-channel (planar) to bulk-channel (Fin)

35

4 30-nm Scaling of CAAC-IGZO FET

36

Trench Gate Self-aligned FET

L-direction W-direction

L-direction W-direction

CAAC-OS

Gate Electrode Gate Insulating Film

CAAC-OSDrain

ElectrodeSource

Electrode

Gate Electrode

Gate Insulating Film

48 nm

Gate Electrode

Gate Insulating Film

CAAC-OS34 nm

Source Electrode

Drain Electrode

CAAC-OS

Gate Insulating FilmGate Electrode

19 nm

50 nm

S-ch structure

FETrsquos active layer (CAAC-IGZO OS2 layer) is electrically surrounded by the gate electrodeWe call this FET structure a

surrounded-channel (S-ch) structure

37

Stacked Structure of OS FET and Si FET

pMOSSi

nMOSOS

GND

VDD

A Arsquo

B

Brsquo gate metal

source drain

gate insulator

CAAC-IGZO

electrode

gate

source drain

Si

SiO2

A Arsquo

B

Brsquo

OS FET

Si FET

High integration by stacking the CAAC-OS FET over the Si-FET

Si Substrate Si Substrate

W-directionL-direction

38

Comparison between CAAC-OS FET and Si nMOS FETItem CAAC-OS FET Si nMOS FET

1 Short-channel effect Small or none timesLarge (largest issue in Si NMOS FET)

2 Scaling le 30 nm (Possibility of 5 nm) Possible to ge 5 nm

3 Off-state current yAμm (10minus24 Aμm) times fAμm (10minus15 Aμm)

4 Mobility

Long channel Low High

Short channel Slightly decrease

Decrease (110 in 30-nm device)

5 Temperature characteristics

On-state current

Increase at high temperature

Decrease at high temperature

Off-state current Sufficiently low times

Drastically increase at high temperature

6 Drain breakdown voltage High Low7 Impact ionization Not observed Observed+2 +1 minus1 times minus2

39

Item CAAC-OS FET Si nMOS FET

8 Hot carrier degradation Not observed Large

9 Punch-through Not observed Strongly need balance with scaling

10 Frequency characteristics gt 30 GHz gt 300 GHz

11 Drift velocity Close to Si with channel length about 10 nm

Saturates with channel length about 100 nm

12 Sub-threshold value Small even with thick GI

Need thinner GI by miniaturizing

13 Dielectric anisotropy Observed Not observed

14 S-channel structure(Fin tri-gate type)

Extremely important and effective

Extremely important in shorter channel and effective

+25 minus1+2 +1 minus1 times minus2

Comparison between CAAC-OS FET and Si nMOS FET

40

5 CAAC-IGZO FET for LSI Application

41

Two-terminal circuit(diode)

Potential as Logic Circuit

Dependent control of input and output Need a transistor for four-terminal control Increased F2

Independently controllable inputs and outputs Desirable logic design Sufficiently low Ioff Practically an insulator

Four-terminal circuit

A B

C D

Input Output

42

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

Features of CAAC-IGZO as Device

CAAC‐IGZO c‐Si

1) Four-terminal circuitFour-terminal circuit MRAM and FeRAM are two-terminal circuits

2) Almost no short-channel effects Short-channel effects are most troublesome

3) Normally off Uncontrollable Vth high purity and intrinsic

Vth is controllable by channel doping with B

4) IonIoff ratio of 1020 IonIoff le 1010

5) nMOS onlyCMOS feasible with Si pMOS

CMOS Si nMOSSi pMOS

6) Bulk channel buried channel Shifting from surface-channel (planar) to bulk-channel (Fin)

35

4 30-nm Scaling of CAAC-IGZO FET

36

Trench Gate Self-aligned FET

L-direction W-direction

L-direction W-direction

CAAC-OS

Gate Electrode Gate Insulating Film

CAAC-OSDrain

ElectrodeSource

Electrode

Gate Electrode

Gate Insulating Film

48 nm

Gate Electrode

Gate Insulating Film

CAAC-OS34 nm

Source Electrode

Drain Electrode

CAAC-OS

Gate Insulating FilmGate Electrode

19 nm

50 nm

S-ch structure

FETrsquos active layer (CAAC-IGZO OS2 layer) is electrically surrounded by the gate electrodeWe call this FET structure a

surrounded-channel (S-ch) structure

37

Stacked Structure of OS FET and Si FET

pMOSSi

nMOSOS

GND

VDD

A Arsquo

B

Brsquo gate metal

source drain

gate insulator

CAAC-IGZO

electrode

gate

source drain

Si

SiO2

A Arsquo

B

Brsquo

OS FET

Si FET

High integration by stacking the CAAC-OS FET over the Si-FET

Si Substrate Si Substrate

W-directionL-direction

38

Comparison between CAAC-OS FET and Si nMOS FETItem CAAC-OS FET Si nMOS FET

1 Short-channel effect Small or none timesLarge (largest issue in Si NMOS FET)

2 Scaling le 30 nm (Possibility of 5 nm) Possible to ge 5 nm

3 Off-state current yAμm (10minus24 Aμm) times fAμm (10minus15 Aμm)

4 Mobility

Long channel Low High

Short channel Slightly decrease

Decrease (110 in 30-nm device)

5 Temperature characteristics

On-state current

Increase at high temperature

Decrease at high temperature

Off-state current Sufficiently low times

Drastically increase at high temperature

6 Drain breakdown voltage High Low7 Impact ionization Not observed Observed+2 +1 minus1 times minus2

39

Item CAAC-OS FET Si nMOS FET

8 Hot carrier degradation Not observed Large

9 Punch-through Not observed Strongly need balance with scaling

10 Frequency characteristics gt 30 GHz gt 300 GHz

11 Drift velocity Close to Si with channel length about 10 nm

Saturates with channel length about 100 nm

12 Sub-threshold value Small even with thick GI

Need thinner GI by miniaturizing

13 Dielectric anisotropy Observed Not observed

14 S-channel structure(Fin tri-gate type)

Extremely important and effective

Extremely important in shorter channel and effective

+25 minus1+2 +1 minus1 times minus2

Comparison between CAAC-OS FET and Si nMOS FET

40

5 CAAC-IGZO FET for LSI Application

41

Two-terminal circuit(diode)

Potential as Logic Circuit

Dependent control of input and output Need a transistor for four-terminal control Increased F2

Independently controllable inputs and outputs Desirable logic design Sufficiently low Ioff Practically an insulator

Four-terminal circuit

A B

C D

Input Output

42

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

4 30-nm Scaling of CAAC-IGZO FET

36

Trench Gate Self-aligned FET

L-direction W-direction

L-direction W-direction

CAAC-OS

Gate Electrode Gate Insulating Film

CAAC-OSDrain

ElectrodeSource

Electrode

Gate Electrode

Gate Insulating Film

48 nm

Gate Electrode

Gate Insulating Film

CAAC-OS34 nm

Source Electrode

Drain Electrode

CAAC-OS

Gate Insulating FilmGate Electrode

19 nm

50 nm

S-ch structure

FETrsquos active layer (CAAC-IGZO OS2 layer) is electrically surrounded by the gate electrodeWe call this FET structure a

surrounded-channel (S-ch) structure

37

Stacked Structure of OS FET and Si FET

pMOSSi

nMOSOS

GND

VDD

A Arsquo

B

Brsquo gate metal

source drain

gate insulator

CAAC-IGZO

electrode

gate

source drain

Si

SiO2

A Arsquo

B

Brsquo

OS FET

Si FET

High integration by stacking the CAAC-OS FET over the Si-FET

Si Substrate Si Substrate

W-directionL-direction

38

Comparison between CAAC-OS FET and Si nMOS FETItem CAAC-OS FET Si nMOS FET

1 Short-channel effect Small or none timesLarge (largest issue in Si NMOS FET)

2 Scaling le 30 nm (Possibility of 5 nm) Possible to ge 5 nm

3 Off-state current yAμm (10minus24 Aμm) times fAμm (10minus15 Aμm)

4 Mobility

Long channel Low High

Short channel Slightly decrease

Decrease (110 in 30-nm device)

5 Temperature characteristics

On-state current

Increase at high temperature

Decrease at high temperature

Off-state current Sufficiently low times

Drastically increase at high temperature

6 Drain breakdown voltage High Low7 Impact ionization Not observed Observed+2 +1 minus1 times minus2

39

Item CAAC-OS FET Si nMOS FET

8 Hot carrier degradation Not observed Large

9 Punch-through Not observed Strongly need balance with scaling

10 Frequency characteristics gt 30 GHz gt 300 GHz

11 Drift velocity Close to Si with channel length about 10 nm

Saturates with channel length about 100 nm

12 Sub-threshold value Small even with thick GI

Need thinner GI by miniaturizing

13 Dielectric anisotropy Observed Not observed

14 S-channel structure(Fin tri-gate type)

Extremely important and effective

Extremely important in shorter channel and effective

+25 minus1+2 +1 minus1 times minus2

Comparison between CAAC-OS FET and Si nMOS FET

40

5 CAAC-IGZO FET for LSI Application

41

Two-terminal circuit(diode)

Potential as Logic Circuit

Dependent control of input and output Need a transistor for four-terminal control Increased F2

Independently controllable inputs and outputs Desirable logic design Sufficiently low Ioff Practically an insulator

Four-terminal circuit

A B

C D

Input Output

42

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

Trench Gate Self-aligned FET

L-direction W-direction

L-direction W-direction

CAAC-OS

Gate Electrode Gate Insulating Film

CAAC-OSDrain

ElectrodeSource

Electrode

Gate Electrode

Gate Insulating Film

48 nm

Gate Electrode

Gate Insulating Film

CAAC-OS34 nm

Source Electrode

Drain Electrode

CAAC-OS

Gate Insulating FilmGate Electrode

19 nm

50 nm

S-ch structure

FETrsquos active layer (CAAC-IGZO OS2 layer) is electrically surrounded by the gate electrodeWe call this FET structure a

surrounded-channel (S-ch) structure

37

Stacked Structure of OS FET and Si FET

pMOSSi

nMOSOS

GND

VDD

A Arsquo

B

Brsquo gate metal

source drain

gate insulator

CAAC-IGZO

electrode

gate

source drain

Si

SiO2

A Arsquo

B

Brsquo

OS FET

Si FET

High integration by stacking the CAAC-OS FET over the Si-FET

Si Substrate Si Substrate

W-directionL-direction

38

Comparison between CAAC-OS FET and Si nMOS FETItem CAAC-OS FET Si nMOS FET

1 Short-channel effect Small or none timesLarge (largest issue in Si NMOS FET)

2 Scaling le 30 nm (Possibility of 5 nm) Possible to ge 5 nm

3 Off-state current yAμm (10minus24 Aμm) times fAμm (10minus15 Aμm)

4 Mobility

Long channel Low High

Short channel Slightly decrease

Decrease (110 in 30-nm device)

5 Temperature characteristics

On-state current

Increase at high temperature

Decrease at high temperature

Off-state current Sufficiently low times

Drastically increase at high temperature

6 Drain breakdown voltage High Low7 Impact ionization Not observed Observed+2 +1 minus1 times minus2

39

Item CAAC-OS FET Si nMOS FET

8 Hot carrier degradation Not observed Large

9 Punch-through Not observed Strongly need balance with scaling

10 Frequency characteristics gt 30 GHz gt 300 GHz

11 Drift velocity Close to Si with channel length about 10 nm

Saturates with channel length about 100 nm

12 Sub-threshold value Small even with thick GI

Need thinner GI by miniaturizing

13 Dielectric anisotropy Observed Not observed

14 S-channel structure(Fin tri-gate type)

Extremely important and effective

Extremely important in shorter channel and effective

+25 minus1+2 +1 minus1 times minus2

Comparison between CAAC-OS FET and Si nMOS FET

40

5 CAAC-IGZO FET for LSI Application

41

Two-terminal circuit(diode)

Potential as Logic Circuit

Dependent control of input and output Need a transistor for four-terminal control Increased F2

Independently controllable inputs and outputs Desirable logic design Sufficiently low Ioff Practically an insulator

Four-terminal circuit

A B

C D

Input Output

42

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

Stacked Structure of OS FET and Si FET

pMOSSi

nMOSOS

GND

VDD

A Arsquo

B

Brsquo gate metal

source drain

gate insulator

CAAC-IGZO

electrode

gate

source drain

Si

SiO2

A Arsquo

B

Brsquo

OS FET

Si FET

High integration by stacking the CAAC-OS FET over the Si-FET

Si Substrate Si Substrate

W-directionL-direction

38

Comparison between CAAC-OS FET and Si nMOS FETItem CAAC-OS FET Si nMOS FET

1 Short-channel effect Small or none timesLarge (largest issue in Si NMOS FET)

2 Scaling le 30 nm (Possibility of 5 nm) Possible to ge 5 nm

3 Off-state current yAμm (10minus24 Aμm) times fAμm (10minus15 Aμm)

4 Mobility

Long channel Low High

Short channel Slightly decrease

Decrease (110 in 30-nm device)

5 Temperature characteristics

On-state current

Increase at high temperature

Decrease at high temperature

Off-state current Sufficiently low times

Drastically increase at high temperature

6 Drain breakdown voltage High Low7 Impact ionization Not observed Observed+2 +1 minus1 times minus2

39

Item CAAC-OS FET Si nMOS FET

8 Hot carrier degradation Not observed Large

9 Punch-through Not observed Strongly need balance with scaling

10 Frequency characteristics gt 30 GHz gt 300 GHz

11 Drift velocity Close to Si with channel length about 10 nm

Saturates with channel length about 100 nm

12 Sub-threshold value Small even with thick GI

Need thinner GI by miniaturizing

13 Dielectric anisotropy Observed Not observed

14 S-channel structure(Fin tri-gate type)

Extremely important and effective

Extremely important in shorter channel and effective

+25 minus1+2 +1 minus1 times minus2

Comparison between CAAC-OS FET and Si nMOS FET

40

5 CAAC-IGZO FET for LSI Application

41

Two-terminal circuit(diode)

Potential as Logic Circuit

Dependent control of input and output Need a transistor for four-terminal control Increased F2

Independently controllable inputs and outputs Desirable logic design Sufficiently low Ioff Practically an insulator

Four-terminal circuit

A B

C D

Input Output

42

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

Comparison between CAAC-OS FET and Si nMOS FETItem CAAC-OS FET Si nMOS FET

1 Short-channel effect Small or none timesLarge (largest issue in Si NMOS FET)

2 Scaling le 30 nm (Possibility of 5 nm) Possible to ge 5 nm

3 Off-state current yAμm (10minus24 Aμm) times fAμm (10minus15 Aμm)

4 Mobility

Long channel Low High

Short channel Slightly decrease

Decrease (110 in 30-nm device)

5 Temperature characteristics

On-state current

Increase at high temperature

Decrease at high temperature

Off-state current Sufficiently low times

Drastically increase at high temperature

6 Drain breakdown voltage High Low7 Impact ionization Not observed Observed+2 +1 minus1 times minus2

39

Item CAAC-OS FET Si nMOS FET

8 Hot carrier degradation Not observed Large

9 Punch-through Not observed Strongly need balance with scaling

10 Frequency characteristics gt 30 GHz gt 300 GHz

11 Drift velocity Close to Si with channel length about 10 nm

Saturates with channel length about 100 nm

12 Sub-threshold value Small even with thick GI

Need thinner GI by miniaturizing

13 Dielectric anisotropy Observed Not observed

14 S-channel structure(Fin tri-gate type)

Extremely important and effective

Extremely important in shorter channel and effective

+25 minus1+2 +1 minus1 times minus2

Comparison between CAAC-OS FET and Si nMOS FET

40

5 CAAC-IGZO FET for LSI Application

41

Two-terminal circuit(diode)

Potential as Logic Circuit

Dependent control of input and output Need a transistor for four-terminal control Increased F2

Independently controllable inputs and outputs Desirable logic design Sufficiently low Ioff Practically an insulator

Four-terminal circuit

A B

C D

Input Output

42

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

Item CAAC-OS FET Si nMOS FET

8 Hot carrier degradation Not observed Large

9 Punch-through Not observed Strongly need balance with scaling

10 Frequency characteristics gt 30 GHz gt 300 GHz

11 Drift velocity Close to Si with channel length about 10 nm

Saturates with channel length about 100 nm

12 Sub-threshold value Small even with thick GI

Need thinner GI by miniaturizing

13 Dielectric anisotropy Observed Not observed

14 S-channel structure(Fin tri-gate type)

Extremely important and effective

Extremely important in shorter channel and effective

+25 minus1+2 +1 minus1 times minus2

Comparison between CAAC-OS FET and Si nMOS FET

40

5 CAAC-IGZO FET for LSI Application

41

Two-terminal circuit(diode)

Potential as Logic Circuit

Dependent control of input and output Need a transistor for four-terminal control Increased F2

Independently controllable inputs and outputs Desirable logic design Sufficiently low Ioff Practically an insulator

Four-terminal circuit

A B

C D

Input Output

42

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

5 CAAC-IGZO FET for LSI Application

41

Two-terminal circuit(diode)

Potential as Logic Circuit

Dependent control of input and output Need a transistor for four-terminal control Increased F2

Independently controllable inputs and outputs Desirable logic design Sufficiently low Ioff Practically an insulator

Four-terminal circuit

A B

C D

Input Output

42

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

Two-terminal circuit(diode)

Potential as Logic Circuit

Dependent control of input and output Need a transistor for four-terminal control Increased F2

Independently controllable inputs and outputs Desirable logic design Sufficiently low Ioff Practically an insulator

Four-terminal circuit

A B

C D

Input Output

42

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

DOSRAM NOSRAM STT-MRAM ReRAM PCM FeRAM

Configuration 1OS1C 2OS1C 1T1MTJ 1T1R 1T1R 1T1C

Device size 60 nm 30 nm 30 nm Φ [1] 24 nm [3] 20 nm [7] 130 nm [9][10]

Endurance gt 1012

unlimited gt 1012 [2] 106 to 107 [4][5] 106 to 109 [2][8] 1014 [2]

Write Energy lt 24 fJbit gt 50 fJbit [1] gt 300 fJbit [4][6] gt 6 pJbit [2] gt 30 fJbit [10]

Write Time 2 ns 2 ns [1] lt 10 ns [6] 150 ns [7] 65 ns [10]

Write Voltage 12 V 33 V 06 V [1] lt 2 V [4] lt 3 V [8] 15 V [10]

[1] H Noguchi et al VLSI (2014) [2] ITRS 2013 ERD [3] T Liu et al ISSCC (2013) [4] S Sills et al VLSI (2014) [5] A Kawahara et al ISSCC (2013) [6] A Kawahara et al ISSCC (2012) [7] Y Choiet al ISSCC (2012) [8] C Villa et al ISSCC (2010) [9] S Bartling et al ISSCC(2013) [10] D Takashima et al ISSCC(2010)

Higher Energy

Lower Endurance Larger Device Size

Comparison of Memory ElementsCAAC-OS vs Two-terminal Memory Elements

43

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

Potential as Logic Circuit

Applicable to electronic circuits learnt at university leading to easy application by electrical and electronic engineers

Potentially capable of countless applications by combination with L C and R in the low-power electronics industry

MRAM and ReRAM for example are two-terminal circuits whose input and output are dependent In contrast an OS FET can constitute a four-terminal circuit whose inputs and outputs are independent

44

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

CAAC-OS

CsAlmost no leakage

DOSRAM Dynamic Oxide Semiconductor Random Access MemoryNOSRAM Nonvolatile Oxide Semiconductor Random Access Memory

Almost no refresh power due to long data retention

Process friendly due to small Cs This is enabled by stack of cells over sense amps

High write endurance Power can be turned off during sleep

DOSRAM Cell

Almost no leakage

Read

CAAC-OS Cs

NOSRAM Cell Fast read access time by using the dedicated FET

High write endurance Power can be turned off during sleep Multi-bit per cell is feasible

Advantages of NOSRAM and DOSRAM

Q (FN)

Q

[1] H Inoue et al ldquoNonvolatile Memory With Extremely Low-leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistorrdquo IEEE J Solid-State Circuits vol 47 no 9 pp 2258-2265 Sept 2012[2] T Atsumi et al ldquoDRAM Using Crystalline Oxide Semiconductor for Access Transistors and not Requiring Refresh for More than Ten Daysrdquo IMW Dig Tech Papers May 2012

Flash Memory[1]

[2]

45

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

CMOS by SiFin-type SiOS Hybrid CMOS Planar CMOS Shallow Trench Isolation (STI) LDD Strained FET Implantation for Si nMOS Well or pMOS or nMOS Larger F2

Increased leakage due to ultrathin GI by scaling

No STI necessary No LDD necessary No strained FET necessary No implantation necessary for Si nMOS No well necessary Smaller F2 (stacked structure) Thicker GI

SiOS Hybrid CMOS Structure

GND

VDD

VDD GND

Stacked CMOS FET Planar CMOS FET

pMOSSi

nMOSOS

pMOSSi

nMOSSi

Same plane

Upper layer

Lowerlayer

46

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

Super Low Power Flash (NOSRAM)Test Chip vs Commercial Chip

0

20

40

60

80

100

065 μW

50 μW

490 μW

480

500

Writ

e po

wer

(μW

)

Test Chip (Fabricated)

1kbit

NOSR

AMLogicCircuit

AnalogCircuit

Write to memory (lt 01 ms)

Test Chip

Commercial Chip A

Write to memory (gt 6 ms)

Test Chip (NOSRAM)

Commercial Chip A

(FLASH)

Commercial Chip B

(FLASH)

Reduction to 13

[1] M Tsubuku et al ldquoAnalysis for Extremely Low Off‐state Current in CAAC‐IGZO FETsrdquo ULSI vs TFT Jun 2015 (to be published)[2] Datasheet of a commercial chip with flash memory

[1]

[2]

Memory Module 1-kbit NOSRAM

Protocol ISOIEC18000-6 Type C

Technology Si 035 μmCAAC-OS 08 μm

Supply Voltage Si 33 VCAAC-OS 18 V 12 V

Carrier Frequency 920 MHz

47

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

-3

-2

-1

0

1

Vth

[V]

Write cycle number1 102 104 106 108 1010 1012

data ldquo1rdquo

data ldquo0rdquo

1012 cyclesUnlimited Endurance

01

1

10

01 1 10

Writ

e Ti

me

[ns]

Cload [fF]

Short Write Time

WL = 6060 nm

Long Data Retention

Low Write Energy

gt 1 year (85ordmC)

WL = 6060 nm

lt x110

300 fJ 6000 fJOS FET WL = 6060 nm

lt 1 ns (NOSRAM)

lt 2 ns (DOSRAM)

Switching of FET onlyNeither tunneling nor displacement of atoms

Charging a small capacitor onlyNo resistive element

High on-state current and a small capacitor

Low off-state current of CAAC-OS FET

Evaluation of 60-nm OS FET NOSRAM

[STT‐MRAM] H Noguchi et al VLSI (2014) [ReRAM] S Sills et al VLSI (2014)A Kawahara et al ISSCC (2012)[PCM] ITRS 2013 ERD

48

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

Row Decoder

CellArray

SenseAmps

Bit Line

Sense Amp Array

Short Bit Line (small Cbit)

Stacked Structure

Key Structure

Small Storage Capacitance (Cs)Sense Amp

Features Stacked structure Area reduction Small Cbit and Cs Small Cbit and Cs Fast RW Process Friendly

DOSRAM Dynamic Oxide Semiconductor Random Access Memory

Si

OS

DOSRAM Architecture

Si DRAM Stacked CMOSDOSRAM using OS memory

49

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

0

5

10

15

20

25

25 85Battery Life (year)

Temperature ()

MCU ANoff CPU

8KBDOSRAM

Test Chip (Design)

SensorModule

MCU

Example of Sensor IC

Power Consumption at 50 MHz (μW)

Battery life is extended 5 to 25 times by using Noff CPU and DOSRAM

x5

x25

CPU

Super Low Power DRAM (DOSRAM)

[1] T Ohuki et al ldquoDRAM with Storage Capacitance of 39 fF using CAAC‐OS Transistor with L of 60 nm and having More Than 1‐h Retention Characteristicsrdquo SSDM Sept 2014[2]Datasheet of a commercial MCU with Cortex‐M0 and SRAM

[1]

Mode25ordmC 85ordmC

MCU A[2] Test Chip MCU A[2] Test ChipActive 7689 1700 8052 1900Sleep 8118 03 12616 215

50

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

1E-02

1E+00

1E+02

1E+04

1E+06

1E+08

1E-24 1E-21 1E-18 1E-15 1E-12

Low off-state current of OS FET enables long retention and small Cs In the DOSRAM cell data can be refreshed only once every hour at Cs = 3 fF

Furthermore DOSRAM has potential to function as nonvolatile memory The refresh power of DRAM can be reduced to substantially zero

Normally-Off Use

Nonvolatile

Si FET

Almost Zero Refresh Power

LargeRefresh Power

64 ms

1 hour

1 day

1 year

Ret

entio

n Ti

me

10 years

Cell Leakage [Acell]

CAAC-OS FET

1 Year Retention (60‐nm FET measurement and estimation)

Lower Refresh Rate

DOSRAM with 5‐ns access and refresh once every hour(60‐nm FET typical sim)

Low Refresh Rate

51

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

52H Tamura et al IEEE Micro vol34 no6 pp42-53 NovDec 2014

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

BAN (Body Area Network)

IoT(Sensor Network)trillion sensors

(market 130 billion US dollarsin 20231)

Infrastructure Monitoring System1 Estimated by Janusz Bryzek IoT advocate

Sensor Network Applications

Healthcare

SmartEnvironment

Traffic Control

Smart Lighting

Structural Health(eg bridges and historical monuments)Smart Agriculture

Logistics

IndustrialControl

Security ampEmergency

Smart Metering

53

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

6 Targets for the Next Three Years

54

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

Homework from Dr R N Noyce one of the founders of Intel

(Currently manufactured flash memory becomes inoperable after 102ndash105 rewritings)

Target

ldquoDevelop degradation-free flash memoryrdquo Is it really possible to make such flash memory at the terabyte level

At Dr Noycersquos house in 1980 (left Mr Borovoy center Yamazaki right Dr Noyce)

TI visit in 1986 (right Dr J Kilby)

55

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

(1) 8-bit Noff CPUSSDM 2012

(2) 32-bit Noff CPUSSDM 2013

PAGE BUFFERamp SL DRIVER

1 Mb Array

RO

W D

RIV

ER

(6) 1-Mbit NOSRAMISSCC 2015JSSC 2012

(7) 4-bitcell NOSRAMIMW 2012

(5) DOSRAM

(3) FPGAISSCC 2014

(4)Cortex-M0 with SRAMCool Chips 2014

ISSCC 2015(8) Image Sensor

OS LSI 3D LSI composed of SiCAAC-OS hybrid CMOS

Pixel array20 μm 20 μm

240 (H) 160 (V)

8b ADC ampY-decoder

Analog processor

Noff Normally-Off

LSIs developed by SEL using CAAC-OS Technology

56

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

OS-FET Scaling

4) H Tamura et al ldquoEmbedded SRAM and Cortex‐M0 Core Using a 60‐nm Crystalline Oxide Semiconductorrdquo Proc of COOLChips XVII Apr 20145) A Isobe et al ldquoA 32‐bit CPU with Zero Standby Power and 15‐clock Sleep25‐clock Wake‐up Achieved by Utilizing a 180‐nm C‐axis Aligned Crystalline In‐Ga‐Zn Oxide Transistorrdquo IEEE Symp VLSI Circuits Jun 201410) T Matsuzaki et al ldquoA 128kbit 4bitcell Nonvolatile Memory with Crystalline In‐Ga‐Zn Oxide FET Using Vt Cancel Write Methodrdquo ISSCC pp 306‐307 Feb 201512) Y Yakubo et al ldquoHigh‐speed and Low‐leakage Characteristics of 60‐nm C‐axis Aligned Crystalline Oxide Semiconductor FET with GHz‐ordered Cutoff Frequencyrdquo SSDM Sept 2014

10

100

1000

10000

20101 20111 20121 20131 20141 20151 20161 20171

OS‐FET Ch

anne

l Len

gth (nm)

Date

ProcessorMemoryDevice

Processor1) SSDM 20122) COOL Chips 20133) SSDM 20134) COOL Chips 20145) VLSI 2014

Memory6) IMW 20127) IMW 20138) IMW 20149) SSDM 201410) ISSCC 2015

OS-FET11) SSDM 201312) SSDM 2014

Si-FET Scaling

OS-FET Scaling1)

2)

3)

4)

5)

6)

7)

8)9)

10)

11) 12)60-nm OSFET

30-nm OSFET

15-nm OSFET

57

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

Concept of Stacked NOSRAM

1st OS Layer (Memory)2nd OS Layer (Memory)3rd OS Layer (Memory)4th OS Layer (Memory)

4th OS LayerNOSRAM

3rd OS LayerNOSRAM

2nd OS LayerNOSRAM

1st OS LayerNOSRAM

1 Word

Si CMOS Layer (Control)

NOSRAM cell

Each cell stores 4 bits

0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1

58

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

Stacked NOSRAM Scaling

A 15-nm-node 4-layer structure equivalent to a 256 GB SSD A 10-nm-node 6-layer structure equivalent to a 1 TB SSD

000001

00001

0001

001

1 10

Are

a pe

r bit

[μm

2 ]

Number of stacked layers

30nm15nm10nm

equivalent to a 256 GB SSD

equivalent to a 1 TB SSD

4 packages (stacked chips) in SSD

(100 nm2)

(10 nm2)

(1000 nm2)

59

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

Targets for the Next Three YearsTarget Design rule

1) NOSRAM (Flash) 1-TB SSD (Solid-state Drive) 10ndash20 nm (10 nm)

2) DOSRAM (DRAM) 1-Gbit Cache (Cache Memory) 10ndash20 nm

3) Noff CPU (CPU) 1-GHz driving 10ndash20 nm

4) FPGA (FPGA) 1M LE (Logic Element) 10ndash20 nm

5) Image Sensor (Image Sensor) 8K (130 million pixels) 10ndash20 nm

6) Full Driver (LCD Driver） 8K Source Driver + TP (Touch Panel) 55ndash130 nm

7) Decoder 8K 10ndash20 nm

8) RF Device 1Mbit 10fJbit NVM 28-55 nm

9) Sensor networks 10y Operation with Button Cell 28-55 nm

10) Automotive electronicsgt40V High-voltage Device and

Logic Integration28 nm amp ～1 μm

60

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

Market Size of Integrated Circuits in 2014

httpwwwwstsorgPRESSRecent-News-ReleaseWSTS_nr-2015_03pdf

Micro MPU MCU DSPLogic Specified and Custom

Total about 278 [B$]B$ Billion dollars

= 33 trillion yen (at yen120＄)

61

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

7 Conclusion

62

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

Conclusion

1) Oxide semiconductors (OSs) were totally disregarded in the LSI field IGZO an OS which was successfully synthesized by Dr Kimizuka for the first time in the world is now attracting much attention as a result of discovery of a new crystal structure called CAAC

2) CAAC-IGZO can even replace nMOS Si FETs in Si LSI The market size is 278 billion US dollars (33 trillion yen at yen120$)

3) A new semiconductor field of super low power LSI should be opened up This is genuine technology introduced from Japan to the world

4) I would like to ask you not to beat this into the ground but to give warm support

63

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

Closing

ldquoThis reminds me of the historic development of MOS ICs in the era of bipolar ICs into a major player in the industry through the efforts of engineers to overcome various reliability problemsrdquo

ldquoA drastic change like the change from the germanium semiconductor era to the silicon semiconductor era is occurringrdquo

If a pMOS can also be made it can lead to an industry as huge as that started from the invention of the transistor by Shockley and his colleagues in 1948

I hope you can feel CAAC-OS turning into ldquobig giantsrdquo

Comments received so far on OS LSI

64

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

1947ndash1948 Invention of transistor1)

(by Dr W B Shockley Dr J Bardeen Dr W Brattain and others)1947 Point-contact transistor (germanium)1948 Bipolar transistor (silicon)

19592 Invention of LSI (integrated circuit IC) (by Dr J Kilby)2)

19597 Invention of planar IC (by Dr R Noyce)3)

1960 Invention of MOS transistor4)

1963 Invention of CMOS transistor5)

1967 Development of nonvolatile memory6)

(by Dr D Kahng and Dr S Sze at Bell Labs) 1968 Foundation of Intel

6) D Kahng and S M Sze Bell Syst Tech J pp 1288‐1295 (1967)

1) httpwwwshmjorjpmuseum2010exhibi304htm

2) United States Patent No 3183743

4) httpwwwshmjorjpmuseum2010exhibi337htm

5) httpwwwshmjorjpmuseum2010exhibi307htm

3) United States Patent No 2981877

History of Si

65

Thank you for your attention

66

Thank you for your attention

66